2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/highmem.h>
35 #include <linux/clk.h>
36 #include <linux/err.h>
37 #include <linux/completion.h>
38 #include <linux/mmc/host.h>
39 #include <linux/mmc/mmc.h>
40 #include <linux/mmc/sdio.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/module.h>
44 #include <linux/fsl/mxs-dma.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/stmp_device.h>
47 #include <linux/mmc/mxs-mmc.h>
49 #define DRIVER_NAME "mxs-mmc"
51 /* card detect polling timeout */
52 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
54 #define ssp_is_old(host) ((host)->devid == IMX23_MMC)
57 #define HW_SSP_CTRL0 0x000
58 #define BM_SSP_CTRL0_RUN (1 << 29)
59 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
60 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
61 #define BM_SSP_CTRL0_READ (1 << 25)
62 #define BM_SSP_CTRL0_DATA_XFER (1 << 24)
63 #define BP_SSP_CTRL0_BUS_WIDTH (22)
64 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
65 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
66 #define BM_SSP_CTRL0_LONG_RESP (1 << 19)
67 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
68 #define BM_SSP_CTRL0_ENABLE (1 << 16)
69 #define BP_SSP_CTRL0_XFER_COUNT (0)
70 #define BM_SSP_CTRL0_XFER_COUNT (0xffff)
71 #define HW_SSP_CMD0 0x010
72 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
73 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
74 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
75 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
76 #define BP_SSP_CMD0_BLOCK_SIZE (16)
77 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
78 #define BP_SSP_CMD0_BLOCK_COUNT (8)
79 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
80 #define BP_SSP_CMD0_CMD (0)
81 #define BM_SSP_CMD0_CMD (0xff)
82 #define HW_SSP_CMD1 0x020
83 #define HW_SSP_XFER_SIZE 0x030
84 #define HW_SSP_BLOCK_SIZE 0x040
85 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
86 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
87 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
88 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
89 #define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
90 #define BP_SSP_TIMING_TIMEOUT (16)
91 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
92 #define BP_SSP_TIMING_CLOCK_DIVIDE (8)
93 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
94 #define BP_SSP_TIMING_CLOCK_RATE (0)
95 #define BM_SSP_TIMING_CLOCK_RATE (0xff)
96 #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
97 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
98 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
99 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
100 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
101 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
102 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
103 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
104 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
105 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
106 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
107 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
108 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
109 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
110 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
111 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
112 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
113 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
114 #define BM_SSP_CTRL1_POLARITY (1 << 9)
115 #define BP_SSP_CTRL1_WORD_LENGTH (4)
116 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
117 #define BP_SSP_CTRL1_SSP_MODE (0)
118 #define BM_SSP_CTRL1_SSP_MODE (0xf)
119 #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
120 #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
121 #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
122 #define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
123 #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
124 #define BM_SSP_STATUS_CARD_DETECT (1 << 28)
125 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
127 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
129 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
130 BM_SSP_CTRL1_RESP_ERR_IRQ | \
131 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
132 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_CRC_IRQ | \
134 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
135 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
136 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
138 #define SSP_PIO_NUM 3
145 struct mxs_mmc_host
{
146 struct mmc_host
*mmc
;
147 struct mmc_request
*mrq
;
148 struct mmc_command
*cmd
;
149 struct mmc_data
*data
;
154 unsigned int clk_rate
;
156 struct dma_chan
*dmach
;
157 struct mxs_dma_data dma_data
;
158 unsigned int dma_dir
;
159 enum dma_transfer_direction slave_dirn
;
160 u32 ssp_pio_words
[SSP_PIO_NUM
];
162 enum mxs_mmc_id devid
;
163 unsigned char bus_width
;
169 static int mxs_mmc_get_ro(struct mmc_host
*mmc
)
171 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
173 if (!gpio_is_valid(host
->wp_gpio
))
176 return gpio_get_value(host
->wp_gpio
);
179 static int mxs_mmc_get_cd(struct mmc_host
*mmc
)
181 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
183 return !(readl(host
->base
+ HW_SSP_STATUS(host
)) &
184 BM_SSP_STATUS_CARD_DETECT
);
187 static void mxs_mmc_reset(struct mxs_mmc_host
*host
)
191 stmp_reset_block(host
->base
);
193 ctrl0
= BM_SSP_CTRL0_IGNORE_CRC
;
194 ctrl1
= BF_SSP(0x3, CTRL1_SSP_MODE
) |
195 BF_SSP(0x7, CTRL1_WORD_LENGTH
) |
196 BM_SSP_CTRL1_DMA_ENABLE
|
197 BM_SSP_CTRL1_POLARITY
|
198 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN
|
199 BM_SSP_CTRL1_DATA_CRC_IRQ_EN
|
200 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN
|
201 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN
|
202 BM_SSP_CTRL1_RESP_ERR_IRQ_EN
;
204 writel(BF_SSP(0xffff, TIMING_TIMEOUT
) |
205 BF_SSP(2, TIMING_CLOCK_DIVIDE
) |
206 BF_SSP(0, TIMING_CLOCK_RATE
),
207 host
->base
+ HW_SSP_TIMING(host
));
209 if (host
->sdio_irq_en
) {
210 ctrl0
|= BM_SSP_CTRL0_SDIO_IRQ_CHECK
;
211 ctrl1
|= BM_SSP_CTRL1_SDIO_IRQ_EN
;
214 writel(ctrl0
, host
->base
+ HW_SSP_CTRL0
);
215 writel(ctrl1
, host
->base
+ HW_SSP_CTRL1(host
));
218 static void mxs_mmc_start_cmd(struct mxs_mmc_host
*host
,
219 struct mmc_command
*cmd
);
221 static void mxs_mmc_request_done(struct mxs_mmc_host
*host
)
223 struct mmc_command
*cmd
= host
->cmd
;
224 struct mmc_data
*data
= host
->data
;
225 struct mmc_request
*mrq
= host
->mrq
;
227 if (mmc_resp_type(cmd
) & MMC_RSP_PRESENT
) {
228 if (mmc_resp_type(cmd
) & MMC_RSP_136
) {
229 cmd
->resp
[3] = readl(host
->base
+ HW_SSP_SDRESP0(host
));
230 cmd
->resp
[2] = readl(host
->base
+ HW_SSP_SDRESP1(host
));
231 cmd
->resp
[1] = readl(host
->base
+ HW_SSP_SDRESP2(host
));
232 cmd
->resp
[0] = readl(host
->base
+ HW_SSP_SDRESP3(host
));
234 cmd
->resp
[0] = readl(host
->base
+ HW_SSP_SDRESP0(host
));
239 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
240 data
->sg_len
, host
->dma_dir
);
242 * If there was an error on any block, we mark all
243 * data blocks as being in error.
246 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
248 data
->bytes_xfered
= 0;
252 mxs_mmc_start_cmd(host
, mrq
->stop
);
258 mmc_request_done(host
->mmc
, mrq
);
261 static void mxs_mmc_dma_irq_callback(void *param
)
263 struct mxs_mmc_host
*host
= param
;
265 mxs_mmc_request_done(host
);
268 static irqreturn_t
mxs_mmc_irq_handler(int irq
, void *dev_id
)
270 struct mxs_mmc_host
*host
= dev_id
;
271 struct mmc_command
*cmd
= host
->cmd
;
272 struct mmc_data
*data
= host
->data
;
275 spin_lock(&host
->lock
);
277 stat
= readl(host
->base
+ HW_SSP_CTRL1(host
));
278 writel(stat
& MXS_MMC_IRQ_BITS
,
279 host
->base
+ HW_SSP_CTRL1(host
) + STMP_OFFSET_REG_CLR
);
281 if ((stat
& BM_SSP_CTRL1_SDIO_IRQ
) && (stat
& BM_SSP_CTRL1_SDIO_IRQ_EN
))
282 mmc_signal_sdio_irq(host
->mmc
);
284 spin_unlock(&host
->lock
);
286 if (stat
& BM_SSP_CTRL1_RESP_TIMEOUT_IRQ
)
287 cmd
->error
= -ETIMEDOUT
;
288 else if (stat
& BM_SSP_CTRL1_RESP_ERR_IRQ
)
292 if (stat
& (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ
|
293 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ
))
294 data
->error
= -ETIMEDOUT
;
295 else if (stat
& BM_SSP_CTRL1_DATA_CRC_IRQ
)
296 data
->error
= -EILSEQ
;
297 else if (stat
& (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ
|
298 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ
))
305 static struct dma_async_tx_descriptor
*mxs_mmc_prep_dma(
306 struct mxs_mmc_host
*host
, unsigned long flags
)
308 struct dma_async_tx_descriptor
*desc
;
309 struct mmc_data
*data
= host
->data
;
310 struct scatterlist
* sgl
;
315 dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
316 data
->sg_len
, host
->dma_dir
);
318 sg_len
= data
->sg_len
;
321 sgl
= (struct scatterlist
*) host
->ssp_pio_words
;
322 sg_len
= SSP_PIO_NUM
;
325 desc
= dmaengine_prep_slave_sg(host
->dmach
,
326 sgl
, sg_len
, host
->slave_dirn
, flags
);
328 desc
->callback
= mxs_mmc_dma_irq_callback
;
329 desc
->callback_param
= host
;
332 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
333 data
->sg_len
, host
->dma_dir
);
339 static void mxs_mmc_bc(struct mxs_mmc_host
*host
)
341 struct mmc_command
*cmd
= host
->cmd
;
342 struct dma_async_tx_descriptor
*desc
;
343 u32 ctrl0
, cmd0
, cmd1
;
345 ctrl0
= BM_SSP_CTRL0_ENABLE
| BM_SSP_CTRL0_IGNORE_CRC
;
346 cmd0
= BF_SSP(cmd
->opcode
, CMD0_CMD
) | BM_SSP_CMD0_APPEND_8CYC
;
349 if (host
->sdio_irq_en
) {
350 ctrl0
|= BM_SSP_CTRL0_SDIO_IRQ_CHECK
;
351 cmd0
|= BM_SSP_CMD0_CONT_CLKING_EN
| BM_SSP_CMD0_SLOW_CLKING_EN
;
354 host
->ssp_pio_words
[0] = ctrl0
;
355 host
->ssp_pio_words
[1] = cmd0
;
356 host
->ssp_pio_words
[2] = cmd1
;
357 host
->dma_dir
= DMA_NONE
;
358 host
->slave_dirn
= DMA_TRANS_NONE
;
359 desc
= mxs_mmc_prep_dma(host
, DMA_CTRL_ACK
);
363 dmaengine_submit(desc
);
364 dma_async_issue_pending(host
->dmach
);
368 dev_warn(mmc_dev(host
->mmc
),
369 "%s: failed to prep dma\n", __func__
);
372 static void mxs_mmc_ac(struct mxs_mmc_host
*host
)
374 struct mmc_command
*cmd
= host
->cmd
;
375 struct dma_async_tx_descriptor
*desc
;
376 u32 ignore_crc
, get_resp
, long_resp
;
377 u32 ctrl0
, cmd0
, cmd1
;
379 ignore_crc
= (mmc_resp_type(cmd
) & MMC_RSP_CRC
) ?
380 0 : BM_SSP_CTRL0_IGNORE_CRC
;
381 get_resp
= (mmc_resp_type(cmd
) & MMC_RSP_PRESENT
) ?
382 BM_SSP_CTRL0_GET_RESP
: 0;
383 long_resp
= (mmc_resp_type(cmd
) & MMC_RSP_136
) ?
384 BM_SSP_CTRL0_LONG_RESP
: 0;
386 ctrl0
= BM_SSP_CTRL0_ENABLE
| ignore_crc
| get_resp
| long_resp
;
387 cmd0
= BF_SSP(cmd
->opcode
, CMD0_CMD
);
390 if (host
->sdio_irq_en
) {
391 ctrl0
|= BM_SSP_CTRL0_SDIO_IRQ_CHECK
;
392 cmd0
|= BM_SSP_CMD0_CONT_CLKING_EN
| BM_SSP_CMD0_SLOW_CLKING_EN
;
395 host
->ssp_pio_words
[0] = ctrl0
;
396 host
->ssp_pio_words
[1] = cmd0
;
397 host
->ssp_pio_words
[2] = cmd1
;
398 host
->dma_dir
= DMA_NONE
;
399 host
->slave_dirn
= DMA_TRANS_NONE
;
400 desc
= mxs_mmc_prep_dma(host
, DMA_CTRL_ACK
);
404 dmaengine_submit(desc
);
405 dma_async_issue_pending(host
->dmach
);
409 dev_warn(mmc_dev(host
->mmc
),
410 "%s: failed to prep dma\n", __func__
);
413 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate
, unsigned ns
)
415 const unsigned int ssp_timeout_mul
= 4096;
417 * Calculate ticks in ms since ns are large numbers
420 const unsigned int clock_per_ms
= clock_rate
/ 1000;
421 const unsigned int ms
= ns
/ 1000;
422 const unsigned int ticks
= ms
* clock_per_ms
;
423 const unsigned int ssp_ticks
= ticks
/ ssp_timeout_mul
;
425 WARN_ON(ssp_ticks
== 0);
429 static void mxs_mmc_adtc(struct mxs_mmc_host
*host
)
431 struct mmc_command
*cmd
= host
->cmd
;
432 struct mmc_data
*data
= cmd
->data
;
433 struct dma_async_tx_descriptor
*desc
;
434 struct scatterlist
*sgl
= data
->sg
, *sg
;
435 unsigned int sg_len
= data
->sg_len
;
438 unsigned short dma_data_dir
, timeout
;
439 enum dma_transfer_direction slave_dirn
;
440 unsigned int data_size
= 0, log2_blksz
;
441 unsigned int blocks
= data
->blocks
;
443 u32 ignore_crc
, get_resp
, long_resp
, read
;
444 u32 ctrl0
, cmd0
, cmd1
, val
;
446 ignore_crc
= (mmc_resp_type(cmd
) & MMC_RSP_CRC
) ?
447 0 : BM_SSP_CTRL0_IGNORE_CRC
;
448 get_resp
= (mmc_resp_type(cmd
) & MMC_RSP_PRESENT
) ?
449 BM_SSP_CTRL0_GET_RESP
: 0;
450 long_resp
= (mmc_resp_type(cmd
) & MMC_RSP_136
) ?
451 BM_SSP_CTRL0_LONG_RESP
: 0;
453 if (data
->flags
& MMC_DATA_WRITE
) {
454 dma_data_dir
= DMA_TO_DEVICE
;
455 slave_dirn
= DMA_MEM_TO_DEV
;
458 dma_data_dir
= DMA_FROM_DEVICE
;
459 slave_dirn
= DMA_DEV_TO_MEM
;
460 read
= BM_SSP_CTRL0_READ
;
463 ctrl0
= BF_SSP(host
->bus_width
, CTRL0_BUS_WIDTH
) |
464 ignore_crc
| get_resp
| long_resp
|
465 BM_SSP_CTRL0_DATA_XFER
| read
|
466 BM_SSP_CTRL0_WAIT_FOR_IRQ
|
469 cmd0
= BF_SSP(cmd
->opcode
, CMD0_CMD
);
471 /* get logarithm to base 2 of block size for setting register */
472 log2_blksz
= ilog2(data
->blksz
);
475 * take special care of the case that data size from data->sg
476 * is not equal to blocks x blksz
478 for_each_sg(sgl
, sg
, sg_len
, i
)
479 data_size
+= sg
->length
;
481 if (data_size
!= data
->blocks
* data
->blksz
)
484 /* xfer count, block size and count need to be set differently */
485 if (ssp_is_old(host
)) {
486 ctrl0
|= BF_SSP(data_size
, CTRL0_XFER_COUNT
);
487 cmd0
|= BF_SSP(log2_blksz
, CMD0_BLOCK_SIZE
) |
488 BF_SSP(blocks
- 1, CMD0_BLOCK_COUNT
);
490 writel(data_size
, host
->base
+ HW_SSP_XFER_SIZE
);
491 writel(BF_SSP(log2_blksz
, BLOCK_SIZE_BLOCK_SIZE
) |
492 BF_SSP(blocks
- 1, BLOCK_SIZE_BLOCK_COUNT
),
493 host
->base
+ HW_SSP_BLOCK_SIZE
);
496 if ((cmd
->opcode
== MMC_STOP_TRANSMISSION
) ||
497 (cmd
->opcode
== SD_IO_RW_EXTENDED
))
498 cmd0
|= BM_SSP_CMD0_APPEND_8CYC
;
502 if (host
->sdio_irq_en
) {
503 ctrl0
|= BM_SSP_CTRL0_SDIO_IRQ_CHECK
;
504 cmd0
|= BM_SSP_CMD0_CONT_CLKING_EN
| BM_SSP_CMD0_SLOW_CLKING_EN
;
507 /* set the timeout count */
508 timeout
= mxs_ns_to_ssp_ticks(host
->clk_rate
, data
->timeout_ns
);
509 val
= readl(host
->base
+ HW_SSP_TIMING(host
));
510 val
&= ~(BM_SSP_TIMING_TIMEOUT
);
511 val
|= BF_SSP(timeout
, TIMING_TIMEOUT
);
512 writel(val
, host
->base
+ HW_SSP_TIMING(host
));
515 host
->ssp_pio_words
[0] = ctrl0
;
516 host
->ssp_pio_words
[1] = cmd0
;
517 host
->ssp_pio_words
[2] = cmd1
;
518 host
->dma_dir
= DMA_NONE
;
519 host
->slave_dirn
= DMA_TRANS_NONE
;
520 desc
= mxs_mmc_prep_dma(host
, 0);
525 WARN_ON(host
->data
!= NULL
);
527 host
->dma_dir
= dma_data_dir
;
528 host
->slave_dirn
= slave_dirn
;
529 desc
= mxs_mmc_prep_dma(host
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
533 dmaengine_submit(desc
);
534 dma_async_issue_pending(host
->dmach
);
537 dev_warn(mmc_dev(host
->mmc
),
538 "%s: failed to prep dma\n", __func__
);
541 static void mxs_mmc_start_cmd(struct mxs_mmc_host
*host
,
542 struct mmc_command
*cmd
)
546 switch (mmc_cmd_type(cmd
)) {
560 dev_warn(mmc_dev(host
->mmc
),
561 "%s: unknown MMC command\n", __func__
);
566 static void mxs_mmc_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
568 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
570 WARN_ON(host
->mrq
!= NULL
);
572 mxs_mmc_start_cmd(host
, mrq
->cmd
);
575 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host
*host
, unsigned int rate
)
577 unsigned int ssp_clk
, ssp_sck
;
578 u32 clock_divide
, clock_rate
;
581 ssp_clk
= clk_get_rate(host
->clk
);
583 for (clock_divide
= 2; clock_divide
<= 254; clock_divide
+= 2) {
584 clock_rate
= DIV_ROUND_UP(ssp_clk
, rate
* clock_divide
);
585 clock_rate
= (clock_rate
> 0) ? clock_rate
- 1 : 0;
586 if (clock_rate
<= 255)
590 if (clock_divide
> 254) {
591 dev_err(mmc_dev(host
->mmc
),
592 "%s: cannot set clock to %d\n", __func__
, rate
);
596 ssp_sck
= ssp_clk
/ clock_divide
/ (1 + clock_rate
);
598 val
= readl(host
->base
+ HW_SSP_TIMING(host
));
599 val
&= ~(BM_SSP_TIMING_CLOCK_DIVIDE
| BM_SSP_TIMING_CLOCK_RATE
);
600 val
|= BF_SSP(clock_divide
, TIMING_CLOCK_DIVIDE
);
601 val
|= BF_SSP(clock_rate
, TIMING_CLOCK_RATE
);
602 writel(val
, host
->base
+ HW_SSP_TIMING(host
));
604 host
->clk_rate
= ssp_sck
;
606 dev_dbg(mmc_dev(host
->mmc
),
607 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
608 __func__
, clock_divide
, clock_rate
, ssp_clk
, ssp_sck
, rate
);
611 static void mxs_mmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
613 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
615 if (ios
->bus_width
== MMC_BUS_WIDTH_8
)
617 else if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
623 mxs_mmc_set_clk_rate(host
, ios
->clock
);
626 static void mxs_mmc_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
628 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
631 spin_lock_irqsave(&host
->lock
, flags
);
633 host
->sdio_irq_en
= enable
;
636 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK
,
637 host
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_SET
);
638 writel(BM_SSP_CTRL1_SDIO_IRQ_EN
,
639 host
->base
+ HW_SSP_CTRL1(host
) + STMP_OFFSET_REG_SET
);
641 if (readl(host
->base
+ HW_SSP_STATUS(host
)) &
642 BM_SSP_STATUS_SDIO_IRQ
)
643 mmc_signal_sdio_irq(host
->mmc
);
646 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK
,
647 host
->base
+ HW_SSP_CTRL0
+ STMP_OFFSET_REG_CLR
);
648 writel(BM_SSP_CTRL1_SDIO_IRQ_EN
,
649 host
->base
+ HW_SSP_CTRL1(host
) + STMP_OFFSET_REG_CLR
);
652 spin_unlock_irqrestore(&host
->lock
, flags
);
655 static const struct mmc_host_ops mxs_mmc_ops
= {
656 .request
= mxs_mmc_request
,
657 .get_ro
= mxs_mmc_get_ro
,
658 .get_cd
= mxs_mmc_get_cd
,
659 .set_ios
= mxs_mmc_set_ios
,
660 .enable_sdio_irq
= mxs_mmc_enable_sdio_irq
,
663 static bool mxs_mmc_dma_filter(struct dma_chan
*chan
, void *param
)
665 struct mxs_mmc_host
*host
= param
;
667 if (!mxs_dma_is_apbh(chan
))
670 if (chan
->chan_id
!= host
->dma_channel
)
673 chan
->private = &host
->dma_data
;
678 static struct platform_device_id mxs_mmc_ids
[] = {
681 .driver_data
= IMX23_MMC
,
684 .driver_data
= IMX28_MMC
,
689 MODULE_DEVICE_TABLE(platform
, mxs_mmc_ids
);
691 static const struct of_device_id mxs_mmc_dt_ids
[] = {
692 { .compatible
= "fsl,imx23-mmc", .data
= (void *) IMX23_MMC
, },
693 { .compatible
= "fsl,imx28-mmc", .data
= (void *) IMX28_MMC
, },
696 MODULE_DEVICE_TABLE(of
, mxs_mmc_dt_ids
);
698 static int mxs_mmc_probe(struct platform_device
*pdev
)
700 const struct of_device_id
*of_id
=
701 of_match_device(mxs_mmc_dt_ids
, &pdev
->dev
);
702 struct device_node
*np
= pdev
->dev
.of_node
;
703 struct mxs_mmc_host
*host
;
704 struct mmc_host
*mmc
;
705 struct resource
*iores
, *dmares
;
706 struct mxs_mmc_platform_data
*pdata
;
707 struct pinctrl
*pinctrl
;
708 int ret
= 0, irq_err
, irq_dma
;
711 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
712 dmares
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
713 irq_err
= platform_get_irq(pdev
, 0);
714 irq_dma
= platform_get_irq(pdev
, 1);
715 if (!iores
|| irq_err
< 0 || irq_dma
< 0)
718 mmc
= mmc_alloc_host(sizeof(struct mxs_mmc_host
), &pdev
->dev
);
722 host
= mmc_priv(mmc
);
723 host
->base
= devm_request_and_ioremap(&pdev
->dev
, iores
);
725 ret
= -EADDRNOTAVAIL
;
730 host
->devid
= (enum mxs_mmc_id
) of_id
->data
;
732 * TODO: This is a temporary solution and should be changed
733 * to use generic DMA binding later when the helpers get in.
735 ret
= of_property_read_u32(np
, "fsl,ssp-dma-channel",
738 dev_err(mmc_dev(host
->mmc
),
739 "failed to get dma channel\n");
743 host
->devid
= pdev
->id_entry
->driver_data
;
744 host
->dma_channel
= dmares
->start
;
748 host
->sdio_irq_en
= 0;
750 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
751 if (IS_ERR(pinctrl
)) {
752 ret
= PTR_ERR(pinctrl
);
756 host
->clk
= clk_get(&pdev
->dev
, NULL
);
757 if (IS_ERR(host
->clk
)) {
758 ret
= PTR_ERR(host
->clk
);
761 clk_prepare_enable(host
->clk
);
766 dma_cap_set(DMA_SLAVE
, mask
);
767 host
->dma_data
.chan_irq
= irq_dma
;
768 host
->dmach
= dma_request_channel(mask
, mxs_mmc_dma_filter
, host
);
770 dev_err(mmc_dev(host
->mmc
),
771 "%s: failed to request dma\n", __func__
);
775 /* set mmc core parameters */
776 mmc
->ops
= &mxs_mmc_ops
;
777 mmc
->caps
= MMC_CAP_SD_HIGHSPEED
| MMC_CAP_MMC_HIGHSPEED
|
778 MMC_CAP_SDIO_IRQ
| MMC_CAP_NEEDS_POLL
;
780 pdata
= mmc_dev(host
->mmc
)->platform_data
;
783 of_property_read_u32(np
, "bus-width", &bus_width
);
785 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
786 else if (bus_width
== 8)
787 mmc
->caps
|= MMC_CAP_4_BIT_DATA
| MMC_CAP_8_BIT_DATA
;
788 host
->wp_gpio
= of_get_named_gpio(np
, "wp-gpios", 0);
790 if (pdata
->flags
& SLOTF_8_BIT_CAPABLE
)
791 mmc
->caps
|= MMC_CAP_4_BIT_DATA
| MMC_CAP_8_BIT_DATA
;
792 if (pdata
->flags
& SLOTF_4_BIT_CAPABLE
)
793 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
794 host
->wp_gpio
= pdata
->wp_gpio
;
798 mmc
->f_max
= 288000000;
799 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
802 mmc
->max_blk_size
= 1 << 0xf;
803 mmc
->max_blk_count
= (ssp_is_old(host
)) ? 0xff : 0xffffff;
804 mmc
->max_req_size
= (ssp_is_old(host
)) ? 0xffff : 0xffffffff;
805 mmc
->max_seg_size
= dma_get_max_seg_size(host
->dmach
->device
->dev
);
807 platform_set_drvdata(pdev
, mmc
);
809 ret
= devm_request_irq(&pdev
->dev
, irq_err
, mxs_mmc_irq_handler
, 0,
814 spin_lock_init(&host
->lock
);
816 ret
= mmc_add_host(mmc
);
820 dev_info(mmc_dev(host
->mmc
), "initialized\n");
826 dma_release_channel(host
->dmach
);
828 clk_disable_unprepare(host
->clk
);
835 static int mxs_mmc_remove(struct platform_device
*pdev
)
837 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
838 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
840 mmc_remove_host(mmc
);
842 platform_set_drvdata(pdev
, NULL
);
845 dma_release_channel(host
->dmach
);
847 clk_disable_unprepare(host
->clk
);
856 static int mxs_mmc_suspend(struct device
*dev
)
858 struct mmc_host
*mmc
= dev_get_drvdata(dev
);
859 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
862 ret
= mmc_suspend_host(mmc
);
864 clk_disable_unprepare(host
->clk
);
869 static int mxs_mmc_resume(struct device
*dev
)
871 struct mmc_host
*mmc
= dev_get_drvdata(dev
);
872 struct mxs_mmc_host
*host
= mmc_priv(mmc
);
875 clk_prepare_enable(host
->clk
);
877 ret
= mmc_resume_host(mmc
);
882 static const struct dev_pm_ops mxs_mmc_pm_ops
= {
883 .suspend
= mxs_mmc_suspend
,
884 .resume
= mxs_mmc_resume
,
888 static struct platform_driver mxs_mmc_driver
= {
889 .probe
= mxs_mmc_probe
,
890 .remove
= mxs_mmc_remove
,
891 .id_table
= mxs_mmc_ids
,
894 .owner
= THIS_MODULE
,
896 .pm
= &mxs_mmc_pm_ops
,
897 .of_match_table
= mxs_mmc_dt_ids
,
902 module_platform_driver(mxs_mmc_driver
);
904 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
905 MODULE_AUTHOR("Freescale Semiconductor");
906 MODULE_LICENSE("GPL");