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Merge branch 'for-airlied' of git://people.freedesktop.org/~danvet/drm-intel into...
[deliverable/linux.git] / drivers / mmc / host / mxs-mmc.c
1 /*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/of_gpio.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/interrupt.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dmaengine.h>
34 #include <linux/highmem.h>
35 #include <linux/clk.h>
36 #include <linux/err.h>
37 #include <linux/completion.h>
38 #include <linux/mmc/host.h>
39 #include <linux/mmc/mmc.h>
40 #include <linux/mmc/sdio.h>
41 #include <linux/gpio.h>
42 #include <linux/regulator/consumer.h>
43 #include <linux/module.h>
44 #include <linux/fsl/mxs-dma.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/stmp_device.h>
47 #include <linux/mmc/mxs-mmc.h>
48
49 #define DRIVER_NAME "mxs-mmc"
50
51 /* card detect polling timeout */
52 #define MXS_MMC_DETECT_TIMEOUT (HZ/2)
53
54 #define ssp_is_old(host) ((host)->devid == IMX23_MMC)
55
56 /* SSP registers */
57 #define HW_SSP_CTRL0 0x000
58 #define BM_SSP_CTRL0_RUN (1 << 29)
59 #define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
60 #define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
61 #define BM_SSP_CTRL0_READ (1 << 25)
62 #define BM_SSP_CTRL0_DATA_XFER (1 << 24)
63 #define BP_SSP_CTRL0_BUS_WIDTH (22)
64 #define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
65 #define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
66 #define BM_SSP_CTRL0_LONG_RESP (1 << 19)
67 #define BM_SSP_CTRL0_GET_RESP (1 << 17)
68 #define BM_SSP_CTRL0_ENABLE (1 << 16)
69 #define BP_SSP_CTRL0_XFER_COUNT (0)
70 #define BM_SSP_CTRL0_XFER_COUNT (0xffff)
71 #define HW_SSP_CMD0 0x010
72 #define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
73 #define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
74 #define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
75 #define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
76 #define BP_SSP_CMD0_BLOCK_SIZE (16)
77 #define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
78 #define BP_SSP_CMD0_BLOCK_COUNT (8)
79 #define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
80 #define BP_SSP_CMD0_CMD (0)
81 #define BM_SSP_CMD0_CMD (0xff)
82 #define HW_SSP_CMD1 0x020
83 #define HW_SSP_XFER_SIZE 0x030
84 #define HW_SSP_BLOCK_SIZE 0x040
85 #define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
86 #define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
87 #define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
88 #define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
89 #define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
90 #define BP_SSP_TIMING_TIMEOUT (16)
91 #define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
92 #define BP_SSP_TIMING_CLOCK_DIVIDE (8)
93 #define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
94 #define BP_SSP_TIMING_CLOCK_RATE (0)
95 #define BM_SSP_TIMING_CLOCK_RATE (0xff)
96 #define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
97 #define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
98 #define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
99 #define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
100 #define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
101 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
102 #define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
103 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
104 #define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
105 #define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
106 #define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
107 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
108 #define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
109 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
110 #define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
111 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
112 #define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
113 #define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
114 #define BM_SSP_CTRL1_POLARITY (1 << 9)
115 #define BP_SSP_CTRL1_WORD_LENGTH (4)
116 #define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
117 #define BP_SSP_CTRL1_SSP_MODE (0)
118 #define BM_SSP_CTRL1_SSP_MODE (0xf)
119 #define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
120 #define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
121 #define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
122 #define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
123 #define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
124 #define BM_SSP_STATUS_CARD_DETECT (1 << 28)
125 #define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
126
127 #define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
128
129 #define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
130 BM_SSP_CTRL1_RESP_ERR_IRQ | \
131 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
132 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_CRC_IRQ | \
134 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
135 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
136 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
137
138 #define SSP_PIO_NUM 3
139
140 enum mxs_mmc_id {
141 IMX23_MMC,
142 IMX28_MMC,
143 };
144
145 struct mxs_mmc_host {
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150
151 void __iomem *base;
152 int dma_channel;
153 struct clk *clk;
154 unsigned int clk_rate;
155
156 struct dma_chan *dmach;
157 struct mxs_dma_data dma_data;
158 unsigned int dma_dir;
159 enum dma_transfer_direction slave_dirn;
160 u32 ssp_pio_words[SSP_PIO_NUM];
161
162 enum mxs_mmc_id devid;
163 unsigned char bus_width;
164 spinlock_t lock;
165 int sdio_irq_en;
166 int wp_gpio;
167 bool wp_inverted;
168 };
169
170 static int mxs_mmc_get_ro(struct mmc_host *mmc)
171 {
172 struct mxs_mmc_host *host = mmc_priv(mmc);
173 int ret;
174
175 if (!gpio_is_valid(host->wp_gpio))
176 return -EINVAL;
177
178 ret = gpio_get_value(host->wp_gpio);
179
180 if (host->wp_inverted)
181 ret = !ret;
182
183 return ret;
184 }
185
186 static int mxs_mmc_get_cd(struct mmc_host *mmc)
187 {
188 struct mxs_mmc_host *host = mmc_priv(mmc);
189
190 return !(readl(host->base + HW_SSP_STATUS(host)) &
191 BM_SSP_STATUS_CARD_DETECT);
192 }
193
194 static void mxs_mmc_reset(struct mxs_mmc_host *host)
195 {
196 u32 ctrl0, ctrl1;
197
198 stmp_reset_block(host->base);
199
200 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
201 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
202 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
203 BM_SSP_CTRL1_DMA_ENABLE |
204 BM_SSP_CTRL1_POLARITY |
205 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
206 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
207 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
208 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
209 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
210
211 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
212 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
213 BF_SSP(0, TIMING_CLOCK_RATE),
214 host->base + HW_SSP_TIMING(host));
215
216 if (host->sdio_irq_en) {
217 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
218 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
219 }
220
221 writel(ctrl0, host->base + HW_SSP_CTRL0);
222 writel(ctrl1, host->base + HW_SSP_CTRL1(host));
223 }
224
225 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
226 struct mmc_command *cmd);
227
228 static void mxs_mmc_request_done(struct mxs_mmc_host *host)
229 {
230 struct mmc_command *cmd = host->cmd;
231 struct mmc_data *data = host->data;
232 struct mmc_request *mrq = host->mrq;
233
234 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
235 if (mmc_resp_type(cmd) & MMC_RSP_136) {
236 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
237 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
238 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
239 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
240 } else {
241 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
242 }
243 }
244
245 if (data) {
246 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
247 data->sg_len, host->dma_dir);
248 /*
249 * If there was an error on any block, we mark all
250 * data blocks as being in error.
251 */
252 if (!data->error)
253 data->bytes_xfered = data->blocks * data->blksz;
254 else
255 data->bytes_xfered = 0;
256
257 host->data = NULL;
258 if (mrq->stop) {
259 mxs_mmc_start_cmd(host, mrq->stop);
260 return;
261 }
262 }
263
264 host->mrq = NULL;
265 mmc_request_done(host->mmc, mrq);
266 }
267
268 static void mxs_mmc_dma_irq_callback(void *param)
269 {
270 struct mxs_mmc_host *host = param;
271
272 mxs_mmc_request_done(host);
273 }
274
275 static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
276 {
277 struct mxs_mmc_host *host = dev_id;
278 struct mmc_command *cmd = host->cmd;
279 struct mmc_data *data = host->data;
280 u32 stat;
281
282 spin_lock(&host->lock);
283
284 stat = readl(host->base + HW_SSP_CTRL1(host));
285 writel(stat & MXS_MMC_IRQ_BITS,
286 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
287
288 spin_unlock(&host->lock);
289
290 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
291 mmc_signal_sdio_irq(host->mmc);
292
293 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
294 cmd->error = -ETIMEDOUT;
295 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
296 cmd->error = -EIO;
297
298 if (data) {
299 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
300 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
301 data->error = -ETIMEDOUT;
302 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
303 data->error = -EILSEQ;
304 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
305 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
306 data->error = -EIO;
307 }
308
309 return IRQ_HANDLED;
310 }
311
312 static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
313 struct mxs_mmc_host *host, unsigned long flags)
314 {
315 struct dma_async_tx_descriptor *desc;
316 struct mmc_data *data = host->data;
317 struct scatterlist * sgl;
318 unsigned int sg_len;
319
320 if (data) {
321 /* data */
322 dma_map_sg(mmc_dev(host->mmc), data->sg,
323 data->sg_len, host->dma_dir);
324 sgl = data->sg;
325 sg_len = data->sg_len;
326 } else {
327 /* pio */
328 sgl = (struct scatterlist *) host->ssp_pio_words;
329 sg_len = SSP_PIO_NUM;
330 }
331
332 desc = dmaengine_prep_slave_sg(host->dmach,
333 sgl, sg_len, host->slave_dirn, flags);
334 if (desc) {
335 desc->callback = mxs_mmc_dma_irq_callback;
336 desc->callback_param = host;
337 } else {
338 if (data)
339 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
340 data->sg_len, host->dma_dir);
341 }
342
343 return desc;
344 }
345
346 static void mxs_mmc_bc(struct mxs_mmc_host *host)
347 {
348 struct mmc_command *cmd = host->cmd;
349 struct dma_async_tx_descriptor *desc;
350 u32 ctrl0, cmd0, cmd1;
351
352 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
353 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
354 cmd1 = cmd->arg;
355
356 if (host->sdio_irq_en) {
357 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
358 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
359 }
360
361 host->ssp_pio_words[0] = ctrl0;
362 host->ssp_pio_words[1] = cmd0;
363 host->ssp_pio_words[2] = cmd1;
364 host->dma_dir = DMA_NONE;
365 host->slave_dirn = DMA_TRANS_NONE;
366 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
367 if (!desc)
368 goto out;
369
370 dmaengine_submit(desc);
371 dma_async_issue_pending(host->dmach);
372 return;
373
374 out:
375 dev_warn(mmc_dev(host->mmc),
376 "%s: failed to prep dma\n", __func__);
377 }
378
379 static void mxs_mmc_ac(struct mxs_mmc_host *host)
380 {
381 struct mmc_command *cmd = host->cmd;
382 struct dma_async_tx_descriptor *desc;
383 u32 ignore_crc, get_resp, long_resp;
384 u32 ctrl0, cmd0, cmd1;
385
386 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
387 0 : BM_SSP_CTRL0_IGNORE_CRC;
388 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
389 BM_SSP_CTRL0_GET_RESP : 0;
390 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
391 BM_SSP_CTRL0_LONG_RESP : 0;
392
393 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
394 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
395 cmd1 = cmd->arg;
396
397 if (host->sdio_irq_en) {
398 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
399 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
400 }
401
402 host->ssp_pio_words[0] = ctrl0;
403 host->ssp_pio_words[1] = cmd0;
404 host->ssp_pio_words[2] = cmd1;
405 host->dma_dir = DMA_NONE;
406 host->slave_dirn = DMA_TRANS_NONE;
407 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
408 if (!desc)
409 goto out;
410
411 dmaengine_submit(desc);
412 dma_async_issue_pending(host->dmach);
413 return;
414
415 out:
416 dev_warn(mmc_dev(host->mmc),
417 "%s: failed to prep dma\n", __func__);
418 }
419
420 static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
421 {
422 const unsigned int ssp_timeout_mul = 4096;
423 /*
424 * Calculate ticks in ms since ns are large numbers
425 * and might overflow
426 */
427 const unsigned int clock_per_ms = clock_rate / 1000;
428 const unsigned int ms = ns / 1000;
429 const unsigned int ticks = ms * clock_per_ms;
430 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
431
432 WARN_ON(ssp_ticks == 0);
433 return ssp_ticks;
434 }
435
436 static void mxs_mmc_adtc(struct mxs_mmc_host *host)
437 {
438 struct mmc_command *cmd = host->cmd;
439 struct mmc_data *data = cmd->data;
440 struct dma_async_tx_descriptor *desc;
441 struct scatterlist *sgl = data->sg, *sg;
442 unsigned int sg_len = data->sg_len;
443 int i;
444
445 unsigned short dma_data_dir, timeout;
446 enum dma_transfer_direction slave_dirn;
447 unsigned int data_size = 0, log2_blksz;
448 unsigned int blocks = data->blocks;
449
450 u32 ignore_crc, get_resp, long_resp, read;
451 u32 ctrl0, cmd0, cmd1, val;
452
453 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
454 0 : BM_SSP_CTRL0_IGNORE_CRC;
455 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
456 BM_SSP_CTRL0_GET_RESP : 0;
457 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
458 BM_SSP_CTRL0_LONG_RESP : 0;
459
460 if (data->flags & MMC_DATA_WRITE) {
461 dma_data_dir = DMA_TO_DEVICE;
462 slave_dirn = DMA_MEM_TO_DEV;
463 read = 0;
464 } else {
465 dma_data_dir = DMA_FROM_DEVICE;
466 slave_dirn = DMA_DEV_TO_MEM;
467 read = BM_SSP_CTRL0_READ;
468 }
469
470 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
471 ignore_crc | get_resp | long_resp |
472 BM_SSP_CTRL0_DATA_XFER | read |
473 BM_SSP_CTRL0_WAIT_FOR_IRQ |
474 BM_SSP_CTRL0_ENABLE;
475
476 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
477
478 /* get logarithm to base 2 of block size for setting register */
479 log2_blksz = ilog2(data->blksz);
480
481 /*
482 * take special care of the case that data size from data->sg
483 * is not equal to blocks x blksz
484 */
485 for_each_sg(sgl, sg, sg_len, i)
486 data_size += sg->length;
487
488 if (data_size != data->blocks * data->blksz)
489 blocks = 1;
490
491 /* xfer count, block size and count need to be set differently */
492 if (ssp_is_old(host)) {
493 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
494 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
495 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
496 } else {
497 writel(data_size, host->base + HW_SSP_XFER_SIZE);
498 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
499 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
500 host->base + HW_SSP_BLOCK_SIZE);
501 }
502
503 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
504 (cmd->opcode == SD_IO_RW_EXTENDED))
505 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
506
507 cmd1 = cmd->arg;
508
509 if (host->sdio_irq_en) {
510 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
511 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
512 }
513
514 /* set the timeout count */
515 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
516 val = readl(host->base + HW_SSP_TIMING(host));
517 val &= ~(BM_SSP_TIMING_TIMEOUT);
518 val |= BF_SSP(timeout, TIMING_TIMEOUT);
519 writel(val, host->base + HW_SSP_TIMING(host));
520
521 /* pio */
522 host->ssp_pio_words[0] = ctrl0;
523 host->ssp_pio_words[1] = cmd0;
524 host->ssp_pio_words[2] = cmd1;
525 host->dma_dir = DMA_NONE;
526 host->slave_dirn = DMA_TRANS_NONE;
527 desc = mxs_mmc_prep_dma(host, 0);
528 if (!desc)
529 goto out;
530
531 /* append data sg */
532 WARN_ON(host->data != NULL);
533 host->data = data;
534 host->dma_dir = dma_data_dir;
535 host->slave_dirn = slave_dirn;
536 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
537 if (!desc)
538 goto out;
539
540 dmaengine_submit(desc);
541 dma_async_issue_pending(host->dmach);
542 return;
543 out:
544 dev_warn(mmc_dev(host->mmc),
545 "%s: failed to prep dma\n", __func__);
546 }
547
548 static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
549 struct mmc_command *cmd)
550 {
551 host->cmd = cmd;
552
553 switch (mmc_cmd_type(cmd)) {
554 case MMC_CMD_BC:
555 mxs_mmc_bc(host);
556 break;
557 case MMC_CMD_BCR:
558 mxs_mmc_ac(host);
559 break;
560 case MMC_CMD_AC:
561 mxs_mmc_ac(host);
562 break;
563 case MMC_CMD_ADTC:
564 mxs_mmc_adtc(host);
565 break;
566 default:
567 dev_warn(mmc_dev(host->mmc),
568 "%s: unknown MMC command\n", __func__);
569 break;
570 }
571 }
572
573 static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
574 {
575 struct mxs_mmc_host *host = mmc_priv(mmc);
576
577 WARN_ON(host->mrq != NULL);
578 host->mrq = mrq;
579 mxs_mmc_start_cmd(host, mrq->cmd);
580 }
581
582 static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
583 {
584 unsigned int ssp_clk, ssp_sck;
585 u32 clock_divide, clock_rate;
586 u32 val;
587
588 ssp_clk = clk_get_rate(host->clk);
589
590 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
591 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
592 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
593 if (clock_rate <= 255)
594 break;
595 }
596
597 if (clock_divide > 254) {
598 dev_err(mmc_dev(host->mmc),
599 "%s: cannot set clock to %d\n", __func__, rate);
600 return;
601 }
602
603 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
604
605 val = readl(host->base + HW_SSP_TIMING(host));
606 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
607 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
608 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
609 writel(val, host->base + HW_SSP_TIMING(host));
610
611 host->clk_rate = ssp_sck;
612
613 dev_dbg(mmc_dev(host->mmc),
614 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
615 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
616 }
617
618 static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
619 {
620 struct mxs_mmc_host *host = mmc_priv(mmc);
621
622 if (ios->bus_width == MMC_BUS_WIDTH_8)
623 host->bus_width = 2;
624 else if (ios->bus_width == MMC_BUS_WIDTH_4)
625 host->bus_width = 1;
626 else
627 host->bus_width = 0;
628
629 if (ios->clock)
630 mxs_mmc_set_clk_rate(host, ios->clock);
631 }
632
633 static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
634 {
635 struct mxs_mmc_host *host = mmc_priv(mmc);
636 unsigned long flags;
637
638 spin_lock_irqsave(&host->lock, flags);
639
640 host->sdio_irq_en = enable;
641
642 if (enable) {
643 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
644 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
645 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
646 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
647 } else {
648 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
649 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
650 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
651 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
652 }
653
654 spin_unlock_irqrestore(&host->lock, flags);
655
656 if (enable && readl(host->base + HW_SSP_STATUS(host)) &
657 BM_SSP_STATUS_SDIO_IRQ)
658 mmc_signal_sdio_irq(host->mmc);
659
660 }
661
662 static const struct mmc_host_ops mxs_mmc_ops = {
663 .request = mxs_mmc_request,
664 .get_ro = mxs_mmc_get_ro,
665 .get_cd = mxs_mmc_get_cd,
666 .set_ios = mxs_mmc_set_ios,
667 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
668 };
669
670 static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
671 {
672 struct mxs_mmc_host *host = param;
673
674 if (!mxs_dma_is_apbh(chan))
675 return false;
676
677 if (chan->chan_id != host->dma_channel)
678 return false;
679
680 chan->private = &host->dma_data;
681
682 return true;
683 }
684
685 static struct platform_device_id mxs_mmc_ids[] = {
686 {
687 .name = "imx23-mmc",
688 .driver_data = IMX23_MMC,
689 }, {
690 .name = "imx28-mmc",
691 .driver_data = IMX28_MMC,
692 }, {
693 /* sentinel */
694 }
695 };
696 MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
697
698 static const struct of_device_id mxs_mmc_dt_ids[] = {
699 { .compatible = "fsl,imx23-mmc", .data = (void *) IMX23_MMC, },
700 { .compatible = "fsl,imx28-mmc", .data = (void *) IMX28_MMC, },
701 { /* sentinel */ }
702 };
703 MODULE_DEVICE_TABLE(of, mxs_mmc_dt_ids);
704
705 static int mxs_mmc_probe(struct platform_device *pdev)
706 {
707 const struct of_device_id *of_id =
708 of_match_device(mxs_mmc_dt_ids, &pdev->dev);
709 struct device_node *np = pdev->dev.of_node;
710 struct mxs_mmc_host *host;
711 struct mmc_host *mmc;
712 struct resource *iores, *dmares;
713 struct mxs_mmc_platform_data *pdata;
714 struct pinctrl *pinctrl;
715 int ret = 0, irq_err, irq_dma;
716 dma_cap_mask_t mask;
717 struct regulator *reg_vmmc;
718 enum of_gpio_flags flags;
719
720 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
721 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
722 irq_err = platform_get_irq(pdev, 0);
723 irq_dma = platform_get_irq(pdev, 1);
724 if (!iores || irq_err < 0 || irq_dma < 0)
725 return -EINVAL;
726
727 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
728 if (!mmc)
729 return -ENOMEM;
730
731 host = mmc_priv(mmc);
732 host->base = devm_request_and_ioremap(&pdev->dev, iores);
733 if (!host->base) {
734 ret = -EADDRNOTAVAIL;
735 goto out_mmc_free;
736 }
737
738 if (np) {
739 host->devid = (enum mxs_mmc_id) of_id->data;
740 /*
741 * TODO: This is a temporary solution and should be changed
742 * to use generic DMA binding later when the helpers get in.
743 */
744 ret = of_property_read_u32(np, "fsl,ssp-dma-channel",
745 &host->dma_channel);
746 if (ret) {
747 dev_err(mmc_dev(host->mmc),
748 "failed to get dma channel\n");
749 goto out_mmc_free;
750 }
751 } else {
752 host->devid = pdev->id_entry->driver_data;
753 host->dma_channel = dmares->start;
754 }
755
756 host->mmc = mmc;
757 host->sdio_irq_en = 0;
758
759 reg_vmmc = devm_regulator_get(&pdev->dev, "vmmc");
760 if (!IS_ERR(reg_vmmc)) {
761 ret = regulator_enable(reg_vmmc);
762 if (ret) {
763 dev_err(&pdev->dev,
764 "Failed to enable vmmc regulator: %d\n", ret);
765 goto out_mmc_free;
766 }
767 }
768
769 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
770 if (IS_ERR(pinctrl)) {
771 ret = PTR_ERR(pinctrl);
772 goto out_mmc_free;
773 }
774
775 host->clk = clk_get(&pdev->dev, NULL);
776 if (IS_ERR(host->clk)) {
777 ret = PTR_ERR(host->clk);
778 goto out_mmc_free;
779 }
780 clk_prepare_enable(host->clk);
781
782 mxs_mmc_reset(host);
783
784 dma_cap_zero(mask);
785 dma_cap_set(DMA_SLAVE, mask);
786 host->dma_data.chan_irq = irq_dma;
787 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
788 if (!host->dmach) {
789 dev_err(mmc_dev(host->mmc),
790 "%s: failed to request dma\n", __func__);
791 goto out_clk_put;
792 }
793
794 /* set mmc core parameters */
795 mmc->ops = &mxs_mmc_ops;
796 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
797 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
798
799 pdata = mmc_dev(host->mmc)->platform_data;
800 if (!pdata) {
801 u32 bus_width = 0;
802 of_property_read_u32(np, "bus-width", &bus_width);
803 if (bus_width == 4)
804 mmc->caps |= MMC_CAP_4_BIT_DATA;
805 else if (bus_width == 8)
806 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
807 host->wp_gpio = of_get_named_gpio_flags(np, "wp-gpios", 0,
808 &flags);
809 if (flags & OF_GPIO_ACTIVE_LOW)
810 host->wp_inverted = 1;
811 } else {
812 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
813 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
814 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
815 mmc->caps |= MMC_CAP_4_BIT_DATA;
816 host->wp_gpio = pdata->wp_gpio;
817 }
818
819 mmc->f_min = 400000;
820 mmc->f_max = 288000000;
821 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
822
823 mmc->max_segs = 52;
824 mmc->max_blk_size = 1 << 0xf;
825 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
826 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
827 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
828
829 platform_set_drvdata(pdev, mmc);
830
831 ret = devm_request_irq(&pdev->dev, irq_err, mxs_mmc_irq_handler, 0,
832 DRIVER_NAME, host);
833 if (ret)
834 goto out_free_dma;
835
836 spin_lock_init(&host->lock);
837
838 ret = mmc_add_host(mmc);
839 if (ret)
840 goto out_free_dma;
841
842 dev_info(mmc_dev(host->mmc), "initialized\n");
843
844 return 0;
845
846 out_free_dma:
847 if (host->dmach)
848 dma_release_channel(host->dmach);
849 out_clk_put:
850 clk_disable_unprepare(host->clk);
851 clk_put(host->clk);
852 out_mmc_free:
853 mmc_free_host(mmc);
854 return ret;
855 }
856
857 static int mxs_mmc_remove(struct platform_device *pdev)
858 {
859 struct mmc_host *mmc = platform_get_drvdata(pdev);
860 struct mxs_mmc_host *host = mmc_priv(mmc);
861
862 mmc_remove_host(mmc);
863
864 platform_set_drvdata(pdev, NULL);
865
866 if (host->dmach)
867 dma_release_channel(host->dmach);
868
869 clk_disable_unprepare(host->clk);
870 clk_put(host->clk);
871
872 mmc_free_host(mmc);
873
874 return 0;
875 }
876
877 #ifdef CONFIG_PM
878 static int mxs_mmc_suspend(struct device *dev)
879 {
880 struct mmc_host *mmc = dev_get_drvdata(dev);
881 struct mxs_mmc_host *host = mmc_priv(mmc);
882 int ret = 0;
883
884 ret = mmc_suspend_host(mmc);
885
886 clk_disable_unprepare(host->clk);
887
888 return ret;
889 }
890
891 static int mxs_mmc_resume(struct device *dev)
892 {
893 struct mmc_host *mmc = dev_get_drvdata(dev);
894 struct mxs_mmc_host *host = mmc_priv(mmc);
895 int ret = 0;
896
897 clk_prepare_enable(host->clk);
898
899 ret = mmc_resume_host(mmc);
900
901 return ret;
902 }
903
904 static const struct dev_pm_ops mxs_mmc_pm_ops = {
905 .suspend = mxs_mmc_suspend,
906 .resume = mxs_mmc_resume,
907 };
908 #endif
909
910 static struct platform_driver mxs_mmc_driver = {
911 .probe = mxs_mmc_probe,
912 .remove = mxs_mmc_remove,
913 .id_table = mxs_mmc_ids,
914 .driver = {
915 .name = DRIVER_NAME,
916 .owner = THIS_MODULE,
917 #ifdef CONFIG_PM
918 .pm = &mxs_mmc_pm_ops,
919 #endif
920 .of_match_table = mxs_mmc_dt_ids,
921 },
922 };
923
924 module_platform_driver(mxs_mmc_driver);
925
926 MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
927 MODULE_AUTHOR("Freescale Semiconductor");
928 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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