2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/omap-dma.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
42 #include <plat/board.h>
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSSTATUS 0x0014
48 #define OMAP_HSMMC_CON 0x002C
49 #define OMAP_HSMMC_BLK 0x0104
50 #define OMAP_HSMMC_ARG 0x0108
51 #define OMAP_HSMMC_CMD 0x010C
52 #define OMAP_HSMMC_RSP10 0x0110
53 #define OMAP_HSMMC_RSP32 0x0114
54 #define OMAP_HSMMC_RSP54 0x0118
55 #define OMAP_HSMMC_RSP76 0x011C
56 #define OMAP_HSMMC_DATA 0x0120
57 #define OMAP_HSMMC_HCTL 0x0128
58 #define OMAP_HSMMC_SYSCTL 0x012C
59 #define OMAP_HSMMC_STAT 0x0130
60 #define OMAP_HSMMC_IE 0x0134
61 #define OMAP_HSMMC_ISE 0x0138
62 #define OMAP_HSMMC_CAPA 0x0140
64 #define VS18 (1 << 26)
65 #define VS30 (1 << 25)
66 #define SDVS18 (0x5 << 9)
67 #define SDVS30 (0x6 << 9)
68 #define SDVS33 (0x7 << 9)
69 #define SDVS_MASK 0x00000E00
70 #define SDVSCLR 0xFFFFF1FF
71 #define SDVSDET 0x00000400
78 #define CLKD_MASK 0x0000FFC0
80 #define DTO_MASK 0x000F0000
82 #define INT_EN_MASK 0x307F0033
83 #define BWR_ENABLE (1 << 4)
84 #define BRR_ENABLE (1 << 5)
85 #define DTO_ENABLE (1 << 20)
86 #define INIT_STREAM (1 << 1)
87 #define DP_SELECT (1 << 21)
92 #define FOUR_BIT (1 << 1)
99 #define CMD_TIMEOUT (1 << 16)
100 #define DATA_TIMEOUT (1 << 20)
101 #define CMD_CRC (1 << 17)
102 #define DATA_CRC (1 << 21)
103 #define CARD_ERR (1 << 28)
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
110 #define RESETDONE (1 << 0)
112 #define MMC_AUTOSUSPEND_DELAY 100
113 #define MMC_TIMEOUT_MS 20
114 #define OMAP_MMC_MIN_CLOCK 400000
115 #define OMAP_MMC_MAX_CLOCK 52000000
116 #define DRIVER_NAME "omap_hsmmc"
119 * One controller can have multiple slots, like on some omap boards using
120 * omap.c controller driver. Luckily this is not currently done on any known
121 * omap_hsmmc.c device.
123 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
126 * MMC Host controller read/write API's
128 #define OMAP_HSMMC_READ(base, reg) \
129 __raw_readl((base) + OMAP_HSMMC_##reg)
131 #define OMAP_HSMMC_WRITE(base, reg, val) \
132 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
134 struct omap_hsmmc_next
{
135 unsigned int dma_len
;
139 struct omap_hsmmc_host
{
141 struct mmc_host
*mmc
;
142 struct mmc_request
*mrq
;
143 struct mmc_command
*cmd
;
144 struct mmc_data
*data
;
148 * vcc == configured supply
149 * vcc_aux == optional
150 * - MMC1, supply for DAT4..DAT7
151 * - MMC2/MMC2, external level shifter voltage supply, for
152 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
154 struct regulator
*vcc
;
155 struct regulator
*vcc_aux
;
157 resource_size_t mapbase
;
158 spinlock_t irq_lock
; /* Prevent races with irq handler */
159 unsigned int dma_len
;
160 unsigned int dma_sg_idx
;
161 unsigned char bus_mode
;
162 unsigned char power_mode
;
166 struct dma_chan
*tx_chan
;
167 struct dma_chan
*rx_chan
;
175 struct omap_hsmmc_next next_data
;
177 struct omap_mmc_platform_data
*pdata
;
180 static int omap_hsmmc_card_detect(struct device
*dev
, int slot
)
182 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
184 /* NOTE: assumes card detect signal is active-low */
185 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
188 static int omap_hsmmc_get_wp(struct device
*dev
, int slot
)
190 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
192 /* NOTE: assumes write protect signal is active-high */
193 return gpio_get_value_cansleep(mmc
->slots
[0].gpio_wp
);
196 static int omap_hsmmc_get_cover_state(struct device
*dev
, int slot
)
198 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
206 static int omap_hsmmc_suspend_cdirq(struct device
*dev
, int slot
)
208 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
210 disable_irq(mmc
->slots
[0].card_detect_irq
);
214 static int omap_hsmmc_resume_cdirq(struct device
*dev
, int slot
)
216 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
218 enable_irq(mmc
->slots
[0].card_detect_irq
);
224 #define omap_hsmmc_suspend_cdirq NULL
225 #define omap_hsmmc_resume_cdirq NULL
229 #ifdef CONFIG_REGULATOR
231 static int omap_hsmmc_set_power(struct device
*dev
, int slot
, int power_on
,
234 struct omap_hsmmc_host
*host
=
235 platform_get_drvdata(to_platform_device(dev
));
239 * If we don't see a Vcc regulator, assume it's a fixed
240 * voltage always-on regulator.
245 * With DT, never turn OFF the regulator. This is because
246 * the pbias cell programming support is still missing when
247 * booting with Device tree
249 if (dev
->of_node
&& !vdd
)
252 if (mmc_slot(host
).before_set_reg
)
253 mmc_slot(host
).before_set_reg(dev
, slot
, power_on
, vdd
);
256 * Assume Vcc regulator is used only to power the card ... OMAP
257 * VDDS is used to power the pins, optionally with a transceiver to
258 * support cards using voltages other than VDDS (1.8V nominal). When a
259 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
261 * In some cases this regulator won't support enable/disable;
262 * e.g. it's a fixed rail for a WLAN chip.
264 * In other cases vcc_aux switches interface power. Example, for
265 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
266 * chips/cards need an interface voltage rail too.
269 ret
= mmc_regulator_set_ocr(host
->mmc
, host
->vcc
, vdd
);
270 /* Enable interface voltage rail, if needed */
271 if (ret
== 0 && host
->vcc_aux
) {
272 ret
= regulator_enable(host
->vcc_aux
);
274 ret
= mmc_regulator_set_ocr(host
->mmc
,
278 /* Shut down the rail */
280 ret
= regulator_disable(host
->vcc_aux
);
282 /* Then proceed to shut down the local regulator */
283 ret
= mmc_regulator_set_ocr(host
->mmc
,
288 if (mmc_slot(host
).after_set_reg
)
289 mmc_slot(host
).after_set_reg(dev
, slot
, power_on
, vdd
);
294 static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
296 struct regulator
*reg
;
299 reg
= regulator_get(host
->dev
, "vmmc");
301 dev_dbg(host
->dev
, "vmmc regulator missing\n");
304 mmc_slot(host
).set_power
= omap_hsmmc_set_power
;
306 ocr_value
= mmc_regulator_get_ocrmask(reg
);
307 if (!mmc_slot(host
).ocr_mask
) {
308 mmc_slot(host
).ocr_mask
= ocr_value
;
310 if (!(mmc_slot(host
).ocr_mask
& ocr_value
)) {
311 dev_err(host
->dev
, "ocrmask %x is not supported\n",
312 mmc_slot(host
).ocr_mask
);
313 mmc_slot(host
).ocr_mask
= 0;
318 /* Allow an aux regulator */
319 reg
= regulator_get(host
->dev
, "vmmc_aux");
320 host
->vcc_aux
= IS_ERR(reg
) ? NULL
: reg
;
322 /* For eMMC do not power off when not in sleep state */
323 if (mmc_slot(host
).no_regulator_off_init
)
326 * UGLY HACK: workaround regulator framework bugs.
327 * When the bootloader leaves a supply active, it's
328 * initialized with zero usecount ... and we can't
329 * disable it without first enabling it. Until the
330 * framework is fixed, we need a workaround like this
331 * (which is safe for MMC, but not in general).
333 if (regulator_is_enabled(host
->vcc
) > 0 ||
334 (host
->vcc_aux
&& regulator_is_enabled(host
->vcc_aux
))) {
335 int vdd
= ffs(mmc_slot(host
).ocr_mask
) - 1;
337 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
339 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
347 static void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
349 regulator_put(host
->vcc
);
350 regulator_put(host
->vcc_aux
);
351 mmc_slot(host
).set_power
= NULL
;
354 static inline int omap_hsmmc_have_reg(void)
361 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
366 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
370 static inline int omap_hsmmc_have_reg(void)
377 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data
*pdata
)
381 if (gpio_is_valid(pdata
->slots
[0].switch_pin
)) {
382 if (pdata
->slots
[0].cover
)
383 pdata
->slots
[0].get_cover_state
=
384 omap_hsmmc_get_cover_state
;
386 pdata
->slots
[0].card_detect
= omap_hsmmc_card_detect
;
387 pdata
->slots
[0].card_detect_irq
=
388 gpio_to_irq(pdata
->slots
[0].switch_pin
);
389 ret
= gpio_request(pdata
->slots
[0].switch_pin
, "mmc_cd");
392 ret
= gpio_direction_input(pdata
->slots
[0].switch_pin
);
396 pdata
->slots
[0].switch_pin
= -EINVAL
;
398 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
)) {
399 pdata
->slots
[0].get_ro
= omap_hsmmc_get_wp
;
400 ret
= gpio_request(pdata
->slots
[0].gpio_wp
, "mmc_wp");
403 ret
= gpio_direction_input(pdata
->slots
[0].gpio_wp
);
407 pdata
->slots
[0].gpio_wp
= -EINVAL
;
412 gpio_free(pdata
->slots
[0].gpio_wp
);
414 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
416 gpio_free(pdata
->slots
[0].switch_pin
);
420 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data
*pdata
)
422 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
))
423 gpio_free(pdata
->slots
[0].gpio_wp
);
424 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
425 gpio_free(pdata
->slots
[0].switch_pin
);
429 * Start clock to the card
431 static void omap_hsmmc_start_clock(struct omap_hsmmc_host
*host
)
433 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
434 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
438 * Stop clock to the card
440 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host
*host
)
442 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
443 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
444 if ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & CEN
) != 0x0)
445 dev_dbg(mmc_dev(host
->mmc
), "MMC Clock is not stoped\n");
448 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host
*host
,
449 struct mmc_command
*cmd
)
451 unsigned int irq_mask
;
454 irq_mask
= INT_EN_MASK
& ~(BRR_ENABLE
| BWR_ENABLE
);
456 irq_mask
= INT_EN_MASK
;
458 /* Disable timeout for erases */
459 if (cmd
->opcode
== MMC_ERASE
)
460 irq_mask
&= ~DTO_ENABLE
;
462 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
463 OMAP_HSMMC_WRITE(host
->base
, ISE
, irq_mask
);
464 OMAP_HSMMC_WRITE(host
->base
, IE
, irq_mask
);
467 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host
*host
)
469 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
470 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
471 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
474 /* Calculate divisor for the given clock frequency */
475 static u16
calc_divisor(struct omap_hsmmc_host
*host
, struct mmc_ios
*ios
)
480 dsor
= DIV_ROUND_UP(clk_get_rate(host
->fclk
), ios
->clock
);
488 static void omap_hsmmc_set_clock(struct omap_hsmmc_host
*host
)
490 struct mmc_ios
*ios
= &host
->mmc
->ios
;
491 unsigned long regval
;
492 unsigned long timeout
;
494 dev_vdbg(mmc_dev(host
->mmc
), "Set clock to %uHz\n", ios
->clock
);
496 omap_hsmmc_stop_clock(host
);
498 regval
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
499 regval
= regval
& ~(CLKD_MASK
| DTO_MASK
);
500 regval
= regval
| (calc_divisor(host
, ios
) << 6) | (DTO
<< 16);
501 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, regval
);
502 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
503 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
505 /* Wait till the ICS bit is set */
506 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
507 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
508 && time_before(jiffies
, timeout
))
511 omap_hsmmc_start_clock(host
);
514 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host
*host
)
516 struct mmc_ios
*ios
= &host
->mmc
->ios
;
519 con
= OMAP_HSMMC_READ(host
->base
, CON
);
520 if (ios
->timing
== MMC_TIMING_UHS_DDR50
)
521 con
|= DDR
; /* configure in DDR mode */
524 switch (ios
->bus_width
) {
525 case MMC_BUS_WIDTH_8
:
526 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
528 case MMC_BUS_WIDTH_4
:
529 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
530 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
531 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
533 case MMC_BUS_WIDTH_1
:
534 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
535 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
536 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
541 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host
*host
)
543 struct mmc_ios
*ios
= &host
->mmc
->ios
;
546 con
= OMAP_HSMMC_READ(host
->base
, CON
);
547 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
548 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
550 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
556 * Restore the MMC host context, if it was lost as result of a
557 * power state change.
559 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
561 struct mmc_ios
*ios
= &host
->mmc
->ios
;
562 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
563 int context_loss
= 0;
565 unsigned long timeout
;
567 if (pdata
->get_context_loss_count
) {
568 context_loss
= pdata
->get_context_loss_count(host
->dev
);
569 if (context_loss
< 0)
573 dev_dbg(mmc_dev(host
->mmc
), "context was %slost\n",
574 context_loss
== host
->context_loss
? "not " : "");
575 if (host
->context_loss
== context_loss
)
578 if (!OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
)
581 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
582 if (host
->power_mode
!= MMC_POWER_OFF
&&
583 (1 << ios
->vdd
) <= MMC_VDD_23_24
)
593 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
594 OMAP_HSMMC_READ(host
->base
, HCTL
) | hctl
);
596 OMAP_HSMMC_WRITE(host
->base
, CAPA
,
597 OMAP_HSMMC_READ(host
->base
, CAPA
) | capa
);
599 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
600 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
602 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
603 while ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
) != SDBP
604 && time_before(jiffies
, timeout
))
607 omap_hsmmc_disable_irq(host
);
609 /* Do not initialize card-specific things if the power is off */
610 if (host
->power_mode
== MMC_POWER_OFF
)
613 omap_hsmmc_set_bus_width(host
);
615 omap_hsmmc_set_clock(host
);
617 omap_hsmmc_set_bus_mode(host
);
620 host
->context_loss
= context_loss
;
622 dev_dbg(mmc_dev(host
->mmc
), "context is restored\n");
627 * Save the MMC host context (store the number of power state changes so far).
629 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
631 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
634 if (pdata
->get_context_loss_count
) {
635 context_loss
= pdata
->get_context_loss_count(host
->dev
);
636 if (context_loss
< 0)
638 host
->context_loss
= context_loss
;
644 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
649 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
656 * Send init stream sequence to card
657 * before sending IDLE command
659 static void send_init_stream(struct omap_hsmmc_host
*host
)
662 unsigned long timeout
;
664 if (host
->protect_card
)
667 disable_irq(host
->irq
);
669 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
670 OMAP_HSMMC_WRITE(host
->base
, CON
,
671 OMAP_HSMMC_READ(host
->base
, CON
) | INIT_STREAM
);
672 OMAP_HSMMC_WRITE(host
->base
, CMD
, INIT_STREAM_CMD
);
674 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
675 while ((reg
!= CC
) && time_before(jiffies
, timeout
))
676 reg
= OMAP_HSMMC_READ(host
->base
, STAT
) & CC
;
678 OMAP_HSMMC_WRITE(host
->base
, CON
,
679 OMAP_HSMMC_READ(host
->base
, CON
) & ~INIT_STREAM
);
681 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
682 OMAP_HSMMC_READ(host
->base
, STAT
);
684 enable_irq(host
->irq
);
688 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host
*host
)
692 if (mmc_slot(host
).get_cover_state
)
693 r
= mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
);
698 omap_hsmmc_show_cover_switch(struct device
*dev
, struct device_attribute
*attr
,
701 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
702 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
704 return sprintf(buf
, "%s\n",
705 omap_hsmmc_cover_is_closed(host
) ? "closed" : "open");
708 static DEVICE_ATTR(cover_switch
, S_IRUGO
, omap_hsmmc_show_cover_switch
, NULL
);
711 omap_hsmmc_show_slot_name(struct device
*dev
, struct device_attribute
*attr
,
714 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
715 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
717 return sprintf(buf
, "%s\n", mmc_slot(host
).name
);
720 static DEVICE_ATTR(slot_name
, S_IRUGO
, omap_hsmmc_show_slot_name
, NULL
);
723 * Configure the response type and send the cmd.
726 omap_hsmmc_start_command(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
,
727 struct mmc_data
*data
)
729 int cmdreg
= 0, resptype
= 0, cmdtype
= 0;
731 dev_vdbg(mmc_dev(host
->mmc
), "%s: CMD%d, argument 0x%08x\n",
732 mmc_hostname(host
->mmc
), cmd
->opcode
, cmd
->arg
);
735 omap_hsmmc_enable_irq(host
, cmd
);
737 host
->response_busy
= 0;
738 if (cmd
->flags
& MMC_RSP_PRESENT
) {
739 if (cmd
->flags
& MMC_RSP_136
)
741 else if (cmd
->flags
& MMC_RSP_BUSY
) {
743 host
->response_busy
= 1;
749 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
750 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
751 * a val of 0x3, rest 0x0.
753 if (cmd
== host
->mrq
->stop
)
756 cmdreg
= (cmd
->opcode
<< 24) | (resptype
<< 16) | (cmdtype
<< 22);
759 cmdreg
|= DP_SELECT
| MSBS
| BCE
;
760 if (data
->flags
& MMC_DATA_READ
)
769 host
->req_in_progress
= 1;
771 OMAP_HSMMC_WRITE(host
->base
, ARG
, cmd
->arg
);
772 OMAP_HSMMC_WRITE(host
->base
, CMD
, cmdreg
);
776 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
778 if (data
->flags
& MMC_DATA_WRITE
)
779 return DMA_TO_DEVICE
;
781 return DMA_FROM_DEVICE
;
784 static struct dma_chan
*omap_hsmmc_get_dma_chan(struct omap_hsmmc_host
*host
,
785 struct mmc_data
*data
)
787 return data
->flags
& MMC_DATA_WRITE
? host
->tx_chan
: host
->rx_chan
;
790 static void omap_hsmmc_request_done(struct omap_hsmmc_host
*host
, struct mmc_request
*mrq
)
795 spin_lock_irqsave(&host
->irq_lock
, flags
);
796 host
->req_in_progress
= 0;
797 dma_ch
= host
->dma_ch
;
798 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
800 omap_hsmmc_disable_irq(host
);
801 /* Do not complete the request if DMA is still in progress */
802 if (mrq
->data
&& host
->use_dma
&& dma_ch
!= -1)
805 mmc_request_done(host
->mmc
, mrq
);
809 * Notify the transfer complete to MMC core
812 omap_hsmmc_xfer_done(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
815 struct mmc_request
*mrq
= host
->mrq
;
817 /* TC before CC from CMD6 - don't know why, but it happens */
818 if (host
->cmd
&& host
->cmd
->opcode
== 6 &&
819 host
->response_busy
) {
820 host
->response_busy
= 0;
824 omap_hsmmc_request_done(host
, mrq
);
831 data
->bytes_xfered
+= data
->blocks
* (data
->blksz
);
833 data
->bytes_xfered
= 0;
836 omap_hsmmc_request_done(host
, data
->mrq
);
839 omap_hsmmc_start_command(host
, data
->stop
, NULL
);
843 * Notify the core about command completion
846 omap_hsmmc_cmd_done(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
)
850 if (cmd
->flags
& MMC_RSP_PRESENT
) {
851 if (cmd
->flags
& MMC_RSP_136
) {
852 /* response type 2 */
853 cmd
->resp
[3] = OMAP_HSMMC_READ(host
->base
, RSP10
);
854 cmd
->resp
[2] = OMAP_HSMMC_READ(host
->base
, RSP32
);
855 cmd
->resp
[1] = OMAP_HSMMC_READ(host
->base
, RSP54
);
856 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP76
);
858 /* response types 1, 1b, 3, 4, 5, 6 */
859 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP10
);
862 if ((host
->data
== NULL
&& !host
->response_busy
) || cmd
->error
)
863 omap_hsmmc_request_done(host
, cmd
->mrq
);
867 * DMA clean up for command errors
869 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host
*host
, int errno
)
874 host
->data
->error
= errno
;
876 spin_lock_irqsave(&host
->irq_lock
, flags
);
877 dma_ch
= host
->dma_ch
;
879 spin_unlock_irqrestore(&host
->irq_lock
, flags
);
881 if (host
->use_dma
&& dma_ch
!= -1) {
882 struct dma_chan
*chan
= omap_hsmmc_get_dma_chan(host
, host
->data
);
884 dmaengine_terminate_all(chan
);
885 dma_unmap_sg(chan
->device
->dev
,
886 host
->data
->sg
, host
->data
->sg_len
,
887 omap_hsmmc_get_dma_dir(host
, host
->data
));
889 host
->data
->host_cookie
= 0;
895 * Readable error output
897 #ifdef CONFIG_MMC_DEBUG
898 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host
*host
, u32 status
)
900 /* --- means reserved bit without definition at documentation */
901 static const char *omap_hsmmc_status_bits
[] = {
902 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
903 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
904 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
905 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
911 len
= sprintf(buf
, "MMC IRQ 0x%x :", status
);
914 for (i
= 0; i
< ARRAY_SIZE(omap_hsmmc_status_bits
); i
++)
915 if (status
& (1 << i
)) {
916 len
= sprintf(buf
, " %s", omap_hsmmc_status_bits
[i
]);
920 dev_vdbg(mmc_dev(host
->mmc
), "%s\n", res
);
923 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host
*host
,
927 #endif /* CONFIG_MMC_DEBUG */
930 * MMC controller internal state machines reset
932 * Used to reset command or data internal state machines, using respectively
933 * SRC or SRD bit of SYSCTL register
934 * Can be called from interrupt context
936 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host
*host
,
940 unsigned long limit
= (loops_per_jiffy
*
941 msecs_to_jiffies(MMC_TIMEOUT_MS
));
943 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
944 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | bit
);
947 * OMAP4 ES2 and greater has an updated reset logic.
948 * Monitor a 0->1 transition first
950 if (mmc_slot(host
).features
& HSMMC_HAS_UPDATED_RESET
) {
951 while ((!(OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
))
957 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
) &&
961 if (OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
)
962 dev_err(mmc_dev(host
->mmc
),
963 "Timeout waiting on controller reset in %s\n",
967 static void omap_hsmmc_do_irq(struct omap_hsmmc_host
*host
, int status
)
969 struct mmc_data
*data
;
970 int end_cmd
= 0, end_trans
= 0;
973 dev_vdbg(mmc_dev(host
->mmc
), "IRQ Status is %x\n", status
);
976 omap_hsmmc_dbg_report_irq(host
, status
);
977 if ((status
& CMD_TIMEOUT
) ||
978 (status
& CMD_CRC
)) {
980 if (status
& CMD_TIMEOUT
) {
981 omap_hsmmc_reset_controller_fsm(host
,
983 host
->cmd
->error
= -ETIMEDOUT
;
985 host
->cmd
->error
= -EILSEQ
;
989 if (host
->data
|| host
->response_busy
) {
991 omap_hsmmc_dma_cleanup(host
,
993 host
->response_busy
= 0;
994 omap_hsmmc_reset_controller_fsm(host
, SRD
);
997 if ((status
& DATA_TIMEOUT
) ||
998 (status
& DATA_CRC
)) {
999 if (host
->data
|| host
->response_busy
) {
1000 int err
= (status
& DATA_TIMEOUT
) ?
1001 -ETIMEDOUT
: -EILSEQ
;
1004 omap_hsmmc_dma_cleanup(host
, err
);
1006 host
->mrq
->cmd
->error
= err
;
1007 host
->response_busy
= 0;
1008 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1012 if (status
& CARD_ERR
) {
1013 dev_dbg(mmc_dev(host
->mmc
),
1014 "Ignoring card err CMD%d\n", host
->cmd
->opcode
);
1022 if (end_cmd
|| ((status
& CC
) && host
->cmd
))
1023 omap_hsmmc_cmd_done(host
, host
->cmd
);
1024 if ((end_trans
|| (status
& TC
)) && host
->mrq
)
1025 omap_hsmmc_xfer_done(host
, data
);
1029 * MMC controller IRQ handler
1031 static irqreturn_t
omap_hsmmc_irq(int irq
, void *dev_id
)
1033 struct omap_hsmmc_host
*host
= dev_id
;
1036 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1037 while (status
& INT_EN_MASK
&& host
->req_in_progress
) {
1038 omap_hsmmc_do_irq(host
, status
);
1040 /* Flush posted write */
1041 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
1042 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
1048 static void set_sd_bus_power(struct omap_hsmmc_host
*host
)
1052 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1053 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
1054 for (i
= 0; i
< loops_per_jiffy
; i
++) {
1055 if (OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
)
1062 * Switch MMC interface voltage ... only relevant for MMC1.
1064 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1065 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1066 * Some chips, like eMMC ones, use internal transceivers.
1068 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host
*host
, int vdd
)
1073 /* Disable the clocks */
1074 pm_runtime_put_sync(host
->dev
);
1076 clk_disable_unprepare(host
->dbclk
);
1078 /* Turn the power off */
1079 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 0, 0);
1081 /* Turn the power ON with given VDD 1.8 or 3.0v */
1083 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 1,
1085 pm_runtime_get_sync(host
->dev
);
1087 clk_prepare_enable(host
->dbclk
);
1092 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1093 OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSCLR
);
1094 reg_val
= OMAP_HSMMC_READ(host
->base
, HCTL
);
1097 * If a MMC dual voltage card is detected, the set_ios fn calls
1098 * this fn with VDD bit set for 1.8V. Upon card removal from the
1099 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1101 * Cope with a bit of slop in the range ... per data sheets:
1102 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1103 * but recommended values are 1.71V to 1.89V
1104 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1105 * but recommended values are 2.7V to 3.3V
1107 * Board setup code shouldn't permit anything very out-of-range.
1108 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1109 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1111 if ((1 << vdd
) <= MMC_VDD_23_24
)
1116 OMAP_HSMMC_WRITE(host
->base
, HCTL
, reg_val
);
1117 set_sd_bus_power(host
);
1121 dev_dbg(mmc_dev(host
->mmc
), "Unable to switch operating voltage\n");
1125 /* Protect the card while the cover is open */
1126 static void omap_hsmmc_protect_card(struct omap_hsmmc_host
*host
)
1128 if (!mmc_slot(host
).get_cover_state
)
1131 host
->reqs_blocked
= 0;
1132 if (mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)) {
1133 if (host
->protect_card
) {
1134 dev_info(host
->dev
, "%s: cover is closed, "
1135 "card is now accessible\n",
1136 mmc_hostname(host
->mmc
));
1137 host
->protect_card
= 0;
1140 if (!host
->protect_card
) {
1141 dev_info(host
->dev
, "%s: cover is open, "
1142 "card is now inaccessible\n",
1143 mmc_hostname(host
->mmc
));
1144 host
->protect_card
= 1;
1150 * irq handler to notify the core about card insertion/removal
1152 static irqreturn_t
omap_hsmmc_detect(int irq
, void *dev_id
)
1154 struct omap_hsmmc_host
*host
= dev_id
;
1155 struct omap_mmc_slot_data
*slot
= &mmc_slot(host
);
1158 if (host
->suspended
)
1161 sysfs_notify(&host
->mmc
->class_dev
.kobj
, NULL
, "cover_switch");
1163 if (slot
->card_detect
)
1164 carddetect
= slot
->card_detect(host
->dev
, host
->slot_id
);
1166 omap_hsmmc_protect_card(host
);
1167 carddetect
= -ENOSYS
;
1171 mmc_detect_change(host
->mmc
, (HZ
* 200) / 1000);
1173 mmc_detect_change(host
->mmc
, (HZ
* 50) / 1000);
1177 static void omap_hsmmc_dma_callback(void *param
)
1179 struct omap_hsmmc_host
*host
= param
;
1180 struct dma_chan
*chan
;
1181 struct mmc_data
*data
;
1182 int req_in_progress
;
1184 spin_lock_irq(&host
->irq_lock
);
1185 if (host
->dma_ch
< 0) {
1186 spin_unlock_irq(&host
->irq_lock
);
1190 data
= host
->mrq
->data
;
1191 chan
= omap_hsmmc_get_dma_chan(host
, data
);
1192 if (!data
->host_cookie
)
1193 dma_unmap_sg(chan
->device
->dev
,
1194 data
->sg
, data
->sg_len
,
1195 omap_hsmmc_get_dma_dir(host
, data
));
1197 req_in_progress
= host
->req_in_progress
;
1199 spin_unlock_irq(&host
->irq_lock
);
1201 /* If DMA has finished after TC, complete the request */
1202 if (!req_in_progress
) {
1203 struct mmc_request
*mrq
= host
->mrq
;
1206 mmc_request_done(host
->mmc
, mrq
);
1210 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host
*host
,
1211 struct mmc_data
*data
,
1212 struct omap_hsmmc_next
*next
,
1213 struct dma_chan
*chan
)
1217 if (!next
&& data
->host_cookie
&&
1218 data
->host_cookie
!= host
->next_data
.cookie
) {
1219 dev_warn(host
->dev
, "[%s] invalid cookie: data->host_cookie %d"
1220 " host->next_data.cookie %d\n",
1221 __func__
, data
->host_cookie
, host
->next_data
.cookie
);
1222 data
->host_cookie
= 0;
1225 /* Check if next job is already prepared */
1227 (!next
&& data
->host_cookie
!= host
->next_data
.cookie
)) {
1228 dma_len
= dma_map_sg(chan
->device
->dev
, data
->sg
, data
->sg_len
,
1229 omap_hsmmc_get_dma_dir(host
, data
));
1232 dma_len
= host
->next_data
.dma_len
;
1233 host
->next_data
.dma_len
= 0;
1241 next
->dma_len
= dma_len
;
1242 data
->host_cookie
= ++next
->cookie
< 0 ? 1 : next
->cookie
;
1244 host
->dma_len
= dma_len
;
1250 * Routine to configure and start DMA for the MMC card
1252 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host
*host
,
1253 struct mmc_request
*req
)
1255 struct dma_slave_config cfg
;
1256 struct dma_async_tx_descriptor
*tx
;
1258 struct mmc_data
*data
= req
->data
;
1259 struct dma_chan
*chan
;
1261 /* Sanity check: all the SG entries must be aligned by block size. */
1262 for (i
= 0; i
< data
->sg_len
; i
++) {
1263 struct scatterlist
*sgl
;
1266 if (sgl
->length
% data
->blksz
)
1269 if ((data
->blksz
% 4) != 0)
1270 /* REVISIT: The MMC buffer increments only when MSB is written.
1271 * Return error for blksz which is non multiple of four.
1275 BUG_ON(host
->dma_ch
!= -1);
1277 chan
= omap_hsmmc_get_dma_chan(host
, data
);
1279 cfg
.src_addr
= host
->mapbase
+ OMAP_HSMMC_DATA
;
1280 cfg
.dst_addr
= host
->mapbase
+ OMAP_HSMMC_DATA
;
1281 cfg
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1282 cfg
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
1283 cfg
.src_maxburst
= data
->blksz
/ 4;
1284 cfg
.dst_maxburst
= data
->blksz
/ 4;
1286 ret
= dmaengine_slave_config(chan
, &cfg
);
1290 ret
= omap_hsmmc_pre_dma_transfer(host
, data
, NULL
, chan
);
1294 tx
= dmaengine_prep_slave_sg(chan
, data
->sg
, data
->sg_len
,
1295 data
->flags
& MMC_DATA_WRITE
? DMA_MEM_TO_DEV
: DMA_DEV_TO_MEM
,
1296 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1298 dev_err(mmc_dev(host
->mmc
), "prep_slave_sg() failed\n");
1299 /* FIXME: cleanup */
1303 tx
->callback
= omap_hsmmc_dma_callback
;
1304 tx
->callback_param
= host
;
1307 dmaengine_submit(tx
);
1311 dma_async_issue_pending(chan
);
1316 static void set_data_timeout(struct omap_hsmmc_host
*host
,
1317 unsigned int timeout_ns
,
1318 unsigned int timeout_clks
)
1320 unsigned int timeout
, cycle_ns
;
1321 uint32_t reg
, clkd
, dto
= 0;
1323 reg
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1324 clkd
= (reg
& CLKD_MASK
) >> CLKD_SHIFT
;
1328 cycle_ns
= 1000000000 / (clk_get_rate(host
->fclk
) / clkd
);
1329 timeout
= timeout_ns
/ cycle_ns
;
1330 timeout
+= timeout_clks
;
1332 while ((timeout
& 0x80000000) == 0) {
1349 reg
|= dto
<< DTO_SHIFT
;
1350 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, reg
);
1354 * Configure block length for MMC/SD cards and initiate the transfer.
1357 omap_hsmmc_prepare_data(struct omap_hsmmc_host
*host
, struct mmc_request
*req
)
1360 host
->data
= req
->data
;
1362 if (req
->data
== NULL
) {
1363 OMAP_HSMMC_WRITE(host
->base
, BLK
, 0);
1365 * Set an arbitrary 100ms data timeout for commands with
1368 if (req
->cmd
->flags
& MMC_RSP_BUSY
)
1369 set_data_timeout(host
, 100000000U, 0);
1373 OMAP_HSMMC_WRITE(host
->base
, BLK
, (req
->data
->blksz
)
1374 | (req
->data
->blocks
<< 16));
1375 set_data_timeout(host
, req
->data
->timeout_ns
, req
->data
->timeout_clks
);
1377 if (host
->use_dma
) {
1378 ret
= omap_hsmmc_start_dma_transfer(host
, req
);
1380 dev_dbg(mmc_dev(host
->mmc
), "MMC start dma failure\n");
1387 static void omap_hsmmc_post_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
1390 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1391 struct mmc_data
*data
= mrq
->data
;
1393 if (host
->use_dma
&& data
->host_cookie
) {
1394 struct dma_chan
*c
= omap_hsmmc_get_dma_chan(host
, data
);
1396 dma_unmap_sg(c
->device
->dev
, data
->sg
, data
->sg_len
,
1397 omap_hsmmc_get_dma_dir(host
, data
));
1398 data
->host_cookie
= 0;
1402 static void omap_hsmmc_pre_req(struct mmc_host
*mmc
, struct mmc_request
*mrq
,
1405 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1407 if (mrq
->data
->host_cookie
) {
1408 mrq
->data
->host_cookie
= 0;
1412 if (host
->use_dma
) {
1413 struct dma_chan
*c
= omap_hsmmc_get_dma_chan(host
, mrq
->data
);
1415 if (omap_hsmmc_pre_dma_transfer(host
, mrq
->data
,
1416 &host
->next_data
, c
))
1417 mrq
->data
->host_cookie
= 0;
1422 * Request function. for read/write operation
1424 static void omap_hsmmc_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
1426 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1429 BUG_ON(host
->req_in_progress
);
1430 BUG_ON(host
->dma_ch
!= -1);
1431 if (host
->protect_card
) {
1432 if (host
->reqs_blocked
< 3) {
1434 * Ensure the controller is left in a consistent
1435 * state by resetting the command and data state
1438 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1439 omap_hsmmc_reset_controller_fsm(host
, SRC
);
1440 host
->reqs_blocked
+= 1;
1442 req
->cmd
->error
= -EBADF
;
1444 req
->data
->error
= -EBADF
;
1445 req
->cmd
->retries
= 0;
1446 mmc_request_done(mmc
, req
);
1448 } else if (host
->reqs_blocked
)
1449 host
->reqs_blocked
= 0;
1450 WARN_ON(host
->mrq
!= NULL
);
1452 err
= omap_hsmmc_prepare_data(host
, req
);
1454 req
->cmd
->error
= err
;
1456 req
->data
->error
= err
;
1458 mmc_request_done(mmc
, req
);
1462 omap_hsmmc_start_command(host
, req
->cmd
, req
->data
);
1465 /* Routine to configure clock values. Exposed API to core */
1466 static void omap_hsmmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1468 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1469 int do_send_init_stream
= 0;
1471 pm_runtime_get_sync(host
->dev
);
1473 if (ios
->power_mode
!= host
->power_mode
) {
1474 switch (ios
->power_mode
) {
1476 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1480 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1484 do_send_init_stream
= 1;
1487 host
->power_mode
= ios
->power_mode
;
1490 /* FIXME: set registers based only on changes to ios */
1492 omap_hsmmc_set_bus_width(host
);
1494 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
1495 /* Only MMC1 can interface at 3V without some flavor
1496 * of external transceiver; but they all handle 1.8V.
1498 if ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSDET
) &&
1499 (ios
->vdd
== DUAL_VOLT_OCR_BIT
) &&
1501 * With pbias cell programming missing, this
1502 * can't be allowed when booting with device
1505 !host
->dev
->of_node
) {
1507 * The mmc_select_voltage fn of the core does
1508 * not seem to set the power_mode to
1509 * MMC_POWER_UP upon recalculating the voltage.
1512 if (omap_hsmmc_switch_opcond(host
, ios
->vdd
) != 0)
1513 dev_dbg(mmc_dev(host
->mmc
),
1514 "Switch operation failed\n");
1518 omap_hsmmc_set_clock(host
);
1520 if (do_send_init_stream
)
1521 send_init_stream(host
);
1523 omap_hsmmc_set_bus_mode(host
);
1525 pm_runtime_put_autosuspend(host
->dev
);
1528 static int omap_hsmmc_get_cd(struct mmc_host
*mmc
)
1530 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1532 if (!mmc_slot(host
).card_detect
)
1534 return mmc_slot(host
).card_detect(host
->dev
, host
->slot_id
);
1537 static int omap_hsmmc_get_ro(struct mmc_host
*mmc
)
1539 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1541 if (!mmc_slot(host
).get_ro
)
1543 return mmc_slot(host
).get_ro(host
->dev
, 0);
1546 static void omap_hsmmc_init_card(struct mmc_host
*mmc
, struct mmc_card
*card
)
1548 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1550 if (mmc_slot(host
).init_card
)
1551 mmc_slot(host
).init_card(card
);
1554 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host
*host
)
1556 u32 hctl
, capa
, value
;
1558 /* Only MMC1 supports 3.0V */
1559 if (host
->pdata
->controller_flags
& OMAP_HSMMC_SUPPORTS_DUAL_VOLT
) {
1567 value
= OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDVS_MASK
;
1568 OMAP_HSMMC_WRITE(host
->base
, HCTL
, value
| hctl
);
1570 value
= OMAP_HSMMC_READ(host
->base
, CAPA
);
1571 OMAP_HSMMC_WRITE(host
->base
, CAPA
, value
| capa
);
1573 /* Set SD bus power bit */
1574 set_sd_bus_power(host
);
1577 static int omap_hsmmc_enable_fclk(struct mmc_host
*mmc
)
1579 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1581 pm_runtime_get_sync(host
->dev
);
1586 static int omap_hsmmc_disable_fclk(struct mmc_host
*mmc
)
1588 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1590 pm_runtime_mark_last_busy(host
->dev
);
1591 pm_runtime_put_autosuspend(host
->dev
);
1596 static const struct mmc_host_ops omap_hsmmc_ops
= {
1597 .enable
= omap_hsmmc_enable_fclk
,
1598 .disable
= omap_hsmmc_disable_fclk
,
1599 .post_req
= omap_hsmmc_post_req
,
1600 .pre_req
= omap_hsmmc_pre_req
,
1601 .request
= omap_hsmmc_request
,
1602 .set_ios
= omap_hsmmc_set_ios
,
1603 .get_cd
= omap_hsmmc_get_cd
,
1604 .get_ro
= omap_hsmmc_get_ro
,
1605 .init_card
= omap_hsmmc_init_card
,
1606 /* NYET -- enable_sdio_irq */
1609 #ifdef CONFIG_DEBUG_FS
1611 static int omap_hsmmc_regs_show(struct seq_file
*s
, void *data
)
1613 struct mmc_host
*mmc
= s
->private;
1614 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1615 int context_loss
= 0;
1617 if (host
->pdata
->get_context_loss_count
)
1618 context_loss
= host
->pdata
->get_context_loss_count(host
->dev
);
1620 seq_printf(s
, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1621 mmc
->index
, host
->context_loss
, context_loss
);
1623 if (host
->suspended
) {
1624 seq_printf(s
, "host suspended, can't read registers\n");
1628 pm_runtime_get_sync(host
->dev
);
1630 seq_printf(s
, "CON:\t\t0x%08x\n",
1631 OMAP_HSMMC_READ(host
->base
, CON
));
1632 seq_printf(s
, "HCTL:\t\t0x%08x\n",
1633 OMAP_HSMMC_READ(host
->base
, HCTL
));
1634 seq_printf(s
, "SYSCTL:\t\t0x%08x\n",
1635 OMAP_HSMMC_READ(host
->base
, SYSCTL
));
1636 seq_printf(s
, "IE:\t\t0x%08x\n",
1637 OMAP_HSMMC_READ(host
->base
, IE
));
1638 seq_printf(s
, "ISE:\t\t0x%08x\n",
1639 OMAP_HSMMC_READ(host
->base
, ISE
));
1640 seq_printf(s
, "CAPA:\t\t0x%08x\n",
1641 OMAP_HSMMC_READ(host
->base
, CAPA
));
1643 pm_runtime_mark_last_busy(host
->dev
);
1644 pm_runtime_put_autosuspend(host
->dev
);
1649 static int omap_hsmmc_regs_open(struct inode
*inode
, struct file
*file
)
1651 return single_open(file
, omap_hsmmc_regs_show
, inode
->i_private
);
1654 static const struct file_operations mmc_regs_fops
= {
1655 .open
= omap_hsmmc_regs_open
,
1657 .llseek
= seq_lseek
,
1658 .release
= single_release
,
1661 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1663 if (mmc
->debugfs_root
)
1664 debugfs_create_file("regs", S_IRUSR
, mmc
->debugfs_root
,
1665 mmc
, &mmc_regs_fops
);
1670 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1677 static u16 omap4_reg_offset
= 0x100;
1679 static const struct of_device_id omap_mmc_of_match
[] = {
1681 .compatible
= "ti,omap2-hsmmc",
1684 .compatible
= "ti,omap3-hsmmc",
1687 .compatible
= "ti,omap4-hsmmc",
1688 .data
= &omap4_reg_offset
,
1692 MODULE_DEVICE_TABLE(of
, omap_mmc_of_match
);
1694 static struct omap_mmc_platform_data
*of_get_hsmmc_pdata(struct device
*dev
)
1696 struct omap_mmc_platform_data
*pdata
;
1697 struct device_node
*np
= dev
->of_node
;
1700 pdata
= devm_kzalloc(dev
, sizeof(*pdata
), GFP_KERNEL
);
1702 return NULL
; /* out of memory */
1704 if (of_find_property(np
, "ti,dual-volt", NULL
))
1705 pdata
->controller_flags
|= OMAP_HSMMC_SUPPORTS_DUAL_VOLT
;
1707 /* This driver only supports 1 slot */
1708 pdata
->nr_slots
= 1;
1709 pdata
->slots
[0].switch_pin
= of_get_named_gpio(np
, "cd-gpios", 0);
1710 pdata
->slots
[0].gpio_wp
= of_get_named_gpio(np
, "wp-gpios", 0);
1712 if (of_find_property(np
, "ti,non-removable", NULL
)) {
1713 pdata
->slots
[0].nonremovable
= true;
1714 pdata
->slots
[0].no_regulator_off_init
= true;
1716 of_property_read_u32(np
, "bus-width", &bus_width
);
1718 pdata
->slots
[0].caps
|= MMC_CAP_4_BIT_DATA
;
1719 else if (bus_width
== 8)
1720 pdata
->slots
[0].caps
|= MMC_CAP_8_BIT_DATA
;
1722 if (of_find_property(np
, "ti,needs-special-reset", NULL
))
1723 pdata
->slots
[0].features
|= HSMMC_HAS_UPDATED_RESET
;
1728 static inline struct omap_mmc_platform_data
1729 *of_get_hsmmc_pdata(struct device
*dev
)
1735 static int __devinit
omap_hsmmc_probe(struct platform_device
*pdev
)
1737 struct omap_mmc_platform_data
*pdata
= pdev
->dev
.platform_data
;
1738 struct mmc_host
*mmc
;
1739 struct omap_hsmmc_host
*host
= NULL
;
1740 struct resource
*res
;
1742 const struct of_device_id
*match
;
1743 dma_cap_mask_t mask
;
1744 unsigned tx_req
, rx_req
;
1746 match
= of_match_device(of_match_ptr(omap_mmc_of_match
), &pdev
->dev
);
1748 pdata
= of_get_hsmmc_pdata(&pdev
->dev
);
1750 u16
*offsetp
= match
->data
;
1751 pdata
->reg_offset
= *offsetp
;
1755 if (pdata
== NULL
) {
1756 dev_err(&pdev
->dev
, "Platform Data is missing\n");
1760 if (pdata
->nr_slots
== 0) {
1761 dev_err(&pdev
->dev
, "No Slots\n");
1765 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1766 irq
= platform_get_irq(pdev
, 0);
1767 if (res
== NULL
|| irq
< 0)
1770 res
= request_mem_region(res
->start
, resource_size(res
), pdev
->name
);
1774 ret
= omap_hsmmc_gpio_init(pdata
);
1778 mmc
= mmc_alloc_host(sizeof(struct omap_hsmmc_host
), &pdev
->dev
);
1784 host
= mmc_priv(mmc
);
1786 host
->pdata
= pdata
;
1787 host
->dev
= &pdev
->dev
;
1792 host
->mapbase
= res
->start
+ pdata
->reg_offset
;
1793 host
->base
= ioremap(host
->mapbase
, SZ_4K
);
1794 host
->power_mode
= MMC_POWER_OFF
;
1795 host
->next_data
.cookie
= 1;
1797 platform_set_drvdata(pdev
, host
);
1799 mmc
->ops
= &omap_hsmmc_ops
;
1802 * If regulator_disable can only put vcc_aux to sleep then there is
1805 if (mmc_slot(host
).vcc_aux_disable_is_sleep
)
1806 mmc_slot(host
).no_off
= 1;
1808 mmc
->f_min
= OMAP_MMC_MIN_CLOCK
;
1810 if (pdata
->max_freq
> 0)
1811 mmc
->f_max
= pdata
->max_freq
;
1813 mmc
->f_max
= OMAP_MMC_MAX_CLOCK
;
1815 spin_lock_init(&host
->irq_lock
);
1817 host
->fclk
= clk_get(&pdev
->dev
, "fck");
1818 if (IS_ERR(host
->fclk
)) {
1819 ret
= PTR_ERR(host
->fclk
);
1824 if (host
->pdata
->controller_flags
& OMAP_HSMMC_BROKEN_MULTIBLOCK_READ
) {
1825 dev_info(&pdev
->dev
, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1826 mmc
->caps2
|= MMC_CAP2_NO_MULTI_READ
;
1829 pm_runtime_enable(host
->dev
);
1830 pm_runtime_get_sync(host
->dev
);
1831 pm_runtime_set_autosuspend_delay(host
->dev
, MMC_AUTOSUSPEND_DELAY
);
1832 pm_runtime_use_autosuspend(host
->dev
);
1834 omap_hsmmc_context_save(host
);
1836 host
->dbclk
= clk_get(&pdev
->dev
, "mmchsdb_fck");
1838 * MMC can still work without debounce clock.
1840 if (IS_ERR(host
->dbclk
)) {
1841 dev_warn(mmc_dev(host
->mmc
), "Failed to get debounce clk\n");
1843 } else if (clk_prepare_enable(host
->dbclk
) != 0) {
1844 dev_warn(mmc_dev(host
->mmc
), "Failed to enable debounce clk\n");
1845 clk_put(host
->dbclk
);
1849 /* Since we do only SG emulation, we can have as many segs
1851 mmc
->max_segs
= 1024;
1853 mmc
->max_blk_size
= 512; /* Block Length at max can be 1024 */
1854 mmc
->max_blk_count
= 0xFFFF; /* No. of Blocks is 16 bits */
1855 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
1856 mmc
->max_seg_size
= mmc
->max_req_size
;
1858 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
|
1859 MMC_CAP_WAIT_WHILE_BUSY
| MMC_CAP_ERASE
;
1861 mmc
->caps
|= mmc_slot(host
).caps
;
1862 if (mmc
->caps
& MMC_CAP_8_BIT_DATA
)
1863 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
1865 if (mmc_slot(host
).nonremovable
)
1866 mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
1868 mmc
->pm_caps
= mmc_slot(host
).pm_caps
;
1870 omap_hsmmc_conf_bus_power(host
);
1872 res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "tx");
1874 dev_err(mmc_dev(host
->mmc
), "cannot get DMA TX channel\n");
1878 tx_req
= res
->start
;
1880 res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "rx");
1882 dev_err(mmc_dev(host
->mmc
), "cannot get DMA RX channel\n");
1886 rx_req
= res
->start
;
1889 dma_cap_set(DMA_SLAVE
, mask
);
1891 host
->rx_chan
= dma_request_channel(mask
, omap_dma_filter_fn
, &rx_req
);
1892 if (!host
->rx_chan
) {
1893 dev_err(mmc_dev(host
->mmc
), "unable to obtain RX DMA engine channel %u\n", rx_req
);
1898 host
->tx_chan
= dma_request_channel(mask
, omap_dma_filter_fn
, &tx_req
);
1899 if (!host
->tx_chan
) {
1900 dev_err(mmc_dev(host
->mmc
), "unable to obtain TX DMA engine channel %u\n", tx_req
);
1905 /* Request IRQ for MMC operations */
1906 ret
= request_irq(host
->irq
, omap_hsmmc_irq
, 0,
1907 mmc_hostname(mmc
), host
);
1909 dev_dbg(mmc_dev(host
->mmc
), "Unable to grab HSMMC IRQ\n");
1913 if (pdata
->init
!= NULL
) {
1914 if (pdata
->init(&pdev
->dev
) != 0) {
1915 dev_dbg(mmc_dev(host
->mmc
),
1916 "Unable to configure MMC IRQs\n");
1917 goto err_irq_cd_init
;
1921 if (omap_hsmmc_have_reg() && !mmc_slot(host
).set_power
) {
1922 ret
= omap_hsmmc_reg_get(host
);
1928 mmc
->ocr_avail
= mmc_slot(host
).ocr_mask
;
1930 /* Request IRQ for card detect */
1931 if ((mmc_slot(host
).card_detect_irq
)) {
1932 ret
= request_threaded_irq(mmc_slot(host
).card_detect_irq
,
1935 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
| IRQF_ONESHOT
,
1936 mmc_hostname(mmc
), host
);
1938 dev_dbg(mmc_dev(host
->mmc
),
1939 "Unable to grab MMC CD IRQ\n");
1942 pdata
->suspend
= omap_hsmmc_suspend_cdirq
;
1943 pdata
->resume
= omap_hsmmc_resume_cdirq
;
1946 omap_hsmmc_disable_irq(host
);
1948 omap_hsmmc_protect_card(host
);
1952 if (mmc_slot(host
).name
!= NULL
) {
1953 ret
= device_create_file(&mmc
->class_dev
, &dev_attr_slot_name
);
1957 if (mmc_slot(host
).card_detect_irq
&& mmc_slot(host
).get_cover_state
) {
1958 ret
= device_create_file(&mmc
->class_dev
,
1959 &dev_attr_cover_switch
);
1964 omap_hsmmc_debugfs(mmc
);
1965 pm_runtime_mark_last_busy(host
->dev
);
1966 pm_runtime_put_autosuspend(host
->dev
);
1971 mmc_remove_host(mmc
);
1972 free_irq(mmc_slot(host
).card_detect_irq
, host
);
1975 omap_hsmmc_reg_put(host
);
1977 if (host
->pdata
->cleanup
)
1978 host
->pdata
->cleanup(&pdev
->dev
);
1980 free_irq(host
->irq
, host
);
1983 dma_release_channel(host
->tx_chan
);
1985 dma_release_channel(host
->rx_chan
);
1986 pm_runtime_put_sync(host
->dev
);
1987 pm_runtime_disable(host
->dev
);
1988 clk_put(host
->fclk
);
1990 clk_disable_unprepare(host
->dbclk
);
1991 clk_put(host
->dbclk
);
1994 iounmap(host
->base
);
1995 platform_set_drvdata(pdev
, NULL
);
1998 omap_hsmmc_gpio_free(pdata
);
2000 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2002 release_mem_region(res
->start
, resource_size(res
));
2006 static int __devexit
omap_hsmmc_remove(struct platform_device
*pdev
)
2008 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2009 struct resource
*res
;
2011 pm_runtime_get_sync(host
->dev
);
2012 mmc_remove_host(host
->mmc
);
2014 omap_hsmmc_reg_put(host
);
2015 if (host
->pdata
->cleanup
)
2016 host
->pdata
->cleanup(&pdev
->dev
);
2017 free_irq(host
->irq
, host
);
2018 if (mmc_slot(host
).card_detect_irq
)
2019 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2022 dma_release_channel(host
->tx_chan
);
2024 dma_release_channel(host
->rx_chan
);
2026 pm_runtime_put_sync(host
->dev
);
2027 pm_runtime_disable(host
->dev
);
2028 clk_put(host
->fclk
);
2030 clk_disable_unprepare(host
->dbclk
);
2031 clk_put(host
->dbclk
);
2034 mmc_free_host(host
->mmc
);
2035 iounmap(host
->base
);
2036 omap_hsmmc_gpio_free(pdev
->dev
.platform_data
);
2038 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2040 release_mem_region(res
->start
, resource_size(res
));
2041 platform_set_drvdata(pdev
, NULL
);
2047 static int omap_hsmmc_suspend(struct device
*dev
)
2050 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
2055 if (host
&& host
->suspended
)
2058 pm_runtime_get_sync(host
->dev
);
2059 host
->suspended
= 1;
2060 if (host
->pdata
->suspend
) {
2061 ret
= host
->pdata
->suspend(dev
, host
->slot_id
);
2063 dev_dbg(dev
, "Unable to handle MMC board"
2064 " level suspend\n");
2065 host
->suspended
= 0;
2069 ret
= mmc_suspend_host(host
->mmc
);
2072 host
->suspended
= 0;
2073 if (host
->pdata
->resume
) {
2074 ret
= host
->pdata
->resume(dev
, host
->slot_id
);
2076 dev_dbg(dev
, "Unmask interrupt failed\n");
2081 if (!(host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
)) {
2082 omap_hsmmc_disable_irq(host
);
2083 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
2084 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDBP
);
2088 clk_disable_unprepare(host
->dbclk
);
2090 pm_runtime_put_sync(host
->dev
);
2094 /* Routine to resume the MMC device */
2095 static int omap_hsmmc_resume(struct device
*dev
)
2098 struct omap_hsmmc_host
*host
= dev_get_drvdata(dev
);
2103 if (host
&& !host
->suspended
)
2106 pm_runtime_get_sync(host
->dev
);
2109 clk_prepare_enable(host
->dbclk
);
2111 if (!(host
->mmc
->pm_flags
& MMC_PM_KEEP_POWER
))
2112 omap_hsmmc_conf_bus_power(host
);
2114 if (host
->pdata
->resume
) {
2115 ret
= host
->pdata
->resume(dev
, host
->slot_id
);
2117 dev_dbg(dev
, "Unmask interrupt failed\n");
2120 omap_hsmmc_protect_card(host
);
2122 /* Notify the core to resume the host */
2123 ret
= mmc_resume_host(host
->mmc
);
2125 host
->suspended
= 0;
2127 pm_runtime_mark_last_busy(host
->dev
);
2128 pm_runtime_put_autosuspend(host
->dev
);
2135 #define omap_hsmmc_suspend NULL
2136 #define omap_hsmmc_resume NULL
2139 static int omap_hsmmc_runtime_suspend(struct device
*dev
)
2141 struct omap_hsmmc_host
*host
;
2143 host
= platform_get_drvdata(to_platform_device(dev
));
2144 omap_hsmmc_context_save(host
);
2145 dev_dbg(dev
, "disabled\n");
2150 static int omap_hsmmc_runtime_resume(struct device
*dev
)
2152 struct omap_hsmmc_host
*host
;
2154 host
= platform_get_drvdata(to_platform_device(dev
));
2155 omap_hsmmc_context_restore(host
);
2156 dev_dbg(dev
, "enabled\n");
2161 static struct dev_pm_ops omap_hsmmc_dev_pm_ops
= {
2162 .suspend
= omap_hsmmc_suspend
,
2163 .resume
= omap_hsmmc_resume
,
2164 .runtime_suspend
= omap_hsmmc_runtime_suspend
,
2165 .runtime_resume
= omap_hsmmc_runtime_resume
,
2168 static struct platform_driver omap_hsmmc_driver
= {
2169 .probe
= omap_hsmmc_probe
,
2170 .remove
= __devexit_p(omap_hsmmc_remove
),
2172 .name
= DRIVER_NAME
,
2173 .owner
= THIS_MODULE
,
2174 .pm
= &omap_hsmmc_dev_pm_ops
,
2175 .of_match_table
= of_match_ptr(omap_mmc_of_match
),
2179 module_platform_driver(omap_hsmmc_driver
);
2180 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2181 MODULE_LICENSE("GPL");
2182 MODULE_ALIAS("platform:" DRIVER_NAME
);
2183 MODULE_AUTHOR("Texas Instruments Inc");