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mmc: omap_hsmmc: consolidate error report handling of HSMMC IRQ
[deliverable/linux.git] / drivers / mmc / host / omap_hsmmc.c
1 /*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/kernel.h>
21 #include <linux/debugfs.h>
22 #include <linux/dmaengine.h>
23 #include <linux/seq_file.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/timer.h>
29 #include <linux/clk.h>
30 #include <linux/of.h>
31 #include <linux/of_gpio.h>
32 #include <linux/of_device.h>
33 #include <linux/omap-dma.h>
34 #include <linux/mmc/host.h>
35 #include <linux/mmc/core.h>
36 #include <linux/mmc/mmc.h>
37 #include <linux/io.h>
38 #include <linux/gpio.h>
39 #include <linux/regulator/consumer.h>
40 #include <linux/pm_runtime.h>
41 #include <mach/hardware.h>
42 #include <plat/board.h>
43 #include <plat/mmc.h>
44 #include <plat/cpu.h>
45
46 /* OMAP HSMMC Host Controller Registers */
47 #define OMAP_HSMMC_SYSSTATUS 0x0014
48 #define OMAP_HSMMC_CON 0x002C
49 #define OMAP_HSMMC_BLK 0x0104
50 #define OMAP_HSMMC_ARG 0x0108
51 #define OMAP_HSMMC_CMD 0x010C
52 #define OMAP_HSMMC_RSP10 0x0110
53 #define OMAP_HSMMC_RSP32 0x0114
54 #define OMAP_HSMMC_RSP54 0x0118
55 #define OMAP_HSMMC_RSP76 0x011C
56 #define OMAP_HSMMC_DATA 0x0120
57 #define OMAP_HSMMC_HCTL 0x0128
58 #define OMAP_HSMMC_SYSCTL 0x012C
59 #define OMAP_HSMMC_STAT 0x0130
60 #define OMAP_HSMMC_IE 0x0134
61 #define OMAP_HSMMC_ISE 0x0138
62 #define OMAP_HSMMC_CAPA 0x0140
63
64 #define VS18 (1 << 26)
65 #define VS30 (1 << 25)
66 #define SDVS18 (0x5 << 9)
67 #define SDVS30 (0x6 << 9)
68 #define SDVS33 (0x7 << 9)
69 #define SDVS_MASK 0x00000E00
70 #define SDVSCLR 0xFFFFF1FF
71 #define SDVSDET 0x00000400
72 #define AUTOIDLE 0x1
73 #define SDBP (1 << 8)
74 #define DTO 0xe
75 #define ICE 0x1
76 #define ICS 0x2
77 #define CEN (1 << 2)
78 #define CLKD_MASK 0x0000FFC0
79 #define CLKD_SHIFT 6
80 #define DTO_MASK 0x000F0000
81 #define DTO_SHIFT 16
82 #define INT_EN_MASK 0x307F0033
83 #define BWR_ENABLE (1 << 4)
84 #define BRR_ENABLE (1 << 5)
85 #define DTO_ENABLE (1 << 20)
86 #define INIT_STREAM (1 << 1)
87 #define DP_SELECT (1 << 21)
88 #define DDIR (1 << 4)
89 #define DMA_EN 0x1
90 #define MSBS (1 << 5)
91 #define BCE (1 << 1)
92 #define FOUR_BIT (1 << 1)
93 #define DDR (1 << 19)
94 #define DW8 (1 << 5)
95 #define CC 0x1
96 #define TC 0x02
97 #define OD 0x1
98 #define ERR (1 << 15)
99 #define CMD_TIMEOUT (1 << 16)
100 #define DATA_TIMEOUT (1 << 20)
101 #define CMD_CRC (1 << 17)
102 #define DATA_CRC (1 << 21)
103 #define CARD_ERR (1 << 28)
104 #define STAT_CLEAR 0xFFFFFFFF
105 #define INIT_STREAM_CMD 0x00000000
106 #define DUAL_VOLT_OCR_BIT 7
107 #define SRC (1 << 25)
108 #define SRD (1 << 26)
109 #define SOFTRESET (1 << 1)
110 #define RESETDONE (1 << 0)
111
112 #define MMC_AUTOSUSPEND_DELAY 100
113 #define MMC_TIMEOUT_MS 20
114 #define OMAP_MMC_MIN_CLOCK 400000
115 #define OMAP_MMC_MAX_CLOCK 52000000
116 #define DRIVER_NAME "omap_hsmmc"
117
118 /*
119 * One controller can have multiple slots, like on some omap boards using
120 * omap.c controller driver. Luckily this is not currently done on any known
121 * omap_hsmmc.c device.
122 */
123 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
124
125 /*
126 * MMC Host controller read/write API's
127 */
128 #define OMAP_HSMMC_READ(base, reg) \
129 __raw_readl((base) + OMAP_HSMMC_##reg)
130
131 #define OMAP_HSMMC_WRITE(base, reg, val) \
132 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
133
134 struct omap_hsmmc_next {
135 unsigned int dma_len;
136 s32 cookie;
137 };
138
139 struct omap_hsmmc_host {
140 struct device *dev;
141 struct mmc_host *mmc;
142 struct mmc_request *mrq;
143 struct mmc_command *cmd;
144 struct mmc_data *data;
145 struct clk *fclk;
146 struct clk *dbclk;
147 /*
148 * vcc == configured supply
149 * vcc_aux == optional
150 * - MMC1, supply for DAT4..DAT7
151 * - MMC2/MMC2, external level shifter voltage supply, for
152 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
153 */
154 struct regulator *vcc;
155 struct regulator *vcc_aux;
156 void __iomem *base;
157 resource_size_t mapbase;
158 spinlock_t irq_lock; /* Prevent races with irq handler */
159 unsigned int dma_len;
160 unsigned int dma_sg_idx;
161 unsigned char bus_mode;
162 unsigned char power_mode;
163 int suspended;
164 int irq;
165 int use_dma, dma_ch;
166 struct dma_chan *tx_chan;
167 struct dma_chan *rx_chan;
168 int slot_id;
169 int response_busy;
170 int context_loss;
171 int protect_card;
172 int reqs_blocked;
173 int use_reg;
174 int req_in_progress;
175 struct omap_hsmmc_next next_data;
176
177 struct omap_mmc_platform_data *pdata;
178 };
179
180 static int omap_hsmmc_card_detect(struct device *dev, int slot)
181 {
182 struct omap_mmc_platform_data *mmc = dev->platform_data;
183
184 /* NOTE: assumes card detect signal is active-low */
185 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
186 }
187
188 static int omap_hsmmc_get_wp(struct device *dev, int slot)
189 {
190 struct omap_mmc_platform_data *mmc = dev->platform_data;
191
192 /* NOTE: assumes write protect signal is active-high */
193 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
194 }
195
196 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
197 {
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202 }
203
204 #ifdef CONFIG_PM
205
206 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
207 {
208 struct omap_mmc_platform_data *mmc = dev->platform_data;
209
210 disable_irq(mmc->slots[0].card_detect_irq);
211 return 0;
212 }
213
214 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
215 {
216 struct omap_mmc_platform_data *mmc = dev->platform_data;
217
218 enable_irq(mmc->slots[0].card_detect_irq);
219 return 0;
220 }
221
222 #else
223
224 #define omap_hsmmc_suspend_cdirq NULL
225 #define omap_hsmmc_resume_cdirq NULL
226
227 #endif
228
229 #ifdef CONFIG_REGULATOR
230
231 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
232 int vdd)
233 {
234 struct omap_hsmmc_host *host =
235 platform_get_drvdata(to_platform_device(dev));
236 int ret = 0;
237
238 /*
239 * If we don't see a Vcc regulator, assume it's a fixed
240 * voltage always-on regulator.
241 */
242 if (!host->vcc)
243 return 0;
244 /*
245 * With DT, never turn OFF the regulator. This is because
246 * the pbias cell programming support is still missing when
247 * booting with Device tree
248 */
249 if (dev->of_node && !vdd)
250 return 0;
251
252 if (mmc_slot(host).before_set_reg)
253 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
254
255 /*
256 * Assume Vcc regulator is used only to power the card ... OMAP
257 * VDDS is used to power the pins, optionally with a transceiver to
258 * support cards using voltages other than VDDS (1.8V nominal). When a
259 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
260 *
261 * In some cases this regulator won't support enable/disable;
262 * e.g. it's a fixed rail for a WLAN chip.
263 *
264 * In other cases vcc_aux switches interface power. Example, for
265 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
266 * chips/cards need an interface voltage rail too.
267 */
268 if (power_on) {
269 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
270 /* Enable interface voltage rail, if needed */
271 if (ret == 0 && host->vcc_aux) {
272 ret = regulator_enable(host->vcc_aux);
273 if (ret < 0)
274 ret = mmc_regulator_set_ocr(host->mmc,
275 host->vcc, 0);
276 }
277 } else {
278 /* Shut down the rail */
279 if (host->vcc_aux)
280 ret = regulator_disable(host->vcc_aux);
281 if (!ret) {
282 /* Then proceed to shut down the local regulator */
283 ret = mmc_regulator_set_ocr(host->mmc,
284 host->vcc, 0);
285 }
286 }
287
288 if (mmc_slot(host).after_set_reg)
289 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
290
291 return ret;
292 }
293
294 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
295 {
296 struct regulator *reg;
297 int ocr_value = 0;
298
299 reg = regulator_get(host->dev, "vmmc");
300 if (IS_ERR(reg)) {
301 dev_dbg(host->dev, "vmmc regulator missing\n");
302 return PTR_ERR(reg);
303 } else {
304 mmc_slot(host).set_power = omap_hsmmc_set_power;
305 host->vcc = reg;
306 ocr_value = mmc_regulator_get_ocrmask(reg);
307 if (!mmc_slot(host).ocr_mask) {
308 mmc_slot(host).ocr_mask = ocr_value;
309 } else {
310 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
311 dev_err(host->dev, "ocrmask %x is not supported\n",
312 mmc_slot(host).ocr_mask);
313 mmc_slot(host).ocr_mask = 0;
314 return -EINVAL;
315 }
316 }
317
318 /* Allow an aux regulator */
319 reg = regulator_get(host->dev, "vmmc_aux");
320 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
321
322 /* For eMMC do not power off when not in sleep state */
323 if (mmc_slot(host).no_regulator_off_init)
324 return 0;
325 /*
326 * UGLY HACK: workaround regulator framework bugs.
327 * When the bootloader leaves a supply active, it's
328 * initialized with zero usecount ... and we can't
329 * disable it without first enabling it. Until the
330 * framework is fixed, we need a workaround like this
331 * (which is safe for MMC, but not in general).
332 */
333 if (regulator_is_enabled(host->vcc) > 0 ||
334 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
335 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
336
337 mmc_slot(host).set_power(host->dev, host->slot_id,
338 1, vdd);
339 mmc_slot(host).set_power(host->dev, host->slot_id,
340 0, 0);
341 }
342 }
343
344 return 0;
345 }
346
347 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
348 {
349 regulator_put(host->vcc);
350 regulator_put(host->vcc_aux);
351 mmc_slot(host).set_power = NULL;
352 }
353
354 static inline int omap_hsmmc_have_reg(void)
355 {
356 return 1;
357 }
358
359 #else
360
361 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
362 {
363 return -EINVAL;
364 }
365
366 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
367 {
368 }
369
370 static inline int omap_hsmmc_have_reg(void)
371 {
372 return 0;
373 }
374
375 #endif
376
377 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
378 {
379 int ret;
380
381 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
382 if (pdata->slots[0].cover)
383 pdata->slots[0].get_cover_state =
384 omap_hsmmc_get_cover_state;
385 else
386 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
387 pdata->slots[0].card_detect_irq =
388 gpio_to_irq(pdata->slots[0].switch_pin);
389 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
390 if (ret)
391 return ret;
392 ret = gpio_direction_input(pdata->slots[0].switch_pin);
393 if (ret)
394 goto err_free_sp;
395 } else
396 pdata->slots[0].switch_pin = -EINVAL;
397
398 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
399 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
400 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
401 if (ret)
402 goto err_free_cd;
403 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
404 if (ret)
405 goto err_free_wp;
406 } else
407 pdata->slots[0].gpio_wp = -EINVAL;
408
409 return 0;
410
411 err_free_wp:
412 gpio_free(pdata->slots[0].gpio_wp);
413 err_free_cd:
414 if (gpio_is_valid(pdata->slots[0].switch_pin))
415 err_free_sp:
416 gpio_free(pdata->slots[0].switch_pin);
417 return ret;
418 }
419
420 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
421 {
422 if (gpio_is_valid(pdata->slots[0].gpio_wp))
423 gpio_free(pdata->slots[0].gpio_wp);
424 if (gpio_is_valid(pdata->slots[0].switch_pin))
425 gpio_free(pdata->slots[0].switch_pin);
426 }
427
428 /*
429 * Start clock to the card
430 */
431 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
432 {
433 OMAP_HSMMC_WRITE(host->base, SYSCTL,
434 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
435 }
436
437 /*
438 * Stop clock to the card
439 */
440 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
441 {
442 OMAP_HSMMC_WRITE(host->base, SYSCTL,
443 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
444 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
445 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
446 }
447
448 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
449 struct mmc_command *cmd)
450 {
451 unsigned int irq_mask;
452
453 if (host->use_dma)
454 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
455 else
456 irq_mask = INT_EN_MASK;
457
458 /* Disable timeout for erases */
459 if (cmd->opcode == MMC_ERASE)
460 irq_mask &= ~DTO_ENABLE;
461
462 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
463 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
464 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
465 }
466
467 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
468 {
469 OMAP_HSMMC_WRITE(host->base, ISE, 0);
470 OMAP_HSMMC_WRITE(host->base, IE, 0);
471 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
472 }
473
474 /* Calculate divisor for the given clock frequency */
475 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
476 {
477 u16 dsor = 0;
478
479 if (ios->clock) {
480 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
481 if (dsor > 250)
482 dsor = 250;
483 }
484
485 return dsor;
486 }
487
488 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
489 {
490 struct mmc_ios *ios = &host->mmc->ios;
491 unsigned long regval;
492 unsigned long timeout;
493
494 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
495
496 omap_hsmmc_stop_clock(host);
497
498 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
499 regval = regval & ~(CLKD_MASK | DTO_MASK);
500 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
501 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
502 OMAP_HSMMC_WRITE(host->base, SYSCTL,
503 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
504
505 /* Wait till the ICS bit is set */
506 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
507 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
508 && time_before(jiffies, timeout))
509 cpu_relax();
510
511 omap_hsmmc_start_clock(host);
512 }
513
514 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
515 {
516 struct mmc_ios *ios = &host->mmc->ios;
517 u32 con;
518
519 con = OMAP_HSMMC_READ(host->base, CON);
520 if (ios->timing == MMC_TIMING_UHS_DDR50)
521 con |= DDR; /* configure in DDR mode */
522 else
523 con &= ~DDR;
524 switch (ios->bus_width) {
525 case MMC_BUS_WIDTH_8:
526 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
527 break;
528 case MMC_BUS_WIDTH_4:
529 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
530 OMAP_HSMMC_WRITE(host->base, HCTL,
531 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
532 break;
533 case MMC_BUS_WIDTH_1:
534 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
535 OMAP_HSMMC_WRITE(host->base, HCTL,
536 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
537 break;
538 }
539 }
540
541 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
542 {
543 struct mmc_ios *ios = &host->mmc->ios;
544 u32 con;
545
546 con = OMAP_HSMMC_READ(host->base, CON);
547 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
548 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
549 else
550 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
551 }
552
553 #ifdef CONFIG_PM
554
555 /*
556 * Restore the MMC host context, if it was lost as result of a
557 * power state change.
558 */
559 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
560 {
561 struct mmc_ios *ios = &host->mmc->ios;
562 struct omap_mmc_platform_data *pdata = host->pdata;
563 int context_loss = 0;
564 u32 hctl, capa;
565 unsigned long timeout;
566
567 if (pdata->get_context_loss_count) {
568 context_loss = pdata->get_context_loss_count(host->dev);
569 if (context_loss < 0)
570 return 1;
571 }
572
573 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
574 context_loss == host->context_loss ? "not " : "");
575 if (host->context_loss == context_loss)
576 return 1;
577
578 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
579 return 1;
580
581 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
582 if (host->power_mode != MMC_POWER_OFF &&
583 (1 << ios->vdd) <= MMC_VDD_23_24)
584 hctl = SDVS18;
585 else
586 hctl = SDVS30;
587 capa = VS30 | VS18;
588 } else {
589 hctl = SDVS18;
590 capa = VS18;
591 }
592
593 OMAP_HSMMC_WRITE(host->base, HCTL,
594 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
595
596 OMAP_HSMMC_WRITE(host->base, CAPA,
597 OMAP_HSMMC_READ(host->base, CAPA) | capa);
598
599 OMAP_HSMMC_WRITE(host->base, HCTL,
600 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
601
602 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
603 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
604 && time_before(jiffies, timeout))
605 ;
606
607 omap_hsmmc_disable_irq(host);
608
609 /* Do not initialize card-specific things if the power is off */
610 if (host->power_mode == MMC_POWER_OFF)
611 goto out;
612
613 omap_hsmmc_set_bus_width(host);
614
615 omap_hsmmc_set_clock(host);
616
617 omap_hsmmc_set_bus_mode(host);
618
619 out:
620 host->context_loss = context_loss;
621
622 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
623 return 0;
624 }
625
626 /*
627 * Save the MMC host context (store the number of power state changes so far).
628 */
629 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
630 {
631 struct omap_mmc_platform_data *pdata = host->pdata;
632 int context_loss;
633
634 if (pdata->get_context_loss_count) {
635 context_loss = pdata->get_context_loss_count(host->dev);
636 if (context_loss < 0)
637 return;
638 host->context_loss = context_loss;
639 }
640 }
641
642 #else
643
644 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
645 {
646 return 0;
647 }
648
649 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
650 {
651 }
652
653 #endif
654
655 /*
656 * Send init stream sequence to card
657 * before sending IDLE command
658 */
659 static void send_init_stream(struct omap_hsmmc_host *host)
660 {
661 int reg = 0;
662 unsigned long timeout;
663
664 if (host->protect_card)
665 return;
666
667 disable_irq(host->irq);
668
669 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
670 OMAP_HSMMC_WRITE(host->base, CON,
671 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
672 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
673
674 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
675 while ((reg != CC) && time_before(jiffies, timeout))
676 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
677
678 OMAP_HSMMC_WRITE(host->base, CON,
679 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
680
681 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
682 OMAP_HSMMC_READ(host->base, STAT);
683
684 enable_irq(host->irq);
685 }
686
687 static inline
688 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
689 {
690 int r = 1;
691
692 if (mmc_slot(host).get_cover_state)
693 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
694 return r;
695 }
696
697 static ssize_t
698 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
699 char *buf)
700 {
701 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
702 struct omap_hsmmc_host *host = mmc_priv(mmc);
703
704 return sprintf(buf, "%s\n",
705 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
706 }
707
708 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
709
710 static ssize_t
711 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
712 char *buf)
713 {
714 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
715 struct omap_hsmmc_host *host = mmc_priv(mmc);
716
717 return sprintf(buf, "%s\n", mmc_slot(host).name);
718 }
719
720 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
721
722 /*
723 * Configure the response type and send the cmd.
724 */
725 static void
726 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
727 struct mmc_data *data)
728 {
729 int cmdreg = 0, resptype = 0, cmdtype = 0;
730
731 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
732 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
733 host->cmd = cmd;
734
735 omap_hsmmc_enable_irq(host, cmd);
736
737 host->response_busy = 0;
738 if (cmd->flags & MMC_RSP_PRESENT) {
739 if (cmd->flags & MMC_RSP_136)
740 resptype = 1;
741 else if (cmd->flags & MMC_RSP_BUSY) {
742 resptype = 3;
743 host->response_busy = 1;
744 } else
745 resptype = 2;
746 }
747
748 /*
749 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
750 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
751 * a val of 0x3, rest 0x0.
752 */
753 if (cmd == host->mrq->stop)
754 cmdtype = 0x3;
755
756 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
757
758 if (data) {
759 cmdreg |= DP_SELECT | MSBS | BCE;
760 if (data->flags & MMC_DATA_READ)
761 cmdreg |= DDIR;
762 else
763 cmdreg &= ~(DDIR);
764 }
765
766 if (host->use_dma)
767 cmdreg |= DMA_EN;
768
769 host->req_in_progress = 1;
770
771 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
772 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
773 }
774
775 static int
776 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
777 {
778 if (data->flags & MMC_DATA_WRITE)
779 return DMA_TO_DEVICE;
780 else
781 return DMA_FROM_DEVICE;
782 }
783
784 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
785 struct mmc_data *data)
786 {
787 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
788 }
789
790 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
791 {
792 int dma_ch;
793 unsigned long flags;
794
795 spin_lock_irqsave(&host->irq_lock, flags);
796 host->req_in_progress = 0;
797 dma_ch = host->dma_ch;
798 spin_unlock_irqrestore(&host->irq_lock, flags);
799
800 omap_hsmmc_disable_irq(host);
801 /* Do not complete the request if DMA is still in progress */
802 if (mrq->data && host->use_dma && dma_ch != -1)
803 return;
804 host->mrq = NULL;
805 mmc_request_done(host->mmc, mrq);
806 }
807
808 /*
809 * Notify the transfer complete to MMC core
810 */
811 static void
812 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
813 {
814 if (!data) {
815 struct mmc_request *mrq = host->mrq;
816
817 /* TC before CC from CMD6 - don't know why, but it happens */
818 if (host->cmd && host->cmd->opcode == 6 &&
819 host->response_busy) {
820 host->response_busy = 0;
821 return;
822 }
823
824 omap_hsmmc_request_done(host, mrq);
825 return;
826 }
827
828 host->data = NULL;
829
830 if (!data->error)
831 data->bytes_xfered += data->blocks * (data->blksz);
832 else
833 data->bytes_xfered = 0;
834
835 if (!data->stop) {
836 omap_hsmmc_request_done(host, data->mrq);
837 return;
838 }
839 omap_hsmmc_start_command(host, data->stop, NULL);
840 }
841
842 /*
843 * Notify the core about command completion
844 */
845 static void
846 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
847 {
848 host->cmd = NULL;
849
850 if (cmd->flags & MMC_RSP_PRESENT) {
851 if (cmd->flags & MMC_RSP_136) {
852 /* response type 2 */
853 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
854 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
855 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
856 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
857 } else {
858 /* response types 1, 1b, 3, 4, 5, 6 */
859 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
860 }
861 }
862 if ((host->data == NULL && !host->response_busy) || cmd->error)
863 omap_hsmmc_request_done(host, cmd->mrq);
864 }
865
866 /*
867 * DMA clean up for command errors
868 */
869 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
870 {
871 int dma_ch;
872 unsigned long flags;
873
874 host->data->error = errno;
875
876 spin_lock_irqsave(&host->irq_lock, flags);
877 dma_ch = host->dma_ch;
878 host->dma_ch = -1;
879 spin_unlock_irqrestore(&host->irq_lock, flags);
880
881 if (host->use_dma && dma_ch != -1) {
882 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
883
884 dmaengine_terminate_all(chan);
885 dma_unmap_sg(chan->device->dev,
886 host->data->sg, host->data->sg_len,
887 omap_hsmmc_get_dma_dir(host, host->data));
888
889 host->data->host_cookie = 0;
890 }
891 host->data = NULL;
892 }
893
894 /*
895 * Readable error output
896 */
897 #ifdef CONFIG_MMC_DEBUG
898 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
899 {
900 /* --- means reserved bit without definition at documentation */
901 static const char *omap_hsmmc_status_bits[] = {
902 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
903 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
904 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
905 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
906 };
907 char res[256];
908 char *buf = res;
909 int len, i;
910
911 len = sprintf(buf, "MMC IRQ 0x%x :", status);
912 buf += len;
913
914 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
915 if (status & (1 << i)) {
916 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
917 buf += len;
918 }
919
920 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
921 }
922 #else
923 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
924 u32 status)
925 {
926 }
927 #endif /* CONFIG_MMC_DEBUG */
928
929 /*
930 * MMC controller internal state machines reset
931 *
932 * Used to reset command or data internal state machines, using respectively
933 * SRC or SRD bit of SYSCTL register
934 * Can be called from interrupt context
935 */
936 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
937 unsigned long bit)
938 {
939 unsigned long i = 0;
940 unsigned long limit = (loops_per_jiffy *
941 msecs_to_jiffies(MMC_TIMEOUT_MS));
942
943 OMAP_HSMMC_WRITE(host->base, SYSCTL,
944 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
945
946 /*
947 * OMAP4 ES2 and greater has an updated reset logic.
948 * Monitor a 0->1 transition first
949 */
950 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
951 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
952 && (i++ < limit))
953 cpu_relax();
954 }
955 i = 0;
956
957 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
958 (i++ < limit))
959 cpu_relax();
960
961 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
962 dev_err(mmc_dev(host->mmc),
963 "Timeout waiting on controller reset in %s\n",
964 __func__);
965 }
966
967 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, int err)
968 {
969 omap_hsmmc_reset_controller_fsm(host, SRC);
970 host->cmd->error = err;
971
972 if (host->data) {
973 omap_hsmmc_reset_controller_fsm(host, SRD);
974 omap_hsmmc_dma_cleanup(host, err);
975 }
976
977 }
978
979 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
980 {
981 struct mmc_data *data;
982 int end_cmd = 0, end_trans = 0;
983
984 data = host->data;
985 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
986
987 if (status & ERR) {
988 omap_hsmmc_dbg_report_irq(host, status);
989 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
990 hsmmc_command_incomplete(host, -ETIMEDOUT);
991 else if (status & (CMD_CRC | DATA_CRC))
992 hsmmc_command_incomplete(host, -EILSEQ);
993
994 end_cmd = 1;
995 if (host->data || host->response_busy) {
996 end_trans = 1;
997 host->response_busy = 0;
998 }
999 }
1000
1001 if (end_cmd || ((status & CC) && host->cmd))
1002 omap_hsmmc_cmd_done(host, host->cmd);
1003 if ((end_trans || (status & TC)) && host->mrq)
1004 omap_hsmmc_xfer_done(host, data);
1005 }
1006
1007 /*
1008 * MMC controller IRQ handler
1009 */
1010 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1011 {
1012 struct omap_hsmmc_host *host = dev_id;
1013 int status;
1014
1015 status = OMAP_HSMMC_READ(host->base, STAT);
1016 while (status & INT_EN_MASK && host->req_in_progress) {
1017 omap_hsmmc_do_irq(host, status);
1018
1019 /* Flush posted write */
1020 OMAP_HSMMC_WRITE(host->base, STAT, status);
1021 status = OMAP_HSMMC_READ(host->base, STAT);
1022 }
1023
1024 return IRQ_HANDLED;
1025 }
1026
1027 static void set_sd_bus_power(struct omap_hsmmc_host *host)
1028 {
1029 unsigned long i;
1030
1031 OMAP_HSMMC_WRITE(host->base, HCTL,
1032 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1033 for (i = 0; i < loops_per_jiffy; i++) {
1034 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1035 break;
1036 cpu_relax();
1037 }
1038 }
1039
1040 /*
1041 * Switch MMC interface voltage ... only relevant for MMC1.
1042 *
1043 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1044 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1045 * Some chips, like eMMC ones, use internal transceivers.
1046 */
1047 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
1048 {
1049 u32 reg_val = 0;
1050 int ret;
1051
1052 /* Disable the clocks */
1053 pm_runtime_put_sync(host->dev);
1054 if (host->dbclk)
1055 clk_disable_unprepare(host->dbclk);
1056
1057 /* Turn the power off */
1058 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1059
1060 /* Turn the power ON with given VDD 1.8 or 3.0v */
1061 if (!ret)
1062 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1063 vdd);
1064 pm_runtime_get_sync(host->dev);
1065 if (host->dbclk)
1066 clk_prepare_enable(host->dbclk);
1067
1068 if (ret != 0)
1069 goto err;
1070
1071 OMAP_HSMMC_WRITE(host->base, HCTL,
1072 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1073 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
1074
1075 /*
1076 * If a MMC dual voltage card is detected, the set_ios fn calls
1077 * this fn with VDD bit set for 1.8V. Upon card removal from the
1078 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1079 *
1080 * Cope with a bit of slop in the range ... per data sheets:
1081 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1082 * but recommended values are 1.71V to 1.89V
1083 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1084 * but recommended values are 2.7V to 3.3V
1085 *
1086 * Board setup code shouldn't permit anything very out-of-range.
1087 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1088 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1089 */
1090 if ((1 << vdd) <= MMC_VDD_23_24)
1091 reg_val |= SDVS18;
1092 else
1093 reg_val |= SDVS30;
1094
1095 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
1096 set_sd_bus_power(host);
1097
1098 return 0;
1099 err:
1100 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1101 return ret;
1102 }
1103
1104 /* Protect the card while the cover is open */
1105 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1106 {
1107 if (!mmc_slot(host).get_cover_state)
1108 return;
1109
1110 host->reqs_blocked = 0;
1111 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1112 if (host->protect_card) {
1113 dev_info(host->dev, "%s: cover is closed, "
1114 "card is now accessible\n",
1115 mmc_hostname(host->mmc));
1116 host->protect_card = 0;
1117 }
1118 } else {
1119 if (!host->protect_card) {
1120 dev_info(host->dev, "%s: cover is open, "
1121 "card is now inaccessible\n",
1122 mmc_hostname(host->mmc));
1123 host->protect_card = 1;
1124 }
1125 }
1126 }
1127
1128 /*
1129 * irq handler to notify the core about card insertion/removal
1130 */
1131 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
1132 {
1133 struct omap_hsmmc_host *host = dev_id;
1134 struct omap_mmc_slot_data *slot = &mmc_slot(host);
1135 int carddetect;
1136
1137 if (host->suspended)
1138 return IRQ_HANDLED;
1139
1140 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
1141
1142 if (slot->card_detect)
1143 carddetect = slot->card_detect(host->dev, host->slot_id);
1144 else {
1145 omap_hsmmc_protect_card(host);
1146 carddetect = -ENOSYS;
1147 }
1148
1149 if (carddetect)
1150 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1151 else
1152 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1153 return IRQ_HANDLED;
1154 }
1155
1156 static void omap_hsmmc_dma_callback(void *param)
1157 {
1158 struct omap_hsmmc_host *host = param;
1159 struct dma_chan *chan;
1160 struct mmc_data *data;
1161 int req_in_progress;
1162
1163 spin_lock_irq(&host->irq_lock);
1164 if (host->dma_ch < 0) {
1165 spin_unlock_irq(&host->irq_lock);
1166 return;
1167 }
1168
1169 data = host->mrq->data;
1170 chan = omap_hsmmc_get_dma_chan(host, data);
1171 if (!data->host_cookie)
1172 dma_unmap_sg(chan->device->dev,
1173 data->sg, data->sg_len,
1174 omap_hsmmc_get_dma_dir(host, data));
1175
1176 req_in_progress = host->req_in_progress;
1177 host->dma_ch = -1;
1178 spin_unlock_irq(&host->irq_lock);
1179
1180 /* If DMA has finished after TC, complete the request */
1181 if (!req_in_progress) {
1182 struct mmc_request *mrq = host->mrq;
1183
1184 host->mrq = NULL;
1185 mmc_request_done(host->mmc, mrq);
1186 }
1187 }
1188
1189 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1190 struct mmc_data *data,
1191 struct omap_hsmmc_next *next,
1192 struct dma_chan *chan)
1193 {
1194 int dma_len;
1195
1196 if (!next && data->host_cookie &&
1197 data->host_cookie != host->next_data.cookie) {
1198 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
1199 " host->next_data.cookie %d\n",
1200 __func__, data->host_cookie, host->next_data.cookie);
1201 data->host_cookie = 0;
1202 }
1203
1204 /* Check if next job is already prepared */
1205 if (next ||
1206 (!next && data->host_cookie != host->next_data.cookie)) {
1207 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
1208 omap_hsmmc_get_dma_dir(host, data));
1209
1210 } else {
1211 dma_len = host->next_data.dma_len;
1212 host->next_data.dma_len = 0;
1213 }
1214
1215
1216 if (dma_len == 0)
1217 return -EINVAL;
1218
1219 if (next) {
1220 next->dma_len = dma_len;
1221 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1222 } else
1223 host->dma_len = dma_len;
1224
1225 return 0;
1226 }
1227
1228 /*
1229 * Routine to configure and start DMA for the MMC card
1230 */
1231 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1232 struct mmc_request *req)
1233 {
1234 struct dma_slave_config cfg;
1235 struct dma_async_tx_descriptor *tx;
1236 int ret = 0, i;
1237 struct mmc_data *data = req->data;
1238 struct dma_chan *chan;
1239
1240 /* Sanity check: all the SG entries must be aligned by block size. */
1241 for (i = 0; i < data->sg_len; i++) {
1242 struct scatterlist *sgl;
1243
1244 sgl = data->sg + i;
1245 if (sgl->length % data->blksz)
1246 return -EINVAL;
1247 }
1248 if ((data->blksz % 4) != 0)
1249 /* REVISIT: The MMC buffer increments only when MSB is written.
1250 * Return error for blksz which is non multiple of four.
1251 */
1252 return -EINVAL;
1253
1254 BUG_ON(host->dma_ch != -1);
1255
1256 chan = omap_hsmmc_get_dma_chan(host, data);
1257
1258 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1259 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1260 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1261 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1262 cfg.src_maxburst = data->blksz / 4;
1263 cfg.dst_maxburst = data->blksz / 4;
1264
1265 ret = dmaengine_slave_config(chan, &cfg);
1266 if (ret)
1267 return ret;
1268
1269 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
1270 if (ret)
1271 return ret;
1272
1273 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1274 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1275 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1276 if (!tx) {
1277 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1278 /* FIXME: cleanup */
1279 return -1;
1280 }
1281
1282 tx->callback = omap_hsmmc_dma_callback;
1283 tx->callback_param = host;
1284
1285 /* Does not fail */
1286 dmaengine_submit(tx);
1287
1288 host->dma_ch = 1;
1289
1290 dma_async_issue_pending(chan);
1291
1292 return 0;
1293 }
1294
1295 static void set_data_timeout(struct omap_hsmmc_host *host,
1296 unsigned int timeout_ns,
1297 unsigned int timeout_clks)
1298 {
1299 unsigned int timeout, cycle_ns;
1300 uint32_t reg, clkd, dto = 0;
1301
1302 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1303 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1304 if (clkd == 0)
1305 clkd = 1;
1306
1307 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
1308 timeout = timeout_ns / cycle_ns;
1309 timeout += timeout_clks;
1310 if (timeout) {
1311 while ((timeout & 0x80000000) == 0) {
1312 dto += 1;
1313 timeout <<= 1;
1314 }
1315 dto = 31 - dto;
1316 timeout <<= 1;
1317 if (timeout && dto)
1318 dto += 1;
1319 if (dto >= 13)
1320 dto -= 13;
1321 else
1322 dto = 0;
1323 if (dto > 14)
1324 dto = 14;
1325 }
1326
1327 reg &= ~DTO_MASK;
1328 reg |= dto << DTO_SHIFT;
1329 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1330 }
1331
1332 /*
1333 * Configure block length for MMC/SD cards and initiate the transfer.
1334 */
1335 static int
1336 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
1337 {
1338 int ret;
1339 host->data = req->data;
1340
1341 if (req->data == NULL) {
1342 OMAP_HSMMC_WRITE(host->base, BLK, 0);
1343 /*
1344 * Set an arbitrary 100ms data timeout for commands with
1345 * busy signal.
1346 */
1347 if (req->cmd->flags & MMC_RSP_BUSY)
1348 set_data_timeout(host, 100000000U, 0);
1349 return 0;
1350 }
1351
1352 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1353 | (req->data->blocks << 16));
1354 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
1355
1356 if (host->use_dma) {
1357 ret = omap_hsmmc_start_dma_transfer(host, req);
1358 if (ret != 0) {
1359 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1360 return ret;
1361 }
1362 }
1363 return 0;
1364 }
1365
1366 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1367 int err)
1368 {
1369 struct omap_hsmmc_host *host = mmc_priv(mmc);
1370 struct mmc_data *data = mrq->data;
1371
1372 if (host->use_dma && data->host_cookie) {
1373 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
1374
1375 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1376 omap_hsmmc_get_dma_dir(host, data));
1377 data->host_cookie = 0;
1378 }
1379 }
1380
1381 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1382 bool is_first_req)
1383 {
1384 struct omap_hsmmc_host *host = mmc_priv(mmc);
1385
1386 if (mrq->data->host_cookie) {
1387 mrq->data->host_cookie = 0;
1388 return ;
1389 }
1390
1391 if (host->use_dma) {
1392 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
1393
1394 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1395 &host->next_data, c))
1396 mrq->data->host_cookie = 0;
1397 }
1398 }
1399
1400 /*
1401 * Request function. for read/write operation
1402 */
1403 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
1404 {
1405 struct omap_hsmmc_host *host = mmc_priv(mmc);
1406 int err;
1407
1408 BUG_ON(host->req_in_progress);
1409 BUG_ON(host->dma_ch != -1);
1410 if (host->protect_card) {
1411 if (host->reqs_blocked < 3) {
1412 /*
1413 * Ensure the controller is left in a consistent
1414 * state by resetting the command and data state
1415 * machines.
1416 */
1417 omap_hsmmc_reset_controller_fsm(host, SRD);
1418 omap_hsmmc_reset_controller_fsm(host, SRC);
1419 host->reqs_blocked += 1;
1420 }
1421 req->cmd->error = -EBADF;
1422 if (req->data)
1423 req->data->error = -EBADF;
1424 req->cmd->retries = 0;
1425 mmc_request_done(mmc, req);
1426 return;
1427 } else if (host->reqs_blocked)
1428 host->reqs_blocked = 0;
1429 WARN_ON(host->mrq != NULL);
1430 host->mrq = req;
1431 err = omap_hsmmc_prepare_data(host, req);
1432 if (err) {
1433 req->cmd->error = err;
1434 if (req->data)
1435 req->data->error = err;
1436 host->mrq = NULL;
1437 mmc_request_done(mmc, req);
1438 return;
1439 }
1440
1441 omap_hsmmc_start_command(host, req->cmd, req->data);
1442 }
1443
1444 /* Routine to configure clock values. Exposed API to core */
1445 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1446 {
1447 struct omap_hsmmc_host *host = mmc_priv(mmc);
1448 int do_send_init_stream = 0;
1449
1450 pm_runtime_get_sync(host->dev);
1451
1452 if (ios->power_mode != host->power_mode) {
1453 switch (ios->power_mode) {
1454 case MMC_POWER_OFF:
1455 mmc_slot(host).set_power(host->dev, host->slot_id,
1456 0, 0);
1457 break;
1458 case MMC_POWER_UP:
1459 mmc_slot(host).set_power(host->dev, host->slot_id,
1460 1, ios->vdd);
1461 break;
1462 case MMC_POWER_ON:
1463 do_send_init_stream = 1;
1464 break;
1465 }
1466 host->power_mode = ios->power_mode;
1467 }
1468
1469 /* FIXME: set registers based only on changes to ios */
1470
1471 omap_hsmmc_set_bus_width(host);
1472
1473 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1474 /* Only MMC1 can interface at 3V without some flavor
1475 * of external transceiver; but they all handle 1.8V.
1476 */
1477 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1478 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1479 /*
1480 * With pbias cell programming missing, this
1481 * can't be allowed when booting with device
1482 * tree.
1483 */
1484 !host->dev->of_node) {
1485 /*
1486 * The mmc_select_voltage fn of the core does
1487 * not seem to set the power_mode to
1488 * MMC_POWER_UP upon recalculating the voltage.
1489 * vdd 1.8v.
1490 */
1491 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1492 dev_dbg(mmc_dev(host->mmc),
1493 "Switch operation failed\n");
1494 }
1495 }
1496
1497 omap_hsmmc_set_clock(host);
1498
1499 if (do_send_init_stream)
1500 send_init_stream(host);
1501
1502 omap_hsmmc_set_bus_mode(host);
1503
1504 pm_runtime_put_autosuspend(host->dev);
1505 }
1506
1507 static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1508 {
1509 struct omap_hsmmc_host *host = mmc_priv(mmc);
1510
1511 if (!mmc_slot(host).card_detect)
1512 return -ENOSYS;
1513 return mmc_slot(host).card_detect(host->dev, host->slot_id);
1514 }
1515
1516 static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1517 {
1518 struct omap_hsmmc_host *host = mmc_priv(mmc);
1519
1520 if (!mmc_slot(host).get_ro)
1521 return -ENOSYS;
1522 return mmc_slot(host).get_ro(host->dev, 0);
1523 }
1524
1525 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1526 {
1527 struct omap_hsmmc_host *host = mmc_priv(mmc);
1528
1529 if (mmc_slot(host).init_card)
1530 mmc_slot(host).init_card(card);
1531 }
1532
1533 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1534 {
1535 u32 hctl, capa, value;
1536
1537 /* Only MMC1 supports 3.0V */
1538 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1539 hctl = SDVS30;
1540 capa = VS30 | VS18;
1541 } else {
1542 hctl = SDVS18;
1543 capa = VS18;
1544 }
1545
1546 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1547 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1548
1549 value = OMAP_HSMMC_READ(host->base, CAPA);
1550 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1551
1552 /* Set SD bus power bit */
1553 set_sd_bus_power(host);
1554 }
1555
1556 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
1557 {
1558 struct omap_hsmmc_host *host = mmc_priv(mmc);
1559
1560 pm_runtime_get_sync(host->dev);
1561
1562 return 0;
1563 }
1564
1565 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
1566 {
1567 struct omap_hsmmc_host *host = mmc_priv(mmc);
1568
1569 pm_runtime_mark_last_busy(host->dev);
1570 pm_runtime_put_autosuspend(host->dev);
1571
1572 return 0;
1573 }
1574
1575 static const struct mmc_host_ops omap_hsmmc_ops = {
1576 .enable = omap_hsmmc_enable_fclk,
1577 .disable = omap_hsmmc_disable_fclk,
1578 .post_req = omap_hsmmc_post_req,
1579 .pre_req = omap_hsmmc_pre_req,
1580 .request = omap_hsmmc_request,
1581 .set_ios = omap_hsmmc_set_ios,
1582 .get_cd = omap_hsmmc_get_cd,
1583 .get_ro = omap_hsmmc_get_ro,
1584 .init_card = omap_hsmmc_init_card,
1585 /* NYET -- enable_sdio_irq */
1586 };
1587
1588 #ifdef CONFIG_DEBUG_FS
1589
1590 static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
1591 {
1592 struct mmc_host *mmc = s->private;
1593 struct omap_hsmmc_host *host = mmc_priv(mmc);
1594 int context_loss = 0;
1595
1596 if (host->pdata->get_context_loss_count)
1597 context_loss = host->pdata->get_context_loss_count(host->dev);
1598
1599 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1600 mmc->index, host->context_loss, context_loss);
1601
1602 if (host->suspended) {
1603 seq_printf(s, "host suspended, can't read registers\n");
1604 return 0;
1605 }
1606
1607 pm_runtime_get_sync(host->dev);
1608
1609 seq_printf(s, "CON:\t\t0x%08x\n",
1610 OMAP_HSMMC_READ(host->base, CON));
1611 seq_printf(s, "HCTL:\t\t0x%08x\n",
1612 OMAP_HSMMC_READ(host->base, HCTL));
1613 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1614 OMAP_HSMMC_READ(host->base, SYSCTL));
1615 seq_printf(s, "IE:\t\t0x%08x\n",
1616 OMAP_HSMMC_READ(host->base, IE));
1617 seq_printf(s, "ISE:\t\t0x%08x\n",
1618 OMAP_HSMMC_READ(host->base, ISE));
1619 seq_printf(s, "CAPA:\t\t0x%08x\n",
1620 OMAP_HSMMC_READ(host->base, CAPA));
1621
1622 pm_runtime_mark_last_busy(host->dev);
1623 pm_runtime_put_autosuspend(host->dev);
1624
1625 return 0;
1626 }
1627
1628 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
1629 {
1630 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
1631 }
1632
1633 static const struct file_operations mmc_regs_fops = {
1634 .open = omap_hsmmc_regs_open,
1635 .read = seq_read,
1636 .llseek = seq_lseek,
1637 .release = single_release,
1638 };
1639
1640 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1641 {
1642 if (mmc->debugfs_root)
1643 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1644 mmc, &mmc_regs_fops);
1645 }
1646
1647 #else
1648
1649 static void omap_hsmmc_debugfs(struct mmc_host *mmc)
1650 {
1651 }
1652
1653 #endif
1654
1655 #ifdef CONFIG_OF
1656 static u16 omap4_reg_offset = 0x100;
1657
1658 static const struct of_device_id omap_mmc_of_match[] = {
1659 {
1660 .compatible = "ti,omap2-hsmmc",
1661 },
1662 {
1663 .compatible = "ti,omap3-hsmmc",
1664 },
1665 {
1666 .compatible = "ti,omap4-hsmmc",
1667 .data = &omap4_reg_offset,
1668 },
1669 {},
1670 };
1671 MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1672
1673 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1674 {
1675 struct omap_mmc_platform_data *pdata;
1676 struct device_node *np = dev->of_node;
1677 u32 bus_width;
1678
1679 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1680 if (!pdata)
1681 return NULL; /* out of memory */
1682
1683 if (of_find_property(np, "ti,dual-volt", NULL))
1684 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1685
1686 /* This driver only supports 1 slot */
1687 pdata->nr_slots = 1;
1688 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1689 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1690
1691 if (of_find_property(np, "ti,non-removable", NULL)) {
1692 pdata->slots[0].nonremovable = true;
1693 pdata->slots[0].no_regulator_off_init = true;
1694 }
1695 of_property_read_u32(np, "bus-width", &bus_width);
1696 if (bus_width == 4)
1697 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1698 else if (bus_width == 8)
1699 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1700
1701 if (of_find_property(np, "ti,needs-special-reset", NULL))
1702 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1703
1704 return pdata;
1705 }
1706 #else
1707 static inline struct omap_mmc_platform_data
1708 *of_get_hsmmc_pdata(struct device *dev)
1709 {
1710 return NULL;
1711 }
1712 #endif
1713
1714 static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
1715 {
1716 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1717 struct mmc_host *mmc;
1718 struct omap_hsmmc_host *host = NULL;
1719 struct resource *res;
1720 int ret, irq;
1721 const struct of_device_id *match;
1722 dma_cap_mask_t mask;
1723 unsigned tx_req, rx_req;
1724
1725 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1726 if (match) {
1727 pdata = of_get_hsmmc_pdata(&pdev->dev);
1728 if (match->data) {
1729 u16 *offsetp = match->data;
1730 pdata->reg_offset = *offsetp;
1731 }
1732 }
1733
1734 if (pdata == NULL) {
1735 dev_err(&pdev->dev, "Platform Data is missing\n");
1736 return -ENXIO;
1737 }
1738
1739 if (pdata->nr_slots == 0) {
1740 dev_err(&pdev->dev, "No Slots\n");
1741 return -ENXIO;
1742 }
1743
1744 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1745 irq = platform_get_irq(pdev, 0);
1746 if (res == NULL || irq < 0)
1747 return -ENXIO;
1748
1749 res = request_mem_region(res->start, resource_size(res), pdev->name);
1750 if (res == NULL)
1751 return -EBUSY;
1752
1753 ret = omap_hsmmc_gpio_init(pdata);
1754 if (ret)
1755 goto err;
1756
1757 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
1758 if (!mmc) {
1759 ret = -ENOMEM;
1760 goto err_alloc;
1761 }
1762
1763 host = mmc_priv(mmc);
1764 host->mmc = mmc;
1765 host->pdata = pdata;
1766 host->dev = &pdev->dev;
1767 host->use_dma = 1;
1768 host->dma_ch = -1;
1769 host->irq = irq;
1770 host->slot_id = 0;
1771 host->mapbase = res->start + pdata->reg_offset;
1772 host->base = ioremap(host->mapbase, SZ_4K);
1773 host->power_mode = MMC_POWER_OFF;
1774 host->next_data.cookie = 1;
1775
1776 platform_set_drvdata(pdev, host);
1777
1778 mmc->ops = &omap_hsmmc_ops;
1779
1780 /*
1781 * If regulator_disable can only put vcc_aux to sleep then there is
1782 * no off state.
1783 */
1784 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1785 mmc_slot(host).no_off = 1;
1786
1787 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1788
1789 if (pdata->max_freq > 0)
1790 mmc->f_max = pdata->max_freq;
1791 else
1792 mmc->f_max = OMAP_MMC_MAX_CLOCK;
1793
1794 spin_lock_init(&host->irq_lock);
1795
1796 host->fclk = clk_get(&pdev->dev, "fck");
1797 if (IS_ERR(host->fclk)) {
1798 ret = PTR_ERR(host->fclk);
1799 host->fclk = NULL;
1800 goto err1;
1801 }
1802
1803 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1804 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1805 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1806 }
1807
1808 pm_runtime_enable(host->dev);
1809 pm_runtime_get_sync(host->dev);
1810 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1811 pm_runtime_use_autosuspend(host->dev);
1812
1813 omap_hsmmc_context_save(host);
1814
1815 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1816 /*
1817 * MMC can still work without debounce clock.
1818 */
1819 if (IS_ERR(host->dbclk)) {
1820 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n");
1821 host->dbclk = NULL;
1822 } else if (clk_prepare_enable(host->dbclk) != 0) {
1823 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1824 clk_put(host->dbclk);
1825 host->dbclk = NULL;
1826 }
1827
1828 /* Since we do only SG emulation, we can have as many segs
1829 * as we want. */
1830 mmc->max_segs = 1024;
1831
1832 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1833 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1834 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1835 mmc->max_seg_size = mmc->max_req_size;
1836
1837 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
1838 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
1839
1840 mmc->caps |= mmc_slot(host).caps;
1841 if (mmc->caps & MMC_CAP_8_BIT_DATA)
1842 mmc->caps |= MMC_CAP_4_BIT_DATA;
1843
1844 if (mmc_slot(host).nonremovable)
1845 mmc->caps |= MMC_CAP_NONREMOVABLE;
1846
1847 mmc->pm_caps = mmc_slot(host).pm_caps;
1848
1849 omap_hsmmc_conf_bus_power(host);
1850
1851 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1852 if (!res) {
1853 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1854 ret = -ENXIO;
1855 goto err_irq;
1856 }
1857 tx_req = res->start;
1858
1859 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1860 if (!res) {
1861 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
1862 ret = -ENXIO;
1863 goto err_irq;
1864 }
1865 rx_req = res->start;
1866
1867 dma_cap_zero(mask);
1868 dma_cap_set(DMA_SLAVE, mask);
1869
1870 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1871 if (!host->rx_chan) {
1872 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
1873 ret = -ENXIO;
1874 goto err_irq;
1875 }
1876
1877 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1878 if (!host->tx_chan) {
1879 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
1880 ret = -ENXIO;
1881 goto err_irq;
1882 }
1883
1884 /* Request IRQ for MMC operations */
1885 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
1886 mmc_hostname(mmc), host);
1887 if (ret) {
1888 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1889 goto err_irq;
1890 }
1891
1892 if (pdata->init != NULL) {
1893 if (pdata->init(&pdev->dev) != 0) {
1894 dev_dbg(mmc_dev(host->mmc),
1895 "Unable to configure MMC IRQs\n");
1896 goto err_irq_cd_init;
1897 }
1898 }
1899
1900 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
1901 ret = omap_hsmmc_reg_get(host);
1902 if (ret)
1903 goto err_reg;
1904 host->use_reg = 1;
1905 }
1906
1907 mmc->ocr_avail = mmc_slot(host).ocr_mask;
1908
1909 /* Request IRQ for card detect */
1910 if ((mmc_slot(host).card_detect_irq)) {
1911 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1912 NULL,
1913 omap_hsmmc_detect,
1914 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1915 mmc_hostname(mmc), host);
1916 if (ret) {
1917 dev_dbg(mmc_dev(host->mmc),
1918 "Unable to grab MMC CD IRQ\n");
1919 goto err_irq_cd;
1920 }
1921 pdata->suspend = omap_hsmmc_suspend_cdirq;
1922 pdata->resume = omap_hsmmc_resume_cdirq;
1923 }
1924
1925 omap_hsmmc_disable_irq(host);
1926
1927 omap_hsmmc_protect_card(host);
1928
1929 mmc_add_host(mmc);
1930
1931 if (mmc_slot(host).name != NULL) {
1932 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1933 if (ret < 0)
1934 goto err_slot_name;
1935 }
1936 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
1937 ret = device_create_file(&mmc->class_dev,
1938 &dev_attr_cover_switch);
1939 if (ret < 0)
1940 goto err_slot_name;
1941 }
1942
1943 omap_hsmmc_debugfs(mmc);
1944 pm_runtime_mark_last_busy(host->dev);
1945 pm_runtime_put_autosuspend(host->dev);
1946
1947 return 0;
1948
1949 err_slot_name:
1950 mmc_remove_host(mmc);
1951 free_irq(mmc_slot(host).card_detect_irq, host);
1952 err_irq_cd:
1953 if (host->use_reg)
1954 omap_hsmmc_reg_put(host);
1955 err_reg:
1956 if (host->pdata->cleanup)
1957 host->pdata->cleanup(&pdev->dev);
1958 err_irq_cd_init:
1959 free_irq(host->irq, host);
1960 err_irq:
1961 if (host->tx_chan)
1962 dma_release_channel(host->tx_chan);
1963 if (host->rx_chan)
1964 dma_release_channel(host->rx_chan);
1965 pm_runtime_put_sync(host->dev);
1966 pm_runtime_disable(host->dev);
1967 clk_put(host->fclk);
1968 if (host->dbclk) {
1969 clk_disable_unprepare(host->dbclk);
1970 clk_put(host->dbclk);
1971 }
1972 err1:
1973 iounmap(host->base);
1974 platform_set_drvdata(pdev, NULL);
1975 mmc_free_host(mmc);
1976 err_alloc:
1977 omap_hsmmc_gpio_free(pdata);
1978 err:
1979 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1980 if (res)
1981 release_mem_region(res->start, resource_size(res));
1982 return ret;
1983 }
1984
1985 static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
1986 {
1987 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
1988 struct resource *res;
1989
1990 pm_runtime_get_sync(host->dev);
1991 mmc_remove_host(host->mmc);
1992 if (host->use_reg)
1993 omap_hsmmc_reg_put(host);
1994 if (host->pdata->cleanup)
1995 host->pdata->cleanup(&pdev->dev);
1996 free_irq(host->irq, host);
1997 if (mmc_slot(host).card_detect_irq)
1998 free_irq(mmc_slot(host).card_detect_irq, host);
1999
2000 if (host->tx_chan)
2001 dma_release_channel(host->tx_chan);
2002 if (host->rx_chan)
2003 dma_release_channel(host->rx_chan);
2004
2005 pm_runtime_put_sync(host->dev);
2006 pm_runtime_disable(host->dev);
2007 clk_put(host->fclk);
2008 if (host->dbclk) {
2009 clk_disable_unprepare(host->dbclk);
2010 clk_put(host->dbclk);
2011 }
2012
2013 mmc_free_host(host->mmc);
2014 iounmap(host->base);
2015 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2016
2017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2018 if (res)
2019 release_mem_region(res->start, resource_size(res));
2020 platform_set_drvdata(pdev, NULL);
2021
2022 return 0;
2023 }
2024
2025 #ifdef CONFIG_PM
2026 static int omap_hsmmc_suspend(struct device *dev)
2027 {
2028 int ret = 0;
2029 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2030
2031 if (!host)
2032 return 0;
2033
2034 if (host && host->suspended)
2035 return 0;
2036
2037 pm_runtime_get_sync(host->dev);
2038 host->suspended = 1;
2039 if (host->pdata->suspend) {
2040 ret = host->pdata->suspend(dev, host->slot_id);
2041 if (ret) {
2042 dev_dbg(dev, "Unable to handle MMC board"
2043 " level suspend\n");
2044 host->suspended = 0;
2045 return ret;
2046 }
2047 }
2048 ret = mmc_suspend_host(host->mmc);
2049
2050 if (ret) {
2051 host->suspended = 0;
2052 if (host->pdata->resume) {
2053 ret = host->pdata->resume(dev, host->slot_id);
2054 if (ret)
2055 dev_dbg(dev, "Unmask interrupt failed\n");
2056 }
2057 goto err;
2058 }
2059
2060 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2061 omap_hsmmc_disable_irq(host);
2062 OMAP_HSMMC_WRITE(host->base, HCTL,
2063 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2064 }
2065
2066 if (host->dbclk)
2067 clk_disable_unprepare(host->dbclk);
2068 err:
2069 pm_runtime_put_sync(host->dev);
2070 return ret;
2071 }
2072
2073 /* Routine to resume the MMC device */
2074 static int omap_hsmmc_resume(struct device *dev)
2075 {
2076 int ret = 0;
2077 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2078
2079 if (!host)
2080 return 0;
2081
2082 if (host && !host->suspended)
2083 return 0;
2084
2085 pm_runtime_get_sync(host->dev);
2086
2087 if (host->dbclk)
2088 clk_prepare_enable(host->dbclk);
2089
2090 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2091 omap_hsmmc_conf_bus_power(host);
2092
2093 if (host->pdata->resume) {
2094 ret = host->pdata->resume(dev, host->slot_id);
2095 if (ret)
2096 dev_dbg(dev, "Unmask interrupt failed\n");
2097 }
2098
2099 omap_hsmmc_protect_card(host);
2100
2101 /* Notify the core to resume the host */
2102 ret = mmc_resume_host(host->mmc);
2103 if (ret == 0)
2104 host->suspended = 0;
2105
2106 pm_runtime_mark_last_busy(host->dev);
2107 pm_runtime_put_autosuspend(host->dev);
2108
2109 return ret;
2110
2111 }
2112
2113 #else
2114 #define omap_hsmmc_suspend NULL
2115 #define omap_hsmmc_resume NULL
2116 #endif
2117
2118 static int omap_hsmmc_runtime_suspend(struct device *dev)
2119 {
2120 struct omap_hsmmc_host *host;
2121
2122 host = platform_get_drvdata(to_platform_device(dev));
2123 omap_hsmmc_context_save(host);
2124 dev_dbg(dev, "disabled\n");
2125
2126 return 0;
2127 }
2128
2129 static int omap_hsmmc_runtime_resume(struct device *dev)
2130 {
2131 struct omap_hsmmc_host *host;
2132
2133 host = platform_get_drvdata(to_platform_device(dev));
2134 omap_hsmmc_context_restore(host);
2135 dev_dbg(dev, "enabled\n");
2136
2137 return 0;
2138 }
2139
2140 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
2141 .suspend = omap_hsmmc_suspend,
2142 .resume = omap_hsmmc_resume,
2143 .runtime_suspend = omap_hsmmc_runtime_suspend,
2144 .runtime_resume = omap_hsmmc_runtime_resume,
2145 };
2146
2147 static struct platform_driver omap_hsmmc_driver = {
2148 .probe = omap_hsmmc_probe,
2149 .remove = __devexit_p(omap_hsmmc_remove),
2150 .driver = {
2151 .name = DRIVER_NAME,
2152 .owner = THIS_MODULE,
2153 .pm = &omap_hsmmc_dev_pm_ops,
2154 .of_match_table = of_match_ptr(omap_mmc_of_match),
2155 },
2156 };
2157
2158 module_platform_driver(omap_hsmmc_driver);
2159 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2160 MODULE_LICENSE("GPL");
2161 MODULE_ALIAS("platform:" DRIVER_NAME);
2162 MODULE_AUTHOR("Texas Instruments Inc");
Linux kernel - Deliverables
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