drivers/mmc/host/sdhci-bcm2835.c

   1 /*
   2  * BCM2835 SDHCI
   3  * Copyright (C) 2012 Stephen Warren
   4  * Based on U-Boot's MMC driver for the BCM2835 by Oleksandr Tymoshenko & me
   5  * Portions of the code there were obviously based on the Linux kernel at:
   6  * git://github.com/raspberrypi/linux.git rpi-3.6.y
   7  * commit f5b930b "Main bcm2708 linux port" signed-off-by Dom Cobley.
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms and conditions of the GNU General Public License,
  11  * version 2, as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope it will be useful, but WITHOUT
  14  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16  * more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/delay.h>
  23 #include <linux/module.h>
  24 #include <linux/mmc/host.h>
  25 #include "sdhci-pltfm.h"
  26
  27 /*
  28  * 400KHz is max freq for card ID etc. Use that as min card clock. We need to
  29  * know the min to enable static calculation of max BCM2835_SDHCI_WRITE_DELAY.
  30  */
  31 #define MIN_FREQ 400000
  32
  33 /*
  34  * The Arasan has a bugette whereby it may lose the content of successive
  35  * writes to registers that are within two SD-card clock cycles of each other
  36  * (a clock domain crossing problem). It seems, however, that the data
  37  * register does not have this problem, which is just as well - otherwise we'd
  38  * have to nobble the DMA engine too.
  39  *
  40  * This should probably be dynamically calculated based on the actual card
  41  * frequency. However, this is the longest we'll have to wait, and doesn't
  42  * seem to slow access down too much, so the added complexity doesn't seem
  43  * worth it for now.
  44  *
  45  * 1/MIN_FREQ is (max) time per tick of eMMC clock.
  46  * 2/MIN_FREQ is time for two ticks.
  47  * Multiply by 1000000 to get uS per two ticks.
  48  * *1000000 for uSecs.
  49  * +1 for hack rounding.
  50  */
  51 #define BCM2835_SDHCI_WRITE_DELAY       (((2 * 1000000) / MIN_FREQ) + 1)
  52
  53 struct bcm2835_sdhci {
  54         u32 shadow;
  55 };
  56
  57 static void bcm2835_sdhci_writel(struct sdhci_host *host, u32 val, int reg)
  58 {
  59         writel(val, host->ioaddr + reg);
  60
  61         udelay(BCM2835_SDHCI_WRITE_DELAY);
  62 }
  63
  64 static inline u32 bcm2835_sdhci_readl(struct sdhci_host *host, int reg)
  65 {
  66         u32 val = readl(host->ioaddr + reg);
  67
  68         if (reg == SDHCI_CAPABILITIES)
  69                 val |= SDHCI_CAN_VDD_330;
  70
  71         return val;
  72 }
  73
  74 static void bcm2835_sdhci_writew(struct sdhci_host *host, u16 val, int reg)
  75 {
  76         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  77         struct bcm2835_sdhci *bcm2835_host = sdhci_pltfm_priv(pltfm_host);
  78         u32 oldval = (reg == SDHCI_COMMAND) ? bcm2835_host->shadow :
  79                 bcm2835_sdhci_readl(host, reg & ~3);
  80         u32 word_num = (reg >> 1) & 1;
  81         u32 word_shift = word_num * 16;
  82         u32 mask = 0xffff << word_shift;
  83         u32 newval = (oldval & ~mask) | (val << word_shift);
  84
  85         if (reg == SDHCI_TRANSFER_MODE)
  86                 bcm2835_host->shadow = newval;
  87         else
  88                 bcm2835_sdhci_writel(host, newval, reg & ~3);
  89 }
  90
  91 static u16 bcm2835_sdhci_readw(struct sdhci_host *host, int reg)
  92 {
  93         u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
  94         u32 word_num = (reg >> 1) & 1;
  95         u32 word_shift = word_num * 16;
  96         u32 word = (val >> word_shift) & 0xffff;
  97
  98         return word;
  99 }
 100
 101 static void bcm2835_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 102 {
 103         u32 oldval = bcm2835_sdhci_readl(host, reg & ~3);
 104         u32 byte_num = reg & 3;
 105         u32 byte_shift = byte_num * 8;
 106         u32 mask = 0xff << byte_shift;
 107         u32 newval = (oldval & ~mask) | (val << byte_shift);
 108
 109         bcm2835_sdhci_writel(host, newval, reg & ~3);
 110 }
 111
 112 static u8 bcm2835_sdhci_readb(struct sdhci_host *host, int reg)
 113 {
 114         u32 val = bcm2835_sdhci_readl(host, (reg & ~3));
 115         u32 byte_num = reg & 3;
 116         u32 byte_shift = byte_num * 8;
 117         u32 byte = (val >> byte_shift) & 0xff;
 118
 119         return byte;
 120 }
 121
 122 static unsigned int bcm2835_sdhci_get_min_clock(struct sdhci_host *host)
 123 {
 124         return MIN_FREQ;
 125 }
 126
 127 static const struct sdhci_ops bcm2835_sdhci_ops = {
 128         .write_l = bcm2835_sdhci_writel,
 129         .write_w = bcm2835_sdhci_writew,
 130         .write_b = bcm2835_sdhci_writeb,
 131         .read_l = bcm2835_sdhci_readl,
 132         .read_w = bcm2835_sdhci_readw,
 133         .read_b = bcm2835_sdhci_readb,
 134         .set_clock = sdhci_set_clock,
 135         .get_max_clock = sdhci_pltfm_clk_get_max_clock,
 136         .get_min_clock = bcm2835_sdhci_get_min_clock,
 137         .set_bus_width = sdhci_set_bus_width,
 138         .reset = sdhci_reset,
 139         .set_uhs_signaling = sdhci_set_uhs_signaling,
 140 };
 141
 142 static const struct sdhci_pltfm_data bcm2835_sdhci_pdata = {
 143         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 144                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
 145         .ops = &bcm2835_sdhci_ops,
 146 };
 147
 148 static int bcm2835_sdhci_probe(struct platform_device *pdev)
 149 {
 150         struct sdhci_host *host;
 151         struct bcm2835_sdhci *bcm2835_host;
 152         struct sdhci_pltfm_host *pltfm_host;
 153         int ret;
 154
 155         host = sdhci_pltfm_init(pdev, &bcm2835_sdhci_pdata,
 156                                 sizeof(*bcm2835_host));
 157         if (IS_ERR(host))
 158                 return PTR_ERR(host);
 159
 160         pltfm_host = sdhci_priv(host);
 161
 162         pltfm_host->clk = devm_clk_get(&pdev->dev, NULL);
 163         if (IS_ERR(pltfm_host->clk)) {
 164                 ret = PTR_ERR(pltfm_host->clk);
 165                 goto err;
 166         }
 167         ret = clk_prepare_enable(pltfm_host->clk);
 168         if (ret) {
 169                 dev_err(&pdev->dev, "failed to enable host clk\n");
 170                 goto err;
 171         }
 172
 173         ret = sdhci_add_host(host);
 174         if (ret)
 175                 goto err_clk;
 176
 177         return 0;
 178 err_clk:
 179         clk_disable_unprepare(pltfm_host->clk);
 180 err:
 181         sdhci_pltfm_free(pdev);
 182         return ret;
 183 }
 184
 185 static const struct of_device_id bcm2835_sdhci_of_match[] = {
 186         { .compatible = "brcm,bcm2835-sdhci" },
 187         { }
 188 };
 189 MODULE_DEVICE_TABLE(of, bcm2835_sdhci_of_match);
 190
 191 static struct platform_driver bcm2835_sdhci_driver = {
 192         .driver = {
 193                 .name = "sdhci-bcm2835",
 194                 .of_match_table = bcm2835_sdhci_of_match,
 195                 .pm = SDHCI_PLTFM_PMOPS,
 196         },
 197         .probe = bcm2835_sdhci_probe,
 198         .remove = sdhci_pltfm_unregister,
 199 };
 200 module_platform_driver(bcm2835_sdhci_driver);
 201
 202 MODULE_DESCRIPTION("BCM2835 SDHCI driver");
 203 MODULE_AUTHOR("Stephen Warren");
 204 MODULE_LICENSE("GPL v2");