2 * Freescale eSDHC i.MX controller driver for the platform bus.
4 * derived from the OF-version.
6 * Copyright (c) 2010 Pengutronix e.K.
7 * Author: Wolfram Sang <kernel@pengutronix.de>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/gpio.h>
19 #include <linux/module.h>
20 #include <linux/slab.h>
21 #include <linux/mmc/host.h>
22 #include <linux/mmc/mmc.h>
23 #include <linux/mmc/sdio.h>
24 #include <linux/mmc/slot-gpio.h>
26 #include <linux/of_device.h>
27 #include <linux/of_gpio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/platform_data/mmc-esdhc-imx.h>
30 #include <linux/pm_runtime.h>
31 #include "sdhci-pltfm.h"
32 #include "sdhci-esdhc.h"
34 #define ESDHC_CTRL_D3CD 0x08
35 /* VENDOR SPEC register */
36 #define ESDHC_VENDOR_SPEC 0xc0
37 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1)
38 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1)
39 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8)
40 #define ESDHC_WTMK_LVL 0x44
41 #define ESDHC_MIX_CTRL 0x48
42 #define ESDHC_MIX_CTRL_DDREN (1 << 3)
43 #define ESDHC_MIX_CTRL_AC23EN (1 << 7)
44 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
45 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
46 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
47 /* Bits 3 and 6 are not SDHCI standard definitions */
48 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
50 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000
52 /* dll control register */
53 #define ESDHC_DLL_CTRL 0x60
54 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9
55 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8
57 /* tune control register */
58 #define ESDHC_TUNE_CTRL_STATUS 0x68
59 #define ESDHC_TUNE_CTRL_STEP 1
60 #define ESDHC_TUNE_CTRL_MIN 0
61 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
63 #define ESDHC_TUNING_CTRL 0xcc
64 #define ESDHC_STD_TUNING_EN (1 << 24)
65 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
66 #define ESDHC_TUNING_START_TAP 0x1
69 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz"
70 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz"
73 * Our interpretation of the SDHCI_HOST_CONTROL register
75 #define ESDHC_CTRL_4BITBUS (0x1 << 1)
76 #define ESDHC_CTRL_8BITBUS (0x2 << 1)
77 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1)
80 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
81 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
82 * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
83 * Define this macro DMA error INT for fsl eSDHC
85 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28)
88 * The CMDTYPE of the CMD register (offset 0xE) should be set to
89 * "11" when the STOP CMD12 is issued on imx53 to abort one
90 * open ended multi-blk IO. Otherwise the TC INT wouldn't
92 * In exact block transfer, the controller doesn't complete the
93 * operations automatically as required at the end of the
94 * transfer and remains on hold if the abort command is not sent.
95 * As a result, the TC flag is not asserted and SW received timeout
96 * exeception. Bit1 of Vendor Spec registor is used to fix it.
98 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
100 * The flag enables the workaround for ESDHC errata ENGcm07207 which
101 * affects i.MX25 and i.MX35.
103 #define ESDHC_FLAG_ENGCM07207 BIT(2)
105 * The flag tells that the ESDHC controller is an USDHC block that is
106 * integrated on the i.MX6 series.
108 #define ESDHC_FLAG_USDHC BIT(3)
109 /* The IP supports manual tuning process */
110 #define ESDHC_FLAG_MAN_TUNING BIT(4)
111 /* The IP supports standard tuning process */
112 #define ESDHC_FLAG_STD_TUNING BIT(5)
113 /* The IP has SDHCI_CAPABILITIES_1 register */
114 #define ESDHC_FLAG_HAVE_CAP1 BIT(6)
116 * The IP has errata ERR004536
117 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow,
118 * when reading data from the card
120 #define ESDHC_FLAG_ERR004536 BIT(7)
122 struct esdhc_soc_data
{
126 static struct esdhc_soc_data esdhc_imx25_data
= {
127 .flags
= ESDHC_FLAG_ENGCM07207
,
130 static struct esdhc_soc_data esdhc_imx35_data
= {
131 .flags
= ESDHC_FLAG_ENGCM07207
,
134 static struct esdhc_soc_data esdhc_imx51_data
= {
138 static struct esdhc_soc_data esdhc_imx53_data
= {
139 .flags
= ESDHC_FLAG_MULTIBLK_NO_INT
,
142 static struct esdhc_soc_data usdhc_imx6q_data
= {
143 .flags
= ESDHC_FLAG_USDHC
| ESDHC_FLAG_MAN_TUNING
,
146 static struct esdhc_soc_data usdhc_imx6sl_data
= {
147 .flags
= ESDHC_FLAG_USDHC
| ESDHC_FLAG_STD_TUNING
148 | ESDHC_FLAG_HAVE_CAP1
| ESDHC_FLAG_ERR004536
,
151 struct pltfm_imx_data
{
153 struct pinctrl
*pinctrl
;
154 struct pinctrl_state
*pins_default
;
155 struct pinctrl_state
*pins_100mhz
;
156 struct pinctrl_state
*pins_200mhz
;
157 const struct esdhc_soc_data
*socdata
;
158 struct esdhc_platform_data boarddata
;
163 NO_CMD_PENDING
, /* no multiblock command pending*/
164 MULTIBLK_IN_PROCESS
, /* exact multiblock cmd in process */
165 WAIT_FOR_INT
, /* sent CMD12, waiting for response INT */
170 static const struct platform_device_id imx_esdhc_devtype
[] = {
172 .name
= "sdhci-esdhc-imx25",
173 .driver_data
= (kernel_ulong_t
) &esdhc_imx25_data
,
175 .name
= "sdhci-esdhc-imx35",
176 .driver_data
= (kernel_ulong_t
) &esdhc_imx35_data
,
178 .name
= "sdhci-esdhc-imx51",
179 .driver_data
= (kernel_ulong_t
) &esdhc_imx51_data
,
184 MODULE_DEVICE_TABLE(platform
, imx_esdhc_devtype
);
186 static const struct of_device_id imx_esdhc_dt_ids
[] = {
187 { .compatible
= "fsl,imx25-esdhc", .data
= &esdhc_imx25_data
, },
188 { .compatible
= "fsl,imx35-esdhc", .data
= &esdhc_imx35_data
, },
189 { .compatible
= "fsl,imx51-esdhc", .data
= &esdhc_imx51_data
, },
190 { .compatible
= "fsl,imx53-esdhc", .data
= &esdhc_imx53_data
, },
191 { .compatible
= "fsl,imx6sl-usdhc", .data
= &usdhc_imx6sl_data
, },
192 { .compatible
= "fsl,imx6q-usdhc", .data
= &usdhc_imx6q_data
, },
195 MODULE_DEVICE_TABLE(of
, imx_esdhc_dt_ids
);
197 static inline int is_imx25_esdhc(struct pltfm_imx_data
*data
)
199 return data
->socdata
== &esdhc_imx25_data
;
202 static inline int is_imx53_esdhc(struct pltfm_imx_data
*data
)
204 return data
->socdata
== &esdhc_imx53_data
;
207 static inline int is_imx6q_usdhc(struct pltfm_imx_data
*data
)
209 return data
->socdata
== &usdhc_imx6q_data
;
212 static inline int esdhc_is_usdhc(struct pltfm_imx_data
*data
)
214 return !!(data
->socdata
->flags
& ESDHC_FLAG_USDHC
);
217 static inline void esdhc_clrset_le(struct sdhci_host
*host
, u32 mask
, u32 val
, int reg
)
219 void __iomem
*base
= host
->ioaddr
+ (reg
& ~0x3);
220 u32 shift
= (reg
& 0x3) * 8;
222 writel(((readl(base
) & ~(mask
<< shift
)) | (val
<< shift
)), base
);
225 static u32
esdhc_readl_le(struct sdhci_host
*host
, int reg
)
227 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
228 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
229 u32 val
= readl(host
->ioaddr
+ reg
);
231 if (unlikely(reg
== SDHCI_PRESENT_STATE
)) {
233 /* save the least 20 bits */
234 val
= fsl_prss
& 0x000FFFFF;
235 /* move dat[0-3] bits */
236 val
|= (fsl_prss
& 0x0F000000) >> 4;
237 /* move cmd line bit */
238 val
|= (fsl_prss
& 0x00800000) << 1;
241 if (unlikely(reg
== SDHCI_CAPABILITIES
)) {
242 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */
243 if (imx_data
->socdata
->flags
& ESDHC_FLAG_HAVE_CAP1
)
246 /* In FSL esdhc IC module, only bit20 is used to indicate the
247 * ADMA2 capability of esdhc, but this bit is messed up on
248 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
249 * don't actually support ADMA2). So set the BROKEN_ADMA
250 * uirk on MX25/35 platforms.
253 if (val
& SDHCI_CAN_DO_ADMA1
) {
254 val
&= ~SDHCI_CAN_DO_ADMA1
;
255 val
|= SDHCI_CAN_DO_ADMA2
;
259 if (unlikely(reg
== SDHCI_CAPABILITIES_1
)) {
260 if (esdhc_is_usdhc(imx_data
)) {
261 if (imx_data
->socdata
->flags
& ESDHC_FLAG_HAVE_CAP1
)
262 val
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES
) & 0xFFFF;
264 /* imx6q/dl does not have cap_1 register, fake one */
265 val
= SDHCI_SUPPORT_DDR50
| SDHCI_SUPPORT_SDR104
266 | SDHCI_SUPPORT_SDR50
267 | SDHCI_USE_SDR50_TUNING
;
271 if (unlikely(reg
== SDHCI_MAX_CURRENT
) && esdhc_is_usdhc(imx_data
)) {
273 val
|= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT
;
274 val
|= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT
;
275 val
|= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT
;
278 if (unlikely(reg
== SDHCI_INT_STATUS
)) {
279 if (val
& ESDHC_INT_VENDOR_SPEC_DMA_ERR
) {
280 val
&= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR
;
281 val
|= SDHCI_INT_ADMA_ERROR
;
285 * mask off the interrupt we get in response to the manually
288 if ((imx_data
->multiblock_status
== WAIT_FOR_INT
) &&
289 ((val
& SDHCI_INT_RESPONSE
) == SDHCI_INT_RESPONSE
)) {
290 val
&= ~SDHCI_INT_RESPONSE
;
291 writel(SDHCI_INT_RESPONSE
, host
->ioaddr
+
293 imx_data
->multiblock_status
= NO_CMD_PENDING
;
300 static void esdhc_writel_le(struct sdhci_host
*host
, u32 val
, int reg
)
302 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
303 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
306 if (unlikely(reg
== SDHCI_INT_ENABLE
|| reg
== SDHCI_SIGNAL_ENABLE
)) {
307 if ((val
& SDHCI_INT_CARD_INT
) && !esdhc_is_usdhc(imx_data
)) {
309 * Clear and then set D3CD bit to avoid missing the
310 * card interrupt. This is a eSDHC controller problem
311 * so we need to apply the following workaround: clear
312 * and set D3CD bit will make eSDHC re-sample the card
313 * interrupt. In case a card interrupt was lost,
314 * re-sample it by the following steps.
316 data
= readl(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
317 data
&= ~ESDHC_CTRL_D3CD
;
318 writel(data
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
319 data
|= ESDHC_CTRL_D3CD
;
320 writel(data
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
323 if (val
& SDHCI_INT_ADMA_ERROR
) {
324 val
&= ~SDHCI_INT_ADMA_ERROR
;
325 val
|= ESDHC_INT_VENDOR_SPEC_DMA_ERR
;
329 if (unlikely((imx_data
->socdata
->flags
& ESDHC_FLAG_MULTIBLK_NO_INT
)
330 && (reg
== SDHCI_INT_STATUS
)
331 && (val
& SDHCI_INT_DATA_END
))) {
333 v
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
334 v
&= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK
;
335 writel(v
, host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
337 if (imx_data
->multiblock_status
== MULTIBLK_IN_PROCESS
)
339 /* send a manual CMD12 with RESPTYP=none */
340 data
= MMC_STOP_TRANSMISSION
<< 24 |
341 SDHCI_CMD_ABORTCMD
<< 16;
342 writel(data
, host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
343 imx_data
->multiblock_status
= WAIT_FOR_INT
;
347 writel(val
, host
->ioaddr
+ reg
);
350 static u16
esdhc_readw_le(struct sdhci_host
*host
, int reg
)
352 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
353 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
357 if (unlikely(reg
== SDHCI_HOST_VERSION
)) {
359 if (esdhc_is_usdhc(imx_data
)) {
361 * The usdhc register returns a wrong host version.
364 return SDHCI_SPEC_300
;
368 if (unlikely(reg
== SDHCI_HOST_CONTROL2
)) {
369 val
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
370 if (val
& ESDHC_VENDOR_SPEC_VSELECT
)
371 ret
|= SDHCI_CTRL_VDD_180
;
373 if (esdhc_is_usdhc(imx_data
)) {
374 if (imx_data
->socdata
->flags
& ESDHC_FLAG_MAN_TUNING
)
375 val
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
376 else if (imx_data
->socdata
->flags
& ESDHC_FLAG_STD_TUNING
)
377 /* the std tuning bits is in ACMD12_ERR for imx6sl */
378 val
= readl(host
->ioaddr
+ SDHCI_ACMD12_ERR
);
381 if (val
& ESDHC_MIX_CTRL_EXE_TUNE
)
382 ret
|= SDHCI_CTRL_EXEC_TUNING
;
383 if (val
& ESDHC_MIX_CTRL_SMPCLK_SEL
)
384 ret
|= SDHCI_CTRL_TUNED_CLK
;
386 ret
&= ~SDHCI_CTRL_PRESET_VAL_ENABLE
;
391 if (unlikely(reg
== SDHCI_TRANSFER_MODE
)) {
392 if (esdhc_is_usdhc(imx_data
)) {
393 u32 m
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
394 ret
= m
& ESDHC_MIX_CTRL_SDHCI_MASK
;
396 if (m
& ESDHC_MIX_CTRL_AC23EN
) {
397 ret
&= ~ESDHC_MIX_CTRL_AC23EN
;
398 ret
|= SDHCI_TRNS_AUTO_CMD23
;
401 ret
= readw(host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
407 return readw(host
->ioaddr
+ reg
);
410 static void esdhc_writew_le(struct sdhci_host
*host
, u16 val
, int reg
)
412 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
413 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
417 case SDHCI_CLOCK_CONTROL
:
418 new_val
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
419 if (val
& SDHCI_CLOCK_CARD_EN
)
420 new_val
|= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON
;
422 new_val
&= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON
;
423 writel(new_val
, host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
425 case SDHCI_HOST_CONTROL2
:
426 new_val
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
427 if (val
& SDHCI_CTRL_VDD_180
)
428 new_val
|= ESDHC_VENDOR_SPEC_VSELECT
;
430 new_val
&= ~ESDHC_VENDOR_SPEC_VSELECT
;
431 writel(new_val
, host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
432 if (imx_data
->socdata
->flags
& ESDHC_FLAG_MAN_TUNING
) {
433 new_val
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
434 if (val
& SDHCI_CTRL_TUNED_CLK
)
435 new_val
|= ESDHC_MIX_CTRL_SMPCLK_SEL
;
437 new_val
&= ~ESDHC_MIX_CTRL_SMPCLK_SEL
;
438 writel(new_val
, host
->ioaddr
+ ESDHC_MIX_CTRL
);
439 } else if (imx_data
->socdata
->flags
& ESDHC_FLAG_STD_TUNING
) {
440 u32 v
= readl(host
->ioaddr
+ SDHCI_ACMD12_ERR
);
441 u32 m
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
442 if (val
& SDHCI_CTRL_TUNED_CLK
) {
443 v
|= ESDHC_MIX_CTRL_SMPCLK_SEL
;
445 v
&= ~ESDHC_MIX_CTRL_SMPCLK_SEL
;
446 m
&= ~ESDHC_MIX_CTRL_FBCLK_SEL
;
449 if (val
& SDHCI_CTRL_EXEC_TUNING
) {
450 v
|= ESDHC_MIX_CTRL_EXE_TUNE
;
451 m
|= ESDHC_MIX_CTRL_FBCLK_SEL
;
453 v
&= ~ESDHC_MIX_CTRL_EXE_TUNE
;
456 writel(v
, host
->ioaddr
+ SDHCI_ACMD12_ERR
);
457 writel(m
, host
->ioaddr
+ ESDHC_MIX_CTRL
);
460 case SDHCI_TRANSFER_MODE
:
461 if ((imx_data
->socdata
->flags
& ESDHC_FLAG_MULTIBLK_NO_INT
)
462 && (host
->cmd
->opcode
== SD_IO_RW_EXTENDED
)
463 && (host
->cmd
->data
->blocks
> 1)
464 && (host
->cmd
->data
->flags
& MMC_DATA_READ
)) {
466 v
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
467 v
|= ESDHC_VENDOR_SPEC_SDIO_QUIRK
;
468 writel(v
, host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
471 if (esdhc_is_usdhc(imx_data
)) {
472 u32 m
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
474 if (val
& SDHCI_TRNS_AUTO_CMD23
) {
475 val
&= ~SDHCI_TRNS_AUTO_CMD23
;
476 val
|= ESDHC_MIX_CTRL_AC23EN
;
478 m
= val
| (m
& ~ESDHC_MIX_CTRL_SDHCI_MASK
);
479 writel(m
, host
->ioaddr
+ ESDHC_MIX_CTRL
);
482 * Postpone this write, we must do it together with a
483 * command write that is down below.
485 imx_data
->scratchpad
= val
;
489 if (host
->cmd
->opcode
== MMC_STOP_TRANSMISSION
)
490 val
|= SDHCI_CMD_ABORTCMD
;
492 if ((host
->cmd
->opcode
== MMC_SET_BLOCK_COUNT
) &&
493 (imx_data
->socdata
->flags
& ESDHC_FLAG_MULTIBLK_NO_INT
))
494 imx_data
->multiblock_status
= MULTIBLK_IN_PROCESS
;
496 if (esdhc_is_usdhc(imx_data
))
498 host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
500 writel(val
<< 16 | imx_data
->scratchpad
,
501 host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
503 case SDHCI_BLOCK_SIZE
:
504 val
&= ~SDHCI_MAKE_BLKSZ(0x7, 0);
507 esdhc_clrset_le(host
, 0xffff, val
, reg
);
510 static void esdhc_writeb_le(struct sdhci_host
*host
, u8 val
, int reg
)
512 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
513 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
518 case SDHCI_POWER_CONTROL
:
520 * FSL put some DMA bits here
521 * If your board has a regulator, code should be here
524 case SDHCI_HOST_CONTROL
:
525 /* FSL messed up here, so we need to manually compose it. */
526 new_val
= val
& SDHCI_CTRL_LED
;
527 /* ensure the endianness */
528 new_val
|= ESDHC_HOST_CONTROL_LE
;
529 /* bits 8&9 are reserved on mx25 */
530 if (!is_imx25_esdhc(imx_data
)) {
531 /* DMA mode bits are shifted */
532 new_val
|= (val
& SDHCI_CTRL_DMA_MASK
) << 5;
536 * Do not touch buswidth bits here. This is done in
537 * esdhc_pltfm_bus_width.
538 * Do not touch the D3CD bit either which is used for the
539 * SDIO interrupt errata workaround.
541 mask
= 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK
| ESDHC_CTRL_D3CD
);
543 esdhc_clrset_le(host
, mask
, new_val
, reg
);
546 esdhc_clrset_le(host
, 0xff, val
, reg
);
549 * The esdhc has a design violation to SDHC spec which tells
550 * that software reset should not affect card detection circuit.
551 * But esdhc clears its SYSCTL register bits [0..2] during the
552 * software reset. This will stop those clocks that card detection
553 * circuit relies on. To work around it, we turn the clocks on back
554 * to keep card detection circuit functional.
556 if ((reg
== SDHCI_SOFTWARE_RESET
) && (val
& 1)) {
557 esdhc_clrset_le(host
, 0x7, 0x7, ESDHC_SYSTEM_CONTROL
);
559 * The reset on usdhc fails to clear MIX_CTRL register.
560 * Do it manually here.
562 if (esdhc_is_usdhc(imx_data
)) {
563 /* the tuning bits should be kept during reset */
564 new_val
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
565 writel(new_val
& ESDHC_MIX_CTRL_TUNING_MASK
,
566 host
->ioaddr
+ ESDHC_MIX_CTRL
);
567 imx_data
->is_ddr
= 0;
572 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host
*host
)
574 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
575 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
576 struct esdhc_platform_data
*boarddata
= &imx_data
->boarddata
;
578 if (boarddata
->f_max
&& (boarddata
->f_max
< pltfm_host
->clock
))
579 return boarddata
->f_max
;
581 return pltfm_host
->clock
;
584 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host
*host
)
586 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
588 return pltfm_host
->clock
/ 256 / 16;
591 static inline void esdhc_pltfm_set_clock(struct sdhci_host
*host
,
594 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
595 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
596 unsigned int host_clock
= pltfm_host
->clock
;
602 host
->mmc
->actual_clock
= 0;
604 if (esdhc_is_usdhc(imx_data
)) {
605 val
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
606 writel(val
& ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON
,
607 host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
612 if (esdhc_is_usdhc(imx_data
) && !imx_data
->is_ddr
)
615 temp
= sdhci_readl(host
, ESDHC_SYSTEM_CONTROL
);
616 temp
&= ~(ESDHC_CLOCK_IPGEN
| ESDHC_CLOCK_HCKEN
| ESDHC_CLOCK_PEREN
618 sdhci_writel(host
, temp
, ESDHC_SYSTEM_CONTROL
);
620 while (host_clock
/ pre_div
/ 16 > clock
&& pre_div
< 256)
623 while (host_clock
/ pre_div
/ div
> clock
&& div
< 16)
626 host
->mmc
->actual_clock
= host_clock
/ pre_div
/ div
;
627 dev_dbg(mmc_dev(host
->mmc
), "desired SD clock: %d, actual: %d\n",
628 clock
, host
->mmc
->actual_clock
);
630 if (imx_data
->is_ddr
)
636 temp
= sdhci_readl(host
, ESDHC_SYSTEM_CONTROL
);
637 temp
|= (ESDHC_CLOCK_IPGEN
| ESDHC_CLOCK_HCKEN
| ESDHC_CLOCK_PEREN
638 | (div
<< ESDHC_DIVIDER_SHIFT
)
639 | (pre_div
<< ESDHC_PREDIV_SHIFT
));
640 sdhci_writel(host
, temp
, ESDHC_SYSTEM_CONTROL
);
642 if (esdhc_is_usdhc(imx_data
)) {
643 val
= readl(host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
644 writel(val
| ESDHC_VENDOR_SPEC_FRC_SDCLK_ON
,
645 host
->ioaddr
+ ESDHC_VENDOR_SPEC
);
651 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host
*host
)
653 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
654 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
655 struct esdhc_platform_data
*boarddata
= &imx_data
->boarddata
;
657 switch (boarddata
->wp_type
) {
659 return mmc_gpio_get_ro(host
->mmc
);
660 case ESDHC_WP_CONTROLLER
:
661 return !(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) &
662 SDHCI_WRITE_PROTECT
);
670 static void esdhc_pltfm_set_bus_width(struct sdhci_host
*host
, int width
)
675 case MMC_BUS_WIDTH_8
:
676 ctrl
= ESDHC_CTRL_8BITBUS
;
678 case MMC_BUS_WIDTH_4
:
679 ctrl
= ESDHC_CTRL_4BITBUS
;
686 esdhc_clrset_le(host
, ESDHC_CTRL_BUSWIDTH_MASK
, ctrl
,
690 static void esdhc_prepare_tuning(struct sdhci_host
*host
, u32 val
)
694 /* FIXME: delay a bit for card to be ready for next tuning due to errors */
697 reg
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
698 reg
|= ESDHC_MIX_CTRL_EXE_TUNE
| ESDHC_MIX_CTRL_SMPCLK_SEL
|
699 ESDHC_MIX_CTRL_FBCLK_SEL
;
700 writel(reg
, host
->ioaddr
+ ESDHC_MIX_CTRL
);
701 writel(val
<< 8, host
->ioaddr
+ ESDHC_TUNE_CTRL_STATUS
);
702 dev_dbg(mmc_dev(host
->mmc
),
703 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n",
704 val
, readl(host
->ioaddr
+ ESDHC_TUNE_CTRL_STATUS
));
707 static void esdhc_post_tuning(struct sdhci_host
*host
)
711 reg
= readl(host
->ioaddr
+ ESDHC_MIX_CTRL
);
712 reg
&= ~ESDHC_MIX_CTRL_EXE_TUNE
;
713 writel(reg
, host
->ioaddr
+ ESDHC_MIX_CTRL
);
716 static int esdhc_executing_tuning(struct sdhci_host
*host
, u32 opcode
)
718 int min
, max
, avg
, ret
;
720 /* find the mininum delay first which can pass tuning */
721 min
= ESDHC_TUNE_CTRL_MIN
;
722 while (min
< ESDHC_TUNE_CTRL_MAX
) {
723 esdhc_prepare_tuning(host
, min
);
724 if (!mmc_send_tuning(host
->mmc
))
726 min
+= ESDHC_TUNE_CTRL_STEP
;
729 /* find the maxinum delay which can not pass tuning */
730 max
= min
+ ESDHC_TUNE_CTRL_STEP
;
731 while (max
< ESDHC_TUNE_CTRL_MAX
) {
732 esdhc_prepare_tuning(host
, max
);
733 if (mmc_send_tuning(host
->mmc
)) {
734 max
-= ESDHC_TUNE_CTRL_STEP
;
737 max
+= ESDHC_TUNE_CTRL_STEP
;
740 /* use average delay to get the best timing */
741 avg
= (min
+ max
) / 2;
742 esdhc_prepare_tuning(host
, avg
);
743 ret
= mmc_send_tuning(host
->mmc
);
744 esdhc_post_tuning(host
);
746 dev_dbg(mmc_dev(host
->mmc
), "tunning %s at 0x%x ret %d\n",
747 ret
? "failed" : "passed", avg
, ret
);
752 static int esdhc_change_pinstate(struct sdhci_host
*host
,
755 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
756 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
757 struct pinctrl_state
*pinctrl
;
759 dev_dbg(mmc_dev(host
->mmc
), "change pinctrl state for uhs %d\n", uhs
);
761 if (IS_ERR(imx_data
->pinctrl
) ||
762 IS_ERR(imx_data
->pins_default
) ||
763 IS_ERR(imx_data
->pins_100mhz
) ||
764 IS_ERR(imx_data
->pins_200mhz
))
768 case MMC_TIMING_UHS_SDR50
:
769 pinctrl
= imx_data
->pins_100mhz
;
771 case MMC_TIMING_UHS_SDR104
:
772 case MMC_TIMING_MMC_HS200
:
773 pinctrl
= imx_data
->pins_200mhz
;
776 /* back to default state for other legacy timing */
777 pinctrl
= imx_data
->pins_default
;
780 return pinctrl_select_state(imx_data
->pinctrl
, pinctrl
);
783 static void esdhc_set_uhs_signaling(struct sdhci_host
*host
, unsigned timing
)
785 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
786 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
787 struct esdhc_platform_data
*boarddata
= &imx_data
->boarddata
;
790 case MMC_TIMING_UHS_SDR12
:
791 case MMC_TIMING_UHS_SDR25
:
792 case MMC_TIMING_UHS_SDR50
:
793 case MMC_TIMING_UHS_SDR104
:
794 case MMC_TIMING_MMC_HS200
:
796 case MMC_TIMING_UHS_DDR50
:
797 case MMC_TIMING_MMC_DDR52
:
798 writel(readl(host
->ioaddr
+ ESDHC_MIX_CTRL
) |
799 ESDHC_MIX_CTRL_DDREN
,
800 host
->ioaddr
+ ESDHC_MIX_CTRL
);
801 imx_data
->is_ddr
= 1;
802 if (boarddata
->delay_line
) {
804 v
= boarddata
->delay_line
<<
805 ESDHC_DLL_OVERRIDE_VAL_SHIFT
|
806 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT
);
807 if (is_imx53_esdhc(imx_data
))
809 writel(v
, host
->ioaddr
+ ESDHC_DLL_CTRL
);
814 esdhc_change_pinstate(host
, timing
);
817 static void esdhc_reset(struct sdhci_host
*host
, u8 mask
)
819 sdhci_reset(host
, mask
);
821 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
822 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
825 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host
*host
)
827 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
828 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
830 return esdhc_is_usdhc(imx_data
) ? 1 << 28 : 1 << 27;
833 static void esdhc_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
835 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
836 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
838 /* use maximum timeout counter */
839 sdhci_writeb(host
, esdhc_is_usdhc(imx_data
) ? 0xF : 0xE,
840 SDHCI_TIMEOUT_CONTROL
);
843 static struct sdhci_ops sdhci_esdhc_ops
= {
844 .read_l
= esdhc_readl_le
,
845 .read_w
= esdhc_readw_le
,
846 .write_l
= esdhc_writel_le
,
847 .write_w
= esdhc_writew_le
,
848 .write_b
= esdhc_writeb_le
,
849 .set_clock
= esdhc_pltfm_set_clock
,
850 .get_max_clock
= esdhc_pltfm_get_max_clock
,
851 .get_min_clock
= esdhc_pltfm_get_min_clock
,
852 .get_max_timeout_count
= esdhc_get_max_timeout_count
,
853 .get_ro
= esdhc_pltfm_get_ro
,
854 .set_timeout
= esdhc_set_timeout
,
855 .set_bus_width
= esdhc_pltfm_set_bus_width
,
856 .set_uhs_signaling
= esdhc_set_uhs_signaling
,
857 .reset
= esdhc_reset
,
860 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata
= {
861 .quirks
= ESDHC_DEFAULT_QUIRKS
| SDHCI_QUIRK_NO_HISPD_BIT
862 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
863 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
864 | SDHCI_QUIRK_BROKEN_CARD_DETECTION
,
865 .ops
= &sdhci_esdhc_ops
,
870 sdhci_esdhc_imx_probe_dt(struct platform_device
*pdev
,
871 struct sdhci_host
*host
,
872 struct esdhc_platform_data
*boarddata
)
874 struct device_node
*np
= pdev
->dev
.of_node
;
879 if (of_get_property(np
, "non-removable", NULL
))
880 boarddata
->cd_type
= ESDHC_CD_PERMANENT
;
882 if (of_get_property(np
, "fsl,cd-controller", NULL
))
883 boarddata
->cd_type
= ESDHC_CD_CONTROLLER
;
885 if (of_get_property(np
, "fsl,wp-controller", NULL
))
886 boarddata
->wp_type
= ESDHC_WP_CONTROLLER
;
888 boarddata
->cd_gpio
= of_get_named_gpio(np
, "cd-gpios", 0);
889 if (gpio_is_valid(boarddata
->cd_gpio
))
890 boarddata
->cd_type
= ESDHC_CD_GPIO
;
892 boarddata
->wp_gpio
= of_get_named_gpio(np
, "wp-gpios", 0);
893 if (gpio_is_valid(boarddata
->wp_gpio
))
894 boarddata
->wp_type
= ESDHC_WP_GPIO
;
896 of_property_read_u32(np
, "bus-width", &boarddata
->max_bus_width
);
898 of_property_read_u32(np
, "max-frequency", &boarddata
->f_max
);
900 if (of_find_property(np
, "no-1-8-v", NULL
))
901 boarddata
->support_vsel
= false;
903 boarddata
->support_vsel
= true;
905 if (of_property_read_u32(np
, "fsl,delay-line", &boarddata
->delay_line
))
906 boarddata
->delay_line
= 0;
908 mmc_of_parse_voltage(np
, &host
->ocr_mask
);
910 /* call to generic mmc_of_parse to support additional capabilities */
911 return mmc_of_parse(host
->mmc
);
915 sdhci_esdhc_imx_probe_dt(struct platform_device
*pdev
,
916 struct sdhci_host
*host
,
917 struct esdhc_platform_data
*boarddata
)
923 static int sdhci_esdhc_imx_probe(struct platform_device
*pdev
)
925 const struct of_device_id
*of_id
=
926 of_match_device(imx_esdhc_dt_ids
, &pdev
->dev
);
927 struct sdhci_pltfm_host
*pltfm_host
;
928 struct sdhci_host
*host
;
929 struct esdhc_platform_data
*boarddata
;
931 struct pltfm_imx_data
*imx_data
;
934 host
= sdhci_pltfm_init(pdev
, &sdhci_esdhc_imx_pdata
, 0);
936 return PTR_ERR(host
);
938 pltfm_host
= sdhci_priv(host
);
940 imx_data
= devm_kzalloc(&pdev
->dev
, sizeof(*imx_data
), GFP_KERNEL
);
946 imx_data
->socdata
= of_id
? of_id
->data
: (struct esdhc_soc_data
*)
947 pdev
->id_entry
->driver_data
;
948 pltfm_host
->priv
= imx_data
;
950 imx_data
->clk_ipg
= devm_clk_get(&pdev
->dev
, "ipg");
951 if (IS_ERR(imx_data
->clk_ipg
)) {
952 err
= PTR_ERR(imx_data
->clk_ipg
);
956 imx_data
->clk_ahb
= devm_clk_get(&pdev
->dev
, "ahb");
957 if (IS_ERR(imx_data
->clk_ahb
)) {
958 err
= PTR_ERR(imx_data
->clk_ahb
);
962 imx_data
->clk_per
= devm_clk_get(&pdev
->dev
, "per");
963 if (IS_ERR(imx_data
->clk_per
)) {
964 err
= PTR_ERR(imx_data
->clk_per
);
968 pltfm_host
->clk
= imx_data
->clk_per
;
969 pltfm_host
->clock
= clk_get_rate(pltfm_host
->clk
);
970 clk_prepare_enable(imx_data
->clk_per
);
971 clk_prepare_enable(imx_data
->clk_ipg
);
972 clk_prepare_enable(imx_data
->clk_ahb
);
974 imx_data
->pinctrl
= devm_pinctrl_get(&pdev
->dev
);
975 if (IS_ERR(imx_data
->pinctrl
)) {
976 err
= PTR_ERR(imx_data
->pinctrl
);
980 imx_data
->pins_default
= pinctrl_lookup_state(imx_data
->pinctrl
,
981 PINCTRL_STATE_DEFAULT
);
982 if (IS_ERR(imx_data
->pins_default
))
983 dev_warn(mmc_dev(host
->mmc
), "could not get default state\n");
985 host
->quirks
|= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
;
987 if (imx_data
->socdata
->flags
& ESDHC_FLAG_ENGCM07207
)
988 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
989 host
->quirks
|= SDHCI_QUIRK_NO_MULTIBLOCK
990 | SDHCI_QUIRK_BROKEN_ADMA
;
993 * The imx6q ROM code will change the default watermark level setting
994 * to something insane. Change it back here.
996 if (esdhc_is_usdhc(imx_data
)) {
997 writel(0x08100810, host
->ioaddr
+ ESDHC_WTMK_LVL
);
998 host
->quirks2
|= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
;
999 host
->mmc
->caps
|= MMC_CAP_1_8V_DDR
;
1002 * errata ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL
1003 * TO1.1, it's harmless for MX6SL
1005 writel(readl(host
->ioaddr
+ 0x6c) | BIT(7),
1006 host
->ioaddr
+ 0x6c);
1009 if (imx_data
->socdata
->flags
& ESDHC_FLAG_MAN_TUNING
)
1010 sdhci_esdhc_ops
.platform_execute_tuning
=
1011 esdhc_executing_tuning
;
1013 if (imx_data
->socdata
->flags
& ESDHC_FLAG_STD_TUNING
)
1014 writel(readl(host
->ioaddr
+ ESDHC_TUNING_CTRL
) |
1015 ESDHC_STD_TUNING_EN
| ESDHC_TUNING_START_TAP
,
1016 host
->ioaddr
+ ESDHC_TUNING_CTRL
);
1018 if (imx_data
->socdata
->flags
& ESDHC_FLAG_ERR004536
)
1019 host
->quirks
|= SDHCI_QUIRK_BROKEN_ADMA
;
1021 boarddata
= &imx_data
->boarddata
;
1022 if (sdhci_esdhc_imx_probe_dt(pdev
, host
, boarddata
) < 0) {
1023 if (!host
->mmc
->parent
->platform_data
) {
1024 dev_err(mmc_dev(host
->mmc
), "no board data!\n");
1028 imx_data
->boarddata
= *((struct esdhc_platform_data
*)
1029 host
->mmc
->parent
->platform_data
);
1033 if (boarddata
->wp_type
== ESDHC_WP_GPIO
&& !dt
) {
1034 err
= mmc_gpio_request_ro(host
->mmc
, boarddata
->wp_gpio
);
1036 dev_err(mmc_dev(host
->mmc
),
1037 "failed to request write-protect gpio!\n");
1040 host
->mmc
->caps2
|= MMC_CAP2_RO_ACTIVE_HIGH
;
1044 switch (boarddata
->cd_type
) {
1048 err
= mmc_gpio_request_cd(host
->mmc
, boarddata
->cd_gpio
, 0);
1050 dev_err(mmc_dev(host
->mmc
),
1051 "failed to request card-detect gpio!\n");
1056 case ESDHC_CD_CONTROLLER
:
1057 /* we have a working card_detect back */
1058 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
1061 case ESDHC_CD_PERMANENT
:
1062 host
->mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
1069 switch (boarddata
->max_bus_width
) {
1071 host
->mmc
->caps
|= MMC_CAP_8_BIT_DATA
| MMC_CAP_4_BIT_DATA
;
1074 host
->mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
1078 host
->quirks
|= SDHCI_QUIRK_FORCE_1_BIT_DATA
;
1082 /* sdr50 and sdr104 needs work on 1.8v signal voltage */
1083 if ((boarddata
->support_vsel
) && esdhc_is_usdhc(imx_data
) &&
1084 !IS_ERR(imx_data
->pins_default
)) {
1085 imx_data
->pins_100mhz
= pinctrl_lookup_state(imx_data
->pinctrl
,
1086 ESDHC_PINCTRL_STATE_100MHZ
);
1087 imx_data
->pins_200mhz
= pinctrl_lookup_state(imx_data
->pinctrl
,
1088 ESDHC_PINCTRL_STATE_200MHZ
);
1089 if (IS_ERR(imx_data
->pins_100mhz
) ||
1090 IS_ERR(imx_data
->pins_200mhz
)) {
1091 dev_warn(mmc_dev(host
->mmc
),
1092 "could not get ultra high speed state, work on normal mode\n");
1093 /* fall back to not support uhs by specify no 1.8v quirk */
1094 host
->quirks2
|= SDHCI_QUIRK2_NO_1_8_V
;
1097 host
->quirks2
|= SDHCI_QUIRK2_NO_1_8_V
;
1100 err
= sdhci_add_host(host
);
1104 pm_runtime_set_active(&pdev
->dev
);
1105 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
1106 pm_runtime_use_autosuspend(&pdev
->dev
);
1107 pm_suspend_ignore_children(&pdev
->dev
, 1);
1108 pm_runtime_enable(&pdev
->dev
);
1113 clk_disable_unprepare(imx_data
->clk_per
);
1114 clk_disable_unprepare(imx_data
->clk_ipg
);
1115 clk_disable_unprepare(imx_data
->clk_ahb
);
1117 sdhci_pltfm_free(pdev
);
1121 static int sdhci_esdhc_imx_remove(struct platform_device
*pdev
)
1123 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
1124 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1125 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
1126 int dead
= (readl(host
->ioaddr
+ SDHCI_INT_STATUS
) == 0xffffffff);
1128 pm_runtime_get_sync(&pdev
->dev
);
1129 pm_runtime_disable(&pdev
->dev
);
1130 pm_runtime_put_noidle(&pdev
->dev
);
1132 sdhci_remove_host(host
, dead
);
1134 clk_disable_unprepare(imx_data
->clk_per
);
1135 clk_disable_unprepare(imx_data
->clk_ipg
);
1136 clk_disable_unprepare(imx_data
->clk_ahb
);
1138 sdhci_pltfm_free(pdev
);
1144 static int sdhci_esdhc_runtime_suspend(struct device
*dev
)
1146 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1147 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1148 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
1151 ret
= sdhci_runtime_suspend_host(host
);
1153 if (!sdhci_sdio_irq_enabled(host
)) {
1154 clk_disable_unprepare(imx_data
->clk_per
);
1155 clk_disable_unprepare(imx_data
->clk_ipg
);
1157 clk_disable_unprepare(imx_data
->clk_ahb
);
1162 static int sdhci_esdhc_runtime_resume(struct device
*dev
)
1164 struct sdhci_host
*host
= dev_get_drvdata(dev
);
1165 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1166 struct pltfm_imx_data
*imx_data
= pltfm_host
->priv
;
1168 if (!sdhci_sdio_irq_enabled(host
)) {
1169 clk_prepare_enable(imx_data
->clk_per
);
1170 clk_prepare_enable(imx_data
->clk_ipg
);
1172 clk_prepare_enable(imx_data
->clk_ahb
);
1174 return sdhci_runtime_resume_host(host
);
1178 static const struct dev_pm_ops sdhci_esdhc_pmops
= {
1179 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend
, sdhci_pltfm_resume
)
1180 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend
,
1181 sdhci_esdhc_runtime_resume
, NULL
)
1184 static struct platform_driver sdhci_esdhc_imx_driver
= {
1186 .name
= "sdhci-esdhc-imx",
1187 .of_match_table
= imx_esdhc_dt_ids
,
1188 .pm
= &sdhci_esdhc_pmops
,
1190 .id_table
= imx_esdhc_devtype
,
1191 .probe
= sdhci_esdhc_imx_probe
,
1192 .remove
= sdhci_esdhc_imx_remove
,
1195 module_platform_driver(sdhci_esdhc_imx_driver
);
1197 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
1198 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>");
1199 MODULE_LICENSE("GPL v2");