drivers/mmc/host/sdhci-of-esdhc.c

   1 /*
   2  * Freescale eSDHC controller driver.
   3  *
   4  * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
   5  * Copyright (c) 2009 MontaVista Software, Inc.
   6  *
   7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
   8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/of.h>
  19 #include <linux/delay.h>
  20 #include <linux/module.h>
  21 #include <linux/mmc/host.h>
  22 #include "sdhci-pltfm.h"
  23 #include "sdhci-esdhc.h"
  24
  25 #define VENDOR_V_22     0x12
  26 #define VENDOR_V_23     0x13
  27 static u32 esdhc_readl(struct sdhci_host *host, int reg)
  28 {
  29         u32 ret;
  30
  31         ret = in_be32(host->ioaddr + reg);
  32         /*
  33          * The bit of ADMA flag in eSDHC is not compatible with standard
  34          * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
  35          * supported by eSDHC.
  36          * And for many FSL eSDHC controller, the reset value of field
  37          * SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA,
  38          * only these vendor version is greater than 2.2/0x12 support ADMA.
  39          * For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
  40          * the verdor version number, oxFE is SDHCI_HOST_VERSION.
  41          */
  42         if ((reg == SDHCI_CAPABILITIES) && (ret & SDHCI_CAN_DO_ADMA1)) {
  43                 u32 tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
  44                 tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
  45                 if (tmp > VENDOR_V_22)
  46                         ret |= SDHCI_CAN_DO_ADMA2;
  47         }
  48
  49         return ret;
  50 }
  51
  52 static u16 esdhc_readw(struct sdhci_host *host, int reg)
  53 {
  54         u16 ret;
  55         int base = reg & ~0x3;
  56         int shift = (reg & 0x2) * 8;
  57
  58         if (unlikely(reg == SDHCI_HOST_VERSION))
  59                 ret = in_be32(host->ioaddr + base) & 0xffff;
  60         else
  61                 ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff;
  62         return ret;
  63 }
  64
  65 static u8 esdhc_readb(struct sdhci_host *host, int reg)
  66 {
  67         int base = reg & ~0x3;
  68         int shift = (reg & 0x3) * 8;
  69         u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff;
  70
  71         /*
  72          * "DMA select" locates at offset 0x28 in SD specification, but on
  73          * P5020 or P3041, it locates at 0x29.
  74          */
  75         if (reg == SDHCI_HOST_CONTROL) {
  76                 u32 dma_bits;
  77
  78                 dma_bits = in_be32(host->ioaddr + reg);
  79                 /* DMA select is 22,23 bits in Protocol Control Register */
  80                 dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK;
  81
  82                 /* fixup the result */
  83                 ret &= ~SDHCI_CTRL_DMA_MASK;
  84                 ret |= dma_bits;
  85         }
  86
  87         return ret;
  88 }
  89
  90 static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
  91 {
  92         /*
  93          * Enable IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
  94          * when SYSCTL[RSTD]) is set for some special operations.
  95          * No any impact other operation.
  96          */
  97         if (reg == SDHCI_INT_ENABLE)
  98                 val |= SDHCI_INT_BLK_GAP;
  99         sdhci_be32bs_writel(host, val, reg);
 100 }
 101
 102 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
 103 {
 104         if (reg == SDHCI_BLOCK_SIZE) {
 105                 /*
 106                  * Two last DMA bits are reserved, and first one is used for
 107                  * non-standard blksz of 4096 bytes that we don't support
 108                  * yet. So clear the DMA boundary bits.
 109                  */
 110                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 111         }
 112         sdhci_be32bs_writew(host, val, reg);
 113 }
 114
 115 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
 116 {
 117         /*
 118          * "DMA select" location is offset 0x28 in SD specification, but on
 119          * P5020 or P3041, it's located at 0x29.
 120          */
 121         if (reg == SDHCI_HOST_CONTROL) {
 122                 u32 dma_bits;
 123
 124                 /* DMA select is 22,23 bits in Protocol Control Register */
 125                 dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5;
 126                 clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5,
 127                         dma_bits);
 128                 val &= ~SDHCI_CTRL_DMA_MASK;
 129                 val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK;
 130         }
 131
 132         /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
 133         if (reg == SDHCI_HOST_CONTROL)
 134                 val &= ~ESDHC_HOST_CONTROL_RES;
 135         sdhci_be32bs_writeb(host, val, reg);
 136 }
 137
 138 /*
 139  * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
 140  * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
 141  * and Block Gap Event(IRQSTAT[BGE]) are also set.
 142  * For Continue, apply soft reset for data(SYSCTL[RSTD]);
 143  * and re-issue the entire read transaction from beginning.
 144  */
 145 static void esdhci_of_adma_workaround(struct sdhci_host *host, u32 intmask)
 146 {
 147         u32 tmp;
 148         bool applicable;
 149         dma_addr_t dmastart;
 150         dma_addr_t dmanow;
 151
 152         tmp = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
 153         tmp = (tmp & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
 154
 155         applicable = (intmask & SDHCI_INT_DATA_END) &&
 156                 (intmask & SDHCI_INT_BLK_GAP) &&
 157                 (tmp == VENDOR_V_23);
 158         if (!applicable)
 159                 return;
 160
 161         host->data->error = 0;
 162         dmastart = sg_dma_address(host->data->sg);
 163         dmanow = dmastart + host->data->bytes_xfered;
 164         /*
 165          * Force update to the next DMA block boundary.
 166          */
 167         dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
 168                 SDHCI_DEFAULT_BOUNDARY_SIZE;
 169         host->data->bytes_xfered = dmanow - dmastart;
 170         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
 171 }
 172
 173 static int esdhc_of_enable_dma(struct sdhci_host *host)
 174 {
 175         setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
 176         return 0;
 177 }
 178
 179 static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host)
 180 {
 181         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 182
 183         return pltfm_host->clock;
 184 }
 185
 186 static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host)
 187 {
 188         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 189
 190         return pltfm_host->clock / 256 / 16;
 191 }
 192
 193 static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock)
 194 {
 195         /* Workaround to reduce the clock frequency for p1010 esdhc */
 196         if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) {
 197                 if (clock > 20000000)
 198                         clock -= 5000000;
 199                 if (clock > 40000000)
 200                         clock -= 5000000;
 201         }
 202
 203         /* Set the clock */
 204         esdhc_set_clock(host, clock, host->max_clk);
 205 }
 206
 207 #ifdef CONFIG_PM
 208 static u32 esdhc_proctl;
 209 static void esdhc_of_suspend(struct sdhci_host *host)
 210 {
 211         esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL);
 212 }
 213
 214 static void esdhc_of_resume(struct sdhci_host *host)
 215 {
 216         esdhc_of_enable_dma(host);
 217         sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL);
 218 }
 219 #endif
 220
 221 static void esdhc_of_platform_init(struct sdhci_host *host)
 222 {
 223         u32 vvn;
 224
 225         vvn = in_be32(host->ioaddr + SDHCI_SLOT_INT_STATUS);
 226         vvn = (vvn & SDHCI_VENDOR_VER_MASK) >> SDHCI_VENDOR_VER_SHIFT;
 227         if (vvn == VENDOR_V_22)
 228                 host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23;
 229
 230         if (vvn > VENDOR_V_22)
 231                 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ;
 232 }
 233
 234 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width)
 235 {
 236         u32 ctrl;
 237
 238         switch (width) {
 239         case MMC_BUS_WIDTH_8:
 240                 ctrl = ESDHC_CTRL_8BITBUS;
 241                 break;
 242
 243         case MMC_BUS_WIDTH_4:
 244                 ctrl = ESDHC_CTRL_4BITBUS;
 245                 break;
 246
 247         default:
 248                 ctrl = 0;
 249                 break;
 250         }
 251
 252         clrsetbits_be32(host->ioaddr + SDHCI_HOST_CONTROL,
 253                         ESDHC_CTRL_BUSWIDTH_MASK, ctrl);
 254
 255         return 0;
 256 }
 257
 258 static const struct sdhci_ops sdhci_esdhc_ops = {
 259         .read_l = esdhc_readl,
 260         .read_w = esdhc_readw,
 261         .read_b = esdhc_readb,
 262         .write_l = esdhc_writel,
 263         .write_w = esdhc_writew,
 264         .write_b = esdhc_writeb,
 265         .set_clock = esdhc_of_set_clock,
 266         .enable_dma = esdhc_of_enable_dma,
 267         .get_max_clock = esdhc_of_get_max_clock,
 268         .get_min_clock = esdhc_of_get_min_clock,
 269         .platform_init = esdhc_of_platform_init,
 270 #ifdef CONFIG_PM
 271         .platform_suspend = esdhc_of_suspend,
 272         .platform_resume = esdhc_of_resume,
 273 #endif
 274         .adma_workaround = esdhci_of_adma_workaround,
 275         .platform_bus_width = esdhc_pltfm_bus_width,
 276 };
 277
 278 static const struct sdhci_pltfm_data sdhci_esdhc_pdata = {
 279         /*
 280          * card detection could be handled via GPIO
 281          * eSDHC cannot support End Attribute in NOP ADMA descriptor
 282          */
 283         .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION
 284                 | SDHCI_QUIRK_NO_CARD_NO_RESET
 285                 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
 286         .ops = &sdhci_esdhc_ops,
 287 };
 288
 289 static int sdhci_esdhc_probe(struct platform_device *pdev)
 290 {
 291         struct sdhci_host *host;
 292         int ret;
 293
 294         host = sdhci_pltfm_init(pdev, &sdhci_esdhc_pdata, 0);
 295         if (IS_ERR(host))
 296                 return PTR_ERR(host);
 297
 298         sdhci_get_of_property(pdev);
 299
 300         /* call to generic mmc_of_parse to support additional capabilities */
 301         mmc_of_parse(host->mmc);
 302
 303         ret = sdhci_add_host(host);
 304         if (ret)
 305                 sdhci_pltfm_free(pdev);
 306
 307         return ret;
 308 }
 309
 310 static int sdhci_esdhc_remove(struct platform_device *pdev)
 311 {
 312         return sdhci_pltfm_unregister(pdev);
 313 }
 314
 315 static const struct of_device_id sdhci_esdhc_of_match[] = {
 316         { .compatible = "fsl,mpc8379-esdhc" },
 317         { .compatible = "fsl,mpc8536-esdhc" },
 318         { .compatible = "fsl,esdhc" },
 319         { }
 320 };
 321 MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match);
 322
 323 static struct platform_driver sdhci_esdhc_driver = {
 324         .driver = {
 325                 .name = "sdhci-esdhc",
 326                 .owner = THIS_MODULE,
 327                 .of_match_table = sdhci_esdhc_of_match,
 328                 .pm = SDHCI_PLTFM_PMOPS,
 329         },
 330         .probe = sdhci_esdhc_probe,
 331         .remove = sdhci_esdhc_remove,
 332 };
 333
 334 module_platform_driver(sdhci_esdhc_driver);
 335
 336 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
 337 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
 338               "Anton Vorontsov <avorontsov@ru.mvista.com>");
 339 MODULE_LICENSE("GPL v2");