drivers/mmc/host/sdhci-of.c

   1 /*
   2  * OpenFirmware bindings for Secure Digital Host Controller Interface.
   3  *
   4  * Copyright (c) 2007 Freescale Semiconductor, Inc.
   5  * Copyright (c) 2009 MontaVista Software, Inc.
   6  *
   7  * Authors: Xiaobo Xie <X.Xie@freescale.com>
   8  *          Anton Vorontsov <avorontsov@ru.mvista.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21 #include <linux/of.h>
  22 #include <linux/of_platform.h>
  23 #include <linux/mmc/host.h>
  24 #include "sdhci.h"
  25
  26 struct sdhci_of_data {
  27         unsigned int quirks;
  28         struct sdhci_ops ops;
  29 };
  30
  31 struct sdhci_of_host {
  32         unsigned int clock;
  33         u16 xfer_mode_shadow;
  34 };
  35
  36 /*
  37  * Ops and quirks for the Freescale eSDHC controller.
  38  */
  39
  40 #define ESDHC_DMA_SYSCTL        0x40c
  41 #define ESDHC_DMA_SNOOP         0x00000040
  42
  43 #define ESDHC_SYSTEM_CONTROL    0x2c
  44 #define ESDHC_CLOCK_MASK        0x0000fff0
  45 #define ESDHC_PREDIV_SHIFT      8
  46 #define ESDHC_DIVIDER_SHIFT     4
  47 #define ESDHC_CLOCK_PEREN       0x00000004
  48 #define ESDHC_CLOCK_HCKEN       0x00000002
  49 #define ESDHC_CLOCK_IPGEN       0x00000001
  50
  51 static u32 esdhc_readl(struct sdhci_host *host, int reg)
  52 {
  53         return in_be32(host->ioaddr + reg);
  54 }
  55
  56 static u16 esdhc_readw(struct sdhci_host *host, int reg)
  57 {
  58         u16 ret;
  59
  60         if (unlikely(reg == SDHCI_HOST_VERSION))
  61                 ret = in_be16(host->ioaddr + reg);
  62         else
  63                 ret = in_be16(host->ioaddr + (reg ^ 0x2));
  64         return ret;
  65 }
  66
  67 static u8 esdhc_readb(struct sdhci_host *host, int reg)
  68 {
  69         return in_8(host->ioaddr + (reg ^ 0x3));
  70 }
  71
  72 static void esdhc_writel(struct sdhci_host *host, u32 val, int reg)
  73 {
  74         out_be32(host->ioaddr + reg, val);
  75 }
  76
  77 static void esdhc_writew(struct sdhci_host *host, u16 val, int reg)
  78 {
  79         struct sdhci_of_host *of_host = sdhci_priv(host);
  80         int base = reg & ~0x3;
  81         int shift = (reg & 0x2) * 8;
  82
  83         switch (reg) {
  84         case SDHCI_TRANSFER_MODE:
  85                 /*
  86                  * Postpone this write, we must do it together with a
  87                  * command write that is down below.
  88                  */
  89                 of_host->xfer_mode_shadow = val;
  90                 return;
  91         case SDHCI_COMMAND:
  92                 esdhc_writel(host, val << 16 | of_host->xfer_mode_shadow,
  93                              SDHCI_TRANSFER_MODE);
  94                 return;
  95         case SDHCI_BLOCK_SIZE:
  96                 /*
  97                  * Two last DMA bits are reserved, and first one is used for
  98                  * non-standard blksz of 4096 bytes that we don't support
  99                  * yet. So clear the DMA boundary bits.
 100                  */
 101                 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
 102                 /* fall through */
 103         }
 104         clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
 105 }
 106
 107 static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg)
 108 {
 109         int base = reg & ~0x3;
 110         int shift = (reg & 0x3) * 8;
 111
 112         clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
 113 }
 114
 115 static void esdhc_set_clock(struct sdhci_host *host, unsigned int clock)
 116 {
 117         int div;
 118         int pre_div = 2;
 119
 120         clrbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
 121                   ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK);
 122
 123         if (clock == 0)
 124                 goto out;
 125
 126         if (host->max_clk / 16 > clock) {
 127                 for (; pre_div < 256; pre_div *= 2) {
 128                         if (host->max_clk / pre_div < clock * 16)
 129                                 break;
 130                 }
 131         }
 132
 133         for (div = 1; div <= 16; div++) {
 134                 if (host->max_clk / (div * pre_div) <= clock)
 135                         break;
 136         }
 137
 138         pre_div >>= 1;
 139
 140         setbits32(host->ioaddr + ESDHC_SYSTEM_CONTROL, ESDHC_CLOCK_IPGEN |
 141                   ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN |
 142                   div << ESDHC_DIVIDER_SHIFT | pre_div << ESDHC_PREDIV_SHIFT);
 143         mdelay(100);
 144 out:
 145         host->clock = clock;
 146 }
 147
 148 static int esdhc_enable_dma(struct sdhci_host *host)
 149 {
 150         setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP);
 151         return 0;
 152 }
 153
 154 static unsigned int esdhc_get_max_clock(struct sdhci_host *host)
 155 {
 156         struct sdhci_of_host *of_host = sdhci_priv(host);
 157
 158         return of_host->clock;
 159 }
 160
 161 static unsigned int esdhc_get_timeout_clock(struct sdhci_host *host)
 162 {
 163         struct sdhci_of_host *of_host = sdhci_priv(host);
 164
 165         return of_host->clock / 1000;
 166 }
 167
 168 static struct sdhci_of_data sdhci_esdhc = {
 169         .quirks = SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
 170                   SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 171                   SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
 172                   SDHCI_QUIRK_NO_BUSY_IRQ |
 173                   SDHCI_QUIRK_NONSTANDARD_CLOCK |
 174                   SDHCI_QUIRK_PIO_NEEDS_DELAY |
 175                   SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
 176                   SDHCI_QUIRK_NO_CARD_NO_RESET,
 177         .ops = {
 178                 .readl = esdhc_readl,
 179                 .readw = esdhc_readw,
 180                 .readb = esdhc_readb,
 181                 .writel = esdhc_writel,
 182                 .writew = esdhc_writew,
 183                 .writeb = esdhc_writeb,
 184                 .set_clock = esdhc_set_clock,
 185                 .enable_dma = esdhc_enable_dma,
 186                 .get_max_clock = esdhc_get_max_clock,
 187                 .get_timeout_clock = esdhc_get_timeout_clock,
 188         },
 189 };
 190
 191 #ifdef CONFIG_PM
 192
 193 static int sdhci_of_suspend(struct of_device *ofdev, pm_message_t state)
 194 {
 195         struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
 196
 197         return mmc_suspend_host(host->mmc, state);
 198 }
 199
 200 static int sdhci_of_resume(struct of_device *ofdev)
 201 {
 202         struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
 203
 204         return mmc_resume_host(host->mmc);
 205 }
 206
 207 #else
 208
 209 #define sdhci_of_suspend NULL
 210 #define sdhci_of_resume NULL
 211
 212 #endif
 213
 214 static int __devinit sdhci_of_probe(struct of_device *ofdev,
 215                                  const struct of_device_id *match)
 216 {
 217         struct device_node *np = ofdev->node;
 218         struct sdhci_of_data *sdhci_of_data = match->data;
 219         struct sdhci_host *host;
 220         struct sdhci_of_host *of_host;
 221         const u32 *clk;
 222         int size;
 223         int ret;
 224
 225         if (!of_device_is_available(np))
 226                 return -ENODEV;
 227
 228         host = sdhci_alloc_host(&ofdev->dev, sizeof(*of_host));
 229         if (!host)
 230                 return -ENOMEM;
 231
 232         of_host = sdhci_priv(host);
 233         dev_set_drvdata(&ofdev->dev, host);
 234
 235         host->ioaddr = of_iomap(np, 0);
 236         if (!host->ioaddr) {
 237                 ret = -ENOMEM;
 238                 goto err_addr_map;
 239         }
 240
 241         host->irq = irq_of_parse_and_map(np, 0);
 242         if (!host->irq) {
 243                 ret = -EINVAL;
 244                 goto err_no_irq;
 245         }
 246
 247         host->hw_name = dev_name(&ofdev->dev);
 248         if (sdhci_of_data) {
 249                 host->quirks = sdhci_of_data->quirks;
 250                 host->ops = &sdhci_of_data->ops;
 251         }
 252
 253         clk = of_get_property(np, "clock-frequency", &size);
 254         if (clk && size == sizeof(*clk) && *clk)
 255                 of_host->clock = *clk;
 256
 257         ret = sdhci_add_host(host);
 258         if (ret)
 259                 goto err_add_host;
 260
 261         return 0;
 262
 263 err_add_host:
 264         irq_dispose_mapping(host->irq);
 265 err_no_irq:
 266         iounmap(host->ioaddr);
 267 err_addr_map:
 268         sdhci_free_host(host);
 269         return ret;
 270 }
 271
 272 static int __devexit sdhci_of_remove(struct of_device *ofdev)
 273 {
 274         struct sdhci_host *host = dev_get_drvdata(&ofdev->dev);
 275
 276         sdhci_remove_host(host, 0);
 277         sdhci_free_host(host);
 278         irq_dispose_mapping(host->irq);
 279         iounmap(host->ioaddr);
 280         return 0;
 281 }
 282
 283 static const struct of_device_id sdhci_of_match[] = {
 284         { .compatible = "fsl,mpc8379-esdhc", .data = &sdhci_esdhc, },
 285         { .compatible = "fsl,mpc8536-esdhc", .data = &sdhci_esdhc, },
 286         { .compatible = "fsl,esdhc", .data = &sdhci_esdhc, },
 287         { .compatible = "generic-sdhci", },
 288         {},
 289 };
 290 MODULE_DEVICE_TABLE(of, sdhci_of_match);
 291
 292 static struct of_platform_driver sdhci_of_driver = {
 293         .driver.name = "sdhci-of",
 294         .match_table = sdhci_of_match,
 295         .probe = sdhci_of_probe,
 296         .remove = __devexit_p(sdhci_of_remove),
 297         .suspend = sdhci_of_suspend,
 298         .resume = sdhci_of_resume,
 299 };
 300
 301 static int __init sdhci_of_init(void)
 302 {
 303         return of_register_platform_driver(&sdhci_of_driver);
 304 }
 305 module_init(sdhci_of_init);
 306
 307 static void __exit sdhci_of_exit(void)
 308 {
 309         of_unregister_platform_driver(&sdhci_of_driver);
 310 }
 311 module_exit(sdhci_of_exit);
 312
 313 MODULE_DESCRIPTION("Secure Digital Host Controller Interface OF driver");
 314 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
 315               "Anton Vorontsov <avorontsov@ru.mvista.com>");
 316 MODULE_LICENSE("GPL");