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mmc: sdhci-pci: Enable HS400 for some Intel host controllers
[deliverable/linux.git] / drivers / mmc / host / sdhci-pci.c
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/delay.h>
16 #include <linux/highmem.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/slab.h>
21 #include <linux/device.h>
22 #include <linux/mmc/host.h>
23 #include <linux/mmc/mmc.h>
24 #include <linux/scatterlist.h>
25 #include <linux/io.h>
26 #include <linux/gpio.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/mmc/slot-gpio.h>
29 #include <linux/mmc/sdhci-pci-data.h>
30
31 #include "sdhci.h"
32 #include "sdhci-pci.h"
33 #include "sdhci-pci-o2micro.h"
34
35 /*****************************************************************************\
36 * *
37 * Hardware specific quirk handling *
38 * *
39 \*****************************************************************************/
40
41 static int ricoh_probe(struct sdhci_pci_chip *chip)
42 {
43 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
44 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
45 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
46 return 0;
47 }
48
49 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
50 {
51 slot->host->caps =
52 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
53 & SDHCI_TIMEOUT_CLK_MASK) |
54
55 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
56 & SDHCI_CLOCK_BASE_MASK) |
57
58 SDHCI_TIMEOUT_CLK_UNIT |
59 SDHCI_CAN_VDD_330 |
60 SDHCI_CAN_DO_HISPD |
61 SDHCI_CAN_DO_SDMA;
62 return 0;
63 }
64
65 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
66 {
67 /* Apply a delay to allow controller to settle */
68 /* Otherwise it becomes confused if card state changed
69 during suspend */
70 msleep(500);
71 return 0;
72 }
73
74 static const struct sdhci_pci_fixes sdhci_ricoh = {
75 .probe = ricoh_probe,
76 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
77 SDHCI_QUIRK_FORCE_DMA |
78 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
79 };
80
81 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
82 .probe_slot = ricoh_mmc_probe_slot,
83 .resume = ricoh_mmc_resume,
84 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
85 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
86 SDHCI_QUIRK_NO_CARD_NO_RESET |
87 SDHCI_QUIRK_MISSING_CAPS
88 };
89
90 static const struct sdhci_pci_fixes sdhci_ene_712 = {
91 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93 };
94
95 static const struct sdhci_pci_fixes sdhci_ene_714 = {
96 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
97 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
98 SDHCI_QUIRK_BROKEN_DMA,
99 };
100
101 static const struct sdhci_pci_fixes sdhci_cafe = {
102 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
103 SDHCI_QUIRK_NO_BUSY_IRQ |
104 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
105 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
106 };
107
108 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
109 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
110 };
111
112 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
113 {
114 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
115 return 0;
116 }
117
118 /*
119 * ADMA operation is disabled for Moorestown platform due to
120 * hardware bugs.
121 */
122 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
123 {
124 /*
125 * slots number is fixed here for MRST as SDIO3/5 are never used and
126 * have hardware bugs.
127 */
128 chip->num_slots = 1;
129 return 0;
130 }
131
132 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
133 {
134 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
135 return 0;
136 }
137
138 #ifdef CONFIG_PM
139
140 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
141 {
142 struct sdhci_pci_slot *slot = dev_id;
143 struct sdhci_host *host = slot->host;
144
145 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
146 return IRQ_HANDLED;
147 }
148
149 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
150 {
151 int err, irq, gpio = slot->cd_gpio;
152
153 slot->cd_gpio = -EINVAL;
154 slot->cd_irq = -EINVAL;
155
156 if (!gpio_is_valid(gpio))
157 return;
158
159 err = gpio_request(gpio, "sd_cd");
160 if (err < 0)
161 goto out;
162
163 err = gpio_direction_input(gpio);
164 if (err < 0)
165 goto out_free;
166
167 irq = gpio_to_irq(gpio);
168 if (irq < 0)
169 goto out_free;
170
171 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
172 IRQF_TRIGGER_FALLING, "sd_cd", slot);
173 if (err)
174 goto out_free;
175
176 slot->cd_gpio = gpio;
177 slot->cd_irq = irq;
178
179 return;
180
181 out_free:
182 gpio_free(gpio);
183 out:
184 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
185 }
186
187 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
188 {
189 if (slot->cd_irq >= 0)
190 free_irq(slot->cd_irq, slot);
191 if (gpio_is_valid(slot->cd_gpio))
192 gpio_free(slot->cd_gpio);
193 }
194
195 #else
196
197 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
198 {
199 }
200
201 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
202 {
203 }
204
205 #endif
206
207 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
208 {
209 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
210 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC |
211 MMC_CAP2_HC_ERASE_SZ;
212 return 0;
213 }
214
215 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
216 {
217 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
218 return 0;
219 }
220
221 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
222 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
223 .probe_slot = mrst_hc_probe_slot,
224 };
225
226 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
227 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
228 .probe = mrst_hc_probe,
229 };
230
231 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
232 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
233 .allow_runtime_pm = true,
234 .own_cd_for_runtime_pm = true,
235 };
236
237 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
238 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
239 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
240 .allow_runtime_pm = true,
241 .probe_slot = mfd_sdio_probe_slot,
242 };
243
244 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
245 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
246 .allow_runtime_pm = true,
247 .probe_slot = mfd_emmc_probe_slot,
248 };
249
250 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
251 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
252 .probe_slot = pch_hc_probe_slot,
253 };
254
255 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
256 {
257 u8 reg;
258
259 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
260 reg |= 0x10;
261 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
262 /* For eMMC, minimum is 1us but give it 9us for good measure */
263 udelay(9);
264 reg &= ~0x10;
265 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
266 /* For eMMC, minimum is 200us but give it 300us for good measure */
267 usleep_range(300, 1000);
268 }
269
270 static int spt_select_drive_strength(struct sdhci_host *host,
271 struct mmc_card *card,
272 unsigned int max_dtr,
273 int host_drv, int card_drv, int *drv_type)
274 {
275 int drive_strength;
276
277 if (sdhci_pci_spt_drive_strength > 0)
278 drive_strength = sdhci_pci_spt_drive_strength & 0xf;
279 else
280 drive_strength = 1; /* 33-ohm */
281
282 if ((mmc_driver_type_mask(drive_strength) & card_drv) == 0)
283 drive_strength = 0; /* Default 50-ohm */
284
285 return drive_strength;
286 }
287
288 /* Try to read the drive strength from the card */
289 static void spt_read_drive_strength(struct sdhci_host *host)
290 {
291 u32 val, i, t;
292 u16 m;
293
294 if (sdhci_pci_spt_drive_strength)
295 return;
296
297 sdhci_pci_spt_drive_strength = -1;
298
299 m = sdhci_readw(host, SDHCI_HOST_CONTROL2) & 0x7;
300 if (m != 3 && m != 5)
301 return;
302 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
303 if (val & 0x3)
304 return;
305 sdhci_writel(host, 0x007f0023, SDHCI_INT_ENABLE);
306 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
307 sdhci_writew(host, 0x10, SDHCI_TRANSFER_MODE);
308 sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
309 sdhci_writew(host, 512, SDHCI_BLOCK_SIZE);
310 sdhci_writew(host, 1, SDHCI_BLOCK_COUNT);
311 sdhci_writel(host, 0, SDHCI_ARGUMENT);
312 sdhci_writew(host, 0x83b, SDHCI_COMMAND);
313 for (i = 0; i < 1000; i++) {
314 val = sdhci_readl(host, SDHCI_INT_STATUS);
315 if (val & 0xffff8000)
316 return;
317 if (val & 0x20)
318 break;
319 udelay(1);
320 }
321 val = sdhci_readl(host, SDHCI_PRESENT_STATE);
322 if (!(val & 0x800))
323 return;
324 for (i = 0; i < 47; i++)
325 val = sdhci_readl(host, SDHCI_BUFFER);
326 t = val & 0xf00;
327 if (t != 0x200 && t != 0x300)
328 return;
329
330 sdhci_pci_spt_drive_strength = 0x10 | ((val >> 12) & 0xf);
331 }
332
333 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
334 {
335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
336 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
337 MMC_CAP_BUS_WIDTH_TEST |
338 MMC_CAP_WAIT_WHILE_BUSY;
339 slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
340 slot->hw_reset = sdhci_pci_int_hw_reset;
341 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
342 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
343 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_SPT_EMMC) {
344 spt_read_drive_strength(slot->host);
345 slot->select_drive_strength = spt_select_drive_strength;
346 }
347 return 0;
348 }
349
350 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
351 {
352 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
353 MMC_CAP_BUS_WIDTH_TEST |
354 MMC_CAP_WAIT_WHILE_BUSY;
355 return 0;
356 }
357
358 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
359 {
360 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST |
361 MMC_CAP_WAIT_WHILE_BUSY;
362 slot->cd_con_id = NULL;
363 slot->cd_idx = 0;
364 slot->cd_override_level = true;
365 return 0;
366 }
367
368 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
369 .allow_runtime_pm = true,
370 .probe_slot = byt_emmc_probe_slot,
371 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
372 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
373 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
374 SDHCI_QUIRK2_STOP_WITH_TC,
375 };
376
377 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
378 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
379 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
380 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
381 .allow_runtime_pm = true,
382 .probe_slot = byt_sdio_probe_slot,
383 };
384
385 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
386 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
387 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
388 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
389 SDHCI_QUIRK2_STOP_WITH_TC,
390 .allow_runtime_pm = true,
391 .own_cd_for_runtime_pm = true,
392 .probe_slot = byt_sd_probe_slot,
393 };
394
395 /* Define Host controllers for Intel Merrifield platform */
396 #define INTEL_MRFL_EMMC_0 0
397 #define INTEL_MRFL_EMMC_1 1
398
399 static int intel_mrfl_mmc_probe_slot(struct sdhci_pci_slot *slot)
400 {
401 if ((PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_0) &&
402 (PCI_FUNC(slot->chip->pdev->devfn) != INTEL_MRFL_EMMC_1))
403 /* SD support is not ready yet */
404 return -ENODEV;
405
406 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
407 MMC_CAP_1_8V_DDR;
408
409 return 0;
410 }
411
412 static const struct sdhci_pci_fixes sdhci_intel_mrfl_mmc = {
413 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
414 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
415 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
416 .allow_runtime_pm = true,
417 .probe_slot = intel_mrfl_mmc_probe_slot,
418 };
419
420 /* O2Micro extra registers */
421 #define O2_SD_LOCK_WP 0xD3
422 #define O2_SD_MULTI_VCC3V 0xEE
423 #define O2_SD_CLKREQ 0xEC
424 #define O2_SD_CAPS 0xE0
425 #define O2_SD_ADMA1 0xE2
426 #define O2_SD_ADMA2 0xE7
427 #define O2_SD_INF_MOD 0xF1
428
429 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
430 {
431 u8 scratch;
432 int ret;
433
434 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
435 if (ret)
436 return ret;
437
438 /*
439 * Turn PMOS on [bit 0], set over current detection to 2.4 V
440 * [bit 1:2] and enable over current debouncing [bit 6].
441 */
442 if (on)
443 scratch |= 0x47;
444 else
445 scratch &= ~0x47;
446
447 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
448 if (ret)
449 return ret;
450
451 return 0;
452 }
453
454 static int jmicron_probe(struct sdhci_pci_chip *chip)
455 {
456 int ret;
457 u16 mmcdev = 0;
458
459 if (chip->pdev->revision == 0) {
460 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
461 SDHCI_QUIRK_32BIT_DMA_SIZE |
462 SDHCI_QUIRK_32BIT_ADMA_SIZE |
463 SDHCI_QUIRK_RESET_AFTER_REQUEST |
464 SDHCI_QUIRK_BROKEN_SMALL_PIO;
465 }
466
467 /*
468 * JMicron chips can have two interfaces to the same hardware
469 * in order to work around limitations in Microsoft's driver.
470 * We need to make sure we only bind to one of them.
471 *
472 * This code assumes two things:
473 *
474 * 1. The PCI code adds subfunctions in order.
475 *
476 * 2. The MMC interface has a lower subfunction number
477 * than the SD interface.
478 */
479 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
480 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
481 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
482 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
483
484 if (mmcdev) {
485 struct pci_dev *sd_dev;
486
487 sd_dev = NULL;
488 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
489 mmcdev, sd_dev)) != NULL) {
490 if ((PCI_SLOT(chip->pdev->devfn) ==
491 PCI_SLOT(sd_dev->devfn)) &&
492 (chip->pdev->bus == sd_dev->bus))
493 break;
494 }
495
496 if (sd_dev) {
497 pci_dev_put(sd_dev);
498 dev_info(&chip->pdev->dev, "Refusing to bind to "
499 "secondary interface.\n");
500 return -ENODEV;
501 }
502 }
503
504 /*
505 * JMicron chips need a bit of a nudge to enable the power
506 * output pins.
507 */
508 ret = jmicron_pmos(chip, 1);
509 if (ret) {
510 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
511 return ret;
512 }
513
514 /* quirk for unsable RO-detection on JM388 chips */
515 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
516 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
517 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
518
519 return 0;
520 }
521
522 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
523 {
524 u8 scratch;
525
526 scratch = readb(host->ioaddr + 0xC0);
527
528 if (on)
529 scratch |= 0x01;
530 else
531 scratch &= ~0x01;
532
533 writeb(scratch, host->ioaddr + 0xC0);
534 }
535
536 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
537 {
538 if (slot->chip->pdev->revision == 0) {
539 u16 version;
540
541 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
542 version = (version & SDHCI_VENDOR_VER_MASK) >>
543 SDHCI_VENDOR_VER_SHIFT;
544
545 /*
546 * Older versions of the chip have lots of nasty glitches
547 * in the ADMA engine. It's best just to avoid it
548 * completely.
549 */
550 if (version < 0xAC)
551 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
552 }
553
554 /* JM388 MMC doesn't support 1.8V while SD supports it */
555 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
556 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
557 MMC_VDD_29_30 | MMC_VDD_30_31 |
558 MMC_VDD_165_195; /* allow 1.8V */
559 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
560 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
561 }
562
563 /*
564 * The secondary interface requires a bit set to get the
565 * interrupts.
566 */
567 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
568 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
569 jmicron_enable_mmc(slot->host, 1);
570
571 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
572
573 return 0;
574 }
575
576 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
577 {
578 if (dead)
579 return;
580
581 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
582 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
583 jmicron_enable_mmc(slot->host, 0);
584 }
585
586 static int jmicron_suspend(struct sdhci_pci_chip *chip)
587 {
588 int i;
589
590 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
591 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
592 for (i = 0; i < chip->num_slots; i++)
593 jmicron_enable_mmc(chip->slots[i]->host, 0);
594 }
595
596 return 0;
597 }
598
599 static int jmicron_resume(struct sdhci_pci_chip *chip)
600 {
601 int ret, i;
602
603 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
604 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
605 for (i = 0; i < chip->num_slots; i++)
606 jmicron_enable_mmc(chip->slots[i]->host, 1);
607 }
608
609 ret = jmicron_pmos(chip, 1);
610 if (ret) {
611 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
612 return ret;
613 }
614
615 return 0;
616 }
617
618 static const struct sdhci_pci_fixes sdhci_o2 = {
619 .probe = sdhci_pci_o2_probe,
620 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
621 .probe_slot = sdhci_pci_o2_probe_slot,
622 .resume = sdhci_pci_o2_resume,
623 };
624
625 static const struct sdhci_pci_fixes sdhci_jmicron = {
626 .probe = jmicron_probe,
627
628 .probe_slot = jmicron_probe_slot,
629 .remove_slot = jmicron_remove_slot,
630
631 .suspend = jmicron_suspend,
632 .resume = jmicron_resume,
633 };
634
635 /* SysKonnect CardBus2SDIO extra registers */
636 #define SYSKT_CTRL 0x200
637 #define SYSKT_RDFIFO_STAT 0x204
638 #define SYSKT_WRFIFO_STAT 0x208
639 #define SYSKT_POWER_DATA 0x20c
640 #define SYSKT_POWER_330 0xef
641 #define SYSKT_POWER_300 0xf8
642 #define SYSKT_POWER_184 0xcc
643 #define SYSKT_POWER_CMD 0x20d
644 #define SYSKT_POWER_START (1 << 7)
645 #define SYSKT_POWER_STATUS 0x20e
646 #define SYSKT_POWER_STATUS_OK (1 << 0)
647 #define SYSKT_BOARD_REV 0x210
648 #define SYSKT_CHIP_REV 0x211
649 #define SYSKT_CONF_DATA 0x212
650 #define SYSKT_CONF_DATA_1V8 (1 << 2)
651 #define SYSKT_CONF_DATA_2V5 (1 << 1)
652 #define SYSKT_CONF_DATA_3V3 (1 << 0)
653
654 static int syskt_probe(struct sdhci_pci_chip *chip)
655 {
656 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
657 chip->pdev->class &= ~0x0000FF;
658 chip->pdev->class |= PCI_SDHCI_IFDMA;
659 }
660 return 0;
661 }
662
663 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
664 {
665 int tm, ps;
666
667 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
668 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
669 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
670 "board rev %d.%d, chip rev %d.%d\n",
671 board_rev >> 4, board_rev & 0xf,
672 chip_rev >> 4, chip_rev & 0xf);
673 if (chip_rev >= 0x20)
674 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
675
676 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
677 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
678 udelay(50);
679 tm = 10; /* Wait max 1 ms */
680 do {
681 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
682 if (ps & SYSKT_POWER_STATUS_OK)
683 break;
684 udelay(100);
685 } while (--tm);
686 if (!tm) {
687 dev_err(&slot->chip->pdev->dev,
688 "power regulator never stabilized");
689 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
690 return -ENODEV;
691 }
692
693 return 0;
694 }
695
696 static const struct sdhci_pci_fixes sdhci_syskt = {
697 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
698 .probe = syskt_probe,
699 .probe_slot = syskt_probe_slot,
700 };
701
702 static int via_probe(struct sdhci_pci_chip *chip)
703 {
704 if (chip->pdev->revision == 0x10)
705 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
706
707 return 0;
708 }
709
710 static const struct sdhci_pci_fixes sdhci_via = {
711 .probe = via_probe,
712 };
713
714 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
715 {
716 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
717 return 0;
718 }
719
720 static const struct sdhci_pci_fixes sdhci_rtsx = {
721 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
722 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
723 SDHCI_QUIRK2_BROKEN_DDR50,
724 .probe_slot = rtsx_probe_slot,
725 };
726
727 static int amd_probe(struct sdhci_pci_chip *chip)
728 {
729 struct pci_dev *smbus_dev;
730
731 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
732 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
733
734 if (smbus_dev && (smbus_dev->revision < 0x51)) {
735 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
736 chip->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200;
737 }
738
739 return 0;
740 }
741
742 static const struct sdhci_pci_fixes sdhci_amd = {
743 .probe = amd_probe,
744 };
745
746 static const struct pci_device_id pci_ids[] = {
747 {
748 .vendor = PCI_VENDOR_ID_RICOH,
749 .device = PCI_DEVICE_ID_RICOH_R5C822,
750 .subvendor = PCI_ANY_ID,
751 .subdevice = PCI_ANY_ID,
752 .driver_data = (kernel_ulong_t)&sdhci_ricoh,
753 },
754
755 {
756 .vendor = PCI_VENDOR_ID_RICOH,
757 .device = 0x843,
758 .subvendor = PCI_ANY_ID,
759 .subdevice = PCI_ANY_ID,
760 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
761 },
762
763 {
764 .vendor = PCI_VENDOR_ID_RICOH,
765 .device = 0xe822,
766 .subvendor = PCI_ANY_ID,
767 .subdevice = PCI_ANY_ID,
768 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
769 },
770
771 {
772 .vendor = PCI_VENDOR_ID_RICOH,
773 .device = 0xe823,
774 .subvendor = PCI_ANY_ID,
775 .subdevice = PCI_ANY_ID,
776 .driver_data = (kernel_ulong_t)&sdhci_ricoh_mmc,
777 },
778
779 {
780 .vendor = PCI_VENDOR_ID_ENE,
781 .device = PCI_DEVICE_ID_ENE_CB712_SD,
782 .subvendor = PCI_ANY_ID,
783 .subdevice = PCI_ANY_ID,
784 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
785 },
786
787 {
788 .vendor = PCI_VENDOR_ID_ENE,
789 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
790 .subvendor = PCI_ANY_ID,
791 .subdevice = PCI_ANY_ID,
792 .driver_data = (kernel_ulong_t)&sdhci_ene_712,
793 },
794
795 {
796 .vendor = PCI_VENDOR_ID_ENE,
797 .device = PCI_DEVICE_ID_ENE_CB714_SD,
798 .subvendor = PCI_ANY_ID,
799 .subdevice = PCI_ANY_ID,
800 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
801 },
802
803 {
804 .vendor = PCI_VENDOR_ID_ENE,
805 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
806 .subvendor = PCI_ANY_ID,
807 .subdevice = PCI_ANY_ID,
808 .driver_data = (kernel_ulong_t)&sdhci_ene_714,
809 },
810
811 {
812 .vendor = PCI_VENDOR_ID_MARVELL,
813 .device = PCI_DEVICE_ID_MARVELL_88ALP01_SD,
814 .subvendor = PCI_ANY_ID,
815 .subdevice = PCI_ANY_ID,
816 .driver_data = (kernel_ulong_t)&sdhci_cafe,
817 },
818
819 {
820 .vendor = PCI_VENDOR_ID_JMICRON,
821 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
822 .subvendor = PCI_ANY_ID,
823 .subdevice = PCI_ANY_ID,
824 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
825 },
826
827 {
828 .vendor = PCI_VENDOR_ID_JMICRON,
829 .device = PCI_DEVICE_ID_JMICRON_JMB38X_MMC,
830 .subvendor = PCI_ANY_ID,
831 .subdevice = PCI_ANY_ID,
832 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
833 },
834
835 {
836 .vendor = PCI_VENDOR_ID_JMICRON,
837 .device = PCI_DEVICE_ID_JMICRON_JMB388_SD,
838 .subvendor = PCI_ANY_ID,
839 .subdevice = PCI_ANY_ID,
840 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
841 },
842
843 {
844 .vendor = PCI_VENDOR_ID_JMICRON,
845 .device = PCI_DEVICE_ID_JMICRON_JMB388_ESD,
846 .subvendor = PCI_ANY_ID,
847 .subdevice = PCI_ANY_ID,
848 .driver_data = (kernel_ulong_t)&sdhci_jmicron,
849 },
850
851 {
852 .vendor = PCI_VENDOR_ID_SYSKONNECT,
853 .device = 0x8000,
854 .subvendor = PCI_ANY_ID,
855 .subdevice = PCI_ANY_ID,
856 .driver_data = (kernel_ulong_t)&sdhci_syskt,
857 },
858
859 {
860 .vendor = PCI_VENDOR_ID_VIA,
861 .device = 0x95d0,
862 .subvendor = PCI_ANY_ID,
863 .subdevice = PCI_ANY_ID,
864 .driver_data = (kernel_ulong_t)&sdhci_via,
865 },
866
867 {
868 .vendor = PCI_VENDOR_ID_REALTEK,
869 .device = 0x5250,
870 .subvendor = PCI_ANY_ID,
871 .subdevice = PCI_ANY_ID,
872 .driver_data = (kernel_ulong_t)&sdhci_rtsx,
873 },
874
875 {
876 .vendor = PCI_VENDOR_ID_INTEL,
877 .device = PCI_DEVICE_ID_INTEL_QRK_SD,
878 .subvendor = PCI_ANY_ID,
879 .subdevice = PCI_ANY_ID,
880 .driver_data = (kernel_ulong_t)&sdhci_intel_qrk,
881 },
882
883 {
884 .vendor = PCI_VENDOR_ID_INTEL,
885 .device = PCI_DEVICE_ID_INTEL_MRST_SD0,
886 .subvendor = PCI_ANY_ID,
887 .subdevice = PCI_ANY_ID,
888 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc0,
889 },
890
891 {
892 .vendor = PCI_VENDOR_ID_INTEL,
893 .device = PCI_DEVICE_ID_INTEL_MRST_SD1,
894 .subvendor = PCI_ANY_ID,
895 .subdevice = PCI_ANY_ID,
896 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
897 },
898
899 {
900 .vendor = PCI_VENDOR_ID_INTEL,
901 .device = PCI_DEVICE_ID_INTEL_MRST_SD2,
902 .subvendor = PCI_ANY_ID,
903 .subdevice = PCI_ANY_ID,
904 .driver_data = (kernel_ulong_t)&sdhci_intel_mrst_hc1_hc2,
905 },
906
907 {
908 .vendor = PCI_VENDOR_ID_INTEL,
909 .device = PCI_DEVICE_ID_INTEL_MFD_SD,
910 .subvendor = PCI_ANY_ID,
911 .subdevice = PCI_ANY_ID,
912 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
913 },
914
915 {
916 .vendor = PCI_VENDOR_ID_INTEL,
917 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO1,
918 .subvendor = PCI_ANY_ID,
919 .subdevice = PCI_ANY_ID,
920 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
921 },
922
923 {
924 .vendor = PCI_VENDOR_ID_INTEL,
925 .device = PCI_DEVICE_ID_INTEL_MFD_SDIO2,
926 .subvendor = PCI_ANY_ID,
927 .subdevice = PCI_ANY_ID,
928 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
929 },
930
931 {
932 .vendor = PCI_VENDOR_ID_INTEL,
933 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC0,
934 .subvendor = PCI_ANY_ID,
935 .subdevice = PCI_ANY_ID,
936 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
937 },
938
939 {
940 .vendor = PCI_VENDOR_ID_INTEL,
941 .device = PCI_DEVICE_ID_INTEL_MFD_EMMC1,
942 .subvendor = PCI_ANY_ID,
943 .subdevice = PCI_ANY_ID,
944 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
945 },
946
947 {
948 .vendor = PCI_VENDOR_ID_INTEL,
949 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO0,
950 .subvendor = PCI_ANY_ID,
951 .subdevice = PCI_ANY_ID,
952 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
953 },
954
955 {
956 .vendor = PCI_VENDOR_ID_INTEL,
957 .device = PCI_DEVICE_ID_INTEL_PCH_SDIO1,
958 .subvendor = PCI_ANY_ID,
959 .subdevice = PCI_ANY_ID,
960 .driver_data = (kernel_ulong_t)&sdhci_intel_pch_sdio,
961 },
962
963 {
964 .vendor = PCI_VENDOR_ID_INTEL,
965 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC,
966 .subvendor = PCI_ANY_ID,
967 .subdevice = PCI_ANY_ID,
968 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
969 },
970
971 {
972 .vendor = PCI_VENDOR_ID_INTEL,
973 .device = PCI_DEVICE_ID_INTEL_BYT_SDIO,
974 .subvendor = PCI_ANY_ID,
975 .subdevice = PCI_ANY_ID,
976 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
977 },
978
979 {
980 .vendor = PCI_VENDOR_ID_INTEL,
981 .device = PCI_DEVICE_ID_INTEL_BYT_SD,
982 .subvendor = PCI_ANY_ID,
983 .subdevice = PCI_ANY_ID,
984 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
985 },
986
987 {
988 .vendor = PCI_VENDOR_ID_INTEL,
989 .device = PCI_DEVICE_ID_INTEL_BYT_EMMC2,
990 .subvendor = PCI_ANY_ID,
991 .subdevice = PCI_ANY_ID,
992 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
993 },
994
995 {
996 .vendor = PCI_VENDOR_ID_INTEL,
997 .device = PCI_DEVICE_ID_INTEL_BSW_EMMC,
998 .subvendor = PCI_ANY_ID,
999 .subdevice = PCI_ANY_ID,
1000 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1001 },
1002
1003 {
1004 .vendor = PCI_VENDOR_ID_INTEL,
1005 .device = PCI_DEVICE_ID_INTEL_BSW_SDIO,
1006 .subvendor = PCI_ANY_ID,
1007 .subdevice = PCI_ANY_ID,
1008 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1009 },
1010
1011 {
1012 .vendor = PCI_VENDOR_ID_INTEL,
1013 .device = PCI_DEVICE_ID_INTEL_BSW_SD,
1014 .subvendor = PCI_ANY_ID,
1015 .subdevice = PCI_ANY_ID,
1016 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1017 },
1018
1019 {
1020 .vendor = PCI_VENDOR_ID_INTEL,
1021 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO0,
1022 .subvendor = PCI_ANY_ID,
1023 .subdevice = PCI_ANY_ID,
1024 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sd,
1025 },
1026
1027 {
1028 .vendor = PCI_VENDOR_ID_INTEL,
1029 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO1,
1030 .subvendor = PCI_ANY_ID,
1031 .subdevice = PCI_ANY_ID,
1032 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1033 },
1034
1035 {
1036 .vendor = PCI_VENDOR_ID_INTEL,
1037 .device = PCI_DEVICE_ID_INTEL_CLV_SDIO2,
1038 .subvendor = PCI_ANY_ID,
1039 .subdevice = PCI_ANY_ID,
1040 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_sdio,
1041 },
1042
1043 {
1044 .vendor = PCI_VENDOR_ID_INTEL,
1045 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC0,
1046 .subvendor = PCI_ANY_ID,
1047 .subdevice = PCI_ANY_ID,
1048 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1049 },
1050
1051 {
1052 .vendor = PCI_VENDOR_ID_INTEL,
1053 .device = PCI_DEVICE_ID_INTEL_CLV_EMMC1,
1054 .subvendor = PCI_ANY_ID,
1055 .subdevice = PCI_ANY_ID,
1056 .driver_data = (kernel_ulong_t)&sdhci_intel_mfd_emmc,
1057 },
1058
1059 {
1060 .vendor = PCI_VENDOR_ID_INTEL,
1061 .device = PCI_DEVICE_ID_INTEL_MRFL_MMC,
1062 .subvendor = PCI_ANY_ID,
1063 .subdevice = PCI_ANY_ID,
1064 .driver_data = (kernel_ulong_t)&sdhci_intel_mrfl_mmc,
1065 },
1066
1067 {
1068 .vendor = PCI_VENDOR_ID_INTEL,
1069 .device = PCI_DEVICE_ID_INTEL_SPT_EMMC,
1070 .subvendor = PCI_ANY_ID,
1071 .subdevice = PCI_ANY_ID,
1072 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_emmc,
1073 },
1074
1075 {
1076 .vendor = PCI_VENDOR_ID_INTEL,
1077 .device = PCI_DEVICE_ID_INTEL_SPT_SDIO,
1078 .subvendor = PCI_ANY_ID,
1079 .subdevice = PCI_ANY_ID,
1080 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sdio,
1081 },
1082
1083 {
1084 .vendor = PCI_VENDOR_ID_INTEL,
1085 .device = PCI_DEVICE_ID_INTEL_SPT_SD,
1086 .subvendor = PCI_ANY_ID,
1087 .subdevice = PCI_ANY_ID,
1088 .driver_data = (kernel_ulong_t)&sdhci_intel_byt_sd,
1089 },
1090
1091 {
1092 .vendor = PCI_VENDOR_ID_O2,
1093 .device = PCI_DEVICE_ID_O2_8120,
1094 .subvendor = PCI_ANY_ID,
1095 .subdevice = PCI_ANY_ID,
1096 .driver_data = (kernel_ulong_t)&sdhci_o2,
1097 },
1098
1099 {
1100 .vendor = PCI_VENDOR_ID_O2,
1101 .device = PCI_DEVICE_ID_O2_8220,
1102 .subvendor = PCI_ANY_ID,
1103 .subdevice = PCI_ANY_ID,
1104 .driver_data = (kernel_ulong_t)&sdhci_o2,
1105 },
1106
1107 {
1108 .vendor = PCI_VENDOR_ID_O2,
1109 .device = PCI_DEVICE_ID_O2_8221,
1110 .subvendor = PCI_ANY_ID,
1111 .subdevice = PCI_ANY_ID,
1112 .driver_data = (kernel_ulong_t)&sdhci_o2,
1113 },
1114
1115 {
1116 .vendor = PCI_VENDOR_ID_O2,
1117 .device = PCI_DEVICE_ID_O2_8320,
1118 .subvendor = PCI_ANY_ID,
1119 .subdevice = PCI_ANY_ID,
1120 .driver_data = (kernel_ulong_t)&sdhci_o2,
1121 },
1122
1123 {
1124 .vendor = PCI_VENDOR_ID_O2,
1125 .device = PCI_DEVICE_ID_O2_8321,
1126 .subvendor = PCI_ANY_ID,
1127 .subdevice = PCI_ANY_ID,
1128 .driver_data = (kernel_ulong_t)&sdhci_o2,
1129 },
1130
1131 {
1132 .vendor = PCI_VENDOR_ID_O2,
1133 .device = PCI_DEVICE_ID_O2_FUJIN2,
1134 .subvendor = PCI_ANY_ID,
1135 .subdevice = PCI_ANY_ID,
1136 .driver_data = (kernel_ulong_t)&sdhci_o2,
1137 },
1138
1139 {
1140 .vendor = PCI_VENDOR_ID_O2,
1141 .device = PCI_DEVICE_ID_O2_SDS0,
1142 .subvendor = PCI_ANY_ID,
1143 .subdevice = PCI_ANY_ID,
1144 .driver_data = (kernel_ulong_t)&sdhci_o2,
1145 },
1146
1147 {
1148 .vendor = PCI_VENDOR_ID_O2,
1149 .device = PCI_DEVICE_ID_O2_SDS1,
1150 .subvendor = PCI_ANY_ID,
1151 .subdevice = PCI_ANY_ID,
1152 .driver_data = (kernel_ulong_t)&sdhci_o2,
1153 },
1154
1155 {
1156 .vendor = PCI_VENDOR_ID_O2,
1157 .device = PCI_DEVICE_ID_O2_SEABIRD0,
1158 .subvendor = PCI_ANY_ID,
1159 .subdevice = PCI_ANY_ID,
1160 .driver_data = (kernel_ulong_t)&sdhci_o2,
1161 },
1162
1163 {
1164 .vendor = PCI_VENDOR_ID_O2,
1165 .device = PCI_DEVICE_ID_O2_SEABIRD1,
1166 .subvendor = PCI_ANY_ID,
1167 .subdevice = PCI_ANY_ID,
1168 .driver_data = (kernel_ulong_t)&sdhci_o2,
1169 },
1170 {
1171 .vendor = PCI_VENDOR_ID_AMD,
1172 .device = PCI_ANY_ID,
1173 .class = PCI_CLASS_SYSTEM_SDHCI << 8,
1174 .class_mask = 0xFFFF00,
1175 .subvendor = PCI_ANY_ID,
1176 .subdevice = PCI_ANY_ID,
1177 .driver_data = (kernel_ulong_t)&sdhci_amd,
1178 },
1179 { /* Generic SD host controller */
1180 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
1181 },
1182
1183 { /* end: all zeroes */ },
1184 };
1185
1186 MODULE_DEVICE_TABLE(pci, pci_ids);
1187
1188 /*****************************************************************************\
1189 * *
1190 * SDHCI core callbacks *
1191 * *
1192 \*****************************************************************************/
1193
1194 static int sdhci_pci_enable_dma(struct sdhci_host *host)
1195 {
1196 struct sdhci_pci_slot *slot;
1197 struct pci_dev *pdev;
1198 int ret = -1;
1199
1200 slot = sdhci_priv(host);
1201 pdev = slot->chip->pdev;
1202
1203 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1204 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1205 (host->flags & SDHCI_USE_SDMA)) {
1206 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1207 "doesn't fully claim to support it.\n");
1208 }
1209
1210 if (host->flags & SDHCI_USE_64_BIT_DMA) {
1211 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) {
1212 host->flags &= ~SDHCI_USE_64_BIT_DMA;
1213 } else {
1214 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1215 if (ret)
1216 dev_warn(&pdev->dev, "Failed to set 64-bit DMA mask\n");
1217 }
1218 }
1219 if (ret)
1220 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1221 if (ret)
1222 return ret;
1223
1224 pci_set_master(pdev);
1225
1226 return 0;
1227 }
1228
1229 static void sdhci_pci_set_bus_width(struct sdhci_host *host, int width)
1230 {
1231 u8 ctrl;
1232
1233 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1234
1235 switch (width) {
1236 case MMC_BUS_WIDTH_8:
1237 ctrl |= SDHCI_CTRL_8BITBUS;
1238 ctrl &= ~SDHCI_CTRL_4BITBUS;
1239 break;
1240 case MMC_BUS_WIDTH_4:
1241 ctrl |= SDHCI_CTRL_4BITBUS;
1242 ctrl &= ~SDHCI_CTRL_8BITBUS;
1243 break;
1244 default:
1245 ctrl &= ~(SDHCI_CTRL_8BITBUS | SDHCI_CTRL_4BITBUS);
1246 break;
1247 }
1248
1249 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1250 }
1251
1252 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1253 {
1254 struct sdhci_pci_slot *slot = sdhci_priv(host);
1255 int rst_n_gpio = slot->rst_n_gpio;
1256
1257 if (!gpio_is_valid(rst_n_gpio))
1258 return;
1259 gpio_set_value_cansleep(rst_n_gpio, 0);
1260 /* For eMMC, minimum is 1us but give it 10us for good measure */
1261 udelay(10);
1262 gpio_set_value_cansleep(rst_n_gpio, 1);
1263 /* For eMMC, minimum is 200us but give it 300us for good measure */
1264 usleep_range(300, 1000);
1265 }
1266
1267 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1268 {
1269 struct sdhci_pci_slot *slot = sdhci_priv(host);
1270
1271 if (slot->hw_reset)
1272 slot->hw_reset(host);
1273 }
1274
1275 static int sdhci_pci_select_drive_strength(struct sdhci_host *host,
1276 struct mmc_card *card,
1277 unsigned int max_dtr, int host_drv,
1278 int card_drv, int *drv_type)
1279 {
1280 struct sdhci_pci_slot *slot = sdhci_priv(host);
1281
1282 if (!slot->select_drive_strength)
1283 return 0;
1284
1285 return slot->select_drive_strength(host, card, max_dtr, host_drv,
1286 card_drv, drv_type);
1287 }
1288
1289 static const struct sdhci_ops sdhci_pci_ops = {
1290 .set_clock = sdhci_set_clock,
1291 .enable_dma = sdhci_pci_enable_dma,
1292 .set_bus_width = sdhci_pci_set_bus_width,
1293 .reset = sdhci_reset,
1294 .set_uhs_signaling = sdhci_set_uhs_signaling,
1295 .hw_reset = sdhci_pci_hw_reset,
1296 .select_drive_strength = sdhci_pci_select_drive_strength,
1297 };
1298
1299 /*****************************************************************************\
1300 * *
1301 * Suspend/resume *
1302 * *
1303 \*****************************************************************************/
1304
1305 #ifdef CONFIG_PM
1306
1307 static int sdhci_pci_suspend(struct device *dev)
1308 {
1309 struct pci_dev *pdev = to_pci_dev(dev);
1310 struct sdhci_pci_chip *chip;
1311 struct sdhci_pci_slot *slot;
1312 mmc_pm_flag_t slot_pm_flags;
1313 mmc_pm_flag_t pm_flags = 0;
1314 int i, ret;
1315
1316 chip = pci_get_drvdata(pdev);
1317 if (!chip)
1318 return 0;
1319
1320 for (i = 0; i < chip->num_slots; i++) {
1321 slot = chip->slots[i];
1322 if (!slot)
1323 continue;
1324
1325 ret = sdhci_suspend_host(slot->host);
1326
1327 if (ret)
1328 goto err_pci_suspend;
1329
1330 slot_pm_flags = slot->host->mmc->pm_flags;
1331 if (slot_pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1332 sdhci_enable_irq_wakeups(slot->host);
1333
1334 pm_flags |= slot_pm_flags;
1335 }
1336
1337 if (chip->fixes && chip->fixes->suspend) {
1338 ret = chip->fixes->suspend(chip);
1339 if (ret)
1340 goto err_pci_suspend;
1341 }
1342
1343 if (pm_flags & MMC_PM_KEEP_POWER) {
1344 if (pm_flags & MMC_PM_WAKE_SDIO_IRQ)
1345 device_init_wakeup(dev, true);
1346 else
1347 device_init_wakeup(dev, false);
1348 } else
1349 device_init_wakeup(dev, false);
1350
1351 return 0;
1352
1353 err_pci_suspend:
1354 while (--i >= 0)
1355 sdhci_resume_host(chip->slots[i]->host);
1356 return ret;
1357 }
1358
1359 static int sdhci_pci_resume(struct device *dev)
1360 {
1361 struct pci_dev *pdev = to_pci_dev(dev);
1362 struct sdhci_pci_chip *chip;
1363 struct sdhci_pci_slot *slot;
1364 int i, ret;
1365
1366 chip = pci_get_drvdata(pdev);
1367 if (!chip)
1368 return 0;
1369
1370 if (chip->fixes && chip->fixes->resume) {
1371 ret = chip->fixes->resume(chip);
1372 if (ret)
1373 return ret;
1374 }
1375
1376 for (i = 0; i < chip->num_slots; i++) {
1377 slot = chip->slots[i];
1378 if (!slot)
1379 continue;
1380
1381 ret = sdhci_resume_host(slot->host);
1382 if (ret)
1383 return ret;
1384 }
1385
1386 return 0;
1387 }
1388
1389 static int sdhci_pci_runtime_suspend(struct device *dev)
1390 {
1391 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1392 struct sdhci_pci_chip *chip;
1393 struct sdhci_pci_slot *slot;
1394 int i, ret;
1395
1396 chip = pci_get_drvdata(pdev);
1397 if (!chip)
1398 return 0;
1399
1400 for (i = 0; i < chip->num_slots; i++) {
1401 slot = chip->slots[i];
1402 if (!slot)
1403 continue;
1404
1405 ret = sdhci_runtime_suspend_host(slot->host);
1406
1407 if (ret)
1408 goto err_pci_runtime_suspend;
1409 }
1410
1411 if (chip->fixes && chip->fixes->suspend) {
1412 ret = chip->fixes->suspend(chip);
1413 if (ret)
1414 goto err_pci_runtime_suspend;
1415 }
1416
1417 return 0;
1418
1419 err_pci_runtime_suspend:
1420 while (--i >= 0)
1421 sdhci_runtime_resume_host(chip->slots[i]->host);
1422 return ret;
1423 }
1424
1425 static int sdhci_pci_runtime_resume(struct device *dev)
1426 {
1427 struct pci_dev *pdev = container_of(dev, struct pci_dev, dev);
1428 struct sdhci_pci_chip *chip;
1429 struct sdhci_pci_slot *slot;
1430 int i, ret;
1431
1432 chip = pci_get_drvdata(pdev);
1433 if (!chip)
1434 return 0;
1435
1436 if (chip->fixes && chip->fixes->resume) {
1437 ret = chip->fixes->resume(chip);
1438 if (ret)
1439 return ret;
1440 }
1441
1442 for (i = 0; i < chip->num_slots; i++) {
1443 slot = chip->slots[i];
1444 if (!slot)
1445 continue;
1446
1447 ret = sdhci_runtime_resume_host(slot->host);
1448 if (ret)
1449 return ret;
1450 }
1451
1452 return 0;
1453 }
1454
1455 #else /* CONFIG_PM */
1456
1457 #define sdhci_pci_suspend NULL
1458 #define sdhci_pci_resume NULL
1459
1460 #endif /* CONFIG_PM */
1461
1462 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1463 .suspend = sdhci_pci_suspend,
1464 .resume = sdhci_pci_resume,
1465 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1466 sdhci_pci_runtime_resume, NULL)
1467 };
1468
1469 /*****************************************************************************\
1470 * *
1471 * Device probing/removal *
1472 * *
1473 \*****************************************************************************/
1474
1475 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1476 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1477 int slotno)
1478 {
1479 struct sdhci_pci_slot *slot;
1480 struct sdhci_host *host;
1481 int ret, bar = first_bar + slotno;
1482
1483 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1484 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1485 return ERR_PTR(-ENODEV);
1486 }
1487
1488 if (pci_resource_len(pdev, bar) < 0x100) {
1489 dev_err(&pdev->dev, "Invalid iomem size. You may "
1490 "experience problems.\n");
1491 }
1492
1493 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1494 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1495 return ERR_PTR(-ENODEV);
1496 }
1497
1498 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1499 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1500 return ERR_PTR(-ENODEV);
1501 }
1502
1503 host = sdhci_alloc_host(&pdev->dev, sizeof(struct sdhci_pci_slot));
1504 if (IS_ERR(host)) {
1505 dev_err(&pdev->dev, "cannot allocate host\n");
1506 return ERR_CAST(host);
1507 }
1508
1509 slot = sdhci_priv(host);
1510
1511 slot->chip = chip;
1512 slot->host = host;
1513 slot->pci_bar = bar;
1514 slot->rst_n_gpio = -EINVAL;
1515 slot->cd_gpio = -EINVAL;
1516 slot->cd_idx = -1;
1517
1518 /* Retrieve platform data if there is any */
1519 if (*sdhci_pci_get_data)
1520 slot->data = sdhci_pci_get_data(pdev, slotno);
1521
1522 if (slot->data) {
1523 if (slot->data->setup) {
1524 ret = slot->data->setup(slot->data);
1525 if (ret) {
1526 dev_err(&pdev->dev, "platform setup failed\n");
1527 goto free;
1528 }
1529 }
1530 slot->rst_n_gpio = slot->data->rst_n_gpio;
1531 slot->cd_gpio = slot->data->cd_gpio;
1532 }
1533
1534 host->hw_name = "PCI";
1535 host->ops = &sdhci_pci_ops;
1536 host->quirks = chip->quirks;
1537 host->quirks2 = chip->quirks2;
1538
1539 host->irq = pdev->irq;
1540
1541 ret = pci_request_region(pdev, bar, mmc_hostname(host->mmc));
1542 if (ret) {
1543 dev_err(&pdev->dev, "cannot request region\n");
1544 goto cleanup;
1545 }
1546
1547 host->ioaddr = pci_ioremap_bar(pdev, bar);
1548 if (!host->ioaddr) {
1549 dev_err(&pdev->dev, "failed to remap registers\n");
1550 ret = -ENOMEM;
1551 goto release;
1552 }
1553
1554 if (chip->fixes && chip->fixes->probe_slot) {
1555 ret = chip->fixes->probe_slot(slot);
1556 if (ret)
1557 goto unmap;
1558 }
1559
1560 if (gpio_is_valid(slot->rst_n_gpio)) {
1561 if (!gpio_request(slot->rst_n_gpio, "eMMC_reset")) {
1562 gpio_direction_output(slot->rst_n_gpio, 1);
1563 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1564 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1565 } else {
1566 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1567 slot->rst_n_gpio = -EINVAL;
1568 }
1569 }
1570
1571 host->mmc->pm_caps = MMC_PM_KEEP_POWER | MMC_PM_WAKE_SDIO_IRQ;
1572 host->mmc->slotno = slotno;
1573 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1574
1575 if (slot->cd_idx >= 0 &&
1576 mmc_gpiod_request_cd(host->mmc, slot->cd_con_id, slot->cd_idx,
1577 slot->cd_override_level, 0, NULL)) {
1578 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1579 slot->cd_idx = -1;
1580 }
1581
1582 ret = sdhci_add_host(host);
1583 if (ret)
1584 goto remove;
1585
1586 sdhci_pci_add_own_cd(slot);
1587
1588 /*
1589 * Check if the chip needs a separate GPIO for card detect to wake up
1590 * from runtime suspend. If it is not there, don't allow runtime PM.
1591 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1592 */
1593 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1594 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1595 chip->allow_runtime_pm = false;
1596
1597 return slot;
1598
1599 remove:
1600 if (gpio_is_valid(slot->rst_n_gpio))
1601 gpio_free(slot->rst_n_gpio);
1602
1603 if (chip->fixes && chip->fixes->remove_slot)
1604 chip->fixes->remove_slot(slot, 0);
1605
1606 unmap:
1607 iounmap(host->ioaddr);
1608
1609 release:
1610 pci_release_region(pdev, bar);
1611
1612 cleanup:
1613 if (slot->data && slot->data->cleanup)
1614 slot->data->cleanup(slot->data);
1615
1616 free:
1617 sdhci_free_host(host);
1618
1619 return ERR_PTR(ret);
1620 }
1621
1622 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1623 {
1624 int dead;
1625 u32 scratch;
1626
1627 sdhci_pci_remove_own_cd(slot);
1628
1629 dead = 0;
1630 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1631 if (scratch == (u32)-1)
1632 dead = 1;
1633
1634 sdhci_remove_host(slot->host, dead);
1635
1636 if (gpio_is_valid(slot->rst_n_gpio))
1637 gpio_free(slot->rst_n_gpio);
1638
1639 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1640 slot->chip->fixes->remove_slot(slot, dead);
1641
1642 if (slot->data && slot->data->cleanup)
1643 slot->data->cleanup(slot->data);
1644
1645 pci_release_region(slot->chip->pdev, slot->pci_bar);
1646
1647 sdhci_free_host(slot->host);
1648 }
1649
1650 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1651 {
1652 pm_runtime_put_noidle(dev);
1653 pm_runtime_allow(dev);
1654 pm_runtime_set_autosuspend_delay(dev, 50);
1655 pm_runtime_use_autosuspend(dev);
1656 pm_suspend_ignore_children(dev, 1);
1657 }
1658
1659 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1660 {
1661 pm_runtime_forbid(dev);
1662 pm_runtime_get_noresume(dev);
1663 }
1664
1665 static int sdhci_pci_probe(struct pci_dev *pdev,
1666 const struct pci_device_id *ent)
1667 {
1668 struct sdhci_pci_chip *chip;
1669 struct sdhci_pci_slot *slot;
1670
1671 u8 slots, first_bar;
1672 int ret, i;
1673
1674 BUG_ON(pdev == NULL);
1675 BUG_ON(ent == NULL);
1676
1677 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1678 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1679
1680 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1681 if (ret)
1682 return ret;
1683
1684 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1685 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1686 if (slots == 0)
1687 return -ENODEV;
1688
1689 BUG_ON(slots > MAX_SLOTS);
1690
1691 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1692 if (ret)
1693 return ret;
1694
1695 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1696
1697 if (first_bar > 5) {
1698 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1699 return -ENODEV;
1700 }
1701
1702 ret = pci_enable_device(pdev);
1703 if (ret)
1704 return ret;
1705
1706 chip = kzalloc(sizeof(struct sdhci_pci_chip), GFP_KERNEL);
1707 if (!chip) {
1708 ret = -ENOMEM;
1709 goto err;
1710 }
1711
1712 chip->pdev = pdev;
1713 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1714 if (chip->fixes) {
1715 chip->quirks = chip->fixes->quirks;
1716 chip->quirks2 = chip->fixes->quirks2;
1717 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1718 }
1719 chip->num_slots = slots;
1720
1721 pci_set_drvdata(pdev, chip);
1722
1723 if (chip->fixes && chip->fixes->probe) {
1724 ret = chip->fixes->probe(chip);
1725 if (ret)
1726 goto free;
1727 }
1728
1729 slots = chip->num_slots; /* Quirk may have changed this */
1730
1731 for (i = 0; i < slots; i++) {
1732 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1733 if (IS_ERR(slot)) {
1734 for (i--; i >= 0; i--)
1735 sdhci_pci_remove_slot(chip->slots[i]);
1736 ret = PTR_ERR(slot);
1737 goto free;
1738 }
1739
1740 chip->slots[i] = slot;
1741 }
1742
1743 if (chip->allow_runtime_pm)
1744 sdhci_pci_runtime_pm_allow(&pdev->dev);
1745
1746 return 0;
1747
1748 free:
1749 pci_set_drvdata(pdev, NULL);
1750 kfree(chip);
1751
1752 err:
1753 pci_disable_device(pdev);
1754 return ret;
1755 }
1756
1757 static void sdhci_pci_remove(struct pci_dev *pdev)
1758 {
1759 int i;
1760 struct sdhci_pci_chip *chip;
1761
1762 chip = pci_get_drvdata(pdev);
1763
1764 if (chip) {
1765 if (chip->allow_runtime_pm)
1766 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1767
1768 for (i = 0; i < chip->num_slots; i++)
1769 sdhci_pci_remove_slot(chip->slots[i]);
1770
1771 pci_set_drvdata(pdev, NULL);
1772 kfree(chip);
1773 }
1774
1775 pci_disable_device(pdev);
1776 }
1777
1778 static struct pci_driver sdhci_driver = {
1779 .name = "sdhci-pci",
1780 .id_table = pci_ids,
1781 .probe = sdhci_pci_probe,
1782 .remove = sdhci_pci_remove,
1783 .driver = {
1784 .pm = &sdhci_pci_pm_ops
1785 },
1786 };
1787
1788 module_pci_driver(sdhci_driver);
1789
1790 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1791 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1792 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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