1 /* linux/drivers/mmc/host/sdhci-s3c.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * SDHCI (HSMMC) support for Samsung SoC
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/delay.h>
16 #include <linux/dma-mapping.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
19 #include <linux/clk.h>
21 #include <linux/gpio.h>
22 #include <linux/module.h>
24 #include <linux/of_gpio.h>
26 #include <linux/pm_runtime.h>
28 #include <linux/mmc/host.h>
30 #include <plat/sdhci.h>
31 #include <plat/regs-sdhci.h>
35 #define MAX_BUS_CLK (4)
37 /* Number of gpio's used is max data bus width + command and clock lines */
38 #define NUM_GPIOS(x) (x + 2)
41 * struct sdhci_s3c - S3C SDHCI instance
42 * @host: The SDHCI host created
43 * @pdev: The platform device we where created from.
44 * @ioarea: The resource created when we claimed the IO area.
45 * @pdata: The platform data for this controller.
46 * @cur_clk: The index of the current bus clock.
47 * @gpios: List of gpio numbers parsed from device tree.
48 * @clk_io: The clock for the internal bus interface.
49 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
52 struct sdhci_host
*host
;
53 struct platform_device
*pdev
;
54 struct resource
*ioarea
;
55 struct s3c_sdhci_platdata
*pdata
;
62 struct clk
*clk_bus
[MAX_BUS_CLK
];
66 * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data
67 * @sdhci_quirks: sdhci host specific quirks.
69 * Specifies platform specific configuration of sdhci controller.
70 * Note: A structure for driver specific platform data is used for future
71 * expansion of its usage.
73 struct sdhci_s3c_drv_data
{
74 unsigned int sdhci_quirks
;
77 static inline struct sdhci_s3c
*to_s3c(struct sdhci_host
*host
)
79 return sdhci_priv(host
);
83 * get_curclk - convert ctrl2 register to clock source number
84 * @ctrl2: Control2 register value.
86 static u32
get_curclk(u32 ctrl2
)
88 ctrl2
&= S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
89 ctrl2
>>= S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
94 static void sdhci_s3c_check_sclk(struct sdhci_host
*host
)
96 struct sdhci_s3c
*ourhost
= to_s3c(host
);
97 u32 tmp
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
99 if (get_curclk(tmp
) != ourhost
->cur_clk
) {
100 dev_dbg(&ourhost
->pdev
->dev
, "restored ctrl2 clock setting\n");
102 tmp
&= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
103 tmp
|= ourhost
->cur_clk
<< S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
104 writel(tmp
, host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
109 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
110 * @host: The SDHCI host instance.
112 * Callback to return the maximum clock rate acheivable by the controller.
114 static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host
*host
)
116 struct sdhci_s3c
*ourhost
= to_s3c(host
);
118 unsigned int rate
, max
;
121 /* note, a reset will reset the clock source */
123 sdhci_s3c_check_sclk(host
);
125 for (max
= 0, clk
= 0; clk
< MAX_BUS_CLK
; clk
++) {
126 busclk
= ourhost
->clk_bus
[clk
];
130 rate
= clk_get_rate(busclk
);
139 * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
140 * @ourhost: Our SDHCI instance.
141 * @src: The source clock index.
142 * @wanted: The clock frequency wanted.
144 static unsigned int sdhci_s3c_consider_clock(struct sdhci_s3c
*ourhost
,
149 struct clk
*clksrc
= ourhost
->clk_bus
[src
];
156 * If controller uses a non-standard clock division, find the best clock
157 * speed possible with selected clock source and skip the division.
159 if (ourhost
->host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
) {
160 rate
= clk_round_rate(clksrc
, wanted
);
161 return wanted
- rate
;
164 rate
= clk_get_rate(clksrc
);
166 for (div
= 1; div
< 256; div
*= 2) {
167 if ((rate
/ div
) <= wanted
)
171 dev_dbg(&ourhost
->pdev
->dev
, "clk %d: rate %ld, want %d, got %ld\n",
172 src
, rate
, wanted
, rate
/ div
);
174 return wanted
- (rate
/ div
);
178 * sdhci_s3c_set_clock - callback on clock change
179 * @host: The SDHCI host being changed
180 * @clock: The clock rate being requested.
182 * When the card's clock is going to be changed, look at the new frequency
183 * and find the best clock source to go with it.
185 static void sdhci_s3c_set_clock(struct sdhci_host
*host
, unsigned int clock
)
187 struct sdhci_s3c
*ourhost
= to_s3c(host
);
188 unsigned int best
= UINT_MAX
;
194 /* don't bother if the clock is going off. */
198 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
199 delta
= sdhci_s3c_consider_clock(ourhost
, src
, clock
);
206 dev_dbg(&ourhost
->pdev
->dev
,
207 "selected source %d, clock %d, delta %d\n",
208 best_src
, clock
, best
);
210 /* select the new clock source */
211 if (ourhost
->cur_clk
!= best_src
) {
212 struct clk
*clk
= ourhost
->clk_bus
[best_src
];
214 clk_prepare_enable(clk
);
215 clk_disable_unprepare(ourhost
->clk_bus
[ourhost
->cur_clk
]);
217 /* turn clock off to card before changing clock source */
218 writew(0, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
220 ourhost
->cur_clk
= best_src
;
221 host
->max_clk
= clk_get_rate(clk
);
223 ctrl
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
224 ctrl
&= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK
;
225 ctrl
|= best_src
<< S3C_SDHCI_CTRL2_SELBASECLK_SHIFT
;
226 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
229 /* reprogram default hardware configuration */
230 writel(S3C64XX_SDHCI_CONTROL4_DRIVE_9mA
,
231 host
->ioaddr
+ S3C64XX_SDHCI_CONTROL4
);
233 ctrl
= readl(host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
234 ctrl
|= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR
|
235 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK
|
236 S3C_SDHCI_CTRL2_ENFBCLKRX
|
237 S3C_SDHCI_CTRL2_DFCNT_NONE
|
238 S3C_SDHCI_CTRL2_ENCLKOUTHOLD
);
239 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL2
);
241 /* reconfigure the controller for new clock rate */
242 ctrl
= (S3C_SDHCI_CTRL3_FCSEL1
| S3C_SDHCI_CTRL3_FCSEL0
);
243 if (clock
< 25 * 1000000)
244 ctrl
|= (S3C_SDHCI_CTRL3_FCSEL3
| S3C_SDHCI_CTRL3_FCSEL2
);
245 writel(ctrl
, host
->ioaddr
+ S3C_SDHCI_CONTROL3
);
249 * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
250 * @host: The SDHCI host being queried
252 * To init mmc host properly a minimal clock value is needed. For high system
253 * bus clock's values the standard formula gives values out of allowed range.
254 * The clock still can be set to lower values, if clock source other then
255 * system bus is selected.
257 static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host
*host
)
259 struct sdhci_s3c
*ourhost
= to_s3c(host
);
260 unsigned int delta
, min
= UINT_MAX
;
263 for (src
= 0; src
< MAX_BUS_CLK
; src
++) {
264 delta
= sdhci_s3c_consider_clock(ourhost
, src
, 0);
265 if (delta
== UINT_MAX
)
267 /* delta is a negative value in this case */
274 /* sdhci_cmu_get_max_clk - callback to get maximum clock frequency.*/
275 static unsigned int sdhci_cmu_get_max_clock(struct sdhci_host
*host
)
277 struct sdhci_s3c
*ourhost
= to_s3c(host
);
279 return clk_round_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], UINT_MAX
);
282 /* sdhci_cmu_get_min_clock - callback to get minimal supported clock value. */
283 static unsigned int sdhci_cmu_get_min_clock(struct sdhci_host
*host
)
285 struct sdhci_s3c
*ourhost
= to_s3c(host
);
288 * initial clock can be in the frequency range of
289 * 100KHz-400KHz, so we set it as max value.
291 return clk_round_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], 400000);
294 /* sdhci_cmu_set_clock - callback on clock change.*/
295 static void sdhci_cmu_set_clock(struct sdhci_host
*host
, unsigned int clock
)
297 struct sdhci_s3c
*ourhost
= to_s3c(host
);
298 struct device
*dev
= &ourhost
->pdev
->dev
;
299 unsigned long timeout
;
302 /* don't bother if the clock is going off */
306 sdhci_s3c_set_clock(host
, clock
);
308 clk_set_rate(ourhost
->clk_bus
[ourhost
->cur_clk
], clock
);
312 clk
= SDHCI_CLOCK_INT_EN
;
313 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
317 while (!((clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
))
318 & SDHCI_CLOCK_INT_STABLE
)) {
320 dev_err(dev
, "%s: Internal clock never stabilised.\n",
321 mmc_hostname(host
->mmc
));
328 clk
|= SDHCI_CLOCK_CARD_EN
;
329 sdhci_writew(host
, clk
, SDHCI_CLOCK_CONTROL
);
333 * sdhci_s3c_platform_8bit_width - support 8bit buswidth
334 * @host: The SDHCI host being queried
335 * @width: MMC_BUS_WIDTH_ macro for the bus width being requested
337 * We have 8-bit width support but is not a v3 controller.
338 * So we add platform_8bit_width() and support 8bit width.
340 static int sdhci_s3c_platform_8bit_width(struct sdhci_host
*host
, int width
)
344 ctrl
= sdhci_readb(host
, SDHCI_HOST_CONTROL
);
347 case MMC_BUS_WIDTH_8
:
348 ctrl
|= SDHCI_CTRL_8BITBUS
;
349 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
351 case MMC_BUS_WIDTH_4
:
352 ctrl
|= SDHCI_CTRL_4BITBUS
;
353 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
356 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
357 ctrl
&= ~SDHCI_CTRL_8BITBUS
;
361 sdhci_writeb(host
, ctrl
, SDHCI_HOST_CONTROL
);
366 static struct sdhci_ops sdhci_s3c_ops
= {
367 .get_max_clock
= sdhci_s3c_get_max_clk
,
368 .set_clock
= sdhci_s3c_set_clock
,
369 .get_min_clock
= sdhci_s3c_get_min_clock
,
370 .platform_8bit_width
= sdhci_s3c_platform_8bit_width
,
373 static void sdhci_s3c_notify_change(struct platform_device
*dev
, int state
)
375 struct sdhci_host
*host
= platform_get_drvdata(dev
);
376 struct sdhci_s3c
*sc
= sdhci_priv(host
);
380 spin_lock_irqsave(&host
->lock
, flags
);
382 dev_dbg(&dev
->dev
, "card inserted.\n");
383 #ifdef CONFIG_PM_RUNTIME
384 clk_prepare_enable(sc
->clk_io
);
386 host
->flags
&= ~SDHCI_DEVICE_DEAD
;
387 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
389 dev_dbg(&dev
->dev
, "card removed.\n");
390 host
->flags
|= SDHCI_DEVICE_DEAD
;
391 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
392 #ifdef CONFIG_PM_RUNTIME
393 clk_disable_unprepare(sc
->clk_io
);
396 tasklet_schedule(&host
->card_tasklet
);
397 spin_unlock_irqrestore(&host
->lock
, flags
);
401 static irqreturn_t
sdhci_s3c_gpio_card_detect_thread(int irq
, void *dev_id
)
403 struct sdhci_s3c
*sc
= dev_id
;
404 int status
= gpio_get_value(sc
->ext_cd_gpio
);
405 if (sc
->pdata
->ext_cd_gpio_invert
)
407 sdhci_s3c_notify_change(sc
->pdev
, status
);
411 static void sdhci_s3c_setup_card_detect_gpio(struct sdhci_s3c
*sc
)
413 struct s3c_sdhci_platdata
*pdata
= sc
->pdata
;
414 struct device
*dev
= &sc
->pdev
->dev
;
416 if (gpio_request(pdata
->ext_cd_gpio
, "SDHCI EXT CD") == 0) {
417 sc
->ext_cd_gpio
= pdata
->ext_cd_gpio
;
418 sc
->ext_cd_irq
= gpio_to_irq(pdata
->ext_cd_gpio
);
419 if (sc
->ext_cd_irq
&&
420 request_threaded_irq(sc
->ext_cd_irq
, NULL
,
421 sdhci_s3c_gpio_card_detect_thread
,
422 IRQF_TRIGGER_RISING
|
423 IRQF_TRIGGER_FALLING
|
425 dev_name(dev
), sc
) == 0) {
426 int status
= gpio_get_value(sc
->ext_cd_gpio
);
427 if (pdata
->ext_cd_gpio_invert
)
429 sdhci_s3c_notify_change(sc
->pdev
, status
);
431 dev_warn(dev
, "cannot request irq for card detect\n");
435 dev_err(dev
, "cannot request gpio for card detect\n");
440 static int __devinit
sdhci_s3c_parse_dt(struct device
*dev
,
441 struct sdhci_host
*host
, struct s3c_sdhci_platdata
*pdata
)
443 struct device_node
*node
= dev
->of_node
;
444 struct sdhci_s3c
*ourhost
= to_s3c(host
);
448 /* if the bus-width property is not specified, assume width as 1 */
449 if (of_property_read_u32(node
, "bus-width", &max_width
))
451 pdata
->max_width
= max_width
;
453 ourhost
->gpios
= devm_kzalloc(dev
, NUM_GPIOS(pdata
->max_width
) *
454 sizeof(int), GFP_KERNEL
);
458 /* get the card detection method */
459 if (of_get_property(node
, "broken-cd", 0)) {
460 pdata
->cd_type
= S3C_SDHCI_CD_NONE
;
464 if (of_get_property(node
, "non-removable", 0)) {
465 pdata
->cd_type
= S3C_SDHCI_CD_PERMANENT
;
469 gpio
= of_get_named_gpio(node
, "cd-gpios", 0);
470 if (gpio_is_valid(gpio
)) {
471 pdata
->cd_type
= S3C_SDHCI_CD_GPIO
;
473 } else if (gpio
!= -ENOENT
) {
474 dev_err(dev
, "invalid card detect gpio specified\n");
478 gpio
= of_get_named_gpio(node
, "samsung,cd-pinmux-gpio", 0);
479 if (gpio_is_valid(gpio
)) {
480 pdata
->cd_type
= S3C_SDHCI_CD_INTERNAL
;
482 } else if (gpio
!= -ENOENT
) {
483 dev_err(dev
, "invalid card detect gpio specified\n");
487 dev_info(dev
, "assuming no card detect line available\n");
488 pdata
->cd_type
= S3C_SDHCI_CD_NONE
;
491 if (pdata
->cd_type
== S3C_SDHCI_CD_GPIO
) {
492 pdata
->ext_cd_gpio
= gpio
;
493 ourhost
->ext_cd_gpio
= -1;
494 if (of_get_property(node
, "cd-inverted", NULL
))
495 pdata
->ext_cd_gpio_invert
= 1;
496 } else if (pdata
->cd_type
== S3C_SDHCI_CD_INTERNAL
) {
497 ret
= gpio_request(gpio
, "sdhci-cd");
499 dev_err(dev
, "card detect gpio request failed\n");
502 ourhost
->ext_cd_gpio
= gpio
;
506 /* get the gpios for command, clock and data lines */
507 for (cnt
= 0; cnt
< NUM_GPIOS(pdata
->max_width
); cnt
++) {
508 gpio
= of_get_gpio(node
, cnt
);
509 if (!gpio_is_valid(gpio
)) {
510 dev_err(dev
, "invalid gpio[%d]\n", cnt
);
511 goto err_free_dt_cd_gpio
;
513 ourhost
->gpios
[cnt
] = gpio
;
516 for (cnt
= 0; cnt
< NUM_GPIOS(pdata
->max_width
); cnt
++) {
517 ret
= gpio_request(ourhost
->gpios
[cnt
], "sdhci-gpio");
519 dev_err(dev
, "gpio[%d] request failed\n", cnt
);
520 goto err_free_dt_gpios
;
528 gpio_free(ourhost
->gpios
[cnt
]);
530 if (pdata
->cd_type
== S3C_SDHCI_CD_INTERNAL
)
531 gpio_free(ourhost
->ext_cd_gpio
);
535 static int __devinit
sdhci_s3c_parse_dt(struct device
*dev
,
536 struct sdhci_host
*host
, struct s3c_sdhci_platdata
*pdata
)
542 static const struct of_device_id sdhci_s3c_dt_match
[];
544 static inline struct sdhci_s3c_drv_data
*sdhci_s3c_get_driver_data(
545 struct platform_device
*pdev
)
548 if (pdev
->dev
.of_node
) {
549 const struct of_device_id
*match
;
550 match
= of_match_node(sdhci_s3c_dt_match
, pdev
->dev
.of_node
);
551 return (struct sdhci_s3c_drv_data
*)match
->data
;
554 return (struct sdhci_s3c_drv_data
*)
555 platform_get_device_id(pdev
)->driver_data
;
558 static int __devinit
sdhci_s3c_probe(struct platform_device
*pdev
)
560 struct s3c_sdhci_platdata
*pdata
;
561 struct sdhci_s3c_drv_data
*drv_data
;
562 struct device
*dev
= &pdev
->dev
;
563 struct sdhci_host
*host
;
564 struct sdhci_s3c
*sc
;
565 struct resource
*res
;
566 int ret
, irq
, ptr
, clks
;
568 if (!pdev
->dev
.platform_data
&& !pdev
->dev
.of_node
) {
569 dev_err(dev
, "no device data specified\n");
573 irq
= platform_get_irq(pdev
, 0);
575 dev_err(dev
, "no irq specified\n");
579 host
= sdhci_alloc_host(dev
, sizeof(struct sdhci_s3c
));
581 dev_err(dev
, "sdhci_alloc_host() failed\n");
582 return PTR_ERR(host
);
584 sc
= sdhci_priv(host
);
586 pdata
= devm_kzalloc(&pdev
->dev
, sizeof(*pdata
), GFP_KERNEL
);
592 if (pdev
->dev
.of_node
) {
593 ret
= sdhci_s3c_parse_dt(&pdev
->dev
, host
, pdata
);
597 memcpy(pdata
, pdev
->dev
.platform_data
, sizeof(*pdata
));
598 sc
->ext_cd_gpio
= -1; /* invalid gpio number */
601 drv_data
= sdhci_s3c_get_driver_data(pdev
);
607 platform_set_drvdata(pdev
, host
);
609 sc
->clk_io
= clk_get(dev
, "hsmmc");
610 if (IS_ERR(sc
->clk_io
)) {
611 dev_err(dev
, "failed to get io clock\n");
612 ret
= PTR_ERR(sc
->clk_io
);
616 /* enable the local io clock and keep it running for the moment. */
617 clk_prepare_enable(sc
->clk_io
);
619 for (clks
= 0, ptr
= 0; ptr
< MAX_BUS_CLK
; ptr
++) {
623 snprintf(name
, 14, "mmc_busclk.%d", ptr
);
624 clk
= clk_get(dev
, name
);
629 sc
->clk_bus
[ptr
] = clk
;
632 * save current clock index to know which clock bus
633 * is used later in overriding functions.
637 dev_info(dev
, "clock source %d: %s (%ld Hz)\n",
638 ptr
, name
, clk_get_rate(clk
));
642 dev_err(dev
, "failed to find any bus clocks\n");
647 #ifndef CONFIG_PM_RUNTIME
648 clk_prepare_enable(sc
->clk_bus
[sc
->cur_clk
]);
651 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
652 host
->ioaddr
= devm_request_and_ioremap(&pdev
->dev
, res
);
654 dev_err(dev
, "failed to map registers\n");
659 /* Ensure we have minimal gpio selected CMD/CLK/Detect */
661 pdata
->cfg_gpio(pdev
, pdata
->max_width
);
663 host
->hw_name
= "samsung-hsmmc";
664 host
->ops
= &sdhci_s3c_ops
;
668 /* Setup quirks for the controller */
669 host
->quirks
|= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
;
670 host
->quirks
|= SDHCI_QUIRK_NO_HISPD_BIT
;
672 host
->quirks
|= drv_data
->sdhci_quirks
;
674 #ifndef CONFIG_MMC_SDHCI_S3C_DMA
676 /* we currently see overruns on errors, so disable the SDMA
677 * support as well. */
678 host
->quirks
|= SDHCI_QUIRK_BROKEN_DMA
;
680 #endif /* CONFIG_MMC_SDHCI_S3C_DMA */
682 /* It seems we do not get an DATA transfer complete on non-busy
683 * transfers, not sure if this is a problem with this specific
684 * SDHCI block, or a missing configuration that needs to be set. */
685 host
->quirks
|= SDHCI_QUIRK_NO_BUSY_IRQ
;
687 /* This host supports the Auto CMD12 */
688 host
->quirks
|= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
;
690 /* Samsung SoCs need BROKEN_ADMA_ZEROLEN_DESC */
691 host
->quirks
|= SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
;
693 if (pdata
->cd_type
== S3C_SDHCI_CD_NONE
||
694 pdata
->cd_type
== S3C_SDHCI_CD_PERMANENT
)
695 host
->quirks
|= SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
697 if (pdata
->cd_type
== S3C_SDHCI_CD_PERMANENT
)
698 host
->mmc
->caps
= MMC_CAP_NONREMOVABLE
;
700 switch (pdata
->max_width
) {
702 host
->mmc
->caps
|= MMC_CAP_8_BIT_DATA
;
704 host
->mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
709 host
->mmc
->pm_caps
|= pdata
->pm_caps
;
711 host
->quirks
|= (SDHCI_QUIRK_32BIT_DMA_ADDR
|
712 SDHCI_QUIRK_32BIT_DMA_SIZE
);
714 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */
715 host
->quirks
|= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK
;
718 * If controller does not have internal clock divider,
719 * we can use overriding functions instead of default.
721 if (host
->quirks
& SDHCI_QUIRK_NONSTANDARD_CLOCK
) {
722 sdhci_s3c_ops
.set_clock
= sdhci_cmu_set_clock
;
723 sdhci_s3c_ops
.get_min_clock
= sdhci_cmu_get_min_clock
;
724 sdhci_s3c_ops
.get_max_clock
= sdhci_cmu_get_max_clock
;
727 /* It supports additional host capabilities if needed */
728 if (pdata
->host_caps
)
729 host
->mmc
->caps
|= pdata
->host_caps
;
731 if (pdata
->host_caps2
)
732 host
->mmc
->caps2
|= pdata
->host_caps2
;
734 pm_runtime_enable(&pdev
->dev
);
735 pm_runtime_set_autosuspend_delay(&pdev
->dev
, 50);
736 pm_runtime_use_autosuspend(&pdev
->dev
);
737 pm_suspend_ignore_children(&pdev
->dev
, 1);
739 ret
= sdhci_add_host(host
);
741 dev_err(dev
, "sdhci_add_host() failed\n");
742 pm_runtime_forbid(&pdev
->dev
);
743 pm_runtime_get_noresume(&pdev
->dev
);
747 /* The following two methods of card detection might call
748 sdhci_s3c_notify_change() immediately, so they can be called
749 only after sdhci_add_host(). Setup errors are ignored. */
750 if (pdata
->cd_type
== S3C_SDHCI_CD_EXTERNAL
&& pdata
->ext_cd_init
)
751 pdata
->ext_cd_init(&sdhci_s3c_notify_change
);
752 if (pdata
->cd_type
== S3C_SDHCI_CD_GPIO
&&
753 gpio_is_valid(pdata
->ext_cd_gpio
))
754 sdhci_s3c_setup_card_detect_gpio(sc
);
756 #ifdef CONFIG_PM_RUNTIME
757 if (pdata
->cd_type
!= S3C_SDHCI_CD_INTERNAL
)
758 clk_disable_unprepare(sc
->clk_io
);
763 #ifndef CONFIG_PM_RUNTIME
764 clk_disable_unprepare(sc
->clk_bus
[sc
->cur_clk
]);
766 for (ptr
= 0; ptr
< MAX_BUS_CLK
; ptr
++) {
767 if (sc
->clk_bus
[ptr
]) {
768 clk_put(sc
->clk_bus
[ptr
]);
773 clk_disable_unprepare(sc
->clk_io
);
777 for (ptr
= 0; ptr
< NUM_GPIOS(sc
->pdata
->max_width
); ptr
++)
778 gpio_free(sc
->gpios
[ptr
]);
779 if (pdata
->cd_type
== S3C_SDHCI_CD_INTERNAL
)
780 gpio_free(sc
->ext_cd_gpio
);
783 sdhci_free_host(host
);
788 static int __devexit
sdhci_s3c_remove(struct platform_device
*pdev
)
790 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
791 struct sdhci_s3c
*sc
= sdhci_priv(host
);
792 struct s3c_sdhci_platdata
*pdata
= sc
->pdata
;
795 if (pdata
->cd_type
== S3C_SDHCI_CD_EXTERNAL
&& pdata
->ext_cd_cleanup
)
796 pdata
->ext_cd_cleanup(&sdhci_s3c_notify_change
);
799 free_irq(sc
->ext_cd_irq
, sc
);
801 if (gpio_is_valid(sc
->ext_cd_gpio
))
802 gpio_free(sc
->ext_cd_gpio
);
804 #ifdef CONFIG_PM_RUNTIME
805 if (pdata
->cd_type
!= S3C_SDHCI_CD_INTERNAL
)
806 clk_prepare_enable(sc
->clk_io
);
808 sdhci_remove_host(host
, 1);
810 pm_runtime_dont_use_autosuspend(&pdev
->dev
);
811 pm_runtime_disable(&pdev
->dev
);
813 #ifndef CONFIG_PM_RUNTIME
814 clk_disable_unprepare(sc
->clk_bus
[sc
->cur_clk
]);
816 for (ptr
= 0; ptr
< MAX_BUS_CLK
; ptr
++) {
817 if (sc
->clk_bus
[ptr
]) {
818 clk_put(sc
->clk_bus
[ptr
]);
821 clk_disable_unprepare(sc
->clk_io
);
824 if (pdev
->dev
.of_node
) {
825 for (ptr
= 0; ptr
< NUM_GPIOS(sc
->pdata
->max_width
); ptr
++)
826 gpio_free(sc
->gpios
[ptr
]);
829 sdhci_free_host(host
);
830 platform_set_drvdata(pdev
, NULL
);
835 #ifdef CONFIG_PM_SLEEP
836 static int sdhci_s3c_suspend(struct device
*dev
)
838 struct sdhci_host
*host
= dev_get_drvdata(dev
);
840 return sdhci_suspend_host(host
);
843 static int sdhci_s3c_resume(struct device
*dev
)
845 struct sdhci_host
*host
= dev_get_drvdata(dev
);
847 return sdhci_resume_host(host
);
851 #ifdef CONFIG_PM_RUNTIME
852 static int sdhci_s3c_runtime_suspend(struct device
*dev
)
854 struct sdhci_host
*host
= dev_get_drvdata(dev
);
855 struct sdhci_s3c
*ourhost
= to_s3c(host
);
856 struct clk
*busclk
= ourhost
->clk_io
;
859 ret
= sdhci_runtime_suspend_host(host
);
861 clk_disable_unprepare(ourhost
->clk_bus
[ourhost
->cur_clk
]);
862 clk_disable_unprepare(busclk
);
866 static int sdhci_s3c_runtime_resume(struct device
*dev
)
868 struct sdhci_host
*host
= dev_get_drvdata(dev
);
869 struct sdhci_s3c
*ourhost
= to_s3c(host
);
870 struct clk
*busclk
= ourhost
->clk_io
;
873 clk_prepare_enable(busclk
);
874 clk_prepare_enable(ourhost
->clk_bus
[ourhost
->cur_clk
]);
875 ret
= sdhci_runtime_resume_host(host
);
881 static const struct dev_pm_ops sdhci_s3c_pmops
= {
882 SET_SYSTEM_SLEEP_PM_OPS(sdhci_s3c_suspend
, sdhci_s3c_resume
)
883 SET_RUNTIME_PM_OPS(sdhci_s3c_runtime_suspend
, sdhci_s3c_runtime_resume
,
887 #define SDHCI_S3C_PMOPS (&sdhci_s3c_pmops)
890 #define SDHCI_S3C_PMOPS NULL
893 #if defined(CONFIG_CPU_EXYNOS4210) || defined(CONFIG_SOC_EXYNOS4212)
894 static struct sdhci_s3c_drv_data exynos4_sdhci_drv_data
= {
895 .sdhci_quirks
= SDHCI_QUIRK_NONSTANDARD_CLOCK
,
897 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)&exynos4_sdhci_drv_data)
899 #define EXYNOS4_SDHCI_DRV_DATA ((kernel_ulong_t)NULL)
902 static struct platform_device_id sdhci_s3c_driver_ids
[] = {
905 .driver_data
= (kernel_ulong_t
)NULL
,
907 .name
= "exynos4-sdhci",
908 .driver_data
= EXYNOS4_SDHCI_DRV_DATA
,
912 MODULE_DEVICE_TABLE(platform
, sdhci_s3c_driver_ids
);
915 static const struct of_device_id sdhci_s3c_dt_match
[] = {
916 { .compatible
= "samsung,s3c6410-sdhci", },
917 { .compatible
= "samsung,exynos4210-sdhci",
918 .data
= (void *)EXYNOS4_SDHCI_DRV_DATA
},
921 MODULE_DEVICE_TABLE(of
, sdhci_s3c_dt_match
);
924 static struct platform_driver sdhci_s3c_driver
= {
925 .probe
= sdhci_s3c_probe
,
926 .remove
= __devexit_p(sdhci_s3c_remove
),
927 .id_table
= sdhci_s3c_driver_ids
,
929 .owner
= THIS_MODULE
,
931 .of_match_table
= of_match_ptr(sdhci_s3c_dt_match
),
932 .pm
= SDHCI_S3C_PMOPS
,
936 module_platform_driver(sdhci_s3c_driver
);
938 MODULE_DESCRIPTION("Samsung SDHCI (HSMMC) glue");
939 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
940 MODULE_LICENSE("GPL v2");
941 MODULE_ALIAS("platform:s3c-sdhci");