projects / deliverable / linux.git / blob
? search:


58c1770e879d6b73bc9edafa634e0af849f818a8
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
42 defined(CONFIG_MMC_SDHCI_MODULE))
43 #define SDHCI_USE_LEDS_CLASS
44 #endif
45
46 #define MAX_TUNING_LOOP 40
47
48 static unsigned int debug_quirks = 0;
49 static unsigned int debug_quirks2;
50
51 static void sdhci_finish_data(struct sdhci_host *);
52
53 static void sdhci_finish_command(struct sdhci_host *);
54 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
56 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
57 struct mmc_data *data,
58 struct sdhci_host_next *next);
59 static int sdhci_do_get_cd(struct sdhci_host *host);
60
61 #ifdef CONFIG_PM
62 static int sdhci_runtime_pm_get(struct sdhci_host *host);
63 static int sdhci_runtime_pm_put(struct sdhci_host *host);
64 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
65 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
66 #else
67 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
68 {
69 return 0;
70 }
71 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
72 {
73 return 0;
74 }
75 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
76 {
77 }
78 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79 {
80 }
81 #endif
82
83 static void sdhci_dumpregs(struct sdhci_host *host)
84 {
85 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
86 mmc_hostname(host->mmc));
87
88 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
89 sdhci_readl(host, SDHCI_DMA_ADDRESS),
90 sdhci_readw(host, SDHCI_HOST_VERSION));
91 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
92 sdhci_readw(host, SDHCI_BLOCK_SIZE),
93 sdhci_readw(host, SDHCI_BLOCK_COUNT));
94 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
95 sdhci_readl(host, SDHCI_ARGUMENT),
96 sdhci_readw(host, SDHCI_TRANSFER_MODE));
97 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
98 sdhci_readl(host, SDHCI_PRESENT_STATE),
99 sdhci_readb(host, SDHCI_HOST_CONTROL));
100 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
101 sdhci_readb(host, SDHCI_POWER_CONTROL),
102 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
103 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
104 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
105 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
106 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
107 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
108 sdhci_readl(host, SDHCI_INT_STATUS));
109 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
110 sdhci_readl(host, SDHCI_INT_ENABLE),
111 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
112 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
113 sdhci_readw(host, SDHCI_ACMD12_ERR),
114 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
115 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
116 sdhci_readl(host, SDHCI_CAPABILITIES),
117 sdhci_readl(host, SDHCI_CAPABILITIES_1));
118 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
119 sdhci_readw(host, SDHCI_COMMAND),
120 sdhci_readl(host, SDHCI_MAX_CURRENT));
121 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
122 sdhci_readw(host, SDHCI_HOST_CONTROL2));
123
124 if (host->flags & SDHCI_USE_ADMA) {
125 if (host->flags & SDHCI_USE_64_BIT_DMA)
126 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
127 readl(host->ioaddr + SDHCI_ADMA_ERROR),
128 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
129 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
130 else
131 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
132 readl(host->ioaddr + SDHCI_ADMA_ERROR),
133 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
134 }
135
136 pr_debug(DRIVER_NAME ": ===========================================\n");
137 }
138
139 /*****************************************************************************\
140 * *
141 * Low level functions *
142 * *
143 \*****************************************************************************/
144
145 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
146 {
147 u32 present;
148
149 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
150 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
151 return;
152
153 if (enable) {
154 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
155 SDHCI_CARD_PRESENT;
156
157 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
158 SDHCI_INT_CARD_INSERT;
159 } else {
160 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
161 }
162
163 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
164 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
165 }
166
167 static void sdhci_enable_card_detection(struct sdhci_host *host)
168 {
169 sdhci_set_card_detection(host, true);
170 }
171
172 static void sdhci_disable_card_detection(struct sdhci_host *host)
173 {
174 sdhci_set_card_detection(host, false);
175 }
176
177 void sdhci_reset(struct sdhci_host *host, u8 mask)
178 {
179 unsigned long timeout;
180
181 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
182
183 if (mask & SDHCI_RESET_ALL) {
184 host->clock = 0;
185 /* Reset-all turns off SD Bus Power */
186 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
187 sdhci_runtime_pm_bus_off(host);
188 }
189
190 /* Wait max 100 ms */
191 timeout = 100;
192
193 /* hw clears the bit when it's done */
194 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
195 if (timeout == 0) {
196 pr_err("%s: Reset 0x%x never completed.\n",
197 mmc_hostname(host->mmc), (int)mask);
198 sdhci_dumpregs(host);
199 return;
200 }
201 timeout--;
202 mdelay(1);
203 }
204 }
205 EXPORT_SYMBOL_GPL(sdhci_reset);
206
207 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
208 {
209 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
210 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
211 SDHCI_CARD_PRESENT))
212 return;
213 }
214
215 host->ops->reset(host, mask);
216
217 if (mask & SDHCI_RESET_ALL) {
218 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
219 if (host->ops->enable_dma)
220 host->ops->enable_dma(host);
221 }
222
223 /* Resetting the controller clears many */
224 host->preset_enabled = false;
225 }
226 }
227
228 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
229
230 static void sdhci_init(struct sdhci_host *host, int soft)
231 {
232 if (soft)
233 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
234 else
235 sdhci_do_reset(host, SDHCI_RESET_ALL);
236
237 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
238 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
239 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
240 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
241 SDHCI_INT_RESPONSE;
242
243 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
244 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
245
246 if (soft) {
247 /* force clock reconfiguration */
248 host->clock = 0;
249 sdhci_set_ios(host->mmc, &host->mmc->ios);
250 }
251 }
252
253 static void sdhci_reinit(struct sdhci_host *host)
254 {
255 sdhci_init(host, 0);
256 sdhci_enable_card_detection(host);
257 }
258
259 static void sdhci_activate_led(struct sdhci_host *host)
260 {
261 u8 ctrl;
262
263 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
264 ctrl |= SDHCI_CTRL_LED;
265 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
266 }
267
268 static void sdhci_deactivate_led(struct sdhci_host *host)
269 {
270 u8 ctrl;
271
272 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
273 ctrl &= ~SDHCI_CTRL_LED;
274 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
275 }
276
277 #ifdef SDHCI_USE_LEDS_CLASS
278 static void sdhci_led_control(struct led_classdev *led,
279 enum led_brightness brightness)
280 {
281 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
282 unsigned long flags;
283
284 spin_lock_irqsave(&host->lock, flags);
285
286 if (host->runtime_suspended)
287 goto out;
288
289 if (brightness == LED_OFF)
290 sdhci_deactivate_led(host);
291 else
292 sdhci_activate_led(host);
293 out:
294 spin_unlock_irqrestore(&host->lock, flags);
295 }
296 #endif
297
298 /*****************************************************************************\
299 * *
300 * Core functions *
301 * *
302 \*****************************************************************************/
303
304 static void sdhci_read_block_pio(struct sdhci_host *host)
305 {
306 unsigned long flags;
307 size_t blksize, len, chunk;
308 u32 uninitialized_var(scratch);
309 u8 *buf;
310
311 DBG("PIO reading\n");
312
313 blksize = host->data->blksz;
314 chunk = 0;
315
316 local_irq_save(flags);
317
318 while (blksize) {
319 BUG_ON(!sg_miter_next(&host->sg_miter));
320
321 len = min(host->sg_miter.length, blksize);
322
323 blksize -= len;
324 host->sg_miter.consumed = len;
325
326 buf = host->sg_miter.addr;
327
328 while (len) {
329 if (chunk == 0) {
330 scratch = sdhci_readl(host, SDHCI_BUFFER);
331 chunk = 4;
332 }
333
334 *buf = scratch & 0xFF;
335
336 buf++;
337 scratch >>= 8;
338 chunk--;
339 len--;
340 }
341 }
342
343 sg_miter_stop(&host->sg_miter);
344
345 local_irq_restore(flags);
346 }
347
348 static void sdhci_write_block_pio(struct sdhci_host *host)
349 {
350 unsigned long flags;
351 size_t blksize, len, chunk;
352 u32 scratch;
353 u8 *buf;
354
355 DBG("PIO writing\n");
356
357 blksize = host->data->blksz;
358 chunk = 0;
359 scratch = 0;
360
361 local_irq_save(flags);
362
363 while (blksize) {
364 BUG_ON(!sg_miter_next(&host->sg_miter));
365
366 len = min(host->sg_miter.length, blksize);
367
368 blksize -= len;
369 host->sg_miter.consumed = len;
370
371 buf = host->sg_miter.addr;
372
373 while (len) {
374 scratch |= (u32)*buf << (chunk * 8);
375
376 buf++;
377 chunk++;
378 len--;
379
380 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
381 sdhci_writel(host, scratch, SDHCI_BUFFER);
382 chunk = 0;
383 scratch = 0;
384 }
385 }
386 }
387
388 sg_miter_stop(&host->sg_miter);
389
390 local_irq_restore(flags);
391 }
392
393 static void sdhci_transfer_pio(struct sdhci_host *host)
394 {
395 u32 mask;
396
397 BUG_ON(!host->data);
398
399 if (host->blocks == 0)
400 return;
401
402 if (host->data->flags & MMC_DATA_READ)
403 mask = SDHCI_DATA_AVAILABLE;
404 else
405 mask = SDHCI_SPACE_AVAILABLE;
406
407 /*
408 * Some controllers (JMicron JMB38x) mess up the buffer bits
409 * for transfers < 4 bytes. As long as it is just one block,
410 * we can ignore the bits.
411 */
412 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
413 (host->data->blocks == 1))
414 mask = ~0;
415
416 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
417 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
418 udelay(100);
419
420 if (host->data->flags & MMC_DATA_READ)
421 sdhci_read_block_pio(host);
422 else
423 sdhci_write_block_pio(host);
424
425 host->blocks--;
426 if (host->blocks == 0)
427 break;
428 }
429
430 DBG("PIO transfer complete.\n");
431 }
432
433 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
434 {
435 local_irq_save(*flags);
436 return kmap_atomic(sg_page(sg)) + sg->offset;
437 }
438
439 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
440 {
441 kunmap_atomic(buffer);
442 local_irq_restore(*flags);
443 }
444
445 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
446 dma_addr_t addr, int len, unsigned cmd)
447 {
448 struct sdhci_adma2_64_desc *dma_desc = desc;
449
450 /* 32-bit and 64-bit descriptors have these members in same position */
451 dma_desc->cmd = cpu_to_le16(cmd);
452 dma_desc->len = cpu_to_le16(len);
453 dma_desc->addr_lo = cpu_to_le32((u32)addr);
454
455 if (host->flags & SDHCI_USE_64_BIT_DMA)
456 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
457 }
458
459 static void sdhci_adma_mark_end(void *desc)
460 {
461 struct sdhci_adma2_64_desc *dma_desc = desc;
462
463 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
464 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
465 }
466
467 static int sdhci_adma_table_pre(struct sdhci_host *host,
468 struct mmc_data *data)
469 {
470 int direction;
471
472 void *desc;
473 void *align;
474 dma_addr_t addr;
475 dma_addr_t align_addr;
476 int len, offset;
477
478 struct scatterlist *sg;
479 int i;
480 char *buffer;
481 unsigned long flags;
482
483 /*
484 * The spec does not specify endianness of descriptor table.
485 * We currently guess that it is LE.
486 */
487
488 if (data->flags & MMC_DATA_READ)
489 direction = DMA_FROM_DEVICE;
490 else
491 direction = DMA_TO_DEVICE;
492
493 host->align_addr = dma_map_single(mmc_dev(host->mmc),
494 host->align_buffer, host->align_buffer_sz, direction);
495 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
496 goto fail;
497 BUG_ON(host->align_addr & host->align_mask);
498
499 host->sg_count = sdhci_pre_dma_transfer(host, data, NULL);
500 if (host->sg_count < 0)
501 goto unmap_align;
502
503 desc = host->adma_table;
504 align = host->align_buffer;
505
506 align_addr = host->align_addr;
507
508 for_each_sg(data->sg, sg, host->sg_count, i) {
509 addr = sg_dma_address(sg);
510 len = sg_dma_len(sg);
511
512 /*
513 * The SDHCI specification states that ADMA
514 * addresses must be 32-bit aligned. If they
515 * aren't, then we use a bounce buffer for
516 * the (up to three) bytes that screw up the
517 * alignment.
518 */
519 offset = (host->align_sz - (addr & host->align_mask)) &
520 host->align_mask;
521 if (offset) {
522 if (data->flags & MMC_DATA_WRITE) {
523 buffer = sdhci_kmap_atomic(sg, &flags);
524 memcpy(align, buffer, offset);
525 sdhci_kunmap_atomic(buffer, &flags);
526 }
527
528 /* tran, valid */
529 sdhci_adma_write_desc(host, desc, align_addr, offset,
530 ADMA2_TRAN_VALID);
531
532 BUG_ON(offset > 65536);
533
534 align += host->align_sz;
535 align_addr += host->align_sz;
536
537 desc += host->desc_sz;
538
539 addr += offset;
540 len -= offset;
541 }
542
543 BUG_ON(len > 65536);
544
545 /* tran, valid */
546 sdhci_adma_write_desc(host, desc, addr, len, ADMA2_TRAN_VALID);
547 desc += host->desc_sz;
548
549 /*
550 * If this triggers then we have a calculation bug
551 * somewhere. :/
552 */
553 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
554 }
555
556 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
557 /*
558 * Mark the last descriptor as the terminating descriptor
559 */
560 if (desc != host->adma_table) {
561 desc -= host->desc_sz;
562 sdhci_adma_mark_end(desc);
563 }
564 } else {
565 /*
566 * Add a terminating entry.
567 */
568
569 /* nop, end, valid */
570 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
571 }
572
573 /*
574 * Resync align buffer as we might have changed it.
575 */
576 if (data->flags & MMC_DATA_WRITE) {
577 dma_sync_single_for_device(mmc_dev(host->mmc),
578 host->align_addr, host->align_buffer_sz, direction);
579 }
580
581 return 0;
582
583 unmap_align:
584 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
585 host->align_buffer_sz, direction);
586 fail:
587 return -EINVAL;
588 }
589
590 static void sdhci_adma_table_post(struct sdhci_host *host,
591 struct mmc_data *data)
592 {
593 int direction;
594
595 struct scatterlist *sg;
596 int i, size;
597 void *align;
598 char *buffer;
599 unsigned long flags;
600 bool has_unaligned;
601
602 if (data->flags & MMC_DATA_READ)
603 direction = DMA_FROM_DEVICE;
604 else
605 direction = DMA_TO_DEVICE;
606
607 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
608 host->align_buffer_sz, direction);
609
610 /* Do a quick scan of the SG list for any unaligned mappings */
611 has_unaligned = false;
612 for_each_sg(data->sg, sg, host->sg_count, i)
613 if (sg_dma_address(sg) & host->align_mask) {
614 has_unaligned = true;
615 break;
616 }
617
618 if (has_unaligned && data->flags & MMC_DATA_READ) {
619 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
620 data->sg_len, direction);
621
622 align = host->align_buffer;
623
624 for_each_sg(data->sg, sg, host->sg_count, i) {
625 if (sg_dma_address(sg) & host->align_mask) {
626 size = host->align_sz -
627 (sg_dma_address(sg) & host->align_mask);
628
629 buffer = sdhci_kmap_atomic(sg, &flags);
630 memcpy(buffer, align, size);
631 sdhci_kunmap_atomic(buffer, &flags);
632
633 align += host->align_sz;
634 }
635 }
636 }
637
638 if (!data->host_cookie)
639 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
640 data->sg_len, direction);
641 }
642
643 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
644 {
645 u8 count;
646 struct mmc_data *data = cmd->data;
647 unsigned target_timeout, current_timeout;
648
649 /*
650 * If the host controller provides us with an incorrect timeout
651 * value, just skip the check and use 0xE. The hardware may take
652 * longer to time out, but that's much better than having a too-short
653 * timeout value.
654 */
655 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
656 return 0xE;
657
658 /* Unspecified timeout, assume max */
659 if (!data && !cmd->busy_timeout)
660 return 0xE;
661
662 /* timeout in us */
663 if (!data)
664 target_timeout = cmd->busy_timeout * 1000;
665 else {
666 target_timeout = data->timeout_ns / 1000;
667 if (host->clock)
668 target_timeout += data->timeout_clks / host->clock;
669 }
670
671 /*
672 * Figure out needed cycles.
673 * We do this in steps in order to fit inside a 32 bit int.
674 * The first step is the minimum timeout, which will have a
675 * minimum resolution of 6 bits:
676 * (1) 2^13*1000 > 2^22,
677 * (2) host->timeout_clk < 2^16
678 * =>
679 * (1) / (2) > 2^6
680 */
681 count = 0;
682 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
683 while (current_timeout < target_timeout) {
684 count++;
685 current_timeout <<= 1;
686 if (count >= 0xF)
687 break;
688 }
689
690 if (count >= 0xF) {
691 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
692 mmc_hostname(host->mmc), count, cmd->opcode);
693 count = 0xE;
694 }
695
696 return count;
697 }
698
699 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
700 {
701 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
702 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
703
704 if (host->flags & SDHCI_REQ_USE_DMA)
705 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
706 else
707 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
708
709 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
710 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
711 }
712
713 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
714 {
715 u8 count;
716
717 if (host->ops->set_timeout) {
718 host->ops->set_timeout(host, cmd);
719 } else {
720 count = sdhci_calc_timeout(host, cmd);
721 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
722 }
723 }
724
725 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
726 {
727 u8 ctrl;
728 struct mmc_data *data = cmd->data;
729 int ret;
730
731 WARN_ON(host->data);
732
733 if (data || (cmd->flags & MMC_RSP_BUSY))
734 sdhci_set_timeout(host, cmd);
735
736 if (!data)
737 return;
738
739 /* Sanity checks */
740 BUG_ON(data->blksz * data->blocks > 524288);
741 BUG_ON(data->blksz > host->mmc->max_blk_size);
742 BUG_ON(data->blocks > 65535);
743
744 host->data = data;
745 host->data_early = 0;
746 host->data->bytes_xfered = 0;
747
748 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
749 host->flags |= SDHCI_REQ_USE_DMA;
750
751 /*
752 * FIXME: This doesn't account for merging when mapping the
753 * scatterlist.
754 */
755 if (host->flags & SDHCI_REQ_USE_DMA) {
756 int broken, i;
757 struct scatterlist *sg;
758
759 broken = 0;
760 if (host->flags & SDHCI_USE_ADMA) {
761 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
762 broken = 1;
763 } else {
764 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
765 broken = 1;
766 }
767
768 if (unlikely(broken)) {
769 for_each_sg(data->sg, sg, data->sg_len, i) {
770 if (sg->length & 0x3) {
771 DBG("Reverting to PIO because of "
772 "transfer size (%d)\n",
773 sg->length);
774 host->flags &= ~SDHCI_REQ_USE_DMA;
775 break;
776 }
777 }
778 }
779 }
780
781 /*
782 * The assumption here being that alignment is the same after
783 * translation to device address space.
784 */
785 if (host->flags & SDHCI_REQ_USE_DMA) {
786 int broken, i;
787 struct scatterlist *sg;
788
789 broken = 0;
790 if (host->flags & SDHCI_USE_ADMA) {
791 /*
792 * As we use 3 byte chunks to work around
793 * alignment problems, we need to check this
794 * quirk.
795 */
796 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
797 broken = 1;
798 } else {
799 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
800 broken = 1;
801 }
802
803 if (unlikely(broken)) {
804 for_each_sg(data->sg, sg, data->sg_len, i) {
805 if (sg->offset & 0x3) {
806 DBG("Reverting to PIO because of "
807 "bad alignment\n");
808 host->flags &= ~SDHCI_REQ_USE_DMA;
809 break;
810 }
811 }
812 }
813 }
814
815 if (host->flags & SDHCI_REQ_USE_DMA) {
816 if (host->flags & SDHCI_USE_ADMA) {
817 ret = sdhci_adma_table_pre(host, data);
818 if (ret) {
819 /*
820 * This only happens when someone fed
821 * us an invalid request.
822 */
823 WARN_ON(1);
824 host->flags &= ~SDHCI_REQ_USE_DMA;
825 } else {
826 sdhci_writel(host, host->adma_addr,
827 SDHCI_ADMA_ADDRESS);
828 if (host->flags & SDHCI_USE_64_BIT_DMA)
829 sdhci_writel(host,
830 (u64)host->adma_addr >> 32,
831 SDHCI_ADMA_ADDRESS_HI);
832 }
833 } else {
834 int sg_cnt;
835
836 sg_cnt = sdhci_pre_dma_transfer(host, data, NULL);
837 if (sg_cnt == 0) {
838 /*
839 * This only happens when someone fed
840 * us an invalid request.
841 */
842 WARN_ON(1);
843 host->flags &= ~SDHCI_REQ_USE_DMA;
844 } else {
845 WARN_ON(sg_cnt != 1);
846 sdhci_writel(host, sg_dma_address(data->sg),
847 SDHCI_DMA_ADDRESS);
848 }
849 }
850 }
851
852 /*
853 * Always adjust the DMA selection as some controllers
854 * (e.g. JMicron) can't do PIO properly when the selection
855 * is ADMA.
856 */
857 if (host->version >= SDHCI_SPEC_200) {
858 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
859 ctrl &= ~SDHCI_CTRL_DMA_MASK;
860 if ((host->flags & SDHCI_REQ_USE_DMA) &&
861 (host->flags & SDHCI_USE_ADMA)) {
862 if (host->flags & SDHCI_USE_64_BIT_DMA)
863 ctrl |= SDHCI_CTRL_ADMA64;
864 else
865 ctrl |= SDHCI_CTRL_ADMA32;
866 } else {
867 ctrl |= SDHCI_CTRL_SDMA;
868 }
869 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
870 }
871
872 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
873 int flags;
874
875 flags = SG_MITER_ATOMIC;
876 if (host->data->flags & MMC_DATA_READ)
877 flags |= SG_MITER_TO_SG;
878 else
879 flags |= SG_MITER_FROM_SG;
880 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
881 host->blocks = data->blocks;
882 }
883
884 sdhci_set_transfer_irqs(host);
885
886 /* Set the DMA boundary value and block size */
887 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
888 data->blksz), SDHCI_BLOCK_SIZE);
889 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
890 }
891
892 static void sdhci_set_transfer_mode(struct sdhci_host *host,
893 struct mmc_command *cmd)
894 {
895 u16 mode = 0;
896 struct mmc_data *data = cmd->data;
897
898 if (data == NULL) {
899 if (host->quirks2 &
900 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
901 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
902 } else {
903 /* clear Auto CMD settings for no data CMDs */
904 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
905 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
906 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
907 }
908 return;
909 }
910
911 WARN_ON(!host->data);
912
913 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
914 mode = SDHCI_TRNS_BLK_CNT_EN;
915
916 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
917 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
918 /*
919 * If we are sending CMD23, CMD12 never gets sent
920 * on successful completion (so no Auto-CMD12).
921 */
922 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
923 (cmd->opcode != SD_IO_RW_EXTENDED))
924 mode |= SDHCI_TRNS_AUTO_CMD12;
925 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
926 mode |= SDHCI_TRNS_AUTO_CMD23;
927 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
928 }
929 }
930
931 if (data->flags & MMC_DATA_READ)
932 mode |= SDHCI_TRNS_READ;
933 if (host->flags & SDHCI_REQ_USE_DMA)
934 mode |= SDHCI_TRNS_DMA;
935
936 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
937 }
938
939 static void sdhci_finish_data(struct sdhci_host *host)
940 {
941 struct mmc_data *data;
942
943 BUG_ON(!host->data);
944
945 data = host->data;
946 host->data = NULL;
947
948 if (host->flags & SDHCI_REQ_USE_DMA) {
949 if (host->flags & SDHCI_USE_ADMA)
950 sdhci_adma_table_post(host, data);
951 else {
952 if (!data->host_cookie)
953 dma_unmap_sg(mmc_dev(host->mmc),
954 data->sg, data->sg_len,
955 (data->flags & MMC_DATA_READ) ?
956 DMA_FROM_DEVICE : DMA_TO_DEVICE);
957 }
958 }
959
960 /*
961 * The specification states that the block count register must
962 * be updated, but it does not specify at what point in the
963 * data flow. That makes the register entirely useless to read
964 * back so we have to assume that nothing made it to the card
965 * in the event of an error.
966 */
967 if (data->error)
968 data->bytes_xfered = 0;
969 else
970 data->bytes_xfered = data->blksz * data->blocks;
971
972 /*
973 * Need to send CMD12 if -
974 * a) open-ended multiblock transfer (no CMD23)
975 * b) error in multiblock transfer
976 */
977 if (data->stop &&
978 (data->error ||
979 !host->mrq->sbc)) {
980
981 /*
982 * The controller needs a reset of internal state machines
983 * upon error conditions.
984 */
985 if (data->error) {
986 sdhci_do_reset(host, SDHCI_RESET_CMD);
987 sdhci_do_reset(host, SDHCI_RESET_DATA);
988 }
989
990 sdhci_send_command(host, data->stop);
991 } else
992 tasklet_schedule(&host->finish_tasklet);
993 }
994
995 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
996 {
997 int flags;
998 u32 mask;
999 unsigned long timeout;
1000
1001 WARN_ON(host->cmd);
1002
1003 /* Wait max 10 ms */
1004 timeout = 10;
1005
1006 mask = SDHCI_CMD_INHIBIT;
1007 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
1008 mask |= SDHCI_DATA_INHIBIT;
1009
1010 /* We shouldn't wait for data inihibit for stop commands, even
1011 though they might use busy signaling */
1012 if (host->mrq->data && (cmd == host->mrq->data->stop))
1013 mask &= ~SDHCI_DATA_INHIBIT;
1014
1015 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1016 if (timeout == 0) {
1017 pr_err("%s: Controller never released "
1018 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1019 sdhci_dumpregs(host);
1020 cmd->error = -EIO;
1021 tasklet_schedule(&host->finish_tasklet);
1022 return;
1023 }
1024 timeout--;
1025 mdelay(1);
1026 }
1027
1028 timeout = jiffies;
1029 if (!cmd->data && cmd->busy_timeout > 9000)
1030 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1031 else
1032 timeout += 10 * HZ;
1033 mod_timer(&host->timer, timeout);
1034
1035 host->cmd = cmd;
1036 host->busy_handle = 0;
1037
1038 sdhci_prepare_data(host, cmd);
1039
1040 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1041
1042 sdhci_set_transfer_mode(host, cmd);
1043
1044 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1045 pr_err("%s: Unsupported response type!\n",
1046 mmc_hostname(host->mmc));
1047 cmd->error = -EINVAL;
1048 tasklet_schedule(&host->finish_tasklet);
1049 return;
1050 }
1051
1052 if (!(cmd->flags & MMC_RSP_PRESENT))
1053 flags = SDHCI_CMD_RESP_NONE;
1054 else if (cmd->flags & MMC_RSP_136)
1055 flags = SDHCI_CMD_RESP_LONG;
1056 else if (cmd->flags & MMC_RSP_BUSY)
1057 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1058 else
1059 flags = SDHCI_CMD_RESP_SHORT;
1060
1061 if (cmd->flags & MMC_RSP_CRC)
1062 flags |= SDHCI_CMD_CRC;
1063 if (cmd->flags & MMC_RSP_OPCODE)
1064 flags |= SDHCI_CMD_INDEX;
1065
1066 /* CMD19 is special in that the Data Present Select should be set */
1067 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1068 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1069 flags |= SDHCI_CMD_DATA;
1070
1071 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1072 }
1073 EXPORT_SYMBOL_GPL(sdhci_send_command);
1074
1075 static void sdhci_finish_command(struct sdhci_host *host)
1076 {
1077 int i;
1078
1079 BUG_ON(host->cmd == NULL);
1080
1081 if (host->cmd->flags & MMC_RSP_PRESENT) {
1082 if (host->cmd->flags & MMC_RSP_136) {
1083 /* CRC is stripped so we need to do some shifting. */
1084 for (i = 0;i < 4;i++) {
1085 host->cmd->resp[i] = sdhci_readl(host,
1086 SDHCI_RESPONSE + (3-i)*4) << 8;
1087 if (i != 3)
1088 host->cmd->resp[i] |=
1089 sdhci_readb(host,
1090 SDHCI_RESPONSE + (3-i)*4-1);
1091 }
1092 } else {
1093 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1094 }
1095 }
1096
1097 host->cmd->error = 0;
1098
1099 /* Finished CMD23, now send actual command. */
1100 if (host->cmd == host->mrq->sbc) {
1101 host->cmd = NULL;
1102 sdhci_send_command(host, host->mrq->cmd);
1103 } else {
1104
1105 /* Processed actual command. */
1106 if (host->data && host->data_early)
1107 sdhci_finish_data(host);
1108
1109 if (!host->cmd->data)
1110 tasklet_schedule(&host->finish_tasklet);
1111
1112 host->cmd = NULL;
1113 }
1114 }
1115
1116 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1117 {
1118 u16 preset = 0;
1119
1120 switch (host->timing) {
1121 case MMC_TIMING_UHS_SDR12:
1122 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1123 break;
1124 case MMC_TIMING_UHS_SDR25:
1125 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1126 break;
1127 case MMC_TIMING_UHS_SDR50:
1128 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1129 break;
1130 case MMC_TIMING_UHS_SDR104:
1131 case MMC_TIMING_MMC_HS200:
1132 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1133 break;
1134 case MMC_TIMING_UHS_DDR50:
1135 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1136 break;
1137 case MMC_TIMING_MMC_HS400:
1138 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1139 break;
1140 default:
1141 pr_warn("%s: Invalid UHS-I mode selected\n",
1142 mmc_hostname(host->mmc));
1143 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1144 break;
1145 }
1146 return preset;
1147 }
1148
1149 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1150 {
1151 int div = 0; /* Initialized for compiler warning */
1152 int real_div = div, clk_mul = 1;
1153 u16 clk = 0;
1154 unsigned long timeout;
1155
1156 host->mmc->actual_clock = 0;
1157
1158 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1159
1160 if (clock == 0)
1161 return;
1162
1163 if (host->version >= SDHCI_SPEC_300) {
1164 if (host->preset_enabled) {
1165 u16 pre_val;
1166
1167 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1168 pre_val = sdhci_get_preset_value(host);
1169 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1170 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1171 if (host->clk_mul &&
1172 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1173 clk = SDHCI_PROG_CLOCK_MODE;
1174 real_div = div + 1;
1175 clk_mul = host->clk_mul;
1176 } else {
1177 real_div = max_t(int, 1, div << 1);
1178 }
1179 goto clock_set;
1180 }
1181
1182 /*
1183 * Check if the Host Controller supports Programmable Clock
1184 * Mode.
1185 */
1186 if (host->clk_mul) {
1187 for (div = 1; div <= 1024; div++) {
1188 if ((host->max_clk * host->clk_mul / div)
1189 <= clock)
1190 break;
1191 }
1192 /*
1193 * Set Programmable Clock Mode in the Clock
1194 * Control register.
1195 */
1196 clk = SDHCI_PROG_CLOCK_MODE;
1197 real_div = div;
1198 clk_mul = host->clk_mul;
1199 div--;
1200 } else {
1201 /* Version 3.00 divisors must be a multiple of 2. */
1202 if (host->max_clk <= clock)
1203 div = 1;
1204 else {
1205 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1206 div += 2) {
1207 if ((host->max_clk / div) <= clock)
1208 break;
1209 }
1210 }
1211 real_div = div;
1212 div >>= 1;
1213 }
1214 } else {
1215 /* Version 2.00 divisors must be a power of 2. */
1216 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1217 if ((host->max_clk / div) <= clock)
1218 break;
1219 }
1220 real_div = div;
1221 div >>= 1;
1222 }
1223
1224 clock_set:
1225 if (real_div)
1226 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1227 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1228 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1229 << SDHCI_DIVIDER_HI_SHIFT;
1230 clk |= SDHCI_CLOCK_INT_EN;
1231 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1232
1233 /* Wait max 20 ms */
1234 timeout = 20;
1235 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1236 & SDHCI_CLOCK_INT_STABLE)) {
1237 if (timeout == 0) {
1238 pr_err("%s: Internal clock never "
1239 "stabilised.\n", mmc_hostname(host->mmc));
1240 sdhci_dumpregs(host);
1241 return;
1242 }
1243 timeout--;
1244 mdelay(1);
1245 }
1246
1247 clk |= SDHCI_CLOCK_CARD_EN;
1248 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1249 }
1250 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1251
1252 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1253 unsigned short vdd)
1254 {
1255 struct mmc_host *mmc = host->mmc;
1256 u8 pwr = 0;
1257
1258 if (!IS_ERR(mmc->supply.vmmc)) {
1259 spin_unlock_irq(&host->lock);
1260 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1261 spin_lock_irq(&host->lock);
1262
1263 if (mode != MMC_POWER_OFF)
1264 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1265 else
1266 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1267
1268 return;
1269 }
1270
1271 if (mode != MMC_POWER_OFF) {
1272 switch (1 << vdd) {
1273 case MMC_VDD_165_195:
1274 pwr = SDHCI_POWER_180;
1275 break;
1276 case MMC_VDD_29_30:
1277 case MMC_VDD_30_31:
1278 pwr = SDHCI_POWER_300;
1279 break;
1280 case MMC_VDD_32_33:
1281 case MMC_VDD_33_34:
1282 pwr = SDHCI_POWER_330;
1283 break;
1284 default:
1285 BUG();
1286 }
1287 }
1288
1289 if (host->pwr == pwr)
1290 return;
1291
1292 host->pwr = pwr;
1293
1294 if (pwr == 0) {
1295 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1296 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1297 sdhci_runtime_pm_bus_off(host);
1298 vdd = 0;
1299 } else {
1300 /*
1301 * Spec says that we should clear the power reg before setting
1302 * a new value. Some controllers don't seem to like this though.
1303 */
1304 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1305 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1306
1307 /*
1308 * At least the Marvell CaFe chip gets confused if we set the
1309 * voltage and set turn on power at the same time, so set the
1310 * voltage first.
1311 */
1312 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1313 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1314
1315 pwr |= SDHCI_POWER_ON;
1316
1317 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1318
1319 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1320 sdhci_runtime_pm_bus_on(host);
1321
1322 /*
1323 * Some controllers need an extra 10ms delay of 10ms before
1324 * they can apply clock after applying power
1325 */
1326 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1327 mdelay(10);
1328 }
1329 }
1330
1331 /*****************************************************************************\
1332 * *
1333 * MMC callbacks *
1334 * *
1335 \*****************************************************************************/
1336
1337 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1338 {
1339 struct sdhci_host *host;
1340 int present;
1341 unsigned long flags;
1342
1343 host = mmc_priv(mmc);
1344
1345 sdhci_runtime_pm_get(host);
1346
1347 /* Firstly check card presence */
1348 present = sdhci_do_get_cd(host);
1349
1350 spin_lock_irqsave(&host->lock, flags);
1351
1352 WARN_ON(host->mrq != NULL);
1353
1354 #ifndef SDHCI_USE_LEDS_CLASS
1355 sdhci_activate_led(host);
1356 #endif
1357
1358 /*
1359 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1360 * requests if Auto-CMD12 is enabled.
1361 */
1362 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1363 if (mrq->stop) {
1364 mrq->data->stop = NULL;
1365 mrq->stop = NULL;
1366 }
1367 }
1368
1369 host->mrq = mrq;
1370
1371 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1372 host->mrq->cmd->error = -ENOMEDIUM;
1373 tasklet_schedule(&host->finish_tasklet);
1374 } else {
1375 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1376 sdhci_send_command(host, mrq->sbc);
1377 else
1378 sdhci_send_command(host, mrq->cmd);
1379 }
1380
1381 mmiowb();
1382 spin_unlock_irqrestore(&host->lock, flags);
1383 }
1384
1385 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1386 {
1387 u8 ctrl;
1388
1389 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1390 if (width == MMC_BUS_WIDTH_8) {
1391 ctrl &= ~SDHCI_CTRL_4BITBUS;
1392 if (host->version >= SDHCI_SPEC_300)
1393 ctrl |= SDHCI_CTRL_8BITBUS;
1394 } else {
1395 if (host->version >= SDHCI_SPEC_300)
1396 ctrl &= ~SDHCI_CTRL_8BITBUS;
1397 if (width == MMC_BUS_WIDTH_4)
1398 ctrl |= SDHCI_CTRL_4BITBUS;
1399 else
1400 ctrl &= ~SDHCI_CTRL_4BITBUS;
1401 }
1402 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1403 }
1404 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1405
1406 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1407 {
1408 u16 ctrl_2;
1409
1410 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1411 /* Select Bus Speed Mode for host */
1412 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1413 if ((timing == MMC_TIMING_MMC_HS200) ||
1414 (timing == MMC_TIMING_UHS_SDR104))
1415 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1416 else if (timing == MMC_TIMING_UHS_SDR12)
1417 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1418 else if (timing == MMC_TIMING_UHS_SDR25)
1419 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1420 else if (timing == MMC_TIMING_UHS_SDR50)
1421 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1422 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1423 (timing == MMC_TIMING_MMC_DDR52))
1424 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1425 else if (timing == MMC_TIMING_MMC_HS400)
1426 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1427 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1428 }
1429 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1430
1431 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1432 {
1433 unsigned long flags;
1434 u8 ctrl;
1435 struct mmc_host *mmc = host->mmc;
1436
1437 spin_lock_irqsave(&host->lock, flags);
1438
1439 if (host->flags & SDHCI_DEVICE_DEAD) {
1440 spin_unlock_irqrestore(&host->lock, flags);
1441 if (!IS_ERR(mmc->supply.vmmc) &&
1442 ios->power_mode == MMC_POWER_OFF)
1443 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1444 return;
1445 }
1446
1447 /*
1448 * Reset the chip on each power off.
1449 * Should clear out any weird states.
1450 */
1451 if (ios->power_mode == MMC_POWER_OFF) {
1452 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1453 sdhci_reinit(host);
1454 }
1455
1456 if (host->version >= SDHCI_SPEC_300 &&
1457 (ios->power_mode == MMC_POWER_UP) &&
1458 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1459 sdhci_enable_preset_value(host, false);
1460
1461 if (!ios->clock || ios->clock != host->clock) {
1462 host->ops->set_clock(host, ios->clock);
1463 host->clock = ios->clock;
1464
1465 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1466 host->clock) {
1467 host->timeout_clk = host->mmc->actual_clock ?
1468 host->mmc->actual_clock / 1000 :
1469 host->clock / 1000;
1470 host->mmc->max_busy_timeout =
1471 host->ops->get_max_timeout_count ?
1472 host->ops->get_max_timeout_count(host) :
1473 1 << 27;
1474 host->mmc->max_busy_timeout /= host->timeout_clk;
1475 }
1476 }
1477
1478 sdhci_set_power(host, ios->power_mode, ios->vdd);
1479
1480 if (host->ops->platform_send_init_74_clocks)
1481 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1482
1483 host->ops->set_bus_width(host, ios->bus_width);
1484
1485 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1486
1487 if ((ios->timing == MMC_TIMING_SD_HS ||
1488 ios->timing == MMC_TIMING_MMC_HS)
1489 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1490 ctrl |= SDHCI_CTRL_HISPD;
1491 else
1492 ctrl &= ~SDHCI_CTRL_HISPD;
1493
1494 if (host->version >= SDHCI_SPEC_300) {
1495 u16 clk, ctrl_2;
1496
1497 /* In case of UHS-I modes, set High Speed Enable */
1498 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1499 (ios->timing == MMC_TIMING_MMC_HS200) ||
1500 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1501 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1502 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1503 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1504 (ios->timing == MMC_TIMING_UHS_SDR25))
1505 ctrl |= SDHCI_CTRL_HISPD;
1506
1507 if (!host->preset_enabled) {
1508 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1509 /*
1510 * We only need to set Driver Strength if the
1511 * preset value enable is not set.
1512 */
1513 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1514 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1515 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1516 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1517 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1518 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1519
1520 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1521 } else {
1522 /*
1523 * According to SDHC Spec v3.00, if the Preset Value
1524 * Enable in the Host Control 2 register is set, we
1525 * need to reset SD Clock Enable before changing High
1526 * Speed Enable to avoid generating clock gliches.
1527 */
1528
1529 /* Reset SD Clock Enable */
1530 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1531 clk &= ~SDHCI_CLOCK_CARD_EN;
1532 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1533
1534 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1535
1536 /* Re-enable SD Clock */
1537 host->ops->set_clock(host, host->clock);
1538 }
1539
1540 /* Reset SD Clock Enable */
1541 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1542 clk &= ~SDHCI_CLOCK_CARD_EN;
1543 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1544
1545 host->ops->set_uhs_signaling(host, ios->timing);
1546 host->timing = ios->timing;
1547
1548 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1549 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1550 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1551 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1552 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1553 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1554 u16 preset;
1555
1556 sdhci_enable_preset_value(host, true);
1557 preset = sdhci_get_preset_value(host);
1558 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1559 >> SDHCI_PRESET_DRV_SHIFT;
1560 }
1561
1562 /* Re-enable SD Clock */
1563 host->ops->set_clock(host, host->clock);
1564 } else
1565 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1566
1567 /*
1568 * Some (ENE) controllers go apeshit on some ios operation,
1569 * signalling timeout and CRC errors even on CMD0. Resetting
1570 * it on each ios seems to solve the problem.
1571 */
1572 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1573 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1574
1575 mmiowb();
1576 spin_unlock_irqrestore(&host->lock, flags);
1577 }
1578
1579 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1580 {
1581 struct sdhci_host *host = mmc_priv(mmc);
1582
1583 sdhci_runtime_pm_get(host);
1584 sdhci_do_set_ios(host, ios);
1585 sdhci_runtime_pm_put(host);
1586 }
1587
1588 static int sdhci_do_get_cd(struct sdhci_host *host)
1589 {
1590 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1591
1592 if (host->flags & SDHCI_DEVICE_DEAD)
1593 return 0;
1594
1595 /* If polling/nonremovable, assume that the card is always present. */
1596 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1597 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1598 return 1;
1599
1600 /* Try slot gpio detect */
1601 if (!IS_ERR_VALUE(gpio_cd))
1602 return !!gpio_cd;
1603
1604 /* Host native card detect */
1605 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1606 }
1607
1608 static int sdhci_get_cd(struct mmc_host *mmc)
1609 {
1610 struct sdhci_host *host = mmc_priv(mmc);
1611 int ret;
1612
1613 sdhci_runtime_pm_get(host);
1614 ret = sdhci_do_get_cd(host);
1615 sdhci_runtime_pm_put(host);
1616 return ret;
1617 }
1618
1619 static int sdhci_check_ro(struct sdhci_host *host)
1620 {
1621 unsigned long flags;
1622 int is_readonly;
1623
1624 spin_lock_irqsave(&host->lock, flags);
1625
1626 if (host->flags & SDHCI_DEVICE_DEAD)
1627 is_readonly = 0;
1628 else if (host->ops->get_ro)
1629 is_readonly = host->ops->get_ro(host);
1630 else
1631 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1632 & SDHCI_WRITE_PROTECT);
1633
1634 spin_unlock_irqrestore(&host->lock, flags);
1635
1636 /* This quirk needs to be replaced by a callback-function later */
1637 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1638 !is_readonly : is_readonly;
1639 }
1640
1641 #define SAMPLE_COUNT 5
1642
1643 static int sdhci_do_get_ro(struct sdhci_host *host)
1644 {
1645 int i, ro_count;
1646
1647 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1648 return sdhci_check_ro(host);
1649
1650 ro_count = 0;
1651 for (i = 0; i < SAMPLE_COUNT; i++) {
1652 if (sdhci_check_ro(host)) {
1653 if (++ro_count > SAMPLE_COUNT / 2)
1654 return 1;
1655 }
1656 msleep(30);
1657 }
1658 return 0;
1659 }
1660
1661 static void sdhci_hw_reset(struct mmc_host *mmc)
1662 {
1663 struct sdhci_host *host = mmc_priv(mmc);
1664
1665 if (host->ops && host->ops->hw_reset)
1666 host->ops->hw_reset(host);
1667 }
1668
1669 static int sdhci_get_ro(struct mmc_host *mmc)
1670 {
1671 struct sdhci_host *host = mmc_priv(mmc);
1672 int ret;
1673
1674 sdhci_runtime_pm_get(host);
1675 ret = sdhci_do_get_ro(host);
1676 sdhci_runtime_pm_put(host);
1677 return ret;
1678 }
1679
1680 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1681 {
1682 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1683 if (enable)
1684 host->ier |= SDHCI_INT_CARD_INT;
1685 else
1686 host->ier &= ~SDHCI_INT_CARD_INT;
1687
1688 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1689 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1690 mmiowb();
1691 }
1692 }
1693
1694 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1695 {
1696 struct sdhci_host *host = mmc_priv(mmc);
1697 unsigned long flags;
1698
1699 sdhci_runtime_pm_get(host);
1700
1701 spin_lock_irqsave(&host->lock, flags);
1702 if (enable)
1703 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1704 else
1705 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1706
1707 sdhci_enable_sdio_irq_nolock(host, enable);
1708 spin_unlock_irqrestore(&host->lock, flags);
1709
1710 sdhci_runtime_pm_put(host);
1711 }
1712
1713 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1714 struct mmc_ios *ios)
1715 {
1716 struct mmc_host *mmc = host->mmc;
1717 u16 ctrl;
1718 int ret;
1719
1720 /*
1721 * Signal Voltage Switching is only applicable for Host Controllers
1722 * v3.00 and above.
1723 */
1724 if (host->version < SDHCI_SPEC_300)
1725 return 0;
1726
1727 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1728
1729 switch (ios->signal_voltage) {
1730 case MMC_SIGNAL_VOLTAGE_330:
1731 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1732 ctrl &= ~SDHCI_CTRL_VDD_180;
1733 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1734
1735 if (!IS_ERR(mmc->supply.vqmmc)) {
1736 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1737 3600000);
1738 if (ret) {
1739 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1740 mmc_hostname(mmc));
1741 return -EIO;
1742 }
1743 }
1744 /* Wait for 5ms */
1745 usleep_range(5000, 5500);
1746
1747 /* 3.3V regulator output should be stable within 5 ms */
1748 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1749 if (!(ctrl & SDHCI_CTRL_VDD_180))
1750 return 0;
1751
1752 pr_warn("%s: 3.3V regulator output did not became stable\n",
1753 mmc_hostname(mmc));
1754
1755 return -EAGAIN;
1756 case MMC_SIGNAL_VOLTAGE_180:
1757 if (!IS_ERR(mmc->supply.vqmmc)) {
1758 ret = regulator_set_voltage(mmc->supply.vqmmc,
1759 1700000, 1950000);
1760 if (ret) {
1761 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1762 mmc_hostname(mmc));
1763 return -EIO;
1764 }
1765 }
1766
1767 /*
1768 * Enable 1.8V Signal Enable in the Host Control2
1769 * register
1770 */
1771 ctrl |= SDHCI_CTRL_VDD_180;
1772 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1773
1774 /* Some controller need to do more when switching */
1775 if (host->ops->voltage_switch)
1776 host->ops->voltage_switch(host);
1777
1778 /* 1.8V regulator output should be stable within 5 ms */
1779 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1780 if (ctrl & SDHCI_CTRL_VDD_180)
1781 return 0;
1782
1783 pr_warn("%s: 1.8V regulator output did not became stable\n",
1784 mmc_hostname(mmc));
1785
1786 return -EAGAIN;
1787 case MMC_SIGNAL_VOLTAGE_120:
1788 if (!IS_ERR(mmc->supply.vqmmc)) {
1789 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1790 1300000);
1791 if (ret) {
1792 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1793 mmc_hostname(mmc));
1794 return -EIO;
1795 }
1796 }
1797 return 0;
1798 default:
1799 /* No signal voltage switch required */
1800 return 0;
1801 }
1802 }
1803
1804 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1805 struct mmc_ios *ios)
1806 {
1807 struct sdhci_host *host = mmc_priv(mmc);
1808 int err;
1809
1810 if (host->version < SDHCI_SPEC_300)
1811 return 0;
1812 sdhci_runtime_pm_get(host);
1813 err = sdhci_do_start_signal_voltage_switch(host, ios);
1814 sdhci_runtime_pm_put(host);
1815 return err;
1816 }
1817
1818 static int sdhci_card_busy(struct mmc_host *mmc)
1819 {
1820 struct sdhci_host *host = mmc_priv(mmc);
1821 u32 present_state;
1822
1823 sdhci_runtime_pm_get(host);
1824 /* Check whether DAT[3:0] is 0000 */
1825 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1826 sdhci_runtime_pm_put(host);
1827
1828 return !(present_state & SDHCI_DATA_LVL_MASK);
1829 }
1830
1831 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1832 {
1833 struct sdhci_host *host = mmc_priv(mmc);
1834 unsigned long flags;
1835
1836 spin_lock_irqsave(&host->lock, flags);
1837 host->flags |= SDHCI_HS400_TUNING;
1838 spin_unlock_irqrestore(&host->lock, flags);
1839
1840 return 0;
1841 }
1842
1843 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1844 {
1845 struct sdhci_host *host = mmc_priv(mmc);
1846 u16 ctrl;
1847 int tuning_loop_counter = MAX_TUNING_LOOP;
1848 int err = 0;
1849 unsigned long flags;
1850 unsigned int tuning_count = 0;
1851 bool hs400_tuning;
1852
1853 sdhci_runtime_pm_get(host);
1854 spin_lock_irqsave(&host->lock, flags);
1855
1856 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1857 host->flags &= ~SDHCI_HS400_TUNING;
1858
1859 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1860 tuning_count = host->tuning_count;
1861
1862 /*
1863 * The Host Controller needs tuning only in case of SDR104 mode
1864 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1865 * Capabilities register.
1866 * If the Host Controller supports the HS200 mode then the
1867 * tuning function has to be executed.
1868 */
1869 switch (host->timing) {
1870 /* HS400 tuning is done in HS200 mode */
1871 case MMC_TIMING_MMC_HS400:
1872 err = -EINVAL;
1873 goto out_unlock;
1874
1875 case MMC_TIMING_MMC_HS200:
1876 /*
1877 * Periodic re-tuning for HS400 is not expected to be needed, so
1878 * disable it here.
1879 */
1880 if (hs400_tuning)
1881 tuning_count = 0;
1882 break;
1883
1884 case MMC_TIMING_UHS_SDR104:
1885 break;
1886
1887 case MMC_TIMING_UHS_SDR50:
1888 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1889 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1890 break;
1891 /* FALLTHROUGH */
1892
1893 default:
1894 goto out_unlock;
1895 }
1896
1897 if (host->ops->platform_execute_tuning) {
1898 spin_unlock_irqrestore(&host->lock, flags);
1899 err = host->ops->platform_execute_tuning(host, opcode);
1900 sdhci_runtime_pm_put(host);
1901 return err;
1902 }
1903
1904 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1905 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1906 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1907 ctrl |= SDHCI_CTRL_TUNED_CLK;
1908 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1909
1910 /*
1911 * As per the Host Controller spec v3.00, tuning command
1912 * generates Buffer Read Ready interrupt, so enable that.
1913 *
1914 * Note: The spec clearly says that when tuning sequence
1915 * is being performed, the controller does not generate
1916 * interrupts other than Buffer Read Ready interrupt. But
1917 * to make sure we don't hit a controller bug, we _only_
1918 * enable Buffer Read Ready interrupt here.
1919 */
1920 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1921 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1922
1923 /*
1924 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1925 * of loops reaches 40 times or a timeout of 150ms occurs.
1926 */
1927 do {
1928 struct mmc_command cmd = {0};
1929 struct mmc_request mrq = {NULL};
1930
1931 cmd.opcode = opcode;
1932 cmd.arg = 0;
1933 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1934 cmd.retries = 0;
1935 cmd.data = NULL;
1936 cmd.error = 0;
1937
1938 if (tuning_loop_counter-- == 0)
1939 break;
1940
1941 mrq.cmd = &cmd;
1942 host->mrq = &mrq;
1943
1944 /*
1945 * In response to CMD19, the card sends 64 bytes of tuning
1946 * block to the Host Controller. So we set the block size
1947 * to 64 here.
1948 */
1949 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1950 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1951 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1952 SDHCI_BLOCK_SIZE);
1953 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1954 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1955 SDHCI_BLOCK_SIZE);
1956 } else {
1957 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1958 SDHCI_BLOCK_SIZE);
1959 }
1960
1961 /*
1962 * The tuning block is sent by the card to the host controller.
1963 * So we set the TRNS_READ bit in the Transfer Mode register.
1964 * This also takes care of setting DMA Enable and Multi Block
1965 * Select in the same register to 0.
1966 */
1967 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1968
1969 sdhci_send_command(host, &cmd);
1970
1971 host->cmd = NULL;
1972 host->mrq = NULL;
1973
1974 spin_unlock_irqrestore(&host->lock, flags);
1975 /* Wait for Buffer Read Ready interrupt */
1976 wait_event_interruptible_timeout(host->buf_ready_int,
1977 (host->tuning_done == 1),
1978 msecs_to_jiffies(50));
1979 spin_lock_irqsave(&host->lock, flags);
1980
1981 if (!host->tuning_done) {
1982 pr_info(DRIVER_NAME ": Timeout waiting for "
1983 "Buffer Read Ready interrupt during tuning "
1984 "procedure, falling back to fixed sampling "
1985 "clock\n");
1986 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1987 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1988 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1989 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1990
1991 err = -EIO;
1992 goto out;
1993 }
1994
1995 host->tuning_done = 0;
1996
1997 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1998
1999 /* eMMC spec does not require a delay between tuning cycles */
2000 if (opcode == MMC_SEND_TUNING_BLOCK)
2001 mdelay(1);
2002 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2003
2004 /*
2005 * The Host Driver has exhausted the maximum number of loops allowed,
2006 * so use fixed sampling frequency.
2007 */
2008 if (tuning_loop_counter < 0) {
2009 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2010 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2011 }
2012 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2013 pr_info(DRIVER_NAME ": Tuning procedure"
2014 " failed, falling back to fixed sampling"
2015 " clock\n");
2016 err = -EIO;
2017 }
2018
2019 out:
2020 if (tuning_count) {
2021 /*
2022 * In case tuning fails, host controllers which support
2023 * re-tuning can try tuning again at a later time, when the
2024 * re-tuning timer expires. So for these controllers, we
2025 * return 0. Since there might be other controllers who do not
2026 * have this capability, we return error for them.
2027 */
2028 err = 0;
2029 }
2030
2031 host->mmc->retune_period = err ? 0 : tuning_count;
2032
2033 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2034 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2035 out_unlock:
2036 spin_unlock_irqrestore(&host->lock, flags);
2037 sdhci_runtime_pm_put(host);
2038
2039 return err;
2040 }
2041
2042
2043 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2044 {
2045 /* Host Controller v3.00 defines preset value registers */
2046 if (host->version < SDHCI_SPEC_300)
2047 return;
2048
2049 /*
2050 * We only enable or disable Preset Value if they are not already
2051 * enabled or disabled respectively. Otherwise, we bail out.
2052 */
2053 if (host->preset_enabled != enable) {
2054 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2055
2056 if (enable)
2057 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2058 else
2059 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2060
2061 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2062
2063 if (enable)
2064 host->flags |= SDHCI_PV_ENABLED;
2065 else
2066 host->flags &= ~SDHCI_PV_ENABLED;
2067
2068 host->preset_enabled = enable;
2069 }
2070 }
2071
2072 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2073 int err)
2074 {
2075 struct sdhci_host *host = mmc_priv(mmc);
2076 struct mmc_data *data = mrq->data;
2077
2078 if (host->flags & SDHCI_REQ_USE_DMA) {
2079 if (data->host_cookie)
2080 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2081 data->flags & MMC_DATA_WRITE ?
2082 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2083 mrq->data->host_cookie = 0;
2084 }
2085 }
2086
2087 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
2088 struct mmc_data *data,
2089 struct sdhci_host_next *next)
2090 {
2091 int sg_count;
2092
2093 if (!next && data->host_cookie &&
2094 data->host_cookie != host->next_data.cookie) {
2095 pr_debug(DRIVER_NAME "[%s] invalid cookie: %d, next-cookie %d\n",
2096 __func__, data->host_cookie, host->next_data.cookie);
2097 data->host_cookie = 0;
2098 }
2099
2100 /* Check if next job is already prepared */
2101 if (next ||
2102 (!next && data->host_cookie != host->next_data.cookie)) {
2103 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg,
2104 data->sg_len,
2105 data->flags & MMC_DATA_WRITE ?
2106 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2107
2108 } else {
2109 sg_count = host->next_data.sg_count;
2110 host->next_data.sg_count = 0;
2111 }
2112
2113
2114 if (sg_count == 0)
2115 return -EINVAL;
2116
2117 if (next) {
2118 next->sg_count = sg_count;
2119 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
2120 } else
2121 host->sg_count = sg_count;
2122
2123 return sg_count;
2124 }
2125
2126 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2127 bool is_first_req)
2128 {
2129 struct sdhci_host *host = mmc_priv(mmc);
2130
2131 if (mrq->data->host_cookie) {
2132 mrq->data->host_cookie = 0;
2133 return;
2134 }
2135
2136 if (host->flags & SDHCI_REQ_USE_DMA)
2137 if (sdhci_pre_dma_transfer(host,
2138 mrq->data,
2139 &host->next_data) < 0)
2140 mrq->data->host_cookie = 0;
2141 }
2142
2143 static void sdhci_card_event(struct mmc_host *mmc)
2144 {
2145 struct sdhci_host *host = mmc_priv(mmc);
2146 unsigned long flags;
2147 int present;
2148
2149 /* First check if client has provided their own card event */
2150 if (host->ops->card_event)
2151 host->ops->card_event(host);
2152
2153 present = sdhci_do_get_cd(host);
2154
2155 spin_lock_irqsave(&host->lock, flags);
2156
2157 /* Check host->mrq first in case we are runtime suspended */
2158 if (host->mrq && !present) {
2159 pr_err("%s: Card removed during transfer!\n",
2160 mmc_hostname(host->mmc));
2161 pr_err("%s: Resetting controller.\n",
2162 mmc_hostname(host->mmc));
2163
2164 sdhci_do_reset(host, SDHCI_RESET_CMD);
2165 sdhci_do_reset(host, SDHCI_RESET_DATA);
2166
2167 host->mrq->cmd->error = -ENOMEDIUM;
2168 tasklet_schedule(&host->finish_tasklet);
2169 }
2170
2171 spin_unlock_irqrestore(&host->lock, flags);
2172 }
2173
2174 static const struct mmc_host_ops sdhci_ops = {
2175 .request = sdhci_request,
2176 .post_req = sdhci_post_req,
2177 .pre_req = sdhci_pre_req,
2178 .set_ios = sdhci_set_ios,
2179 .get_cd = sdhci_get_cd,
2180 .get_ro = sdhci_get_ro,
2181 .hw_reset = sdhci_hw_reset,
2182 .enable_sdio_irq = sdhci_enable_sdio_irq,
2183 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2184 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2185 .execute_tuning = sdhci_execute_tuning,
2186 .card_event = sdhci_card_event,
2187 .card_busy = sdhci_card_busy,
2188 };
2189
2190 /*****************************************************************************\
2191 * *
2192 * Tasklets *
2193 * *
2194 \*****************************************************************************/
2195
2196 static void sdhci_tasklet_finish(unsigned long param)
2197 {
2198 struct sdhci_host *host;
2199 unsigned long flags;
2200 struct mmc_request *mrq;
2201
2202 host = (struct sdhci_host*)param;
2203
2204 spin_lock_irqsave(&host->lock, flags);
2205
2206 /*
2207 * If this tasklet gets rescheduled while running, it will
2208 * be run again afterwards but without any active request.
2209 */
2210 if (!host->mrq) {
2211 spin_unlock_irqrestore(&host->lock, flags);
2212 return;
2213 }
2214
2215 del_timer(&host->timer);
2216
2217 mrq = host->mrq;
2218
2219 /*
2220 * The controller needs a reset of internal state machines
2221 * upon error conditions.
2222 */
2223 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2224 ((mrq->cmd && mrq->cmd->error) ||
2225 (mrq->sbc && mrq->sbc->error) ||
2226 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2227 (mrq->data->stop && mrq->data->stop->error))) ||
2228 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2229
2230 /* Some controllers need this kick or reset won't work here */
2231 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2232 /* This is to force an update */
2233 host->ops->set_clock(host, host->clock);
2234
2235 /* Spec says we should do both at the same time, but Ricoh
2236 controllers do not like that. */
2237 sdhci_do_reset(host, SDHCI_RESET_CMD);
2238 sdhci_do_reset(host, SDHCI_RESET_DATA);
2239 }
2240
2241 host->mrq = NULL;
2242 host->cmd = NULL;
2243 host->data = NULL;
2244
2245 #ifndef SDHCI_USE_LEDS_CLASS
2246 sdhci_deactivate_led(host);
2247 #endif
2248
2249 mmiowb();
2250 spin_unlock_irqrestore(&host->lock, flags);
2251
2252 mmc_request_done(host->mmc, mrq);
2253 sdhci_runtime_pm_put(host);
2254 }
2255
2256 static void sdhci_timeout_timer(unsigned long data)
2257 {
2258 struct sdhci_host *host;
2259 unsigned long flags;
2260
2261 host = (struct sdhci_host*)data;
2262
2263 spin_lock_irqsave(&host->lock, flags);
2264
2265 if (host->mrq) {
2266 pr_err("%s: Timeout waiting for hardware "
2267 "interrupt.\n", mmc_hostname(host->mmc));
2268 sdhci_dumpregs(host);
2269
2270 if (host->data) {
2271 host->data->error = -ETIMEDOUT;
2272 sdhci_finish_data(host);
2273 } else {
2274 if (host->cmd)
2275 host->cmd->error = -ETIMEDOUT;
2276 else
2277 host->mrq->cmd->error = -ETIMEDOUT;
2278
2279 tasklet_schedule(&host->finish_tasklet);
2280 }
2281 }
2282
2283 mmiowb();
2284 spin_unlock_irqrestore(&host->lock, flags);
2285 }
2286
2287 /*****************************************************************************\
2288 * *
2289 * Interrupt handling *
2290 * *
2291 \*****************************************************************************/
2292
2293 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2294 {
2295 BUG_ON(intmask == 0);
2296
2297 if (!host->cmd) {
2298 pr_err("%s: Got command interrupt 0x%08x even "
2299 "though no command operation was in progress.\n",
2300 mmc_hostname(host->mmc), (unsigned)intmask);
2301 sdhci_dumpregs(host);
2302 return;
2303 }
2304
2305 if (intmask & SDHCI_INT_TIMEOUT)
2306 host->cmd->error = -ETIMEDOUT;
2307 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2308 SDHCI_INT_INDEX))
2309 host->cmd->error = -EILSEQ;
2310
2311 if (host->cmd->error) {
2312 tasklet_schedule(&host->finish_tasklet);
2313 return;
2314 }
2315
2316 /*
2317 * The host can send and interrupt when the busy state has
2318 * ended, allowing us to wait without wasting CPU cycles.
2319 * Unfortunately this is overloaded on the "data complete"
2320 * interrupt, so we need to take some care when handling
2321 * it.
2322 *
2323 * Note: The 1.0 specification is a bit ambiguous about this
2324 * feature so there might be some problems with older
2325 * controllers.
2326 */
2327 if (host->cmd->flags & MMC_RSP_BUSY) {
2328 if (host->cmd->data)
2329 DBG("Cannot wait for busy signal when also "
2330 "doing a data transfer");
2331 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2332 && !host->busy_handle) {
2333 /* Mark that command complete before busy is ended */
2334 host->busy_handle = 1;
2335 return;
2336 }
2337
2338 /* The controller does not support the end-of-busy IRQ,
2339 * fall through and take the SDHCI_INT_RESPONSE */
2340 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2341 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2342 *mask &= ~SDHCI_INT_DATA_END;
2343 }
2344
2345 if (intmask & SDHCI_INT_RESPONSE)
2346 sdhci_finish_command(host);
2347 }
2348
2349 #ifdef CONFIG_MMC_DEBUG
2350 static void sdhci_adma_show_error(struct sdhci_host *host)
2351 {
2352 const char *name = mmc_hostname(host->mmc);
2353 void *desc = host->adma_table;
2354
2355 sdhci_dumpregs(host);
2356
2357 while (true) {
2358 struct sdhci_adma2_64_desc *dma_desc = desc;
2359
2360 if (host->flags & SDHCI_USE_64_BIT_DMA)
2361 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2362 name, desc, le32_to_cpu(dma_desc->addr_hi),
2363 le32_to_cpu(dma_desc->addr_lo),
2364 le16_to_cpu(dma_desc->len),
2365 le16_to_cpu(dma_desc->cmd));
2366 else
2367 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2368 name, desc, le32_to_cpu(dma_desc->addr_lo),
2369 le16_to_cpu(dma_desc->len),
2370 le16_to_cpu(dma_desc->cmd));
2371
2372 desc += host->desc_sz;
2373
2374 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2375 break;
2376 }
2377 }
2378 #else
2379 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2380 #endif
2381
2382 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2383 {
2384 u32 command;
2385 BUG_ON(intmask == 0);
2386
2387 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2388 if (intmask & SDHCI_INT_DATA_AVAIL) {
2389 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2390 if (command == MMC_SEND_TUNING_BLOCK ||
2391 command == MMC_SEND_TUNING_BLOCK_HS200) {
2392 host->tuning_done = 1;
2393 wake_up(&host->buf_ready_int);
2394 return;
2395 }
2396 }
2397
2398 if (!host->data) {
2399 /*
2400 * The "data complete" interrupt is also used to
2401 * indicate that a busy state has ended. See comment
2402 * above in sdhci_cmd_irq().
2403 */
2404 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2405 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2406 host->cmd->error = -ETIMEDOUT;
2407 tasklet_schedule(&host->finish_tasklet);
2408 return;
2409 }
2410 if (intmask & SDHCI_INT_DATA_END) {
2411 /*
2412 * Some cards handle busy-end interrupt
2413 * before the command completed, so make
2414 * sure we do things in the proper order.
2415 */
2416 if (host->busy_handle)
2417 sdhci_finish_command(host);
2418 else
2419 host->busy_handle = 1;
2420 return;
2421 }
2422 }
2423
2424 pr_err("%s: Got data interrupt 0x%08x even "
2425 "though no data operation was in progress.\n",
2426 mmc_hostname(host->mmc), (unsigned)intmask);
2427 sdhci_dumpregs(host);
2428
2429 return;
2430 }
2431
2432 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2433 host->data->error = -ETIMEDOUT;
2434 else if (intmask & SDHCI_INT_DATA_END_BIT)
2435 host->data->error = -EILSEQ;
2436 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2437 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2438 != MMC_BUS_TEST_R)
2439 host->data->error = -EILSEQ;
2440 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2441 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2442 sdhci_adma_show_error(host);
2443 host->data->error = -EIO;
2444 if (host->ops->adma_workaround)
2445 host->ops->adma_workaround(host, intmask);
2446 }
2447
2448 if (host->data->error)
2449 sdhci_finish_data(host);
2450 else {
2451 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2452 sdhci_transfer_pio(host);
2453
2454 /*
2455 * We currently don't do anything fancy with DMA
2456 * boundaries, but as we can't disable the feature
2457 * we need to at least restart the transfer.
2458 *
2459 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2460 * should return a valid address to continue from, but as
2461 * some controllers are faulty, don't trust them.
2462 */
2463 if (intmask & SDHCI_INT_DMA_END) {
2464 u32 dmastart, dmanow;
2465 dmastart = sg_dma_address(host->data->sg);
2466 dmanow = dmastart + host->data->bytes_xfered;
2467 /*
2468 * Force update to the next DMA block boundary.
2469 */
2470 dmanow = (dmanow &
2471 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2472 SDHCI_DEFAULT_BOUNDARY_SIZE;
2473 host->data->bytes_xfered = dmanow - dmastart;
2474 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2475 " next 0x%08x\n",
2476 mmc_hostname(host->mmc), dmastart,
2477 host->data->bytes_xfered, dmanow);
2478 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2479 }
2480
2481 if (intmask & SDHCI_INT_DATA_END) {
2482 if (host->cmd) {
2483 /*
2484 * Data managed to finish before the
2485 * command completed. Make sure we do
2486 * things in the proper order.
2487 */
2488 host->data_early = 1;
2489 } else {
2490 sdhci_finish_data(host);
2491 }
2492 }
2493 }
2494 }
2495
2496 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2497 {
2498 irqreturn_t result = IRQ_NONE;
2499 struct sdhci_host *host = dev_id;
2500 u32 intmask, mask, unexpected = 0;
2501 int max_loops = 16;
2502
2503 spin_lock(&host->lock);
2504
2505 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2506 spin_unlock(&host->lock);
2507 return IRQ_NONE;
2508 }
2509
2510 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2511 if (!intmask || intmask == 0xffffffff) {
2512 result = IRQ_NONE;
2513 goto out;
2514 }
2515
2516 do {
2517 /* Clear selected interrupts. */
2518 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2519 SDHCI_INT_BUS_POWER);
2520 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2521
2522 DBG("*** %s got interrupt: 0x%08x\n",
2523 mmc_hostname(host->mmc), intmask);
2524
2525 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2526 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2527 SDHCI_CARD_PRESENT;
2528
2529 /*
2530 * There is a observation on i.mx esdhc. INSERT
2531 * bit will be immediately set again when it gets
2532 * cleared, if a card is inserted. We have to mask
2533 * the irq to prevent interrupt storm which will
2534 * freeze the system. And the REMOVE gets the
2535 * same situation.
2536 *
2537 * More testing are needed here to ensure it works
2538 * for other platforms though.
2539 */
2540 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2541 SDHCI_INT_CARD_REMOVE);
2542 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2543 SDHCI_INT_CARD_INSERT;
2544 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2545 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2546
2547 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2548 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2549
2550 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2551 SDHCI_INT_CARD_REMOVE);
2552 result = IRQ_WAKE_THREAD;
2553 }
2554
2555 if (intmask & SDHCI_INT_CMD_MASK)
2556 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2557 &intmask);
2558
2559 if (intmask & SDHCI_INT_DATA_MASK)
2560 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2561
2562 if (intmask & SDHCI_INT_BUS_POWER)
2563 pr_err("%s: Card is consuming too much power!\n",
2564 mmc_hostname(host->mmc));
2565
2566 if (intmask & SDHCI_INT_CARD_INT) {
2567 sdhci_enable_sdio_irq_nolock(host, false);
2568 host->thread_isr |= SDHCI_INT_CARD_INT;
2569 result = IRQ_WAKE_THREAD;
2570 }
2571
2572 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2573 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2574 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2575 SDHCI_INT_CARD_INT);
2576
2577 if (intmask) {
2578 unexpected |= intmask;
2579 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2580 }
2581
2582 if (result == IRQ_NONE)
2583 result = IRQ_HANDLED;
2584
2585 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2586 } while (intmask && --max_loops);
2587 out:
2588 spin_unlock(&host->lock);
2589
2590 if (unexpected) {
2591 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2592 mmc_hostname(host->mmc), unexpected);
2593 sdhci_dumpregs(host);
2594 }
2595
2596 return result;
2597 }
2598
2599 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2600 {
2601 struct sdhci_host *host = dev_id;
2602 unsigned long flags;
2603 u32 isr;
2604
2605 spin_lock_irqsave(&host->lock, flags);
2606 isr = host->thread_isr;
2607 host->thread_isr = 0;
2608 spin_unlock_irqrestore(&host->lock, flags);
2609
2610 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2611 sdhci_card_event(host->mmc);
2612 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2613 }
2614
2615 if (isr & SDHCI_INT_CARD_INT) {
2616 sdio_run_irqs(host->mmc);
2617
2618 spin_lock_irqsave(&host->lock, flags);
2619 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2620 sdhci_enable_sdio_irq_nolock(host, true);
2621 spin_unlock_irqrestore(&host->lock, flags);
2622 }
2623
2624 return isr ? IRQ_HANDLED : IRQ_NONE;
2625 }
2626
2627 /*****************************************************************************\
2628 * *
2629 * Suspend/resume *
2630 * *
2631 \*****************************************************************************/
2632
2633 #ifdef CONFIG_PM
2634 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2635 {
2636 u8 val;
2637 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2638 | SDHCI_WAKE_ON_INT;
2639
2640 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2641 val |= mask ;
2642 /* Avoid fake wake up */
2643 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2644 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2645 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2646 }
2647 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2648
2649 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2650 {
2651 u8 val;
2652 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2653 | SDHCI_WAKE_ON_INT;
2654
2655 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2656 val &= ~mask;
2657 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2658 }
2659
2660 int sdhci_suspend_host(struct sdhci_host *host)
2661 {
2662 sdhci_disable_card_detection(host);
2663
2664 mmc_retune_timer_stop(host->mmc);
2665 mmc_retune_needed(host->mmc);
2666
2667 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2668 host->ier = 0;
2669 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2670 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2671 free_irq(host->irq, host);
2672 } else {
2673 sdhci_enable_irq_wakeups(host);
2674 enable_irq_wake(host->irq);
2675 }
2676 return 0;
2677 }
2678
2679 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2680
2681 int sdhci_resume_host(struct sdhci_host *host)
2682 {
2683 int ret = 0;
2684
2685 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2686 if (host->ops->enable_dma)
2687 host->ops->enable_dma(host);
2688 }
2689
2690 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2691 ret = request_threaded_irq(host->irq, sdhci_irq,
2692 sdhci_thread_irq, IRQF_SHARED,
2693 mmc_hostname(host->mmc), host);
2694 if (ret)
2695 return ret;
2696 } else {
2697 sdhci_disable_irq_wakeups(host);
2698 disable_irq_wake(host->irq);
2699 }
2700
2701 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2702 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2703 /* Card keeps power but host controller does not */
2704 sdhci_init(host, 0);
2705 host->pwr = 0;
2706 host->clock = 0;
2707 sdhci_do_set_ios(host, &host->mmc->ios);
2708 } else {
2709 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2710 mmiowb();
2711 }
2712
2713 sdhci_enable_card_detection(host);
2714
2715 return ret;
2716 }
2717
2718 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2719
2720 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2721 {
2722 return pm_runtime_get_sync(host->mmc->parent);
2723 }
2724
2725 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2726 {
2727 pm_runtime_mark_last_busy(host->mmc->parent);
2728 return pm_runtime_put_autosuspend(host->mmc->parent);
2729 }
2730
2731 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2732 {
2733 if (host->runtime_suspended || host->bus_on)
2734 return;
2735 host->bus_on = true;
2736 pm_runtime_get_noresume(host->mmc->parent);
2737 }
2738
2739 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2740 {
2741 if (host->runtime_suspended || !host->bus_on)
2742 return;
2743 host->bus_on = false;
2744 pm_runtime_put_noidle(host->mmc->parent);
2745 }
2746
2747 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2748 {
2749 unsigned long flags;
2750
2751 mmc_retune_timer_stop(host->mmc);
2752 mmc_retune_needed(host->mmc);
2753
2754 spin_lock_irqsave(&host->lock, flags);
2755 host->ier &= SDHCI_INT_CARD_INT;
2756 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2757 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2758 spin_unlock_irqrestore(&host->lock, flags);
2759
2760 synchronize_hardirq(host->irq);
2761
2762 spin_lock_irqsave(&host->lock, flags);
2763 host->runtime_suspended = true;
2764 spin_unlock_irqrestore(&host->lock, flags);
2765
2766 return 0;
2767 }
2768 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2769
2770 int sdhci_runtime_resume_host(struct sdhci_host *host)
2771 {
2772 unsigned long flags;
2773 int host_flags = host->flags;
2774
2775 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2776 if (host->ops->enable_dma)
2777 host->ops->enable_dma(host);
2778 }
2779
2780 sdhci_init(host, 0);
2781
2782 /* Force clock and power re-program */
2783 host->pwr = 0;
2784 host->clock = 0;
2785 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2786 sdhci_do_set_ios(host, &host->mmc->ios);
2787
2788 if ((host_flags & SDHCI_PV_ENABLED) &&
2789 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2790 spin_lock_irqsave(&host->lock, flags);
2791 sdhci_enable_preset_value(host, true);
2792 spin_unlock_irqrestore(&host->lock, flags);
2793 }
2794
2795 spin_lock_irqsave(&host->lock, flags);
2796
2797 host->runtime_suspended = false;
2798
2799 /* Enable SDIO IRQ */
2800 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2801 sdhci_enable_sdio_irq_nolock(host, true);
2802
2803 /* Enable Card Detection */
2804 sdhci_enable_card_detection(host);
2805
2806 spin_unlock_irqrestore(&host->lock, flags);
2807
2808 return 0;
2809 }
2810 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2811
2812 #endif /* CONFIG_PM */
2813
2814 /*****************************************************************************\
2815 * *
2816 * Device allocation/registration *
2817 * *
2818 \*****************************************************************************/
2819
2820 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2821 size_t priv_size)
2822 {
2823 struct mmc_host *mmc;
2824 struct sdhci_host *host;
2825
2826 WARN_ON(dev == NULL);
2827
2828 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2829 if (!mmc)
2830 return ERR_PTR(-ENOMEM);
2831
2832 host = mmc_priv(mmc);
2833 host->mmc = mmc;
2834
2835 return host;
2836 }
2837
2838 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2839
2840 int sdhci_add_host(struct sdhci_host *host)
2841 {
2842 struct mmc_host *mmc;
2843 u32 caps[2] = {0, 0};
2844 u32 max_current_caps;
2845 unsigned int ocr_avail;
2846 unsigned int override_timeout_clk;
2847 int ret;
2848
2849 WARN_ON(host == NULL);
2850 if (host == NULL)
2851 return -EINVAL;
2852
2853 mmc = host->mmc;
2854
2855 if (debug_quirks)
2856 host->quirks = debug_quirks;
2857 if (debug_quirks2)
2858 host->quirks2 = debug_quirks2;
2859
2860 override_timeout_clk = host->timeout_clk;
2861
2862 sdhci_do_reset(host, SDHCI_RESET_ALL);
2863
2864 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2865 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2866 >> SDHCI_SPEC_VER_SHIFT;
2867 if (host->version > SDHCI_SPEC_300) {
2868 pr_err("%s: Unknown controller version (%d). "
2869 "You may experience problems.\n", mmc_hostname(mmc),
2870 host->version);
2871 }
2872
2873 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2874 sdhci_readl(host, SDHCI_CAPABILITIES);
2875
2876 if (host->version >= SDHCI_SPEC_300)
2877 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2878 host->caps1 :
2879 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2880
2881 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2882 host->flags |= SDHCI_USE_SDMA;
2883 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2884 DBG("Controller doesn't have SDMA capability\n");
2885 else
2886 host->flags |= SDHCI_USE_SDMA;
2887
2888 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2889 (host->flags & SDHCI_USE_SDMA)) {
2890 DBG("Disabling DMA as it is marked broken\n");
2891 host->flags &= ~SDHCI_USE_SDMA;
2892 }
2893
2894 if ((host->version >= SDHCI_SPEC_200) &&
2895 (caps[0] & SDHCI_CAN_DO_ADMA2))
2896 host->flags |= SDHCI_USE_ADMA;
2897
2898 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2899 (host->flags & SDHCI_USE_ADMA)) {
2900 DBG("Disabling ADMA as it is marked broken\n");
2901 host->flags &= ~SDHCI_USE_ADMA;
2902 }
2903
2904 /*
2905 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2906 * and *must* do 64-bit DMA. A driver has the opportunity to change
2907 * that during the first call to ->enable_dma(). Similarly
2908 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2909 * implement.
2910 */
2911 if (sdhci_readl(host, SDHCI_CAPABILITIES) & SDHCI_CAN_64BIT)
2912 host->flags |= SDHCI_USE_64_BIT_DMA;
2913
2914 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2915 if (host->ops->enable_dma) {
2916 if (host->ops->enable_dma(host)) {
2917 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2918 mmc_hostname(mmc));
2919 host->flags &=
2920 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2921 }
2922 }
2923 }
2924
2925 /* SDMA does not support 64-bit DMA */
2926 if (host->flags & SDHCI_USE_64_BIT_DMA)
2927 host->flags &= ~SDHCI_USE_SDMA;
2928
2929 if (host->flags & SDHCI_USE_ADMA) {
2930 /*
2931 * The DMA descriptor table size is calculated as the maximum
2932 * number of segments times 2, to allow for an alignment
2933 * descriptor for each segment, plus 1 for a nop end descriptor,
2934 * all multipled by the descriptor size.
2935 */
2936 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2937 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2938 SDHCI_ADMA2_64_DESC_SZ;
2939 host->align_buffer_sz = SDHCI_MAX_SEGS *
2940 SDHCI_ADMA2_64_ALIGN;
2941 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2942 host->align_sz = SDHCI_ADMA2_64_ALIGN;
2943 host->align_mask = SDHCI_ADMA2_64_ALIGN - 1;
2944 } else {
2945 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2946 SDHCI_ADMA2_32_DESC_SZ;
2947 host->align_buffer_sz = SDHCI_MAX_SEGS *
2948 SDHCI_ADMA2_32_ALIGN;
2949 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2950 host->align_sz = SDHCI_ADMA2_32_ALIGN;
2951 host->align_mask = SDHCI_ADMA2_32_ALIGN - 1;
2952 }
2953 host->adma_table = dma_alloc_coherent(mmc_dev(mmc),
2954 host->adma_table_sz,
2955 &host->adma_addr,
2956 GFP_KERNEL);
2957 host->align_buffer = kmalloc(host->align_buffer_sz, GFP_KERNEL);
2958 if (!host->adma_table || !host->align_buffer) {
2959 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2960 host->adma_table, host->adma_addr);
2961 kfree(host->align_buffer);
2962 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2963 mmc_hostname(mmc));
2964 host->flags &= ~SDHCI_USE_ADMA;
2965 host->adma_table = NULL;
2966 host->align_buffer = NULL;
2967 } else if (host->adma_addr & host->align_mask) {
2968 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2969 mmc_hostname(mmc));
2970 host->flags &= ~SDHCI_USE_ADMA;
2971 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
2972 host->adma_table, host->adma_addr);
2973 kfree(host->align_buffer);
2974 host->adma_table = NULL;
2975 host->align_buffer = NULL;
2976 }
2977 }
2978
2979 /*
2980 * If we use DMA, then it's up to the caller to set the DMA
2981 * mask, but PIO does not need the hw shim so we set a new
2982 * mask here in that case.
2983 */
2984 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2985 host->dma_mask = DMA_BIT_MASK(64);
2986 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2987 }
2988
2989 if (host->version >= SDHCI_SPEC_300)
2990 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2991 >> SDHCI_CLOCK_BASE_SHIFT;
2992 else
2993 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2994 >> SDHCI_CLOCK_BASE_SHIFT;
2995
2996 host->max_clk *= 1000000;
2997 if (host->max_clk == 0 || host->quirks &
2998 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2999 if (!host->ops->get_max_clock) {
3000 pr_err("%s: Hardware doesn't specify base clock "
3001 "frequency.\n", mmc_hostname(mmc));
3002 return -ENODEV;
3003 }
3004 host->max_clk = host->ops->get_max_clock(host);
3005 }
3006
3007 host->next_data.cookie = 1;
3008 /*
3009 * In case of Host Controller v3.00, find out whether clock
3010 * multiplier is supported.
3011 */
3012 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3013 SDHCI_CLOCK_MUL_SHIFT;
3014
3015 /*
3016 * In case the value in Clock Multiplier is 0, then programmable
3017 * clock mode is not supported, otherwise the actual clock
3018 * multiplier is one more than the value of Clock Multiplier
3019 * in the Capabilities Register.
3020 */
3021 if (host->clk_mul)
3022 host->clk_mul += 1;
3023
3024 /*
3025 * Set host parameters.
3026 */
3027 mmc->ops = &sdhci_ops;
3028 mmc->f_max = host->max_clk;
3029 if (host->ops->get_min_clock)
3030 mmc->f_min = host->ops->get_min_clock(host);
3031 else if (host->version >= SDHCI_SPEC_300) {
3032 if (host->clk_mul) {
3033 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3034 mmc->f_max = host->max_clk * host->clk_mul;
3035 } else
3036 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3037 } else
3038 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3039
3040 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3041 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3042 SDHCI_TIMEOUT_CLK_SHIFT;
3043 if (host->timeout_clk == 0) {
3044 if (host->ops->get_timeout_clock) {
3045 host->timeout_clk =
3046 host->ops->get_timeout_clock(host);
3047 } else {
3048 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3049 mmc_hostname(mmc));
3050 return -ENODEV;
3051 }
3052 }
3053
3054 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3055 host->timeout_clk *= 1000;
3056
3057 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3058 host->ops->get_max_timeout_count(host) : 1 << 27;
3059 mmc->max_busy_timeout /= host->timeout_clk;
3060 }
3061
3062 if (override_timeout_clk)
3063 host->timeout_clk = override_timeout_clk;
3064
3065 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3066 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3067
3068 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3069 host->flags |= SDHCI_AUTO_CMD12;
3070
3071 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3072 if ((host->version >= SDHCI_SPEC_300) &&
3073 ((host->flags & SDHCI_USE_ADMA) ||
3074 !(host->flags & SDHCI_USE_SDMA)) &&
3075 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3076 host->flags |= SDHCI_AUTO_CMD23;
3077 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3078 } else {
3079 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3080 }
3081
3082 /*
3083 * A controller may support 8-bit width, but the board itself
3084 * might not have the pins brought out. Boards that support
3085 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3086 * their platform code before calling sdhci_add_host(), and we
3087 * won't assume 8-bit width for hosts without that CAP.
3088 */
3089 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3090 mmc->caps |= MMC_CAP_4_BIT_DATA;
3091
3092 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3093 mmc->caps &= ~MMC_CAP_CMD23;
3094
3095 if (caps[0] & SDHCI_CAN_DO_HISPD)
3096 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3097
3098 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3099 !(mmc->caps & MMC_CAP_NONREMOVABLE))
3100 mmc->caps |= MMC_CAP_NEEDS_POLL;
3101
3102 /* If there are external regulators, get them */
3103 if (mmc_regulator_get_supply(mmc) == -EPROBE_DEFER)
3104 return -EPROBE_DEFER;
3105
3106 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3107 if (!IS_ERR(mmc->supply.vqmmc)) {
3108 ret = regulator_enable(mmc->supply.vqmmc);
3109 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3110 1950000))
3111 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3112 SDHCI_SUPPORT_SDR50 |
3113 SDHCI_SUPPORT_DDR50);
3114 if (ret) {
3115 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3116 mmc_hostname(mmc), ret);
3117 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3118 }
3119 }
3120
3121 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3122 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3123 SDHCI_SUPPORT_DDR50);
3124
3125 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3126 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3127 SDHCI_SUPPORT_DDR50))
3128 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3129
3130 /* SDR104 supports also implies SDR50 support */
3131 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3132 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3133 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3134 * field can be promoted to support HS200.
3135 */
3136 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3137 mmc->caps2 |= MMC_CAP2_HS200;
3138 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3139 mmc->caps |= MMC_CAP_UHS_SDR50;
3140
3141 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3142 (caps[1] & SDHCI_SUPPORT_HS400))
3143 mmc->caps2 |= MMC_CAP2_HS400;
3144
3145 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3146 (IS_ERR(mmc->supply.vqmmc) ||
3147 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3148 1300000)))
3149 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3150
3151 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3152 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3153 mmc->caps |= MMC_CAP_UHS_DDR50;
3154
3155 /* Does the host need tuning for SDR50? */
3156 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3157 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3158
3159 /* Does the host need tuning for SDR104 / HS200? */
3160 if (mmc->caps2 & MMC_CAP2_HS200)
3161 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3162
3163 /* Driver Type(s) (A, C, D) supported by the host */
3164 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3165 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3166 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3167 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3168 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3169 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3170
3171 /* Initial value for re-tuning timer count */
3172 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3173 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3174
3175 /*
3176 * In case Re-tuning Timer is not disabled, the actual value of
3177 * re-tuning timer will be 2 ^ (n - 1).
3178 */
3179 if (host->tuning_count)
3180 host->tuning_count = 1 << (host->tuning_count - 1);
3181
3182 /* Re-tuning mode supported by the Host Controller */
3183 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3184 SDHCI_RETUNING_MODE_SHIFT;
3185
3186 ocr_avail = 0;
3187
3188 /*
3189 * According to SD Host Controller spec v3.00, if the Host System
3190 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3191 * the value is meaningful only if Voltage Support in the Capabilities
3192 * register is set. The actual current value is 4 times the register
3193 * value.
3194 */
3195 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3196 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3197 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3198 if (curr > 0) {
3199
3200 /* convert to SDHCI_MAX_CURRENT format */
3201 curr = curr/1000; /* convert to mA */
3202 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3203
3204 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3205 max_current_caps =
3206 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3207 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3208 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3209 }
3210 }
3211
3212 if (caps[0] & SDHCI_CAN_VDD_330) {
3213 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3214
3215 mmc->max_current_330 = ((max_current_caps &
3216 SDHCI_MAX_CURRENT_330_MASK) >>
3217 SDHCI_MAX_CURRENT_330_SHIFT) *
3218 SDHCI_MAX_CURRENT_MULTIPLIER;
3219 }
3220 if (caps[0] & SDHCI_CAN_VDD_300) {
3221 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3222
3223 mmc->max_current_300 = ((max_current_caps &
3224 SDHCI_MAX_CURRENT_300_MASK) >>
3225 SDHCI_MAX_CURRENT_300_SHIFT) *
3226 SDHCI_MAX_CURRENT_MULTIPLIER;
3227 }
3228 if (caps[0] & SDHCI_CAN_VDD_180) {
3229 ocr_avail |= MMC_VDD_165_195;
3230
3231 mmc->max_current_180 = ((max_current_caps &
3232 SDHCI_MAX_CURRENT_180_MASK) >>
3233 SDHCI_MAX_CURRENT_180_SHIFT) *
3234 SDHCI_MAX_CURRENT_MULTIPLIER;
3235 }
3236
3237 /* If OCR set by external regulators, use it instead */
3238 if (mmc->ocr_avail)
3239 ocr_avail = mmc->ocr_avail;
3240
3241 if (host->ocr_mask)
3242 ocr_avail &= host->ocr_mask;
3243
3244 mmc->ocr_avail = ocr_avail;
3245 mmc->ocr_avail_sdio = ocr_avail;
3246 if (host->ocr_avail_sdio)
3247 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3248 mmc->ocr_avail_sd = ocr_avail;
3249 if (host->ocr_avail_sd)
3250 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3251 else /* normal SD controllers don't support 1.8V */
3252 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3253 mmc->ocr_avail_mmc = ocr_avail;
3254 if (host->ocr_avail_mmc)
3255 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3256
3257 if (mmc->ocr_avail == 0) {
3258 pr_err("%s: Hardware doesn't report any "
3259 "support voltages.\n", mmc_hostname(mmc));
3260 return -ENODEV;
3261 }
3262
3263 spin_lock_init(&host->lock);
3264
3265 /*
3266 * Maximum number of segments. Depends on if the hardware
3267 * can do scatter/gather or not.
3268 */
3269 if (host->flags & SDHCI_USE_ADMA)
3270 mmc->max_segs = SDHCI_MAX_SEGS;
3271 else if (host->flags & SDHCI_USE_SDMA)
3272 mmc->max_segs = 1;
3273 else /* PIO */
3274 mmc->max_segs = SDHCI_MAX_SEGS;
3275
3276 /*
3277 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3278 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3279 * is less anyway.
3280 */
3281 mmc->max_req_size = 524288;
3282
3283 /*
3284 * Maximum segment size. Could be one segment with the maximum number
3285 * of bytes. When doing hardware scatter/gather, each entry cannot
3286 * be larger than 64 KiB though.
3287 */
3288 if (host->flags & SDHCI_USE_ADMA) {
3289 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3290 mmc->max_seg_size = 65535;
3291 else
3292 mmc->max_seg_size = 65536;
3293 } else {
3294 mmc->max_seg_size = mmc->max_req_size;
3295 }
3296
3297 /*
3298 * Maximum block size. This varies from controller to controller and
3299 * is specified in the capabilities register.
3300 */
3301 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3302 mmc->max_blk_size = 2;
3303 } else {
3304 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3305 SDHCI_MAX_BLOCK_SHIFT;
3306 if (mmc->max_blk_size >= 3) {
3307 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3308 mmc_hostname(mmc));
3309 mmc->max_blk_size = 0;
3310 }
3311 }
3312
3313 mmc->max_blk_size = 512 << mmc->max_blk_size;
3314
3315 /*
3316 * Maximum block count.
3317 */
3318 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3319
3320 /*
3321 * Init tasklets.
3322 */
3323 tasklet_init(&host->finish_tasklet,
3324 sdhci_tasklet_finish, (unsigned long)host);
3325
3326 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3327
3328 init_waitqueue_head(&host->buf_ready_int);
3329
3330 sdhci_init(host, 0);
3331
3332 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3333 IRQF_SHARED, mmc_hostname(mmc), host);
3334 if (ret) {
3335 pr_err("%s: Failed to request IRQ %d: %d\n",
3336 mmc_hostname(mmc), host->irq, ret);
3337 goto untasklet;
3338 }
3339
3340 #ifdef CONFIG_MMC_DEBUG
3341 sdhci_dumpregs(host);
3342 #endif
3343
3344 #ifdef SDHCI_USE_LEDS_CLASS
3345 snprintf(host->led_name, sizeof(host->led_name),
3346 "%s::", mmc_hostname(mmc));
3347 host->led.name = host->led_name;
3348 host->led.brightness = LED_OFF;
3349 host->led.default_trigger = mmc_hostname(mmc);
3350 host->led.brightness_set = sdhci_led_control;
3351
3352 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3353 if (ret) {
3354 pr_err("%s: Failed to register LED device: %d\n",
3355 mmc_hostname(mmc), ret);
3356 goto reset;
3357 }
3358 #endif
3359
3360 mmiowb();
3361
3362 mmc_add_host(mmc);
3363
3364 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3365 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3366 (host->flags & SDHCI_USE_ADMA) ?
3367 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3368 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3369
3370 sdhci_enable_card_detection(host);
3371
3372 return 0;
3373
3374 #ifdef SDHCI_USE_LEDS_CLASS
3375 reset:
3376 sdhci_do_reset(host, SDHCI_RESET_ALL);
3377 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3378 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3379 free_irq(host->irq, host);
3380 #endif
3381 untasklet:
3382 tasklet_kill(&host->finish_tasklet);
3383
3384 return ret;
3385 }
3386
3387 EXPORT_SYMBOL_GPL(sdhci_add_host);
3388
3389 void sdhci_remove_host(struct sdhci_host *host, int dead)
3390 {
3391 struct mmc_host *mmc = host->mmc;
3392 unsigned long flags;
3393
3394 if (dead) {
3395 spin_lock_irqsave(&host->lock, flags);
3396
3397 host->flags |= SDHCI_DEVICE_DEAD;
3398
3399 if (host->mrq) {
3400 pr_err("%s: Controller removed during "
3401 " transfer!\n", mmc_hostname(mmc));
3402
3403 host->mrq->cmd->error = -ENOMEDIUM;
3404 tasklet_schedule(&host->finish_tasklet);
3405 }
3406
3407 spin_unlock_irqrestore(&host->lock, flags);
3408 }
3409
3410 sdhci_disable_card_detection(host);
3411
3412 mmc_remove_host(mmc);
3413
3414 #ifdef SDHCI_USE_LEDS_CLASS
3415 led_classdev_unregister(&host->led);
3416 #endif
3417
3418 if (!dead)
3419 sdhci_do_reset(host, SDHCI_RESET_ALL);
3420
3421 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3422 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3423 free_irq(host->irq, host);
3424
3425 del_timer_sync(&host->timer);
3426
3427 tasklet_kill(&host->finish_tasklet);
3428
3429 if (!IS_ERR(mmc->supply.vqmmc))
3430 regulator_disable(mmc->supply.vqmmc);
3431
3432 if (host->adma_table)
3433 dma_free_coherent(mmc_dev(mmc), host->adma_table_sz,
3434 host->adma_table, host->adma_addr);
3435 kfree(host->align_buffer);
3436
3437 host->adma_table = NULL;
3438 host->align_buffer = NULL;
3439 }
3440
3441 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3442
3443 void sdhci_free_host(struct sdhci_host *host)
3444 {
3445 mmc_free_host(host->mmc);
3446 }
3447
3448 EXPORT_SYMBOL_GPL(sdhci_free_host);
3449
3450 /*****************************************************************************\
3451 * *
3452 * Driver init/exit *
3453 * *
3454 \*****************************************************************************/
3455
3456 static int __init sdhci_drv_init(void)
3457 {
3458 pr_info(DRIVER_NAME
3459 ": Secure Digital Host Controller Interface driver\n");
3460 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3461
3462 return 0;
3463 }
3464
3465 static void __exit sdhci_drv_exit(void)
3466 {
3467 }
3468
3469 module_init(sdhci_drv_init);
3470 module_exit(sdhci_drv_exit);
3471
3472 module_param(debug_quirks, uint, 0444);
3473 module_param(debug_quirks2, uint, 0444);
3474
3475 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3476 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3477 MODULE_LICENSE("GPL");
3478
3479 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3480 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
This page took 0.181662 seconds and 4 git commands to generate.