2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 static unsigned int debug_quirks
= 0;
35 static void sdhci_prepare_data(struct sdhci_host
*, struct mmc_data
*);
36 static void sdhci_finish_data(struct sdhci_host
*);
38 static void sdhci_send_command(struct sdhci_host
*, struct mmc_command
*);
39 static void sdhci_finish_command(struct sdhci_host
*);
41 static void sdhci_dumpregs(struct sdhci_host
*host
)
43 printk(KERN_DEBUG DRIVER_NAME
": ============== REGISTER DUMP ==============\n");
45 printk(KERN_DEBUG DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
46 readl(host
->ioaddr
+ SDHCI_DMA_ADDRESS
),
47 readw(host
->ioaddr
+ SDHCI_HOST_VERSION
));
48 printk(KERN_DEBUG DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
49 readw(host
->ioaddr
+ SDHCI_BLOCK_SIZE
),
50 readw(host
->ioaddr
+ SDHCI_BLOCK_COUNT
));
51 printk(KERN_DEBUG DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
52 readl(host
->ioaddr
+ SDHCI_ARGUMENT
),
53 readw(host
->ioaddr
+ SDHCI_TRANSFER_MODE
));
54 printk(KERN_DEBUG DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
55 readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
),
56 readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
));
57 printk(KERN_DEBUG DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
58 readb(host
->ioaddr
+ SDHCI_POWER_CONTROL
),
59 readb(host
->ioaddr
+ SDHCI_BLOCK_GAP_CONTROL
));
60 printk(KERN_DEBUG DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
61 readb(host
->ioaddr
+ SDHCI_WAKE_UP_CONTROL
),
62 readw(host
->ioaddr
+ SDHCI_CLOCK_CONTROL
));
63 printk(KERN_DEBUG DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
64 readb(host
->ioaddr
+ SDHCI_TIMEOUT_CONTROL
),
65 readl(host
->ioaddr
+ SDHCI_INT_STATUS
));
66 printk(KERN_DEBUG DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67 readl(host
->ioaddr
+ SDHCI_INT_ENABLE
),
68 readl(host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
));
69 printk(KERN_DEBUG DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70 readw(host
->ioaddr
+ SDHCI_ACMD12_ERR
),
71 readw(host
->ioaddr
+ SDHCI_SLOT_INT_STATUS
));
72 printk(KERN_DEBUG DRIVER_NAME
": Caps: 0x%08x | Max curr: 0x%08x\n",
73 readl(host
->ioaddr
+ SDHCI_CAPABILITIES
),
74 readl(host
->ioaddr
+ SDHCI_MAX_CURRENT
));
76 printk(KERN_DEBUG DRIVER_NAME
": ===========================================\n");
79 /*****************************************************************************\
81 * Low level functions *
83 \*****************************************************************************/
85 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
87 unsigned long timeout
;
89 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
90 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) &
95 writeb(mask
, host
->ioaddr
+ SDHCI_SOFTWARE_RESET
);
97 if (mask
& SDHCI_RESET_ALL
)
100 /* Wait max 100 ms */
103 /* hw clears the bit when it's done */
104 while (readb(host
->ioaddr
+ SDHCI_SOFTWARE_RESET
) & mask
) {
106 printk(KERN_ERR
"%s: Reset 0x%x never completed.\n",
107 mmc_hostname(host
->mmc
), (int)mask
);
108 sdhci_dumpregs(host
);
116 static void sdhci_init(struct sdhci_host
*host
)
120 sdhci_reset(host
, SDHCI_RESET_ALL
);
122 intmask
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
123 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
| SDHCI_INT_INDEX
|
124 SDHCI_INT_END_BIT
| SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
|
125 SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
|
126 SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
|
127 SDHCI_INT_DMA_END
| SDHCI_INT_DATA_END
| SDHCI_INT_RESPONSE
|
128 SDHCI_INT_ADMA_ERROR
;
130 writel(intmask
, host
->ioaddr
+ SDHCI_INT_ENABLE
);
131 writel(intmask
, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
134 static void sdhci_activate_led(struct sdhci_host
*host
)
138 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
139 ctrl
|= SDHCI_CTRL_LED
;
140 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
143 static void sdhci_deactivate_led(struct sdhci_host
*host
)
147 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
148 ctrl
&= ~SDHCI_CTRL_LED
;
149 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
152 #ifdef CONFIG_LEDS_CLASS
153 static void sdhci_led_control(struct led_classdev
*led
,
154 enum led_brightness brightness
)
156 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
159 spin_lock_irqsave(&host
->lock
, flags
);
161 if (brightness
== LED_OFF
)
162 sdhci_deactivate_led(host
);
164 sdhci_activate_led(host
);
166 spin_unlock_irqrestore(&host
->lock
, flags
);
170 /*****************************************************************************\
174 \*****************************************************************************/
176 static void sdhci_read_block_pio(struct sdhci_host
*host
)
179 size_t blksize
, len
, chunk
;
183 DBG("PIO reading\n");
185 blksize
= host
->data
->blksz
;
188 local_irq_save(flags
);
191 if (!sg_miter_next(&host
->sg_miter
))
194 len
= min(host
->sg_miter
.length
, blksize
);
197 host
->sg_miter
.consumed
= len
;
199 buf
= host
->sg_miter
.addr
;
203 scratch
= readl(host
->ioaddr
+ SDHCI_BUFFER
);
207 *buf
= scratch
& 0xFF;
216 sg_miter_stop(&host
->sg_miter
);
218 local_irq_restore(flags
);
221 static void sdhci_write_block_pio(struct sdhci_host
*host
)
224 size_t blksize
, len
, chunk
;
228 DBG("PIO writing\n");
230 blksize
= host
->data
->blksz
;
234 local_irq_save(flags
);
237 if (!sg_miter_next(&host
->sg_miter
))
240 len
= min(host
->sg_miter
.length
, blksize
);
243 host
->sg_miter
.consumed
= len
;
245 buf
= host
->sg_miter
.addr
;
248 scratch
|= (u32
)*buf
<< (chunk
* 8);
254 if ((chunk
== 4) || ((len
== 0) && (blksize
== 0))) {
255 writel(scratch
, host
->ioaddr
+ SDHCI_BUFFER
);
262 sg_miter_stop(&host
->sg_miter
);
264 local_irq_restore(flags
);
267 static void sdhci_transfer_pio(struct sdhci_host
*host
)
273 if (host
->blocks
== 0)
276 if (host
->data
->flags
& MMC_DATA_READ
)
277 mask
= SDHCI_DATA_AVAILABLE
;
279 mask
= SDHCI_SPACE_AVAILABLE
;
281 while (readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & mask
) {
282 if (host
->data
->flags
& MMC_DATA_READ
)
283 sdhci_read_block_pio(host
);
285 sdhci_write_block_pio(host
);
288 if (host
->blocks
== 0)
292 DBG("PIO transfer complete.\n");
295 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
297 local_irq_save(*flags
);
298 return kmap_atomic(sg_page(sg
), KM_BIO_SRC_IRQ
) + sg
->offset
;
301 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
303 kunmap_atomic(buffer
, KM_BIO_SRC_IRQ
);
304 local_irq_restore(*flags
);
307 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
308 struct mmc_data
*data
)
315 dma_addr_t align_addr
;
318 struct scatterlist
*sg
;
324 * The spec does not specify endianness of descriptor table.
325 * We currently guess that it is LE.
328 if (data
->flags
& MMC_DATA_READ
)
329 direction
= DMA_FROM_DEVICE
;
331 direction
= DMA_TO_DEVICE
;
334 * The ADMA descriptor table is mapped further down as we
335 * need to fill it with data first.
338 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
339 host
->align_buffer
, 128 * 4, direction
);
340 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
342 BUG_ON(host
->align_addr
& 0x3);
344 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
345 data
->sg
, data
->sg_len
, direction
);
346 if (host
->sg_count
== 0)
349 desc
= host
->adma_desc
;
350 align
= host
->align_buffer
;
352 align_addr
= host
->align_addr
;
354 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
355 addr
= sg_dma_address(sg
);
356 len
= sg_dma_len(sg
);
359 * The SDHCI specification states that ADMA
360 * addresses must be 32-bit aligned. If they
361 * aren't, then we use a bounce buffer for
362 * the (up to three) bytes that screw up the
365 offset
= (4 - (addr
& 0x3)) & 0x3;
367 if (data
->flags
& MMC_DATA_WRITE
) {
368 buffer
= sdhci_kmap_atomic(sg
, &flags
);
369 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
370 memcpy(align
, buffer
, offset
);
371 sdhci_kunmap_atomic(buffer
, &flags
);
374 desc
[7] = (align_addr
>> 24) & 0xff;
375 desc
[6] = (align_addr
>> 16) & 0xff;
376 desc
[5] = (align_addr
>> 8) & 0xff;
377 desc
[4] = (align_addr
>> 0) & 0xff;
379 BUG_ON(offset
> 65536);
381 desc
[3] = (offset
>> 8) & 0xff;
382 desc
[2] = (offset
>> 0) & 0xff;
385 desc
[0] = 0x21; /* tran, valid */
396 desc
[7] = (addr
>> 24) & 0xff;
397 desc
[6] = (addr
>> 16) & 0xff;
398 desc
[5] = (addr
>> 8) & 0xff;
399 desc
[4] = (addr
>> 0) & 0xff;
403 desc
[3] = (len
>> 8) & 0xff;
404 desc
[2] = (len
>> 0) & 0xff;
407 desc
[0] = 0x21; /* tran, valid */
412 * If this triggers then we have a calculation bug
415 WARN_ON((desc
- host
->adma_desc
) > (128 * 2 + 1) * 4);
419 * Add a terminating entry.
430 desc
[0] = 0x03; /* nop, end, valid */
433 * Resync align buffer as we might have changed it.
435 if (data
->flags
& MMC_DATA_WRITE
) {
436 dma_sync_single_for_device(mmc_dev(host
->mmc
),
437 host
->align_addr
, 128 * 4, direction
);
440 host
->adma_addr
= dma_map_single(mmc_dev(host
->mmc
),
441 host
->adma_desc
, (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
442 if (dma_mapping_error(mmc_dev(host
->mmc
), host
->align_addr
))
444 BUG_ON(host
->adma_addr
& 0x3);
449 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
450 data
->sg_len
, direction
);
452 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
458 static void sdhci_adma_table_post(struct sdhci_host
*host
,
459 struct mmc_data
*data
)
463 struct scatterlist
*sg
;
469 if (data
->flags
& MMC_DATA_READ
)
470 direction
= DMA_FROM_DEVICE
;
472 direction
= DMA_TO_DEVICE
;
474 dma_unmap_single(mmc_dev(host
->mmc
), host
->adma_addr
,
475 (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
477 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
480 if (data
->flags
& MMC_DATA_READ
) {
481 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
482 data
->sg_len
, direction
);
484 align
= host
->align_buffer
;
486 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
487 if (sg_dma_address(sg
) & 0x3) {
488 size
= 4 - (sg_dma_address(sg
) & 0x3);
490 buffer
= sdhci_kmap_atomic(sg
, &flags
);
491 WARN_ON(((long)buffer
& PAGE_MASK
) > (PAGE_SIZE
- 3));
492 memcpy(buffer
, align
, size
);
493 sdhci_kunmap_atomic(buffer
, &flags
);
500 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
501 data
->sg_len
, direction
);
504 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_data
*data
)
507 unsigned target_timeout
, current_timeout
;
510 * If the host controller provides us with an incorrect timeout
511 * value, just skip the check and use 0xE. The hardware may take
512 * longer to time out, but that's much better than having a too-short
515 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
))
519 target_timeout
= data
->timeout_ns
/ 1000 +
520 data
->timeout_clks
/ host
->clock
;
523 * Figure out needed cycles.
524 * We do this in steps in order to fit inside a 32 bit int.
525 * The first step is the minimum timeout, which will have a
526 * minimum resolution of 6 bits:
527 * (1) 2^13*1000 > 2^22,
528 * (2) host->timeout_clk < 2^16
533 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
534 while (current_timeout
< target_timeout
) {
536 current_timeout
<<= 1;
542 printk(KERN_WARNING
"%s: Too large timeout requested!\n",
543 mmc_hostname(host
->mmc
));
550 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_data
*data
)
562 BUG_ON(data
->blksz
* data
->blocks
> 524288);
563 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
564 BUG_ON(data
->blocks
> 65535);
567 host
->data_early
= 0;
569 count
= sdhci_calc_timeout(host
, data
);
570 writeb(count
, host
->ioaddr
+ SDHCI_TIMEOUT_CONTROL
);
572 if (host
->flags
& SDHCI_USE_DMA
)
573 host
->flags
|= SDHCI_REQ_USE_DMA
;
576 * FIXME: This doesn't account for merging when mapping the
579 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
581 struct scatterlist
*sg
;
584 if (host
->flags
& SDHCI_USE_ADMA
) {
585 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
588 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
592 if (unlikely(broken
)) {
593 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
594 if (sg
->length
& 0x3) {
595 DBG("Reverting to PIO because of "
596 "transfer size (%d)\n",
598 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
606 * The assumption here being that alignment is the same after
607 * translation to device address space.
609 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
611 struct scatterlist
*sg
;
614 if (host
->flags
& SDHCI_USE_ADMA
) {
616 * As we use 3 byte chunks to work around
617 * alignment problems, we need to check this
620 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
623 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
627 if (unlikely(broken
)) {
628 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
629 if (sg
->offset
& 0x3) {
630 DBG("Reverting to PIO because of "
632 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
639 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
640 if (host
->flags
& SDHCI_USE_ADMA
) {
641 ret
= sdhci_adma_table_pre(host
, data
);
644 * This only happens when someone fed
645 * us an invalid request.
648 host
->flags
&= ~SDHCI_USE_DMA
;
650 writel(host
->adma_addr
,
651 host
->ioaddr
+ SDHCI_ADMA_ADDRESS
);
656 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
657 data
->sg
, data
->sg_len
,
658 (data
->flags
& MMC_DATA_READ
) ?
663 * This only happens when someone fed
664 * us an invalid request.
667 host
->flags
&= ~SDHCI_USE_DMA
;
669 WARN_ON(sg_cnt
!= 1);
670 writel(sg_dma_address(data
->sg
),
671 host
->ioaddr
+ SDHCI_DMA_ADDRESS
);
677 * Always adjust the DMA selection as some controllers
678 * (e.g. JMicron) can't do PIO properly when the selection
681 if (host
->version
>= SDHCI_SPEC_200
) {
682 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
683 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
684 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
685 (host
->flags
& SDHCI_USE_ADMA
))
686 ctrl
|= SDHCI_CTRL_ADMA32
;
688 ctrl
|= SDHCI_CTRL_SDMA
;
689 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
692 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
693 sg_miter_start(&host
->sg_miter
,
694 data
->sg
, data
->sg_len
, SG_MITER_ATOMIC
);
695 host
->blocks
= data
->blocks
;
698 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
699 writew(SDHCI_MAKE_BLKSZ(7, data
->blksz
),
700 host
->ioaddr
+ SDHCI_BLOCK_SIZE
);
701 writew(data
->blocks
, host
->ioaddr
+ SDHCI_BLOCK_COUNT
);
704 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
705 struct mmc_data
*data
)
712 WARN_ON(!host
->data
);
714 mode
= SDHCI_TRNS_BLK_CNT_EN
;
715 if (data
->blocks
> 1)
716 mode
|= SDHCI_TRNS_MULTI
;
717 if (data
->flags
& MMC_DATA_READ
)
718 mode
|= SDHCI_TRNS_READ
;
719 if (host
->flags
& SDHCI_REQ_USE_DMA
)
720 mode
|= SDHCI_TRNS_DMA
;
722 writew(mode
, host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
725 static void sdhci_finish_data(struct sdhci_host
*host
)
727 struct mmc_data
*data
;
734 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
735 if (host
->flags
& SDHCI_USE_ADMA
)
736 sdhci_adma_table_post(host
, data
);
738 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
739 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
740 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
745 * The specification states that the block count register must
746 * be updated, but it does not specify at what point in the
747 * data flow. That makes the register entirely useless to read
748 * back so we have to assume that nothing made it to the card
749 * in the event of an error.
752 data
->bytes_xfered
= 0;
754 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
758 * The controller needs a reset of internal state machines
759 * upon error conditions.
762 sdhci_reset(host
, SDHCI_RESET_CMD
);
763 sdhci_reset(host
, SDHCI_RESET_DATA
);
766 sdhci_send_command(host
, data
->stop
);
768 tasklet_schedule(&host
->finish_tasklet
);
771 static void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
775 unsigned long timeout
;
782 mask
= SDHCI_CMD_INHIBIT
;
783 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
784 mask
|= SDHCI_DATA_INHIBIT
;
786 /* We shouldn't wait for data inihibit for stop commands, even
787 though they might use busy signaling */
788 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
789 mask
&= ~SDHCI_DATA_INHIBIT
;
791 while (readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & mask
) {
793 printk(KERN_ERR
"%s: Controller never released "
794 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
795 sdhci_dumpregs(host
);
797 tasklet_schedule(&host
->finish_tasklet
);
804 mod_timer(&host
->timer
, jiffies
+ 10 * HZ
);
808 sdhci_prepare_data(host
, cmd
->data
);
810 writel(cmd
->arg
, host
->ioaddr
+ SDHCI_ARGUMENT
);
812 sdhci_set_transfer_mode(host
, cmd
->data
);
814 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
815 printk(KERN_ERR
"%s: Unsupported response type!\n",
816 mmc_hostname(host
->mmc
));
817 cmd
->error
= -EINVAL
;
818 tasklet_schedule(&host
->finish_tasklet
);
822 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
823 flags
= SDHCI_CMD_RESP_NONE
;
824 else if (cmd
->flags
& MMC_RSP_136
)
825 flags
= SDHCI_CMD_RESP_LONG
;
826 else if (cmd
->flags
& MMC_RSP_BUSY
)
827 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
829 flags
= SDHCI_CMD_RESP_SHORT
;
831 if (cmd
->flags
& MMC_RSP_CRC
)
832 flags
|= SDHCI_CMD_CRC
;
833 if (cmd
->flags
& MMC_RSP_OPCODE
)
834 flags
|= SDHCI_CMD_INDEX
;
836 flags
|= SDHCI_CMD_DATA
;
838 writew(SDHCI_MAKE_CMD(cmd
->opcode
, flags
),
839 host
->ioaddr
+ SDHCI_COMMAND
);
842 static void sdhci_finish_command(struct sdhci_host
*host
)
846 BUG_ON(host
->cmd
== NULL
);
848 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
849 if (host
->cmd
->flags
& MMC_RSP_136
) {
850 /* CRC is stripped so we need to do some shifting. */
851 for (i
= 0;i
< 4;i
++) {
852 host
->cmd
->resp
[i
] = readl(host
->ioaddr
+
853 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
855 host
->cmd
->resp
[i
] |=
857 SDHCI_RESPONSE
+ (3-i
)*4-1);
860 host
->cmd
->resp
[0] = readl(host
->ioaddr
+ SDHCI_RESPONSE
);
864 host
->cmd
->error
= 0;
866 if (host
->data
&& host
->data_early
)
867 sdhci_finish_data(host
);
869 if (!host
->cmd
->data
)
870 tasklet_schedule(&host
->finish_tasklet
);
875 static void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
879 unsigned long timeout
;
881 if (clock
== host
->clock
)
884 writew(0, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
889 for (div
= 1;div
< 256;div
*= 2) {
890 if ((host
->max_clk
/ div
) <= clock
)
895 clk
= div
<< SDHCI_DIVIDER_SHIFT
;
896 clk
|= SDHCI_CLOCK_INT_EN
;
897 writew(clk
, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
901 while (!((clk
= readw(host
->ioaddr
+ SDHCI_CLOCK_CONTROL
))
902 & SDHCI_CLOCK_INT_STABLE
)) {
904 printk(KERN_ERR
"%s: Internal clock never "
905 "stabilised.\n", mmc_hostname(host
->mmc
));
906 sdhci_dumpregs(host
);
913 clk
|= SDHCI_CLOCK_CARD_EN
;
914 writew(clk
, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
920 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
924 if (host
->power
== power
)
927 if (power
== (unsigned short)-1) {
928 writeb(0, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
933 * Spec says that we should clear the power reg before setting
934 * a new value. Some controllers don't seem to like this though.
936 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
937 writeb(0, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
939 pwr
= SDHCI_POWER_ON
;
941 switch (1 << power
) {
942 case MMC_VDD_165_195
:
943 pwr
|= SDHCI_POWER_180
;
947 pwr
|= SDHCI_POWER_300
;
951 pwr
|= SDHCI_POWER_330
;
958 * At least the Marvell CaFe chip gets confused if we set the voltage
959 * and set turn on power at the same time, so set the voltage first.
961 if ((host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
))
962 writeb(pwr
& ~SDHCI_POWER_ON
,
963 host
->ioaddr
+ SDHCI_POWER_CONTROL
);
965 writeb(pwr
, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
971 /*****************************************************************************\
975 \*****************************************************************************/
977 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
979 struct sdhci_host
*host
;
982 host
= mmc_priv(mmc
);
984 spin_lock_irqsave(&host
->lock
, flags
);
986 WARN_ON(host
->mrq
!= NULL
);
988 #ifndef CONFIG_LEDS_CLASS
989 sdhci_activate_led(host
);
994 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)
995 || (host
->flags
& SDHCI_DEVICE_DEAD
)) {
996 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
997 tasklet_schedule(&host
->finish_tasklet
);
999 sdhci_send_command(host
, mrq
->cmd
);
1002 spin_unlock_irqrestore(&host
->lock
, flags
);
1005 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1007 struct sdhci_host
*host
;
1008 unsigned long flags
;
1011 host
= mmc_priv(mmc
);
1013 spin_lock_irqsave(&host
->lock
, flags
);
1015 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1019 * Reset the chip on each power off.
1020 * Should clear out any weird states.
1022 if (ios
->power_mode
== MMC_POWER_OFF
) {
1023 writel(0, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
1027 sdhci_set_clock(host
, ios
->clock
);
1029 if (ios
->power_mode
== MMC_POWER_OFF
)
1030 sdhci_set_power(host
, -1);
1032 sdhci_set_power(host
, ios
->vdd
);
1034 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
1036 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1037 ctrl
|= SDHCI_CTRL_4BITBUS
;
1039 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1041 if (ios
->timing
== MMC_TIMING_SD_HS
)
1042 ctrl
|= SDHCI_CTRL_HISPD
;
1044 ctrl
&= ~SDHCI_CTRL_HISPD
;
1046 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
1049 * Some (ENE) controllers go apeshit on some ios operation,
1050 * signalling timeout and CRC errors even on CMD0. Resetting
1051 * it on each ios seems to solve the problem.
1053 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1054 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1058 spin_unlock_irqrestore(&host
->lock
, flags
);
1061 static int sdhci_get_ro(struct mmc_host
*mmc
)
1063 struct sdhci_host
*host
;
1064 unsigned long flags
;
1067 host
= mmc_priv(mmc
);
1069 spin_lock_irqsave(&host
->lock
, flags
);
1071 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1074 present
= readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
);
1076 spin_unlock_irqrestore(&host
->lock
, flags
);
1078 return !(present
& SDHCI_WRITE_PROTECT
);
1081 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1083 struct sdhci_host
*host
;
1084 unsigned long flags
;
1087 host
= mmc_priv(mmc
);
1089 spin_lock_irqsave(&host
->lock
, flags
);
1091 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1094 ier
= readl(host
->ioaddr
+ SDHCI_INT_ENABLE
);
1096 ier
&= ~SDHCI_INT_CARD_INT
;
1098 ier
|= SDHCI_INT_CARD_INT
;
1100 writel(ier
, host
->ioaddr
+ SDHCI_INT_ENABLE
);
1101 writel(ier
, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
1106 spin_unlock_irqrestore(&host
->lock
, flags
);
1109 static const struct mmc_host_ops sdhci_ops
= {
1110 .request
= sdhci_request
,
1111 .set_ios
= sdhci_set_ios
,
1112 .get_ro
= sdhci_get_ro
,
1113 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
1116 /*****************************************************************************\
1120 \*****************************************************************************/
1122 static void sdhci_tasklet_card(unsigned long param
)
1124 struct sdhci_host
*host
;
1125 unsigned long flags
;
1127 host
= (struct sdhci_host
*)param
;
1129 spin_lock_irqsave(&host
->lock
, flags
);
1131 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)) {
1133 printk(KERN_ERR
"%s: Card removed during transfer!\n",
1134 mmc_hostname(host
->mmc
));
1135 printk(KERN_ERR
"%s: Resetting controller.\n",
1136 mmc_hostname(host
->mmc
));
1138 sdhci_reset(host
, SDHCI_RESET_CMD
);
1139 sdhci_reset(host
, SDHCI_RESET_DATA
);
1141 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1142 tasklet_schedule(&host
->finish_tasklet
);
1146 spin_unlock_irqrestore(&host
->lock
, flags
);
1148 mmc_detect_change(host
->mmc
, msecs_to_jiffies(500));
1151 static void sdhci_tasklet_finish(unsigned long param
)
1153 struct sdhci_host
*host
;
1154 unsigned long flags
;
1155 struct mmc_request
*mrq
;
1157 host
= (struct sdhci_host
*)param
;
1159 spin_lock_irqsave(&host
->lock
, flags
);
1161 del_timer(&host
->timer
);
1166 * The controller needs a reset of internal state machines
1167 * upon error conditions.
1169 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
1171 (mrq
->data
&& (mrq
->data
->error
||
1172 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
1173 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
1175 /* Some controllers need this kick or reset won't work here */
1176 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
) {
1179 /* This is to force an update */
1180 clock
= host
->clock
;
1182 sdhci_set_clock(host
, clock
);
1185 /* Spec says we should do both at the same time, but Ricoh
1186 controllers do not like that. */
1187 sdhci_reset(host
, SDHCI_RESET_CMD
);
1188 sdhci_reset(host
, SDHCI_RESET_DATA
);
1195 #ifndef CONFIG_LEDS_CLASS
1196 sdhci_deactivate_led(host
);
1200 spin_unlock_irqrestore(&host
->lock
, flags
);
1202 mmc_request_done(host
->mmc
, mrq
);
1205 static void sdhci_timeout_timer(unsigned long data
)
1207 struct sdhci_host
*host
;
1208 unsigned long flags
;
1210 host
= (struct sdhci_host
*)data
;
1212 spin_lock_irqsave(&host
->lock
, flags
);
1215 printk(KERN_ERR
"%s: Timeout waiting for hardware "
1216 "interrupt.\n", mmc_hostname(host
->mmc
));
1217 sdhci_dumpregs(host
);
1220 host
->data
->error
= -ETIMEDOUT
;
1221 sdhci_finish_data(host
);
1224 host
->cmd
->error
= -ETIMEDOUT
;
1226 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
1228 tasklet_schedule(&host
->finish_tasklet
);
1233 spin_unlock_irqrestore(&host
->lock
, flags
);
1236 /*****************************************************************************\
1238 * Interrupt handling *
1240 \*****************************************************************************/
1242 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
1244 BUG_ON(intmask
== 0);
1247 printk(KERN_ERR
"%s: Got command interrupt 0x%08x even "
1248 "though no command operation was in progress.\n",
1249 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1250 sdhci_dumpregs(host
);
1254 if (intmask
& SDHCI_INT_TIMEOUT
)
1255 host
->cmd
->error
= -ETIMEDOUT
;
1256 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
1258 host
->cmd
->error
= -EILSEQ
;
1260 if (host
->cmd
->error
)
1261 tasklet_schedule(&host
->finish_tasklet
);
1262 else if (intmask
& SDHCI_INT_RESPONSE
)
1263 sdhci_finish_command(host
);
1266 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
1268 BUG_ON(intmask
== 0);
1272 * A data end interrupt is sent together with the response
1273 * for the stop command.
1275 if (intmask
& SDHCI_INT_DATA_END
)
1278 printk(KERN_ERR
"%s: Got data interrupt 0x%08x even "
1279 "though no data operation was in progress.\n",
1280 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1281 sdhci_dumpregs(host
);
1286 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
1287 host
->data
->error
= -ETIMEDOUT
;
1288 else if (intmask
& (SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_END_BIT
))
1289 host
->data
->error
= -EILSEQ
;
1290 else if (intmask
& SDHCI_INT_ADMA_ERROR
)
1291 host
->data
->error
= -EIO
;
1293 if (host
->data
->error
)
1294 sdhci_finish_data(host
);
1296 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
1297 sdhci_transfer_pio(host
);
1300 * We currently don't do anything fancy with DMA
1301 * boundaries, but as we can't disable the feature
1302 * we need to at least restart the transfer.
1304 if (intmask
& SDHCI_INT_DMA_END
)
1305 writel(readl(host
->ioaddr
+ SDHCI_DMA_ADDRESS
),
1306 host
->ioaddr
+ SDHCI_DMA_ADDRESS
);
1308 if (intmask
& SDHCI_INT_DATA_END
) {
1311 * Data managed to finish before the
1312 * command completed. Make sure we do
1313 * things in the proper order.
1315 host
->data_early
= 1;
1317 sdhci_finish_data(host
);
1323 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
1326 struct sdhci_host
* host
= dev_id
;
1330 spin_lock(&host
->lock
);
1332 intmask
= readl(host
->ioaddr
+ SDHCI_INT_STATUS
);
1334 if (!intmask
|| intmask
== 0xffffffff) {
1339 DBG("*** %s got interrupt: 0x%08x\n",
1340 mmc_hostname(host
->mmc
), intmask
);
1342 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
1343 writel(intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
),
1344 host
->ioaddr
+ SDHCI_INT_STATUS
);
1345 tasklet_schedule(&host
->card_tasklet
);
1348 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
1350 if (intmask
& SDHCI_INT_CMD_MASK
) {
1351 writel(intmask
& SDHCI_INT_CMD_MASK
,
1352 host
->ioaddr
+ SDHCI_INT_STATUS
);
1353 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
1356 if (intmask
& SDHCI_INT_DATA_MASK
) {
1357 writel(intmask
& SDHCI_INT_DATA_MASK
,
1358 host
->ioaddr
+ SDHCI_INT_STATUS
);
1359 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
1362 intmask
&= ~(SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
);
1364 intmask
&= ~SDHCI_INT_ERROR
;
1366 if (intmask
& SDHCI_INT_BUS_POWER
) {
1367 printk(KERN_ERR
"%s: Card is consuming too much power!\n",
1368 mmc_hostname(host
->mmc
));
1369 writel(SDHCI_INT_BUS_POWER
, host
->ioaddr
+ SDHCI_INT_STATUS
);
1372 intmask
&= ~SDHCI_INT_BUS_POWER
;
1374 if (intmask
& SDHCI_INT_CARD_INT
)
1377 intmask
&= ~SDHCI_INT_CARD_INT
;
1380 printk(KERN_ERR
"%s: Unexpected interrupt 0x%08x.\n",
1381 mmc_hostname(host
->mmc
), intmask
);
1382 sdhci_dumpregs(host
);
1384 writel(intmask
, host
->ioaddr
+ SDHCI_INT_STATUS
);
1387 result
= IRQ_HANDLED
;
1391 spin_unlock(&host
->lock
);
1394 * We have to delay this as it calls back into the driver.
1397 mmc_signal_sdio_irq(host
->mmc
);
1402 /*****************************************************************************\
1406 \*****************************************************************************/
1410 int sdhci_suspend_host(struct sdhci_host
*host
, pm_message_t state
)
1414 ret
= mmc_suspend_host(host
->mmc
, state
);
1418 free_irq(host
->irq
, host
);
1423 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
1425 int sdhci_resume_host(struct sdhci_host
*host
)
1429 if (host
->flags
& SDHCI_USE_DMA
) {
1430 if (host
->ops
->enable_dma
)
1431 host
->ops
->enable_dma(host
);
1434 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
1435 mmc_hostname(host
->mmc
), host
);
1442 ret
= mmc_resume_host(host
->mmc
);
1449 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
1451 #endif /* CONFIG_PM */
1453 /*****************************************************************************\
1455 * Device allocation/registration *
1457 \*****************************************************************************/
1459 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
1462 struct mmc_host
*mmc
;
1463 struct sdhci_host
*host
;
1465 WARN_ON(dev
== NULL
);
1467 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
1469 return ERR_PTR(-ENOMEM
);
1471 host
= mmc_priv(mmc
);
1477 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
1479 int sdhci_add_host(struct sdhci_host
*host
)
1481 struct mmc_host
*mmc
;
1485 WARN_ON(host
== NULL
);
1492 host
->quirks
= debug_quirks
;
1494 sdhci_reset(host
, SDHCI_RESET_ALL
);
1496 host
->version
= readw(host
->ioaddr
+ SDHCI_HOST_VERSION
);
1497 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
1498 >> SDHCI_SPEC_VER_SHIFT
;
1499 if (host
->version
> SDHCI_SPEC_200
) {
1500 printk(KERN_ERR
"%s: Unknown controller version (%d). "
1501 "You may experience problems.\n", mmc_hostname(mmc
),
1505 caps
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES
);
1507 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
1508 host
->flags
|= SDHCI_USE_DMA
;
1509 else if (!(caps
& SDHCI_CAN_DO_DMA
))
1510 DBG("Controller doesn't have DMA capability\n");
1512 host
->flags
|= SDHCI_USE_DMA
;
1514 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
1515 (host
->flags
& SDHCI_USE_DMA
)) {
1516 DBG("Disabling DMA as it is marked broken\n");
1517 host
->flags
&= ~SDHCI_USE_DMA
;
1520 if (host
->flags
& SDHCI_USE_DMA
) {
1521 if ((host
->version
>= SDHCI_SPEC_200
) &&
1522 (caps
& SDHCI_CAN_DO_ADMA2
))
1523 host
->flags
|= SDHCI_USE_ADMA
;
1526 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
1527 (host
->flags
& SDHCI_USE_ADMA
)) {
1528 DBG("Disabling ADMA as it is marked broken\n");
1529 host
->flags
&= ~SDHCI_USE_ADMA
;
1532 if (host
->flags
& SDHCI_USE_DMA
) {
1533 if (host
->ops
->enable_dma
) {
1534 if (host
->ops
->enable_dma(host
)) {
1535 printk(KERN_WARNING
"%s: No suitable DMA "
1536 "available. Falling back to PIO.\n",
1538 host
->flags
&= ~(SDHCI_USE_DMA
| SDHCI_USE_ADMA
);
1543 if (host
->flags
& SDHCI_USE_ADMA
) {
1545 * We need to allocate descriptors for all sg entries
1546 * (128) and potentially one alignment transfer for
1547 * each of those entries.
1549 host
->adma_desc
= kmalloc((128 * 2 + 1) * 4, GFP_KERNEL
);
1550 host
->align_buffer
= kmalloc(128 * 4, GFP_KERNEL
);
1551 if (!host
->adma_desc
|| !host
->align_buffer
) {
1552 kfree(host
->adma_desc
);
1553 kfree(host
->align_buffer
);
1554 printk(KERN_WARNING
"%s: Unable to allocate ADMA "
1555 "buffers. Falling back to standard DMA.\n",
1557 host
->flags
&= ~SDHCI_USE_ADMA
;
1562 * If we use DMA, then it's up to the caller to set the DMA
1563 * mask, but PIO does not need the hw shim so we set a new
1564 * mask here in that case.
1566 if (!(host
->flags
& SDHCI_USE_DMA
)) {
1567 host
->dma_mask
= DMA_BIT_MASK(64);
1568 mmc_dev(host
->mmc
)->dma_mask
= &host
->dma_mask
;
1572 (caps
& SDHCI_CLOCK_BASE_MASK
) >> SDHCI_CLOCK_BASE_SHIFT
;
1573 if (host
->max_clk
== 0) {
1574 printk(KERN_ERR
"%s: Hardware doesn't specify base clock "
1575 "frequency.\n", mmc_hostname(mmc
));
1578 host
->max_clk
*= 1000000;
1581 (caps
& SDHCI_TIMEOUT_CLK_MASK
) >> SDHCI_TIMEOUT_CLK_SHIFT
;
1582 if (host
->timeout_clk
== 0) {
1583 printk(KERN_ERR
"%s: Hardware doesn't specify timeout clock "
1584 "frequency.\n", mmc_hostname(mmc
));
1587 if (caps
& SDHCI_TIMEOUT_CLK_UNIT
)
1588 host
->timeout_clk
*= 1000;
1591 * Set host parameters.
1593 mmc
->ops
= &sdhci_ops
;
1594 mmc
->f_min
= host
->max_clk
/ 256;
1595 mmc
->f_max
= host
->max_clk
;
1596 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SDIO_IRQ
;
1598 if (caps
& SDHCI_CAN_DO_HISPD
)
1599 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
;
1602 if (caps
& SDHCI_CAN_VDD_330
)
1603 mmc
->ocr_avail
|= MMC_VDD_32_33
|MMC_VDD_33_34
;
1604 if (caps
& SDHCI_CAN_VDD_300
)
1605 mmc
->ocr_avail
|= MMC_VDD_29_30
|MMC_VDD_30_31
;
1606 if (caps
& SDHCI_CAN_VDD_180
)
1607 mmc
->ocr_avail
|= MMC_VDD_165_195
;
1609 if (mmc
->ocr_avail
== 0) {
1610 printk(KERN_ERR
"%s: Hardware doesn't report any "
1611 "support voltages.\n", mmc_hostname(mmc
));
1615 spin_lock_init(&host
->lock
);
1618 * Maximum number of segments. Depends on if the hardware
1619 * can do scatter/gather or not.
1621 if (host
->flags
& SDHCI_USE_ADMA
)
1622 mmc
->max_hw_segs
= 128;
1623 else if (host
->flags
& SDHCI_USE_DMA
)
1624 mmc
->max_hw_segs
= 1;
1626 mmc
->max_hw_segs
= 128;
1627 mmc
->max_phys_segs
= 128;
1630 * Maximum number of sectors in one transfer. Limited by DMA boundary
1633 mmc
->max_req_size
= 524288;
1636 * Maximum segment size. Could be one segment with the maximum number
1637 * of bytes. When doing hardware scatter/gather, each entry cannot
1638 * be larger than 64 KiB though.
1640 if (host
->flags
& SDHCI_USE_ADMA
)
1641 mmc
->max_seg_size
= 65536;
1643 mmc
->max_seg_size
= mmc
->max_req_size
;
1646 * Maximum block size. This varies from controller to controller and
1647 * is specified in the capabilities register.
1649 mmc
->max_blk_size
= (caps
& SDHCI_MAX_BLOCK_MASK
) >> SDHCI_MAX_BLOCK_SHIFT
;
1650 if (mmc
->max_blk_size
>= 3) {
1651 printk(KERN_WARNING
"%s: Invalid maximum block size, "
1652 "assuming 512 bytes\n", mmc_hostname(mmc
));
1653 mmc
->max_blk_size
= 512;
1655 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
1658 * Maximum block count.
1660 mmc
->max_blk_count
= 65535;
1665 tasklet_init(&host
->card_tasklet
,
1666 sdhci_tasklet_card
, (unsigned long)host
);
1667 tasklet_init(&host
->finish_tasklet
,
1668 sdhci_tasklet_finish
, (unsigned long)host
);
1670 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
1672 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
1673 mmc_hostname(mmc
), host
);
1679 #ifdef CONFIG_MMC_DEBUG
1680 sdhci_dumpregs(host
);
1683 #ifdef CONFIG_LEDS_CLASS
1684 host
->led
.name
= mmc_hostname(mmc
);
1685 host
->led
.brightness
= LED_OFF
;
1686 host
->led
.default_trigger
= mmc_hostname(mmc
);
1687 host
->led
.brightness_set
= sdhci_led_control
;
1689 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
1698 printk(KERN_INFO
"%s: SDHCI controller on %s [%s] using %s%s\n",
1699 mmc_hostname(mmc
), host
->hw_name
, mmc_dev(mmc
)->bus_id
,
1700 (host
->flags
& SDHCI_USE_ADMA
)?"A":"",
1701 (host
->flags
& SDHCI_USE_DMA
)?"DMA":"PIO");
1705 #ifdef CONFIG_LEDS_CLASS
1707 sdhci_reset(host
, SDHCI_RESET_ALL
);
1708 free_irq(host
->irq
, host
);
1711 tasklet_kill(&host
->card_tasklet
);
1712 tasklet_kill(&host
->finish_tasklet
);
1717 EXPORT_SYMBOL_GPL(sdhci_add_host
);
1719 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
1721 unsigned long flags
;
1724 spin_lock_irqsave(&host
->lock
, flags
);
1726 host
->flags
|= SDHCI_DEVICE_DEAD
;
1729 printk(KERN_ERR
"%s: Controller removed during "
1730 " transfer!\n", mmc_hostname(host
->mmc
));
1732 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1733 tasklet_schedule(&host
->finish_tasklet
);
1736 spin_unlock_irqrestore(&host
->lock
, flags
);
1739 mmc_remove_host(host
->mmc
);
1741 #ifdef CONFIG_LEDS_CLASS
1742 led_classdev_unregister(&host
->led
);
1746 sdhci_reset(host
, SDHCI_RESET_ALL
);
1748 free_irq(host
->irq
, host
);
1750 del_timer_sync(&host
->timer
);
1752 tasklet_kill(&host
->card_tasklet
);
1753 tasklet_kill(&host
->finish_tasklet
);
1755 kfree(host
->adma_desc
);
1756 kfree(host
->align_buffer
);
1758 host
->adma_desc
= NULL
;
1759 host
->align_buffer
= NULL
;
1762 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
1764 void sdhci_free_host(struct sdhci_host
*host
)
1766 mmc_free_host(host
->mmc
);
1769 EXPORT_SYMBOL_GPL(sdhci_free_host
);
1771 /*****************************************************************************\
1773 * Driver init/exit *
1775 \*****************************************************************************/
1777 static int __init
sdhci_drv_init(void)
1779 printk(KERN_INFO DRIVER_NAME
1780 ": Secure Digital Host Controller Interface driver\n");
1781 printk(KERN_INFO DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
1786 static void __exit
sdhci_drv_exit(void)
1790 module_init(sdhci_drv_init
);
1791 module_exit(sdhci_drv_exit
);
1793 module_param(debug_quirks
, uint
, 0444);
1795 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1796 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1797 MODULE_LICENSE("GPL");
1799 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");