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sdhci: allow led to be controlled freely
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/pci.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
21
22 #include <linux/leds.h>
23
24 #include <linux/mmc/host.h>
25
26 #include "sdhci.h"
27
28 #define DRIVER_NAME "sdhci"
29
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
32
33 static unsigned int debug_quirks = 0;
34
35 /*
36 * Different quirks to handle when the hardware deviates from a strict
37 * interpretation of the SDHCI specification.
38 */
39
40 /* Controller doesn't honor resets unless we touch the clock register */
41 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
42 /* Controller has bad caps bits, but really supports DMA */
43 #define SDHCI_QUIRK_FORCE_DMA (1<<1)
44 /* Controller doesn't like some resets when there is no card inserted. */
45 #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
46 /* Controller doesn't like clearing the power reg before a change */
47 #define SDHCI_QUIRK_SINGLE_POWER_WRITE (1<<3)
48 /* Controller has flaky internal state so reset it on each ios change */
49 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS (1<<4)
50 /* Controller has an unusable DMA engine */
51 #define SDHCI_QUIRK_BROKEN_DMA (1<<5)
52 /* Controller can only DMA from 32-bit aligned addresses */
53 #define SDHCI_QUIRK_32BIT_DMA_ADDR (1<<6)
54 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
55 #define SDHCI_QUIRK_32BIT_DMA_SIZE (1<<7)
56 /* Controller needs to be reset after each request to stay stable */
57 #define SDHCI_QUIRK_RESET_AFTER_REQUEST (1<<8)
58
59 static const struct pci_device_id pci_ids[] __devinitdata = {
60 {
61 .vendor = PCI_VENDOR_ID_RICOH,
62 .device = PCI_DEVICE_ID_RICOH_R5C822,
63 .subvendor = PCI_VENDOR_ID_IBM,
64 .subdevice = PCI_ANY_ID,
65 .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
66 SDHCI_QUIRK_FORCE_DMA,
67 },
68
69 {
70 .vendor = PCI_VENDOR_ID_RICOH,
71 .device = PCI_DEVICE_ID_RICOH_R5C822,
72 .subvendor = PCI_ANY_ID,
73 .subdevice = PCI_ANY_ID,
74 .driver_data = SDHCI_QUIRK_FORCE_DMA |
75 SDHCI_QUIRK_NO_CARD_NO_RESET,
76 },
77
78 {
79 .vendor = PCI_VENDOR_ID_TI,
80 .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
81 .subvendor = PCI_ANY_ID,
82 .subdevice = PCI_ANY_ID,
83 .driver_data = SDHCI_QUIRK_FORCE_DMA,
84 },
85
86 {
87 .vendor = PCI_VENDOR_ID_ENE,
88 .device = PCI_DEVICE_ID_ENE_CB712_SD,
89 .subvendor = PCI_ANY_ID,
90 .subdevice = PCI_ANY_ID,
91 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
92 SDHCI_QUIRK_BROKEN_DMA,
93 },
94
95 {
96 .vendor = PCI_VENDOR_ID_ENE,
97 .device = PCI_DEVICE_ID_ENE_CB712_SD_2,
98 .subvendor = PCI_ANY_ID,
99 .subdevice = PCI_ANY_ID,
100 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
101 SDHCI_QUIRK_BROKEN_DMA,
102 },
103
104 {
105 .vendor = PCI_VENDOR_ID_ENE,
106 .device = PCI_DEVICE_ID_ENE_CB714_SD,
107 .subvendor = PCI_ANY_ID,
108 .subdevice = PCI_ANY_ID,
109 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
110 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
111 },
112
113 {
114 .vendor = PCI_VENDOR_ID_ENE,
115 .device = PCI_DEVICE_ID_ENE_CB714_SD_2,
116 .subvendor = PCI_ANY_ID,
117 .subdevice = PCI_ANY_ID,
118 .driver_data = SDHCI_QUIRK_SINGLE_POWER_WRITE |
119 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS,
120 },
121
122 {
123 .vendor = PCI_VENDOR_ID_JMICRON,
124 .device = PCI_DEVICE_ID_JMICRON_JMB38X_SD,
125 .subvendor = PCI_ANY_ID,
126 .subdevice = PCI_ANY_ID,
127 .driver_data = SDHCI_QUIRK_32BIT_DMA_ADDR |
128 SDHCI_QUIRK_32BIT_DMA_SIZE |
129 SDHCI_QUIRK_RESET_AFTER_REQUEST,
130 },
131
132 { /* Generic SD host controller */
133 PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
134 },
135
136 { /* end: all zeroes */ },
137 };
138
139 MODULE_DEVICE_TABLE(pci, pci_ids);
140
141 static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
142 static void sdhci_finish_data(struct sdhci_host *);
143
144 static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
145 static void sdhci_finish_command(struct sdhci_host *);
146
147 static void sdhci_dumpregs(struct sdhci_host *host)
148 {
149 printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
150
151 printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
152 readl(host->ioaddr + SDHCI_DMA_ADDRESS),
153 readw(host->ioaddr + SDHCI_HOST_VERSION));
154 printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
155 readw(host->ioaddr + SDHCI_BLOCK_SIZE),
156 readw(host->ioaddr + SDHCI_BLOCK_COUNT));
157 printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
158 readl(host->ioaddr + SDHCI_ARGUMENT),
159 readw(host->ioaddr + SDHCI_TRANSFER_MODE));
160 printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
161 readl(host->ioaddr + SDHCI_PRESENT_STATE),
162 readb(host->ioaddr + SDHCI_HOST_CONTROL));
163 printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
164 readb(host->ioaddr + SDHCI_POWER_CONTROL),
165 readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
166 printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
167 readb(host->ioaddr + SDHCI_WAKE_UP_CONTROL),
168 readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
169 printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
170 readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
171 readl(host->ioaddr + SDHCI_INT_STATUS));
172 printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
173 readl(host->ioaddr + SDHCI_INT_ENABLE),
174 readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
175 printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
176 readw(host->ioaddr + SDHCI_ACMD12_ERR),
177 readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
178 printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
179 readl(host->ioaddr + SDHCI_CAPABILITIES),
180 readl(host->ioaddr + SDHCI_MAX_CURRENT));
181
182 printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
183 }
184
185 /*****************************************************************************\
186 * *
187 * Low level functions *
188 * *
189 \*****************************************************************************/
190
191 static void sdhci_reset(struct sdhci_host *host, u8 mask)
192 {
193 unsigned long timeout;
194
195 if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
196 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
197 SDHCI_CARD_PRESENT))
198 return;
199 }
200
201 writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
202
203 if (mask & SDHCI_RESET_ALL)
204 host->clock = 0;
205
206 /* Wait max 100 ms */
207 timeout = 100;
208
209 /* hw clears the bit when it's done */
210 while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
211 if (timeout == 0) {
212 printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
213 mmc_hostname(host->mmc), (int)mask);
214 sdhci_dumpregs(host);
215 return;
216 }
217 timeout--;
218 mdelay(1);
219 }
220 }
221
222 static void sdhci_init(struct sdhci_host *host)
223 {
224 u32 intmask;
225
226 sdhci_reset(host, SDHCI_RESET_ALL);
227
228 intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
229 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
230 SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
231 SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
232 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
233 SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
234
235 writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
236 writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
237 }
238
239 static void sdhci_activate_led(struct sdhci_host *host)
240 {
241 u8 ctrl;
242
243 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
244 ctrl |= SDHCI_CTRL_LED;
245 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
246 }
247
248 static void sdhci_deactivate_led(struct sdhci_host *host)
249 {
250 u8 ctrl;
251
252 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
253 ctrl &= ~SDHCI_CTRL_LED;
254 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
255 }
256
257 #ifdef CONFIG_LEDS_CLASS
258 static void sdhci_led_control(struct led_classdev *led,
259 enum led_brightness brightness)
260 {
261 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
262 unsigned long flags;
263
264 spin_lock_irqsave(&host->lock, flags);
265
266 if (brightness == LED_OFF)
267 sdhci_deactivate_led(host);
268 else
269 sdhci_activate_led(host);
270
271 spin_unlock_irqrestore(&host->lock, flags);
272 }
273 #endif
274
275 /*****************************************************************************\
276 * *
277 * Core functions *
278 * *
279 \*****************************************************************************/
280
281 static inline char* sdhci_sg_to_buffer(struct sdhci_host* host)
282 {
283 return sg_virt(host->cur_sg);
284 }
285
286 static inline int sdhci_next_sg(struct sdhci_host* host)
287 {
288 /*
289 * Skip to next SG entry.
290 */
291 host->cur_sg++;
292 host->num_sg--;
293
294 /*
295 * Any entries left?
296 */
297 if (host->num_sg > 0) {
298 host->offset = 0;
299 host->remain = host->cur_sg->length;
300 }
301
302 return host->num_sg;
303 }
304
305 static void sdhci_read_block_pio(struct sdhci_host *host)
306 {
307 int blksize, chunk_remain;
308 u32 data;
309 char *buffer;
310 int size;
311
312 DBG("PIO reading\n");
313
314 blksize = host->data->blksz;
315 chunk_remain = 0;
316 data = 0;
317
318 buffer = sdhci_sg_to_buffer(host) + host->offset;
319
320 while (blksize) {
321 if (chunk_remain == 0) {
322 data = readl(host->ioaddr + SDHCI_BUFFER);
323 chunk_remain = min(blksize, 4);
324 }
325
326 size = min(host->remain, chunk_remain);
327
328 chunk_remain -= size;
329 blksize -= size;
330 host->offset += size;
331 host->remain -= size;
332
333 while (size) {
334 *buffer = data & 0xFF;
335 buffer++;
336 data >>= 8;
337 size--;
338 }
339
340 if (host->remain == 0) {
341 if (sdhci_next_sg(host) == 0) {
342 BUG_ON(blksize != 0);
343 return;
344 }
345 buffer = sdhci_sg_to_buffer(host);
346 }
347 }
348 }
349
350 static void sdhci_write_block_pio(struct sdhci_host *host)
351 {
352 int blksize, chunk_remain;
353 u32 data;
354 char *buffer;
355 int bytes, size;
356
357 DBG("PIO writing\n");
358
359 blksize = host->data->blksz;
360 chunk_remain = 4;
361 data = 0;
362
363 bytes = 0;
364 buffer = sdhci_sg_to_buffer(host) + host->offset;
365
366 while (blksize) {
367 size = min(host->remain, chunk_remain);
368
369 chunk_remain -= size;
370 blksize -= size;
371 host->offset += size;
372 host->remain -= size;
373
374 while (size) {
375 data >>= 8;
376 data |= (u32)*buffer << 24;
377 buffer++;
378 size--;
379 }
380
381 if (chunk_remain == 0) {
382 writel(data, host->ioaddr + SDHCI_BUFFER);
383 chunk_remain = min(blksize, 4);
384 }
385
386 if (host->remain == 0) {
387 if (sdhci_next_sg(host) == 0) {
388 BUG_ON(blksize != 0);
389 return;
390 }
391 buffer = sdhci_sg_to_buffer(host);
392 }
393 }
394 }
395
396 static void sdhci_transfer_pio(struct sdhci_host *host)
397 {
398 u32 mask;
399
400 BUG_ON(!host->data);
401
402 if (host->num_sg == 0)
403 return;
404
405 if (host->data->flags & MMC_DATA_READ)
406 mask = SDHCI_DATA_AVAILABLE;
407 else
408 mask = SDHCI_SPACE_AVAILABLE;
409
410 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
411 if (host->data->flags & MMC_DATA_READ)
412 sdhci_read_block_pio(host);
413 else
414 sdhci_write_block_pio(host);
415
416 if (host->num_sg == 0)
417 break;
418 }
419
420 DBG("PIO transfer complete.\n");
421 }
422
423 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
424 {
425 u8 count;
426 unsigned target_timeout, current_timeout;
427
428 WARN_ON(host->data);
429
430 if (data == NULL)
431 return;
432
433 /* Sanity checks */
434 BUG_ON(data->blksz * data->blocks > 524288);
435 BUG_ON(data->blksz > host->mmc->max_blk_size);
436 BUG_ON(data->blocks > 65535);
437
438 host->data = data;
439 host->data_early = 0;
440
441 /* timeout in us */
442 target_timeout = data->timeout_ns / 1000 +
443 data->timeout_clks / host->clock;
444
445 /*
446 * Figure out needed cycles.
447 * We do this in steps in order to fit inside a 32 bit int.
448 * The first step is the minimum timeout, which will have a
449 * minimum resolution of 6 bits:
450 * (1) 2^13*1000 > 2^22,
451 * (2) host->timeout_clk < 2^16
452 * =>
453 * (1) / (2) > 2^6
454 */
455 count = 0;
456 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
457 while (current_timeout < target_timeout) {
458 count++;
459 current_timeout <<= 1;
460 if (count >= 0xF)
461 break;
462 }
463
464 if (count >= 0xF) {
465 printk(KERN_WARNING "%s: Too large timeout requested!\n",
466 mmc_hostname(host->mmc));
467 count = 0xE;
468 }
469
470 writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
471
472 if (host->flags & SDHCI_USE_DMA)
473 host->flags |= SDHCI_REQ_USE_DMA;
474
475 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
476 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) &&
477 ((data->blksz * data->blocks) & 0x3))) {
478 DBG("Reverting to PIO because of transfer size (%d)\n",
479 data->blksz * data->blocks);
480 host->flags &= ~SDHCI_REQ_USE_DMA;
481 }
482
483 /*
484 * The assumption here being that alignment is the same after
485 * translation to device address space.
486 */
487 if (unlikely((host->flags & SDHCI_REQ_USE_DMA) &&
488 (host->chip->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
489 (data->sg->offset & 0x3))) {
490 DBG("Reverting to PIO because of bad alignment\n");
491 host->flags &= ~SDHCI_REQ_USE_DMA;
492 }
493
494 if (host->flags & SDHCI_REQ_USE_DMA) {
495 int count;
496
497 count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
498 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
499 BUG_ON(count != 1);
500
501 writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
502 } else {
503 host->cur_sg = data->sg;
504 host->num_sg = data->sg_len;
505
506 host->offset = 0;
507 host->remain = host->cur_sg->length;
508 }
509
510 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
511 writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
512 host->ioaddr + SDHCI_BLOCK_SIZE);
513 writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
514 }
515
516 static void sdhci_set_transfer_mode(struct sdhci_host *host,
517 struct mmc_data *data)
518 {
519 u16 mode;
520
521 if (data == NULL)
522 return;
523
524 WARN_ON(!host->data);
525
526 mode = SDHCI_TRNS_BLK_CNT_EN;
527 if (data->blocks > 1)
528 mode |= SDHCI_TRNS_MULTI;
529 if (data->flags & MMC_DATA_READ)
530 mode |= SDHCI_TRNS_READ;
531 if (host->flags & SDHCI_REQ_USE_DMA)
532 mode |= SDHCI_TRNS_DMA;
533
534 writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
535 }
536
537 static void sdhci_finish_data(struct sdhci_host *host)
538 {
539 struct mmc_data *data;
540 u16 blocks;
541
542 BUG_ON(!host->data);
543
544 data = host->data;
545 host->data = NULL;
546
547 if (host->flags & SDHCI_REQ_USE_DMA) {
548 pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
549 (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
550 }
551
552 /*
553 * Controller doesn't count down when in single block mode.
554 */
555 if (data->blocks == 1)
556 blocks = (data->error == 0) ? 0 : 1;
557 else
558 blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
559 data->bytes_xfered = data->blksz * (data->blocks - blocks);
560
561 if (!data->error && blocks) {
562 printk(KERN_ERR "%s: Controller signalled completion even "
563 "though there were blocks left.\n",
564 mmc_hostname(host->mmc));
565 data->error = -EIO;
566 }
567
568 if (data->stop) {
569 /*
570 * The controller needs a reset of internal state machines
571 * upon error conditions.
572 */
573 if (data->error) {
574 sdhci_reset(host, SDHCI_RESET_CMD);
575 sdhci_reset(host, SDHCI_RESET_DATA);
576 }
577
578 sdhci_send_command(host, data->stop);
579 } else
580 tasklet_schedule(&host->finish_tasklet);
581 }
582
583 static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
584 {
585 int flags;
586 u32 mask;
587 unsigned long timeout;
588
589 WARN_ON(host->cmd);
590
591 /* Wait max 10 ms */
592 timeout = 10;
593
594 mask = SDHCI_CMD_INHIBIT;
595 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
596 mask |= SDHCI_DATA_INHIBIT;
597
598 /* We shouldn't wait for data inihibit for stop commands, even
599 though they might use busy signaling */
600 if (host->mrq->data && (cmd == host->mrq->data->stop))
601 mask &= ~SDHCI_DATA_INHIBIT;
602
603 while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
604 if (timeout == 0) {
605 printk(KERN_ERR "%s: Controller never released "
606 "inhibit bit(s).\n", mmc_hostname(host->mmc));
607 sdhci_dumpregs(host);
608 cmd->error = -EIO;
609 tasklet_schedule(&host->finish_tasklet);
610 return;
611 }
612 timeout--;
613 mdelay(1);
614 }
615
616 mod_timer(&host->timer, jiffies + 10 * HZ);
617
618 host->cmd = cmd;
619
620 sdhci_prepare_data(host, cmd->data);
621
622 writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
623
624 sdhci_set_transfer_mode(host, cmd->data);
625
626 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
627 printk(KERN_ERR "%s: Unsupported response type!\n",
628 mmc_hostname(host->mmc));
629 cmd->error = -EINVAL;
630 tasklet_schedule(&host->finish_tasklet);
631 return;
632 }
633
634 if (!(cmd->flags & MMC_RSP_PRESENT))
635 flags = SDHCI_CMD_RESP_NONE;
636 else if (cmd->flags & MMC_RSP_136)
637 flags = SDHCI_CMD_RESP_LONG;
638 else if (cmd->flags & MMC_RSP_BUSY)
639 flags = SDHCI_CMD_RESP_SHORT_BUSY;
640 else
641 flags = SDHCI_CMD_RESP_SHORT;
642
643 if (cmd->flags & MMC_RSP_CRC)
644 flags |= SDHCI_CMD_CRC;
645 if (cmd->flags & MMC_RSP_OPCODE)
646 flags |= SDHCI_CMD_INDEX;
647 if (cmd->data)
648 flags |= SDHCI_CMD_DATA;
649
650 writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
651 host->ioaddr + SDHCI_COMMAND);
652 }
653
654 static void sdhci_finish_command(struct sdhci_host *host)
655 {
656 int i;
657
658 BUG_ON(host->cmd == NULL);
659
660 if (host->cmd->flags & MMC_RSP_PRESENT) {
661 if (host->cmd->flags & MMC_RSP_136) {
662 /* CRC is stripped so we need to do some shifting. */
663 for (i = 0;i < 4;i++) {
664 host->cmd->resp[i] = readl(host->ioaddr +
665 SDHCI_RESPONSE + (3-i)*4) << 8;
666 if (i != 3)
667 host->cmd->resp[i] |=
668 readb(host->ioaddr +
669 SDHCI_RESPONSE + (3-i)*4-1);
670 }
671 } else {
672 host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
673 }
674 }
675
676 host->cmd->error = 0;
677
678 if (host->data && host->data_early)
679 sdhci_finish_data(host);
680
681 if (!host->cmd->data)
682 tasklet_schedule(&host->finish_tasklet);
683
684 host->cmd = NULL;
685 }
686
687 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
688 {
689 int div;
690 u16 clk;
691 unsigned long timeout;
692
693 if (clock == host->clock)
694 return;
695
696 writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
697
698 if (clock == 0)
699 goto out;
700
701 for (div = 1;div < 256;div *= 2) {
702 if ((host->max_clk / div) <= clock)
703 break;
704 }
705 div >>= 1;
706
707 clk = div << SDHCI_DIVIDER_SHIFT;
708 clk |= SDHCI_CLOCK_INT_EN;
709 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
710
711 /* Wait max 10 ms */
712 timeout = 10;
713 while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
714 & SDHCI_CLOCK_INT_STABLE)) {
715 if (timeout == 0) {
716 printk(KERN_ERR "%s: Internal clock never "
717 "stabilised.\n", mmc_hostname(host->mmc));
718 sdhci_dumpregs(host);
719 return;
720 }
721 timeout--;
722 mdelay(1);
723 }
724
725 clk |= SDHCI_CLOCK_CARD_EN;
726 writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
727
728 out:
729 host->clock = clock;
730 }
731
732 static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
733 {
734 u8 pwr;
735
736 if (host->power == power)
737 return;
738
739 if (power == (unsigned short)-1) {
740 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
741 goto out;
742 }
743
744 /*
745 * Spec says that we should clear the power reg before setting
746 * a new value. Some controllers don't seem to like this though.
747 */
748 if (!(host->chip->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
749 writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
750
751 pwr = SDHCI_POWER_ON;
752
753 switch (1 << power) {
754 case MMC_VDD_165_195:
755 pwr |= SDHCI_POWER_180;
756 break;
757 case MMC_VDD_29_30:
758 case MMC_VDD_30_31:
759 pwr |= SDHCI_POWER_300;
760 break;
761 case MMC_VDD_32_33:
762 case MMC_VDD_33_34:
763 pwr |= SDHCI_POWER_330;
764 break;
765 default:
766 BUG();
767 }
768
769 writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
770
771 out:
772 host->power = power;
773 }
774
775 /*****************************************************************************\
776 * *
777 * MMC callbacks *
778 * *
779 \*****************************************************************************/
780
781 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
782 {
783 struct sdhci_host *host;
784 unsigned long flags;
785
786 host = mmc_priv(mmc);
787
788 spin_lock_irqsave(&host->lock, flags);
789
790 WARN_ON(host->mrq != NULL);
791
792 #ifndef CONFIG_LEDS_CLASS
793 sdhci_activate_led(host);
794 #endif
795
796 host->mrq = mrq;
797
798 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
799 host->mrq->cmd->error = -ENOMEDIUM;
800 tasklet_schedule(&host->finish_tasklet);
801 } else
802 sdhci_send_command(host, mrq->cmd);
803
804 mmiowb();
805 spin_unlock_irqrestore(&host->lock, flags);
806 }
807
808 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
809 {
810 struct sdhci_host *host;
811 unsigned long flags;
812 u8 ctrl;
813
814 host = mmc_priv(mmc);
815
816 spin_lock_irqsave(&host->lock, flags);
817
818 /*
819 * Reset the chip on each power off.
820 * Should clear out any weird states.
821 */
822 if (ios->power_mode == MMC_POWER_OFF) {
823 writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
824 sdhci_init(host);
825 }
826
827 sdhci_set_clock(host, ios->clock);
828
829 if (ios->power_mode == MMC_POWER_OFF)
830 sdhci_set_power(host, -1);
831 else
832 sdhci_set_power(host, ios->vdd);
833
834 ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
835
836 if (ios->bus_width == MMC_BUS_WIDTH_4)
837 ctrl |= SDHCI_CTRL_4BITBUS;
838 else
839 ctrl &= ~SDHCI_CTRL_4BITBUS;
840
841 if (ios->timing == MMC_TIMING_SD_HS)
842 ctrl |= SDHCI_CTRL_HISPD;
843 else
844 ctrl &= ~SDHCI_CTRL_HISPD;
845
846 writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
847
848 /*
849 * Some (ENE) controllers go apeshit on some ios operation,
850 * signalling timeout and CRC errors even on CMD0. Resetting
851 * it on each ios seems to solve the problem.
852 */
853 if(host->chip->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
854 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
855
856 mmiowb();
857 spin_unlock_irqrestore(&host->lock, flags);
858 }
859
860 static int sdhci_get_ro(struct mmc_host *mmc)
861 {
862 struct sdhci_host *host;
863 unsigned long flags;
864 int present;
865
866 host = mmc_priv(mmc);
867
868 spin_lock_irqsave(&host->lock, flags);
869
870 present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
871
872 spin_unlock_irqrestore(&host->lock, flags);
873
874 return !(present & SDHCI_WRITE_PROTECT);
875 }
876
877 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
878 {
879 struct sdhci_host *host;
880 unsigned long flags;
881 u32 ier;
882
883 host = mmc_priv(mmc);
884
885 spin_lock_irqsave(&host->lock, flags);
886
887 ier = readl(host->ioaddr + SDHCI_INT_ENABLE);
888
889 ier &= ~SDHCI_INT_CARD_INT;
890 if (enable)
891 ier |= SDHCI_INT_CARD_INT;
892
893 writel(ier, host->ioaddr + SDHCI_INT_ENABLE);
894 writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
895
896 mmiowb();
897
898 spin_unlock_irqrestore(&host->lock, flags);
899 }
900
901 static const struct mmc_host_ops sdhci_ops = {
902 .request = sdhci_request,
903 .set_ios = sdhci_set_ios,
904 .get_ro = sdhci_get_ro,
905 .enable_sdio_irq = sdhci_enable_sdio_irq,
906 };
907
908 /*****************************************************************************\
909 * *
910 * Tasklets *
911 * *
912 \*****************************************************************************/
913
914 static void sdhci_tasklet_card(unsigned long param)
915 {
916 struct sdhci_host *host;
917 unsigned long flags;
918
919 host = (struct sdhci_host*)param;
920
921 spin_lock_irqsave(&host->lock, flags);
922
923 if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
924 if (host->mrq) {
925 printk(KERN_ERR "%s: Card removed during transfer!\n",
926 mmc_hostname(host->mmc));
927 printk(KERN_ERR "%s: Resetting controller.\n",
928 mmc_hostname(host->mmc));
929
930 sdhci_reset(host, SDHCI_RESET_CMD);
931 sdhci_reset(host, SDHCI_RESET_DATA);
932
933 host->mrq->cmd->error = -ENOMEDIUM;
934 tasklet_schedule(&host->finish_tasklet);
935 }
936 }
937
938 spin_unlock_irqrestore(&host->lock, flags);
939
940 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
941 }
942
943 static void sdhci_tasklet_finish(unsigned long param)
944 {
945 struct sdhci_host *host;
946 unsigned long flags;
947 struct mmc_request *mrq;
948
949 host = (struct sdhci_host*)param;
950
951 spin_lock_irqsave(&host->lock, flags);
952
953 del_timer(&host->timer);
954
955 mrq = host->mrq;
956
957 /*
958 * The controller needs a reset of internal state machines
959 * upon error conditions.
960 */
961 if (mrq->cmd->error ||
962 (mrq->data && (mrq->data->error ||
963 (mrq->data->stop && mrq->data->stop->error))) ||
964 (host->chip->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST)) {
965
966 /* Some controllers need this kick or reset won't work here */
967 if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
968 unsigned int clock;
969
970 /* This is to force an update */
971 clock = host->clock;
972 host->clock = 0;
973 sdhci_set_clock(host, clock);
974 }
975
976 /* Spec says we should do both at the same time, but Ricoh
977 controllers do not like that. */
978 sdhci_reset(host, SDHCI_RESET_CMD);
979 sdhci_reset(host, SDHCI_RESET_DATA);
980 }
981
982 host->mrq = NULL;
983 host->cmd = NULL;
984 host->data = NULL;
985
986 #ifndef CONFIG_LEDS_CLASS
987 sdhci_deactivate_led(host);
988 #endif
989
990 mmiowb();
991 spin_unlock_irqrestore(&host->lock, flags);
992
993 mmc_request_done(host->mmc, mrq);
994 }
995
996 static void sdhci_timeout_timer(unsigned long data)
997 {
998 struct sdhci_host *host;
999 unsigned long flags;
1000
1001 host = (struct sdhci_host*)data;
1002
1003 spin_lock_irqsave(&host->lock, flags);
1004
1005 if (host->mrq) {
1006 printk(KERN_ERR "%s: Timeout waiting for hardware "
1007 "interrupt.\n", mmc_hostname(host->mmc));
1008 sdhci_dumpregs(host);
1009
1010 if (host->data) {
1011 host->data->error = -ETIMEDOUT;
1012 sdhci_finish_data(host);
1013 } else {
1014 if (host->cmd)
1015 host->cmd->error = -ETIMEDOUT;
1016 else
1017 host->mrq->cmd->error = -ETIMEDOUT;
1018
1019 tasklet_schedule(&host->finish_tasklet);
1020 }
1021 }
1022
1023 mmiowb();
1024 spin_unlock_irqrestore(&host->lock, flags);
1025 }
1026
1027 /*****************************************************************************\
1028 * *
1029 * Interrupt handling *
1030 * *
1031 \*****************************************************************************/
1032
1033 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
1034 {
1035 BUG_ON(intmask == 0);
1036
1037 if (!host->cmd) {
1038 printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
1039 "though no command operation was in progress.\n",
1040 mmc_hostname(host->mmc), (unsigned)intmask);
1041 sdhci_dumpregs(host);
1042 return;
1043 }
1044
1045 if (intmask & SDHCI_INT_TIMEOUT)
1046 host->cmd->error = -ETIMEDOUT;
1047 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1048 SDHCI_INT_INDEX))
1049 host->cmd->error = -EILSEQ;
1050
1051 if (host->cmd->error)
1052 tasklet_schedule(&host->finish_tasklet);
1053 else if (intmask & SDHCI_INT_RESPONSE)
1054 sdhci_finish_command(host);
1055 }
1056
1057 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
1058 {
1059 BUG_ON(intmask == 0);
1060
1061 if (!host->data) {
1062 /*
1063 * A data end interrupt is sent together with the response
1064 * for the stop command.
1065 */
1066 if (intmask & SDHCI_INT_DATA_END)
1067 return;
1068
1069 printk(KERN_ERR "%s: Got data interrupt 0x%08x even "
1070 "though no data operation was in progress.\n",
1071 mmc_hostname(host->mmc), (unsigned)intmask);
1072 sdhci_dumpregs(host);
1073
1074 return;
1075 }
1076
1077 if (intmask & SDHCI_INT_DATA_TIMEOUT)
1078 host->data->error = -ETIMEDOUT;
1079 else if (intmask & (SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_END_BIT))
1080 host->data->error = -EILSEQ;
1081
1082 if (host->data->error)
1083 sdhci_finish_data(host);
1084 else {
1085 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1086 sdhci_transfer_pio(host);
1087
1088 /*
1089 * We currently don't do anything fancy with DMA
1090 * boundaries, but as we can't disable the feature
1091 * we need to at least restart the transfer.
1092 */
1093 if (intmask & SDHCI_INT_DMA_END)
1094 writel(readl(host->ioaddr + SDHCI_DMA_ADDRESS),
1095 host->ioaddr + SDHCI_DMA_ADDRESS);
1096
1097 if (intmask & SDHCI_INT_DATA_END) {
1098 if (host->cmd) {
1099 /*
1100 * Data managed to finish before the
1101 * command completed. Make sure we do
1102 * things in the proper order.
1103 */
1104 host->data_early = 1;
1105 } else {
1106 sdhci_finish_data(host);
1107 }
1108 }
1109 }
1110 }
1111
1112 static irqreturn_t sdhci_irq(int irq, void *dev_id)
1113 {
1114 irqreturn_t result;
1115 struct sdhci_host* host = dev_id;
1116 u32 intmask;
1117 int cardint = 0;
1118
1119 spin_lock(&host->lock);
1120
1121 intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
1122
1123 if (!intmask || intmask == 0xffffffff) {
1124 result = IRQ_NONE;
1125 goto out;
1126 }
1127
1128 DBG("*** %s got interrupt: 0x%08x\n",
1129 mmc_hostname(host->mmc), intmask);
1130
1131 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
1132 writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
1133 host->ioaddr + SDHCI_INT_STATUS);
1134 tasklet_schedule(&host->card_tasklet);
1135 }
1136
1137 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
1138
1139 if (intmask & SDHCI_INT_CMD_MASK) {
1140 writel(intmask & SDHCI_INT_CMD_MASK,
1141 host->ioaddr + SDHCI_INT_STATUS);
1142 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1143 }
1144
1145 if (intmask & SDHCI_INT_DATA_MASK) {
1146 writel(intmask & SDHCI_INT_DATA_MASK,
1147 host->ioaddr + SDHCI_INT_STATUS);
1148 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1149 }
1150
1151 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
1152
1153 intmask &= ~SDHCI_INT_ERROR;
1154
1155 if (intmask & SDHCI_INT_BUS_POWER) {
1156 printk(KERN_ERR "%s: Card is consuming too much power!\n",
1157 mmc_hostname(host->mmc));
1158 writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
1159 }
1160
1161 intmask &= ~SDHCI_INT_BUS_POWER;
1162
1163 if (intmask & SDHCI_INT_CARD_INT)
1164 cardint = 1;
1165
1166 intmask &= ~SDHCI_INT_CARD_INT;
1167
1168 if (intmask) {
1169 printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
1170 mmc_hostname(host->mmc), intmask);
1171 sdhci_dumpregs(host);
1172
1173 writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
1174 }
1175
1176 result = IRQ_HANDLED;
1177
1178 mmiowb();
1179 out:
1180 spin_unlock(&host->lock);
1181
1182 /*
1183 * We have to delay this as it calls back into the driver.
1184 */
1185 if (cardint)
1186 mmc_signal_sdio_irq(host->mmc);
1187
1188 return result;
1189 }
1190
1191 /*****************************************************************************\
1192 * *
1193 * Suspend/resume *
1194 * *
1195 \*****************************************************************************/
1196
1197 #ifdef CONFIG_PM
1198
1199 static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
1200 {
1201 struct sdhci_chip *chip;
1202 int i, ret;
1203
1204 chip = pci_get_drvdata(pdev);
1205 if (!chip)
1206 return 0;
1207
1208 DBG("Suspending...\n");
1209
1210 for (i = 0;i < chip->num_slots;i++) {
1211 if (!chip->hosts[i])
1212 continue;
1213 ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
1214 if (ret) {
1215 for (i--;i >= 0;i--)
1216 mmc_resume_host(chip->hosts[i]->mmc);
1217 return ret;
1218 }
1219 }
1220
1221 pci_save_state(pdev);
1222 pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
1223
1224 for (i = 0;i < chip->num_slots;i++) {
1225 if (!chip->hosts[i])
1226 continue;
1227 free_irq(chip->hosts[i]->irq, chip->hosts[i]);
1228 }
1229
1230 pci_disable_device(pdev);
1231 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1232
1233 return 0;
1234 }
1235
1236 static int sdhci_resume (struct pci_dev *pdev)
1237 {
1238 struct sdhci_chip *chip;
1239 int i, ret;
1240
1241 chip = pci_get_drvdata(pdev);
1242 if (!chip)
1243 return 0;
1244
1245 DBG("Resuming...\n");
1246
1247 pci_set_power_state(pdev, PCI_D0);
1248 pci_restore_state(pdev);
1249 ret = pci_enable_device(pdev);
1250 if (ret)
1251 return ret;
1252
1253 for (i = 0;i < chip->num_slots;i++) {
1254 if (!chip->hosts[i])
1255 continue;
1256 if (chip->hosts[i]->flags & SDHCI_USE_DMA)
1257 pci_set_master(pdev);
1258 ret = request_irq(chip->hosts[i]->irq, sdhci_irq,
1259 IRQF_SHARED, mmc_hostname(chip->hosts[i]->mmc),
1260 chip->hosts[i]);
1261 if (ret)
1262 return ret;
1263 sdhci_init(chip->hosts[i]);
1264 mmiowb();
1265 ret = mmc_resume_host(chip->hosts[i]->mmc);
1266 if (ret)
1267 return ret;
1268 }
1269
1270 return 0;
1271 }
1272
1273 #else /* CONFIG_PM */
1274
1275 #define sdhci_suspend NULL
1276 #define sdhci_resume NULL
1277
1278 #endif /* CONFIG_PM */
1279
1280 /*****************************************************************************\
1281 * *
1282 * Device probing/removal *
1283 * *
1284 \*****************************************************************************/
1285
1286 static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
1287 {
1288 int ret;
1289 unsigned int version;
1290 struct sdhci_chip *chip;
1291 struct mmc_host *mmc;
1292 struct sdhci_host *host;
1293
1294 u8 first_bar;
1295 unsigned int caps;
1296
1297 chip = pci_get_drvdata(pdev);
1298 BUG_ON(!chip);
1299
1300 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1301 if (ret)
1302 return ret;
1303
1304 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1305
1306 if (first_bar > 5) {
1307 printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
1308 return -ENODEV;
1309 }
1310
1311 if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
1312 printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
1313 return -ENODEV;
1314 }
1315
1316 if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
1317 printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. "
1318 "You may experience problems.\n");
1319 }
1320
1321 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1322 printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
1323 return -ENODEV;
1324 }
1325
1326 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1327 printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
1328 return -ENODEV;
1329 }
1330
1331 mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
1332 if (!mmc)
1333 return -ENOMEM;
1334
1335 host = mmc_priv(mmc);
1336 host->mmc = mmc;
1337
1338 host->chip = chip;
1339 chip->hosts[slot] = host;
1340
1341 host->bar = first_bar + slot;
1342
1343 host->addr = pci_resource_start(pdev, host->bar);
1344 host->irq = pdev->irq;
1345
1346 DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
1347
1348 ret = pci_request_region(pdev, host->bar, mmc_hostname(mmc));
1349 if (ret)
1350 goto free;
1351
1352 host->ioaddr = ioremap_nocache(host->addr,
1353 pci_resource_len(pdev, host->bar));
1354 if (!host->ioaddr) {
1355 ret = -ENOMEM;
1356 goto release;
1357 }
1358
1359 sdhci_reset(host, SDHCI_RESET_ALL);
1360
1361 version = readw(host->ioaddr + SDHCI_HOST_VERSION);
1362 version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
1363 if (version > 1) {
1364 printk(KERN_ERR "%s: Unknown controller version (%d). "
1365 "You may experience problems.\n", mmc_hostname(mmc),
1366 version);
1367 }
1368
1369 caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
1370
1371 if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
1372 host->flags |= SDHCI_USE_DMA;
1373 else if (!(caps & SDHCI_CAN_DO_DMA))
1374 DBG("Controller doesn't have DMA capability\n");
1375 else
1376 host->flags |= SDHCI_USE_DMA;
1377
1378 if ((chip->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
1379 (host->flags & SDHCI_USE_DMA)) {
1380 DBG("Disabling DMA as it is marked broken\n");
1381 host->flags &= ~SDHCI_USE_DMA;
1382 }
1383
1384 if (((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1385 (host->flags & SDHCI_USE_DMA)) {
1386 printk(KERN_WARNING "%s: Will use DMA "
1387 "mode even though HW doesn't fully "
1388 "claim to support it.\n", mmc_hostname(mmc));
1389 }
1390
1391 if (host->flags & SDHCI_USE_DMA) {
1392 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1393 printk(KERN_WARNING "%s: No suitable DMA available. "
1394 "Falling back to PIO.\n", mmc_hostname(mmc));
1395 host->flags &= ~SDHCI_USE_DMA;
1396 }
1397 }
1398
1399 if (host->flags & SDHCI_USE_DMA)
1400 pci_set_master(pdev);
1401 else /* XXX: Hack to get MMC layer to avoid highmem */
1402 pdev->dma_mask = 0;
1403
1404 host->max_clk =
1405 (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
1406 if (host->max_clk == 0) {
1407 printk(KERN_ERR "%s: Hardware doesn't specify base clock "
1408 "frequency.\n", mmc_hostname(mmc));
1409 ret = -ENODEV;
1410 goto unmap;
1411 }
1412 host->max_clk *= 1000000;
1413
1414 host->timeout_clk =
1415 (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
1416 if (host->timeout_clk == 0) {
1417 printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
1418 "frequency.\n", mmc_hostname(mmc));
1419 ret = -ENODEV;
1420 goto unmap;
1421 }
1422 if (caps & SDHCI_TIMEOUT_CLK_UNIT)
1423 host->timeout_clk *= 1000;
1424
1425 /*
1426 * Set host parameters.
1427 */
1428 mmc->ops = &sdhci_ops;
1429 mmc->f_min = host->max_clk / 256;
1430 mmc->f_max = host->max_clk;
1431 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_SDIO_IRQ;
1432
1433 if (caps & SDHCI_CAN_DO_HISPD)
1434 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1435
1436 mmc->ocr_avail = 0;
1437 if (caps & SDHCI_CAN_VDD_330)
1438 mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
1439 if (caps & SDHCI_CAN_VDD_300)
1440 mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
1441 if (caps & SDHCI_CAN_VDD_180)
1442 mmc->ocr_avail |= MMC_VDD_165_195;
1443
1444 if (mmc->ocr_avail == 0) {
1445 printk(KERN_ERR "%s: Hardware doesn't report any "
1446 "support voltages.\n", mmc_hostname(mmc));
1447 ret = -ENODEV;
1448 goto unmap;
1449 }
1450
1451 spin_lock_init(&host->lock);
1452
1453 /*
1454 * Maximum number of segments. Hardware cannot do scatter lists.
1455 */
1456 if (host->flags & SDHCI_USE_DMA)
1457 mmc->max_hw_segs = 1;
1458 else
1459 mmc->max_hw_segs = 16;
1460 mmc->max_phys_segs = 16;
1461
1462 /*
1463 * Maximum number of sectors in one transfer. Limited by DMA boundary
1464 * size (512KiB).
1465 */
1466 mmc->max_req_size = 524288;
1467
1468 /*
1469 * Maximum segment size. Could be one segment with the maximum number
1470 * of bytes.
1471 */
1472 mmc->max_seg_size = mmc->max_req_size;
1473
1474 /*
1475 * Maximum block size. This varies from controller to controller and
1476 * is specified in the capabilities register.
1477 */
1478 mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
1479 if (mmc->max_blk_size >= 3) {
1480 printk(KERN_WARNING "%s: Invalid maximum block size, "
1481 "assuming 512 bytes\n", mmc_hostname(mmc));
1482 mmc->max_blk_size = 512;
1483 } else
1484 mmc->max_blk_size = 512 << mmc->max_blk_size;
1485
1486 /*
1487 * Maximum block count.
1488 */
1489 mmc->max_blk_count = 65535;
1490
1491 /*
1492 * Init tasklets.
1493 */
1494 tasklet_init(&host->card_tasklet,
1495 sdhci_tasklet_card, (unsigned long)host);
1496 tasklet_init(&host->finish_tasklet,
1497 sdhci_tasklet_finish, (unsigned long)host);
1498
1499 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
1500
1501 ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
1502 mmc_hostname(mmc), host);
1503 if (ret)
1504 goto untasklet;
1505
1506 sdhci_init(host);
1507
1508 #ifdef CONFIG_MMC_DEBUG
1509 sdhci_dumpregs(host);
1510 #endif
1511
1512 #ifdef CONFIG_LEDS_CLASS
1513 host->led.name = mmc_hostname(mmc);
1514 host->led.brightness = LED_OFF;
1515 host->led.default_trigger = mmc_hostname(mmc);
1516 host->led.brightness_set = sdhci_led_control;
1517
1518 ret = led_classdev_register(&pdev->dev, &host->led);
1519 if (ret)
1520 goto reset;
1521 #endif
1522
1523 mmiowb();
1524
1525 mmc_add_host(mmc);
1526
1527 printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n",
1528 mmc_hostname(mmc), host->addr, host->irq,
1529 (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
1530
1531 return 0;
1532
1533 #ifdef CONFIG_LEDS_CLASS
1534 reset:
1535 sdhci_reset(host, SDHCI_RESET_ALL);
1536 free_irq(host->irq, host);
1537 #endif
1538 untasklet:
1539 tasklet_kill(&host->card_tasklet);
1540 tasklet_kill(&host->finish_tasklet);
1541 unmap:
1542 iounmap(host->ioaddr);
1543 release:
1544 pci_release_region(pdev, host->bar);
1545 free:
1546 mmc_free_host(mmc);
1547
1548 return ret;
1549 }
1550
1551 static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
1552 {
1553 struct sdhci_chip *chip;
1554 struct mmc_host *mmc;
1555 struct sdhci_host *host;
1556
1557 chip = pci_get_drvdata(pdev);
1558 host = chip->hosts[slot];
1559 mmc = host->mmc;
1560
1561 chip->hosts[slot] = NULL;
1562
1563 mmc_remove_host(mmc);
1564
1565 #ifdef CONFIG_LEDS_CLASS
1566 led_classdev_unregister(&host->led);
1567 #endif
1568
1569 sdhci_reset(host, SDHCI_RESET_ALL);
1570
1571 free_irq(host->irq, host);
1572
1573 del_timer_sync(&host->timer);
1574
1575 tasklet_kill(&host->card_tasklet);
1576 tasklet_kill(&host->finish_tasklet);
1577
1578 iounmap(host->ioaddr);
1579
1580 pci_release_region(pdev, host->bar);
1581
1582 mmc_free_host(mmc);
1583 }
1584
1585 static int __devinit sdhci_probe(struct pci_dev *pdev,
1586 const struct pci_device_id *ent)
1587 {
1588 int ret, i;
1589 u8 slots, rev;
1590 struct sdhci_chip *chip;
1591
1592 BUG_ON(pdev == NULL);
1593 BUG_ON(ent == NULL);
1594
1595 pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
1596
1597 printk(KERN_INFO DRIVER_NAME
1598 ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
1599 pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
1600 (int)rev);
1601
1602 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1603 if (ret)
1604 return ret;
1605
1606 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1607 DBG("found %d slot(s)\n", slots);
1608 if (slots == 0)
1609 return -ENODEV;
1610
1611 ret = pci_enable_device(pdev);
1612 if (ret)
1613 return ret;
1614
1615 chip = kzalloc(sizeof(struct sdhci_chip) +
1616 sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
1617 if (!chip) {
1618 ret = -ENOMEM;
1619 goto err;
1620 }
1621
1622 chip->pdev = pdev;
1623 chip->quirks = ent->driver_data;
1624
1625 if (debug_quirks)
1626 chip->quirks = debug_quirks;
1627
1628 chip->num_slots = slots;
1629 pci_set_drvdata(pdev, chip);
1630
1631 for (i = 0;i < slots;i++) {
1632 ret = sdhci_probe_slot(pdev, i);
1633 if (ret) {
1634 for (i--;i >= 0;i--)
1635 sdhci_remove_slot(pdev, i);
1636 goto free;
1637 }
1638 }
1639
1640 return 0;
1641
1642 free:
1643 pci_set_drvdata(pdev, NULL);
1644 kfree(chip);
1645
1646 err:
1647 pci_disable_device(pdev);
1648 return ret;
1649 }
1650
1651 static void __devexit sdhci_remove(struct pci_dev *pdev)
1652 {
1653 int i;
1654 struct sdhci_chip *chip;
1655
1656 chip = pci_get_drvdata(pdev);
1657
1658 if (chip) {
1659 for (i = 0;i < chip->num_slots;i++)
1660 sdhci_remove_slot(pdev, i);
1661
1662 pci_set_drvdata(pdev, NULL);
1663
1664 kfree(chip);
1665 }
1666
1667 pci_disable_device(pdev);
1668 }
1669
1670 static struct pci_driver sdhci_driver = {
1671 .name = DRIVER_NAME,
1672 .id_table = pci_ids,
1673 .probe = sdhci_probe,
1674 .remove = __devexit_p(sdhci_remove),
1675 .suspend = sdhci_suspend,
1676 .resume = sdhci_resume,
1677 };
1678
1679 /*****************************************************************************\
1680 * *
1681 * Driver init/exit *
1682 * *
1683 \*****************************************************************************/
1684
1685 static int __init sdhci_drv_init(void)
1686 {
1687 printk(KERN_INFO DRIVER_NAME
1688 ": Secure Digital Host Controller Interface driver\n");
1689 printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
1690
1691 return pci_register_driver(&sdhci_driver);
1692 }
1693
1694 static void __exit sdhci_drv_exit(void)
1695 {
1696 DBG("Exiting\n");
1697
1698 pci_unregister_driver(&sdhci_driver);
1699 }
1700
1701 module_init(sdhci_drv_init);
1702 module_exit(sdhci_drv_exit);
1703
1704 module_param(debug_quirks, uint, 0444);
1705
1706 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1707 MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
1708 MODULE_LICENSE("GPL");
1709
1710 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
Linux kernel - Deliverables
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