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mmc: sdhci: Tidy together LED code
[deliverable/linux.git] / drivers / mmc / host / sdhci.c
1 /*
2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
10 *
11 * Thanks to the following companies for their support:
12 *
13 * - JMicron (hardware and technical support)
14 */
15
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
25
26 #include <linux/leds.h>
27
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/sdio.h>
32 #include <linux/mmc/slot-gpio.h>
33
34 #include "sdhci.h"
35
36 #define DRIVER_NAME "sdhci"
37
38 #define DBG(f, x...) \
39 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40
41 #define MAX_TUNING_LOOP 40
42
43 static unsigned int debug_quirks = 0;
44 static unsigned int debug_quirks2;
45
46 static void sdhci_finish_data(struct sdhci_host *);
47
48 static void sdhci_finish_command(struct sdhci_host *);
49 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
50 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
51 static int sdhci_do_get_cd(struct sdhci_host *host);
52
53 static void sdhci_dumpregs(struct sdhci_host *host)
54 {
55 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
56 mmc_hostname(host->mmc));
57
58 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
59 sdhci_readl(host, SDHCI_DMA_ADDRESS),
60 sdhci_readw(host, SDHCI_HOST_VERSION));
61 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
62 sdhci_readw(host, SDHCI_BLOCK_SIZE),
63 sdhci_readw(host, SDHCI_BLOCK_COUNT));
64 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
65 sdhci_readl(host, SDHCI_ARGUMENT),
66 sdhci_readw(host, SDHCI_TRANSFER_MODE));
67 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
68 sdhci_readl(host, SDHCI_PRESENT_STATE),
69 sdhci_readb(host, SDHCI_HOST_CONTROL));
70 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
71 sdhci_readb(host, SDHCI_POWER_CONTROL),
72 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
73 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
74 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
75 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
76 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
77 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
78 sdhci_readl(host, SDHCI_INT_STATUS));
79 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
80 sdhci_readl(host, SDHCI_INT_ENABLE),
81 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
82 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
83 sdhci_readw(host, SDHCI_ACMD12_ERR),
84 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
85 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
86 sdhci_readl(host, SDHCI_CAPABILITIES),
87 sdhci_readl(host, SDHCI_CAPABILITIES_1));
88 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
89 sdhci_readw(host, SDHCI_COMMAND),
90 sdhci_readl(host, SDHCI_MAX_CURRENT));
91 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
92 sdhci_readw(host, SDHCI_HOST_CONTROL2));
93
94 if (host->flags & SDHCI_USE_ADMA) {
95 if (host->flags & SDHCI_USE_64_BIT_DMA)
96 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n",
97 readl(host->ioaddr + SDHCI_ADMA_ERROR),
98 readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI),
99 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
100 else
101 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
102 readl(host->ioaddr + SDHCI_ADMA_ERROR),
103 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
104 }
105
106 pr_debug(DRIVER_NAME ": ===========================================\n");
107 }
108
109 /*****************************************************************************\
110 * *
111 * Low level functions *
112 * *
113 \*****************************************************************************/
114
115 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
116 {
117 u32 present;
118
119 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
120 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
121 return;
122
123 if (enable) {
124 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
125 SDHCI_CARD_PRESENT;
126
127 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
128 SDHCI_INT_CARD_INSERT;
129 } else {
130 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
131 }
132
133 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
134 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
135 }
136
137 static void sdhci_enable_card_detection(struct sdhci_host *host)
138 {
139 sdhci_set_card_detection(host, true);
140 }
141
142 static void sdhci_disable_card_detection(struct sdhci_host *host)
143 {
144 sdhci_set_card_detection(host, false);
145 }
146
147 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
148 {
149 if (host->bus_on)
150 return;
151 host->bus_on = true;
152 pm_runtime_get_noresume(host->mmc->parent);
153 }
154
155 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
156 {
157 if (!host->bus_on)
158 return;
159 host->bus_on = false;
160 pm_runtime_put_noidle(host->mmc->parent);
161 }
162
163 void sdhci_reset(struct sdhci_host *host, u8 mask)
164 {
165 unsigned long timeout;
166
167 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
168
169 if (mask & SDHCI_RESET_ALL) {
170 host->clock = 0;
171 /* Reset-all turns off SD Bus Power */
172 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
173 sdhci_runtime_pm_bus_off(host);
174 }
175
176 /* Wait max 100 ms */
177 timeout = 100;
178
179 /* hw clears the bit when it's done */
180 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
181 if (timeout == 0) {
182 pr_err("%s: Reset 0x%x never completed.\n",
183 mmc_hostname(host->mmc), (int)mask);
184 sdhci_dumpregs(host);
185 return;
186 }
187 timeout--;
188 mdelay(1);
189 }
190 }
191 EXPORT_SYMBOL_GPL(sdhci_reset);
192
193 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
194 {
195 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
196 if (!sdhci_do_get_cd(host))
197 return;
198 }
199
200 host->ops->reset(host, mask);
201
202 if (mask & SDHCI_RESET_ALL) {
203 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
204 if (host->ops->enable_dma)
205 host->ops->enable_dma(host);
206 }
207
208 /* Resetting the controller clears many */
209 host->preset_enabled = false;
210 }
211 }
212
213 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
214
215 static void sdhci_init(struct sdhci_host *host, int soft)
216 {
217 if (soft)
218 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
219 else
220 sdhci_do_reset(host, SDHCI_RESET_ALL);
221
222 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
223 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
224 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
225 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
226 SDHCI_INT_RESPONSE;
227
228 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
229 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
230
231 if (soft) {
232 /* force clock reconfiguration */
233 host->clock = 0;
234 sdhci_set_ios(host->mmc, &host->mmc->ios);
235 }
236 }
237
238 static void sdhci_reinit(struct sdhci_host *host)
239 {
240 sdhci_init(host, 0);
241 sdhci_enable_card_detection(host);
242 }
243
244 static void __sdhci_led_activate(struct sdhci_host *host)
245 {
246 u8 ctrl;
247
248 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
249 ctrl |= SDHCI_CTRL_LED;
250 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
251 }
252
253 static void __sdhci_led_deactivate(struct sdhci_host *host)
254 {
255 u8 ctrl;
256
257 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
258 ctrl &= ~SDHCI_CTRL_LED;
259 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
260 }
261
262 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
263 defined(CONFIG_MMC_SDHCI_MODULE))
264
265 static void sdhci_led_control(struct led_classdev *led,
266 enum led_brightness brightness)
267 {
268 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
269 unsigned long flags;
270
271 spin_lock_irqsave(&host->lock, flags);
272
273 if (host->runtime_suspended)
274 goto out;
275
276 if (brightness == LED_OFF)
277 __sdhci_led_deactivate(host);
278 else
279 __sdhci_led_activate(host);
280 out:
281 spin_unlock_irqrestore(&host->lock, flags);
282 }
283
284 static int sdhci_led_register(struct sdhci_host *host)
285 {
286 struct mmc_host *mmc = host->mmc;
287
288 snprintf(host->led_name, sizeof(host->led_name),
289 "%s::", mmc_hostname(mmc));
290
291 host->led.name = host->led_name;
292 host->led.brightness = LED_OFF;
293 host->led.default_trigger = mmc_hostname(mmc);
294 host->led.brightness_set = sdhci_led_control;
295
296 return led_classdev_register(mmc_dev(mmc), &host->led);
297 }
298
299 static void sdhci_led_unregister(struct sdhci_host *host)
300 {
301 led_classdev_unregister(&host->led);
302 }
303
304 static inline void sdhci_led_activate(struct sdhci_host *host)
305 {
306 }
307
308 static inline void sdhci_led_deactivate(struct sdhci_host *host)
309 {
310 }
311
312 #else
313
314 static inline int sdhci_led_register(struct sdhci_host *host)
315 {
316 return 0;
317 }
318
319 static inline void sdhci_led_unregister(struct sdhci_host *host)
320 {
321 }
322
323 static inline void sdhci_led_activate(struct sdhci_host *host)
324 {
325 __sdhci_led_activate(host);
326 }
327
328 static inline void sdhci_led_deactivate(struct sdhci_host *host)
329 {
330 __sdhci_led_deactivate(host);
331 }
332
333 #endif
334
335 /*****************************************************************************\
336 * *
337 * Core functions *
338 * *
339 \*****************************************************************************/
340
341 static void sdhci_read_block_pio(struct sdhci_host *host)
342 {
343 unsigned long flags;
344 size_t blksize, len, chunk;
345 u32 uninitialized_var(scratch);
346 u8 *buf;
347
348 DBG("PIO reading\n");
349
350 blksize = host->data->blksz;
351 chunk = 0;
352
353 local_irq_save(flags);
354
355 while (blksize) {
356 BUG_ON(!sg_miter_next(&host->sg_miter));
357
358 len = min(host->sg_miter.length, blksize);
359
360 blksize -= len;
361 host->sg_miter.consumed = len;
362
363 buf = host->sg_miter.addr;
364
365 while (len) {
366 if (chunk == 0) {
367 scratch = sdhci_readl(host, SDHCI_BUFFER);
368 chunk = 4;
369 }
370
371 *buf = scratch & 0xFF;
372
373 buf++;
374 scratch >>= 8;
375 chunk--;
376 len--;
377 }
378 }
379
380 sg_miter_stop(&host->sg_miter);
381
382 local_irq_restore(flags);
383 }
384
385 static void sdhci_write_block_pio(struct sdhci_host *host)
386 {
387 unsigned long flags;
388 size_t blksize, len, chunk;
389 u32 scratch;
390 u8 *buf;
391
392 DBG("PIO writing\n");
393
394 blksize = host->data->blksz;
395 chunk = 0;
396 scratch = 0;
397
398 local_irq_save(flags);
399
400 while (blksize) {
401 BUG_ON(!sg_miter_next(&host->sg_miter));
402
403 len = min(host->sg_miter.length, blksize);
404
405 blksize -= len;
406 host->sg_miter.consumed = len;
407
408 buf = host->sg_miter.addr;
409
410 while (len) {
411 scratch |= (u32)*buf << (chunk * 8);
412
413 buf++;
414 chunk++;
415 len--;
416
417 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
418 sdhci_writel(host, scratch, SDHCI_BUFFER);
419 chunk = 0;
420 scratch = 0;
421 }
422 }
423 }
424
425 sg_miter_stop(&host->sg_miter);
426
427 local_irq_restore(flags);
428 }
429
430 static void sdhci_transfer_pio(struct sdhci_host *host)
431 {
432 u32 mask;
433
434 BUG_ON(!host->data);
435
436 if (host->blocks == 0)
437 return;
438
439 if (host->data->flags & MMC_DATA_READ)
440 mask = SDHCI_DATA_AVAILABLE;
441 else
442 mask = SDHCI_SPACE_AVAILABLE;
443
444 /*
445 * Some controllers (JMicron JMB38x) mess up the buffer bits
446 * for transfers < 4 bytes. As long as it is just one block,
447 * we can ignore the bits.
448 */
449 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
450 (host->data->blocks == 1))
451 mask = ~0;
452
453 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
454 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
455 udelay(100);
456
457 if (host->data->flags & MMC_DATA_READ)
458 sdhci_read_block_pio(host);
459 else
460 sdhci_write_block_pio(host);
461
462 host->blocks--;
463 if (host->blocks == 0)
464 break;
465 }
466
467 DBG("PIO transfer complete.\n");
468 }
469
470 static int sdhci_pre_dma_transfer(struct sdhci_host *host,
471 struct mmc_data *data, int cookie)
472 {
473 int sg_count;
474
475 /*
476 * If the data buffers are already mapped, return the previous
477 * dma_map_sg() result.
478 */
479 if (data->host_cookie == COOKIE_PRE_MAPPED)
480 return data->sg_count;
481
482 sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
483 data->flags & MMC_DATA_WRITE ?
484 DMA_TO_DEVICE : DMA_FROM_DEVICE);
485
486 if (sg_count == 0)
487 return -ENOSPC;
488
489 data->sg_count = sg_count;
490 data->host_cookie = cookie;
491
492 return sg_count;
493 }
494
495 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
496 {
497 local_irq_save(*flags);
498 return kmap_atomic(sg_page(sg)) + sg->offset;
499 }
500
501 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
502 {
503 kunmap_atomic(buffer);
504 local_irq_restore(*flags);
505 }
506
507 static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc,
508 dma_addr_t addr, int len, unsigned cmd)
509 {
510 struct sdhci_adma2_64_desc *dma_desc = desc;
511
512 /* 32-bit and 64-bit descriptors have these members in same position */
513 dma_desc->cmd = cpu_to_le16(cmd);
514 dma_desc->len = cpu_to_le16(len);
515 dma_desc->addr_lo = cpu_to_le32((u32)addr);
516
517 if (host->flags & SDHCI_USE_64_BIT_DMA)
518 dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32);
519 }
520
521 static void sdhci_adma_mark_end(void *desc)
522 {
523 struct sdhci_adma2_64_desc *dma_desc = desc;
524
525 /* 32-bit and 64-bit descriptors have 'cmd' in same position */
526 dma_desc->cmd |= cpu_to_le16(ADMA2_END);
527 }
528
529 static void sdhci_adma_table_pre(struct sdhci_host *host,
530 struct mmc_data *data, int sg_count)
531 {
532 struct scatterlist *sg;
533 unsigned long flags;
534 dma_addr_t addr, align_addr;
535 void *desc, *align;
536 char *buffer;
537 int len, offset, i;
538
539 /*
540 * The spec does not specify endianness of descriptor table.
541 * We currently guess that it is LE.
542 */
543
544 host->sg_count = sg_count;
545
546 desc = host->adma_table;
547 align = host->align_buffer;
548
549 align_addr = host->align_addr;
550
551 for_each_sg(data->sg, sg, host->sg_count, i) {
552 addr = sg_dma_address(sg);
553 len = sg_dma_len(sg);
554
555 /*
556 * The SDHCI specification states that ADMA addresses must
557 * be 32-bit aligned. If they aren't, then we use a bounce
558 * buffer for the (up to three) bytes that screw up the
559 * alignment.
560 */
561 offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) &
562 SDHCI_ADMA2_MASK;
563 if (offset) {
564 if (data->flags & MMC_DATA_WRITE) {
565 buffer = sdhci_kmap_atomic(sg, &flags);
566 memcpy(align, buffer, offset);
567 sdhci_kunmap_atomic(buffer, &flags);
568 }
569
570 /* tran, valid */
571 sdhci_adma_write_desc(host, desc, align_addr, offset,
572 ADMA2_TRAN_VALID);
573
574 BUG_ON(offset > 65536);
575
576 align += SDHCI_ADMA2_ALIGN;
577 align_addr += SDHCI_ADMA2_ALIGN;
578
579 desc += host->desc_sz;
580
581 addr += offset;
582 len -= offset;
583 }
584
585 BUG_ON(len > 65536);
586
587 if (len) {
588 /* tran, valid */
589 sdhci_adma_write_desc(host, desc, addr, len,
590 ADMA2_TRAN_VALID);
591 desc += host->desc_sz;
592 }
593
594 /*
595 * If this triggers then we have a calculation bug
596 * somewhere. :/
597 */
598 WARN_ON((desc - host->adma_table) >= host->adma_table_sz);
599 }
600
601 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
602 /* Mark the last descriptor as the terminating descriptor */
603 if (desc != host->adma_table) {
604 desc -= host->desc_sz;
605 sdhci_adma_mark_end(desc);
606 }
607 } else {
608 /* Add a terminating entry - nop, end, valid */
609 sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID);
610 }
611 }
612
613 static void sdhci_adma_table_post(struct sdhci_host *host,
614 struct mmc_data *data)
615 {
616 struct scatterlist *sg;
617 int i, size;
618 void *align;
619 char *buffer;
620 unsigned long flags;
621
622 if (data->flags & MMC_DATA_READ) {
623 bool has_unaligned = false;
624
625 /* Do a quick scan of the SG list for any unaligned mappings */
626 for_each_sg(data->sg, sg, host->sg_count, i)
627 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
628 has_unaligned = true;
629 break;
630 }
631
632 if (has_unaligned) {
633 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
634 data->sg_len, DMA_FROM_DEVICE);
635
636 align = host->align_buffer;
637
638 for_each_sg(data->sg, sg, host->sg_count, i) {
639 if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) {
640 size = SDHCI_ADMA2_ALIGN -
641 (sg_dma_address(sg) & SDHCI_ADMA2_MASK);
642
643 buffer = sdhci_kmap_atomic(sg, &flags);
644 memcpy(buffer, align, size);
645 sdhci_kunmap_atomic(buffer, &flags);
646
647 align += SDHCI_ADMA2_ALIGN;
648 }
649 }
650 }
651 }
652 }
653
654 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
655 {
656 u8 count;
657 struct mmc_data *data = cmd->data;
658 unsigned target_timeout, current_timeout;
659
660 /*
661 * If the host controller provides us with an incorrect timeout
662 * value, just skip the check and use 0xE. The hardware may take
663 * longer to time out, but that's much better than having a too-short
664 * timeout value.
665 */
666 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
667 return 0xE;
668
669 /* Unspecified timeout, assume max */
670 if (!data && !cmd->busy_timeout)
671 return 0xE;
672
673 /* timeout in us */
674 if (!data)
675 target_timeout = cmd->busy_timeout * 1000;
676 else {
677 target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000);
678 if (host->clock && data->timeout_clks) {
679 unsigned long long val;
680
681 /*
682 * data->timeout_clks is in units of clock cycles.
683 * host->clock is in Hz. target_timeout is in us.
684 * Hence, us = 1000000 * cycles / Hz. Round up.
685 */
686 val = 1000000 * data->timeout_clks;
687 if (do_div(val, host->clock))
688 target_timeout++;
689 target_timeout += val;
690 }
691 }
692
693 /*
694 * Figure out needed cycles.
695 * We do this in steps in order to fit inside a 32 bit int.
696 * The first step is the minimum timeout, which will have a
697 * minimum resolution of 6 bits:
698 * (1) 2^13*1000 > 2^22,
699 * (2) host->timeout_clk < 2^16
700 * =>
701 * (1) / (2) > 2^6
702 */
703 count = 0;
704 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
705 while (current_timeout < target_timeout) {
706 count++;
707 current_timeout <<= 1;
708 if (count >= 0xF)
709 break;
710 }
711
712 if (count >= 0xF) {
713 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
714 mmc_hostname(host->mmc), count, cmd->opcode);
715 count = 0xE;
716 }
717
718 return count;
719 }
720
721 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
722 {
723 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
724 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
725
726 if (host->flags & SDHCI_REQ_USE_DMA)
727 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
728 else
729 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
730
731 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
732 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
733 }
734
735 static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd)
736 {
737 u8 count;
738
739 if (host->ops->set_timeout) {
740 host->ops->set_timeout(host, cmd);
741 } else {
742 count = sdhci_calc_timeout(host, cmd);
743 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
744 }
745 }
746
747 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
748 {
749 u8 ctrl;
750 struct mmc_data *data = cmd->data;
751
752 WARN_ON(host->data);
753
754 if (data || (cmd->flags & MMC_RSP_BUSY))
755 sdhci_set_timeout(host, cmd);
756
757 if (!data)
758 return;
759
760 /* Sanity checks */
761 BUG_ON(data->blksz * data->blocks > 524288);
762 BUG_ON(data->blksz > host->mmc->max_blk_size);
763 BUG_ON(data->blocks > 65535);
764
765 host->data = data;
766 host->data_early = 0;
767 host->data->bytes_xfered = 0;
768
769 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
770 struct scatterlist *sg;
771 unsigned int length_mask, offset_mask;
772 int i;
773
774 host->flags |= SDHCI_REQ_USE_DMA;
775
776 /*
777 * FIXME: This doesn't account for merging when mapping the
778 * scatterlist.
779 *
780 * The assumption here being that alignment and lengths are
781 * the same after DMA mapping to device address space.
782 */
783 length_mask = 0;
784 offset_mask = 0;
785 if (host->flags & SDHCI_USE_ADMA) {
786 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) {
787 length_mask = 3;
788 /*
789 * As we use up to 3 byte chunks to work
790 * around alignment problems, we need to
791 * check the offset as well.
792 */
793 offset_mask = 3;
794 }
795 } else {
796 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
797 length_mask = 3;
798 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
799 offset_mask = 3;
800 }
801
802 if (unlikely(length_mask | offset_mask)) {
803 for_each_sg(data->sg, sg, data->sg_len, i) {
804 if (sg->length & length_mask) {
805 DBG("Reverting to PIO because of transfer size (%d)\n",
806 sg->length);
807 host->flags &= ~SDHCI_REQ_USE_DMA;
808 break;
809 }
810 if (sg->offset & offset_mask) {
811 DBG("Reverting to PIO because of bad alignment\n");
812 host->flags &= ~SDHCI_REQ_USE_DMA;
813 break;
814 }
815 }
816 }
817 }
818
819 if (host->flags & SDHCI_REQ_USE_DMA) {
820 int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED);
821
822 if (sg_cnt <= 0) {
823 /*
824 * This only happens when someone fed
825 * us an invalid request.
826 */
827 WARN_ON(1);
828 host->flags &= ~SDHCI_REQ_USE_DMA;
829 } else if (host->flags & SDHCI_USE_ADMA) {
830 sdhci_adma_table_pre(host, data, sg_cnt);
831
832 sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS);
833 if (host->flags & SDHCI_USE_64_BIT_DMA)
834 sdhci_writel(host,
835 (u64)host->adma_addr >> 32,
836 SDHCI_ADMA_ADDRESS_HI);
837 } else {
838 WARN_ON(sg_cnt != 1);
839 sdhci_writel(host, sg_dma_address(data->sg),
840 SDHCI_DMA_ADDRESS);
841 }
842 }
843
844 /*
845 * Always adjust the DMA selection as some controllers
846 * (e.g. JMicron) can't do PIO properly when the selection
847 * is ADMA.
848 */
849 if (host->version >= SDHCI_SPEC_200) {
850 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
851 ctrl &= ~SDHCI_CTRL_DMA_MASK;
852 if ((host->flags & SDHCI_REQ_USE_DMA) &&
853 (host->flags & SDHCI_USE_ADMA)) {
854 if (host->flags & SDHCI_USE_64_BIT_DMA)
855 ctrl |= SDHCI_CTRL_ADMA64;
856 else
857 ctrl |= SDHCI_CTRL_ADMA32;
858 } else {
859 ctrl |= SDHCI_CTRL_SDMA;
860 }
861 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
862 }
863
864 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
865 int flags;
866
867 flags = SG_MITER_ATOMIC;
868 if (host->data->flags & MMC_DATA_READ)
869 flags |= SG_MITER_TO_SG;
870 else
871 flags |= SG_MITER_FROM_SG;
872 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
873 host->blocks = data->blocks;
874 }
875
876 sdhci_set_transfer_irqs(host);
877
878 /* Set the DMA boundary value and block size */
879 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
880 data->blksz), SDHCI_BLOCK_SIZE);
881 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
882 }
883
884 static void sdhci_set_transfer_mode(struct sdhci_host *host,
885 struct mmc_command *cmd)
886 {
887 u16 mode = 0;
888 struct mmc_data *data = cmd->data;
889
890 if (data == NULL) {
891 if (host->quirks2 &
892 SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) {
893 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
894 } else {
895 /* clear Auto CMD settings for no data CMDs */
896 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
897 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
898 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
899 }
900 return;
901 }
902
903 WARN_ON(!host->data);
904
905 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE))
906 mode = SDHCI_TRNS_BLK_CNT_EN;
907
908 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
909 mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI;
910 /*
911 * If we are sending CMD23, CMD12 never gets sent
912 * on successful completion (so no Auto-CMD12).
913 */
914 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12) &&
915 (cmd->opcode != SD_IO_RW_EXTENDED))
916 mode |= SDHCI_TRNS_AUTO_CMD12;
917 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
918 mode |= SDHCI_TRNS_AUTO_CMD23;
919 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
920 }
921 }
922
923 if (data->flags & MMC_DATA_READ)
924 mode |= SDHCI_TRNS_READ;
925 if (host->flags & SDHCI_REQ_USE_DMA)
926 mode |= SDHCI_TRNS_DMA;
927
928 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
929 }
930
931 static void sdhci_finish_data(struct sdhci_host *host)
932 {
933 struct mmc_data *data;
934
935 BUG_ON(!host->data);
936
937 data = host->data;
938 host->data = NULL;
939
940 if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) ==
941 (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA))
942 sdhci_adma_table_post(host, data);
943
944 /*
945 * The specification states that the block count register must
946 * be updated, but it does not specify at what point in the
947 * data flow. That makes the register entirely useless to read
948 * back so we have to assume that nothing made it to the card
949 * in the event of an error.
950 */
951 if (data->error)
952 data->bytes_xfered = 0;
953 else
954 data->bytes_xfered = data->blksz * data->blocks;
955
956 /*
957 * Need to send CMD12 if -
958 * a) open-ended multiblock transfer (no CMD23)
959 * b) error in multiblock transfer
960 */
961 if (data->stop &&
962 (data->error ||
963 !host->mrq->sbc)) {
964
965 /*
966 * The controller needs a reset of internal state machines
967 * upon error conditions.
968 */
969 if (data->error) {
970 sdhci_do_reset(host, SDHCI_RESET_CMD);
971 sdhci_do_reset(host, SDHCI_RESET_DATA);
972 }
973
974 sdhci_send_command(host, data->stop);
975 } else
976 tasklet_schedule(&host->finish_tasklet);
977 }
978
979 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
980 {
981 int flags;
982 u32 mask;
983 unsigned long timeout;
984
985 WARN_ON(host->cmd);
986
987 /* Initially, a command has no error */
988 cmd->error = 0;
989
990 /* Wait max 10 ms */
991 timeout = 10;
992
993 mask = SDHCI_CMD_INHIBIT;
994 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
995 mask |= SDHCI_DATA_INHIBIT;
996
997 /* We shouldn't wait for data inihibit for stop commands, even
998 though they might use busy signaling */
999 if (host->mrq->data && (cmd == host->mrq->data->stop))
1000 mask &= ~SDHCI_DATA_INHIBIT;
1001
1002 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1003 if (timeout == 0) {
1004 pr_err("%s: Controller never released inhibit bit(s).\n",
1005 mmc_hostname(host->mmc));
1006 sdhci_dumpregs(host);
1007 cmd->error = -EIO;
1008 tasklet_schedule(&host->finish_tasklet);
1009 return;
1010 }
1011 timeout--;
1012 mdelay(1);
1013 }
1014
1015 timeout = jiffies;
1016 if (!cmd->data && cmd->busy_timeout > 9000)
1017 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1018 else
1019 timeout += 10 * HZ;
1020 mod_timer(&host->timer, timeout);
1021
1022 host->cmd = cmd;
1023 host->busy_handle = 0;
1024
1025 sdhci_prepare_data(host, cmd);
1026
1027 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1028
1029 sdhci_set_transfer_mode(host, cmd);
1030
1031 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1032 pr_err("%s: Unsupported response type!\n",
1033 mmc_hostname(host->mmc));
1034 cmd->error = -EINVAL;
1035 tasklet_schedule(&host->finish_tasklet);
1036 return;
1037 }
1038
1039 if (!(cmd->flags & MMC_RSP_PRESENT))
1040 flags = SDHCI_CMD_RESP_NONE;
1041 else if (cmd->flags & MMC_RSP_136)
1042 flags = SDHCI_CMD_RESP_LONG;
1043 else if (cmd->flags & MMC_RSP_BUSY)
1044 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1045 else
1046 flags = SDHCI_CMD_RESP_SHORT;
1047
1048 if (cmd->flags & MMC_RSP_CRC)
1049 flags |= SDHCI_CMD_CRC;
1050 if (cmd->flags & MMC_RSP_OPCODE)
1051 flags |= SDHCI_CMD_INDEX;
1052
1053 /* CMD19 is special in that the Data Present Select should be set */
1054 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1055 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1056 flags |= SDHCI_CMD_DATA;
1057
1058 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1059 }
1060 EXPORT_SYMBOL_GPL(sdhci_send_command);
1061
1062 static void sdhci_finish_command(struct sdhci_host *host)
1063 {
1064 int i;
1065
1066 BUG_ON(host->cmd == NULL);
1067
1068 if (host->cmd->flags & MMC_RSP_PRESENT) {
1069 if (host->cmd->flags & MMC_RSP_136) {
1070 /* CRC is stripped so we need to do some shifting. */
1071 for (i = 0;i < 4;i++) {
1072 host->cmd->resp[i] = sdhci_readl(host,
1073 SDHCI_RESPONSE + (3-i)*4) << 8;
1074 if (i != 3)
1075 host->cmd->resp[i] |=
1076 sdhci_readb(host,
1077 SDHCI_RESPONSE + (3-i)*4-1);
1078 }
1079 } else {
1080 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1081 }
1082 }
1083
1084 /* Finished CMD23, now send actual command. */
1085 if (host->cmd == host->mrq->sbc) {
1086 host->cmd = NULL;
1087 sdhci_send_command(host, host->mrq->cmd);
1088 } else {
1089
1090 /* Processed actual command. */
1091 if (host->data && host->data_early)
1092 sdhci_finish_data(host);
1093
1094 if (!host->cmd->data)
1095 tasklet_schedule(&host->finish_tasklet);
1096
1097 host->cmd = NULL;
1098 }
1099 }
1100
1101 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1102 {
1103 u16 preset = 0;
1104
1105 switch (host->timing) {
1106 case MMC_TIMING_UHS_SDR12:
1107 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1108 break;
1109 case MMC_TIMING_UHS_SDR25:
1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1111 break;
1112 case MMC_TIMING_UHS_SDR50:
1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1114 break;
1115 case MMC_TIMING_UHS_SDR104:
1116 case MMC_TIMING_MMC_HS200:
1117 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1118 break;
1119 case MMC_TIMING_UHS_DDR50:
1120 case MMC_TIMING_MMC_DDR52:
1121 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1122 break;
1123 case MMC_TIMING_MMC_HS400:
1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400);
1125 break;
1126 default:
1127 pr_warn("%s: Invalid UHS-I mode selected\n",
1128 mmc_hostname(host->mmc));
1129 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1130 break;
1131 }
1132 return preset;
1133 }
1134
1135 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
1136 unsigned int *actual_clock)
1137 {
1138 int div = 0; /* Initialized for compiler warning */
1139 int real_div = div, clk_mul = 1;
1140 u16 clk = 0;
1141 bool switch_base_clk = false;
1142
1143 if (host->version >= SDHCI_SPEC_300) {
1144 if (host->preset_enabled) {
1145 u16 pre_val;
1146
1147 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1148 pre_val = sdhci_get_preset_value(host);
1149 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1150 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1151 if (host->clk_mul &&
1152 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1153 clk = SDHCI_PROG_CLOCK_MODE;
1154 real_div = div + 1;
1155 clk_mul = host->clk_mul;
1156 } else {
1157 real_div = max_t(int, 1, div << 1);
1158 }
1159 goto clock_set;
1160 }
1161
1162 /*
1163 * Check if the Host Controller supports Programmable Clock
1164 * Mode.
1165 */
1166 if (host->clk_mul) {
1167 for (div = 1; div <= 1024; div++) {
1168 if ((host->max_clk * host->clk_mul / div)
1169 <= clock)
1170 break;
1171 }
1172 if ((host->max_clk * host->clk_mul / div) <= clock) {
1173 /*
1174 * Set Programmable Clock Mode in the Clock
1175 * Control register.
1176 */
1177 clk = SDHCI_PROG_CLOCK_MODE;
1178 real_div = div;
1179 clk_mul = host->clk_mul;
1180 div--;
1181 } else {
1182 /*
1183 * Divisor can be too small to reach clock
1184 * speed requirement. Then use the base clock.
1185 */
1186 switch_base_clk = true;
1187 }
1188 }
1189
1190 if (!host->clk_mul || switch_base_clk) {
1191 /* Version 3.00 divisors must be a multiple of 2. */
1192 if (host->max_clk <= clock)
1193 div = 1;
1194 else {
1195 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1196 div += 2) {
1197 if ((host->max_clk / div) <= clock)
1198 break;
1199 }
1200 }
1201 real_div = div;
1202 div >>= 1;
1203 if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN)
1204 && !div && host->max_clk <= 25000000)
1205 div = 1;
1206 }
1207 } else {
1208 /* Version 2.00 divisors must be a power of 2. */
1209 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1210 if ((host->max_clk / div) <= clock)
1211 break;
1212 }
1213 real_div = div;
1214 div >>= 1;
1215 }
1216
1217 clock_set:
1218 if (real_div)
1219 *actual_clock = (host->max_clk * clk_mul) / real_div;
1220 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1221 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1222 << SDHCI_DIVIDER_HI_SHIFT;
1223
1224 return clk;
1225 }
1226 EXPORT_SYMBOL_GPL(sdhci_calc_clk);
1227
1228 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1229 {
1230 u16 clk;
1231 unsigned long timeout;
1232
1233 host->mmc->actual_clock = 0;
1234
1235 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1236
1237 if (clock == 0)
1238 return;
1239
1240 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
1241
1242 clk |= SDHCI_CLOCK_INT_EN;
1243 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1244
1245 /* Wait max 20 ms */
1246 timeout = 20;
1247 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1248 & SDHCI_CLOCK_INT_STABLE)) {
1249 if (timeout == 0) {
1250 pr_err("%s: Internal clock never stabilised.\n",
1251 mmc_hostname(host->mmc));
1252 sdhci_dumpregs(host);
1253 return;
1254 }
1255 timeout--;
1256 mdelay(1);
1257 }
1258
1259 clk |= SDHCI_CLOCK_CARD_EN;
1260 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1261 }
1262 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1263
1264 static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode,
1265 unsigned short vdd)
1266 {
1267 struct mmc_host *mmc = host->mmc;
1268
1269 spin_unlock_irq(&host->lock);
1270 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
1271 spin_lock_irq(&host->lock);
1272
1273 if (mode != MMC_POWER_OFF)
1274 sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1275 else
1276 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1277 }
1278
1279 void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1280 unsigned short vdd)
1281 {
1282 u8 pwr = 0;
1283
1284 if (mode != MMC_POWER_OFF) {
1285 switch (1 << vdd) {
1286 case MMC_VDD_165_195:
1287 pwr = SDHCI_POWER_180;
1288 break;
1289 case MMC_VDD_29_30:
1290 case MMC_VDD_30_31:
1291 pwr = SDHCI_POWER_300;
1292 break;
1293 case MMC_VDD_32_33:
1294 case MMC_VDD_33_34:
1295 pwr = SDHCI_POWER_330;
1296 break;
1297 default:
1298 WARN(1, "%s: Invalid vdd %#x\n",
1299 mmc_hostname(host->mmc), vdd);
1300 break;
1301 }
1302 }
1303
1304 if (host->pwr == pwr)
1305 return;
1306
1307 host->pwr = pwr;
1308
1309 if (pwr == 0) {
1310 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1311 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1312 sdhci_runtime_pm_bus_off(host);
1313 } else {
1314 /*
1315 * Spec says that we should clear the power reg before setting
1316 * a new value. Some controllers don't seem to like this though.
1317 */
1318 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1319 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1320
1321 /*
1322 * At least the Marvell CaFe chip gets confused if we set the
1323 * voltage and set turn on power at the same time, so set the
1324 * voltage first.
1325 */
1326 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1327 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1328
1329 pwr |= SDHCI_POWER_ON;
1330
1331 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1332
1333 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1334 sdhci_runtime_pm_bus_on(host);
1335
1336 /*
1337 * Some controllers need an extra 10ms delay of 10ms before
1338 * they can apply clock after applying power
1339 */
1340 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1341 mdelay(10);
1342 }
1343 }
1344 EXPORT_SYMBOL_GPL(sdhci_set_power);
1345
1346 static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1347 unsigned short vdd)
1348 {
1349 struct mmc_host *mmc = host->mmc;
1350
1351 if (host->ops->set_power)
1352 host->ops->set_power(host, mode, vdd);
1353 else if (!IS_ERR(mmc->supply.vmmc))
1354 sdhci_set_power_reg(host, mode, vdd);
1355 else
1356 sdhci_set_power(host, mode, vdd);
1357 }
1358
1359 /*****************************************************************************\
1360 * *
1361 * MMC callbacks *
1362 * *
1363 \*****************************************************************************/
1364
1365 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1366 {
1367 struct sdhci_host *host;
1368 int present;
1369 unsigned long flags;
1370
1371 host = mmc_priv(mmc);
1372
1373 /* Firstly check card presence */
1374 present = mmc->ops->get_cd(mmc);
1375
1376 spin_lock_irqsave(&host->lock, flags);
1377
1378 WARN_ON(host->mrq != NULL);
1379
1380 sdhci_led_activate(host);
1381
1382 /*
1383 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1384 * requests if Auto-CMD12 is enabled.
1385 */
1386 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1387 if (mrq->stop) {
1388 mrq->data->stop = NULL;
1389 mrq->stop = NULL;
1390 }
1391 }
1392
1393 host->mrq = mrq;
1394
1395 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1396 host->mrq->cmd->error = -ENOMEDIUM;
1397 tasklet_schedule(&host->finish_tasklet);
1398 } else {
1399 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1400 sdhci_send_command(host, mrq->sbc);
1401 else
1402 sdhci_send_command(host, mrq->cmd);
1403 }
1404
1405 mmiowb();
1406 spin_unlock_irqrestore(&host->lock, flags);
1407 }
1408
1409 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1410 {
1411 u8 ctrl;
1412
1413 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1414 if (width == MMC_BUS_WIDTH_8) {
1415 ctrl &= ~SDHCI_CTRL_4BITBUS;
1416 if (host->version >= SDHCI_SPEC_300)
1417 ctrl |= SDHCI_CTRL_8BITBUS;
1418 } else {
1419 if (host->version >= SDHCI_SPEC_300)
1420 ctrl &= ~SDHCI_CTRL_8BITBUS;
1421 if (width == MMC_BUS_WIDTH_4)
1422 ctrl |= SDHCI_CTRL_4BITBUS;
1423 else
1424 ctrl &= ~SDHCI_CTRL_4BITBUS;
1425 }
1426 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1427 }
1428 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1429
1430 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1431 {
1432 u16 ctrl_2;
1433
1434 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1435 /* Select Bus Speed Mode for host */
1436 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1437 if ((timing == MMC_TIMING_MMC_HS200) ||
1438 (timing == MMC_TIMING_UHS_SDR104))
1439 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1440 else if (timing == MMC_TIMING_UHS_SDR12)
1441 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1442 else if (timing == MMC_TIMING_UHS_SDR25)
1443 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1444 else if (timing == MMC_TIMING_UHS_SDR50)
1445 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1446 else if ((timing == MMC_TIMING_UHS_DDR50) ||
1447 (timing == MMC_TIMING_MMC_DDR52))
1448 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1449 else if (timing == MMC_TIMING_MMC_HS400)
1450 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1451 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1452 }
1453 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1454
1455 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1456 {
1457 unsigned long flags;
1458 u8 ctrl;
1459 struct mmc_host *mmc = host->mmc;
1460
1461 spin_lock_irqsave(&host->lock, flags);
1462
1463 if (host->flags & SDHCI_DEVICE_DEAD) {
1464 spin_unlock_irqrestore(&host->lock, flags);
1465 if (!IS_ERR(mmc->supply.vmmc) &&
1466 ios->power_mode == MMC_POWER_OFF)
1467 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1468 return;
1469 }
1470
1471 /*
1472 * Reset the chip on each power off.
1473 * Should clear out any weird states.
1474 */
1475 if (ios->power_mode == MMC_POWER_OFF) {
1476 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1477 sdhci_reinit(host);
1478 }
1479
1480 if (host->version >= SDHCI_SPEC_300 &&
1481 (ios->power_mode == MMC_POWER_UP) &&
1482 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1483 sdhci_enable_preset_value(host, false);
1484
1485 if (!ios->clock || ios->clock != host->clock) {
1486 host->ops->set_clock(host, ios->clock);
1487 host->clock = ios->clock;
1488
1489 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK &&
1490 host->clock) {
1491 host->timeout_clk = host->mmc->actual_clock ?
1492 host->mmc->actual_clock / 1000 :
1493 host->clock / 1000;
1494 host->mmc->max_busy_timeout =
1495 host->ops->get_max_timeout_count ?
1496 host->ops->get_max_timeout_count(host) :
1497 1 << 27;
1498 host->mmc->max_busy_timeout /= host->timeout_clk;
1499 }
1500 }
1501
1502 __sdhci_set_power(host, ios->power_mode, ios->vdd);
1503
1504 if (host->ops->platform_send_init_74_clocks)
1505 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1506
1507 host->ops->set_bus_width(host, ios->bus_width);
1508
1509 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1510
1511 if ((ios->timing == MMC_TIMING_SD_HS ||
1512 ios->timing == MMC_TIMING_MMC_HS)
1513 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1514 ctrl |= SDHCI_CTRL_HISPD;
1515 else
1516 ctrl &= ~SDHCI_CTRL_HISPD;
1517
1518 if (host->version >= SDHCI_SPEC_300) {
1519 u16 clk, ctrl_2;
1520
1521 /* In case of UHS-I modes, set High Speed Enable */
1522 if ((ios->timing == MMC_TIMING_MMC_HS400) ||
1523 (ios->timing == MMC_TIMING_MMC_HS200) ||
1524 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1525 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1526 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1527 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1528 (ios->timing == MMC_TIMING_UHS_SDR25))
1529 ctrl |= SDHCI_CTRL_HISPD;
1530
1531 if (!host->preset_enabled) {
1532 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1533 /*
1534 * We only need to set Driver Strength if the
1535 * preset value enable is not set.
1536 */
1537 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1538 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1539 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1540 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1541 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B)
1542 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1543 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1544 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1545 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D)
1546 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D;
1547 else {
1548 pr_warn("%s: invalid driver type, default to driver type B\n",
1549 mmc_hostname(mmc));
1550 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B;
1551 }
1552
1553 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1554 } else {
1555 /*
1556 * According to SDHC Spec v3.00, if the Preset Value
1557 * Enable in the Host Control 2 register is set, we
1558 * need to reset SD Clock Enable before changing High
1559 * Speed Enable to avoid generating clock gliches.
1560 */
1561
1562 /* Reset SD Clock Enable */
1563 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1564 clk &= ~SDHCI_CLOCK_CARD_EN;
1565 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1566
1567 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1568
1569 /* Re-enable SD Clock */
1570 host->ops->set_clock(host, host->clock);
1571 }
1572
1573 /* Reset SD Clock Enable */
1574 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1575 clk &= ~SDHCI_CLOCK_CARD_EN;
1576 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1577
1578 host->ops->set_uhs_signaling(host, ios->timing);
1579 host->timing = ios->timing;
1580
1581 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1582 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1583 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1584 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1585 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1586 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1587 (ios->timing == MMC_TIMING_MMC_DDR52))) {
1588 u16 preset;
1589
1590 sdhci_enable_preset_value(host, true);
1591 preset = sdhci_get_preset_value(host);
1592 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1593 >> SDHCI_PRESET_DRV_SHIFT;
1594 }
1595
1596 /* Re-enable SD Clock */
1597 host->ops->set_clock(host, host->clock);
1598 } else
1599 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1600
1601 /*
1602 * Some (ENE) controllers go apeshit on some ios operation,
1603 * signalling timeout and CRC errors even on CMD0. Resetting
1604 * it on each ios seems to solve the problem.
1605 */
1606 if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1607 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1608
1609 mmiowb();
1610 spin_unlock_irqrestore(&host->lock, flags);
1611 }
1612
1613 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1614 {
1615 struct sdhci_host *host = mmc_priv(mmc);
1616
1617 sdhci_do_set_ios(host, ios);
1618 }
1619
1620 static int sdhci_do_get_cd(struct sdhci_host *host)
1621 {
1622 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1623
1624 if (host->flags & SDHCI_DEVICE_DEAD)
1625 return 0;
1626
1627 /* If nonremovable, assume that the card is always present. */
1628 if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
1629 return 1;
1630
1631 /*
1632 * Try slot gpio detect, if defined it take precedence
1633 * over build in controller functionality
1634 */
1635 if (!IS_ERR_VALUE(gpio_cd))
1636 return !!gpio_cd;
1637
1638 /* If polling, assume that the card is always present. */
1639 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1640 return 1;
1641
1642 /* Host native card detect */
1643 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1644 }
1645
1646 static int sdhci_get_cd(struct mmc_host *mmc)
1647 {
1648 struct sdhci_host *host = mmc_priv(mmc);
1649
1650 return sdhci_do_get_cd(host);
1651 }
1652
1653 static int sdhci_check_ro(struct sdhci_host *host)
1654 {
1655 unsigned long flags;
1656 int is_readonly;
1657
1658 spin_lock_irqsave(&host->lock, flags);
1659
1660 if (host->flags & SDHCI_DEVICE_DEAD)
1661 is_readonly = 0;
1662 else if (host->ops->get_ro)
1663 is_readonly = host->ops->get_ro(host);
1664 else
1665 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1666 & SDHCI_WRITE_PROTECT);
1667
1668 spin_unlock_irqrestore(&host->lock, flags);
1669
1670 /* This quirk needs to be replaced by a callback-function later */
1671 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1672 !is_readonly : is_readonly;
1673 }
1674
1675 #define SAMPLE_COUNT 5
1676
1677 static int sdhci_do_get_ro(struct sdhci_host *host)
1678 {
1679 int i, ro_count;
1680
1681 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1682 return sdhci_check_ro(host);
1683
1684 ro_count = 0;
1685 for (i = 0; i < SAMPLE_COUNT; i++) {
1686 if (sdhci_check_ro(host)) {
1687 if (++ro_count > SAMPLE_COUNT / 2)
1688 return 1;
1689 }
1690 msleep(30);
1691 }
1692 return 0;
1693 }
1694
1695 static void sdhci_hw_reset(struct mmc_host *mmc)
1696 {
1697 struct sdhci_host *host = mmc_priv(mmc);
1698
1699 if (host->ops && host->ops->hw_reset)
1700 host->ops->hw_reset(host);
1701 }
1702
1703 static int sdhci_get_ro(struct mmc_host *mmc)
1704 {
1705 struct sdhci_host *host = mmc_priv(mmc);
1706
1707 return sdhci_do_get_ro(host);
1708 }
1709
1710 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1711 {
1712 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1713 if (enable)
1714 host->ier |= SDHCI_INT_CARD_INT;
1715 else
1716 host->ier &= ~SDHCI_INT_CARD_INT;
1717
1718 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1719 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1720 mmiowb();
1721 }
1722 }
1723
1724 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1725 {
1726 struct sdhci_host *host = mmc_priv(mmc);
1727 unsigned long flags;
1728
1729 spin_lock_irqsave(&host->lock, flags);
1730 if (enable)
1731 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1732 else
1733 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1734
1735 sdhci_enable_sdio_irq_nolock(host, enable);
1736 spin_unlock_irqrestore(&host->lock, flags);
1737 }
1738
1739 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1740 struct mmc_ios *ios)
1741 {
1742 struct mmc_host *mmc = host->mmc;
1743 u16 ctrl;
1744 int ret;
1745
1746 /*
1747 * Signal Voltage Switching is only applicable for Host Controllers
1748 * v3.00 and above.
1749 */
1750 if (host->version < SDHCI_SPEC_300)
1751 return 0;
1752
1753 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1754
1755 switch (ios->signal_voltage) {
1756 case MMC_SIGNAL_VOLTAGE_330:
1757 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1758 ctrl &= ~SDHCI_CTRL_VDD_180;
1759 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1760
1761 if (!IS_ERR(mmc->supply.vqmmc)) {
1762 ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000,
1763 3600000);
1764 if (ret) {
1765 pr_warn("%s: Switching to 3.3V signalling voltage failed\n",
1766 mmc_hostname(mmc));
1767 return -EIO;
1768 }
1769 }
1770 /* Wait for 5ms */
1771 usleep_range(5000, 5500);
1772
1773 /* 3.3V regulator output should be stable within 5 ms */
1774 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1775 if (!(ctrl & SDHCI_CTRL_VDD_180))
1776 return 0;
1777
1778 pr_warn("%s: 3.3V regulator output did not became stable\n",
1779 mmc_hostname(mmc));
1780
1781 return -EAGAIN;
1782 case MMC_SIGNAL_VOLTAGE_180:
1783 if (!IS_ERR(mmc->supply.vqmmc)) {
1784 ret = regulator_set_voltage(mmc->supply.vqmmc,
1785 1700000, 1950000);
1786 if (ret) {
1787 pr_warn("%s: Switching to 1.8V signalling voltage failed\n",
1788 mmc_hostname(mmc));
1789 return -EIO;
1790 }
1791 }
1792
1793 /*
1794 * Enable 1.8V Signal Enable in the Host Control2
1795 * register
1796 */
1797 ctrl |= SDHCI_CTRL_VDD_180;
1798 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1799
1800 /* Some controller need to do more when switching */
1801 if (host->ops->voltage_switch)
1802 host->ops->voltage_switch(host);
1803
1804 /* 1.8V regulator output should be stable within 5 ms */
1805 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1806 if (ctrl & SDHCI_CTRL_VDD_180)
1807 return 0;
1808
1809 pr_warn("%s: 1.8V regulator output did not became stable\n",
1810 mmc_hostname(mmc));
1811
1812 return -EAGAIN;
1813 case MMC_SIGNAL_VOLTAGE_120:
1814 if (!IS_ERR(mmc->supply.vqmmc)) {
1815 ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000,
1816 1300000);
1817 if (ret) {
1818 pr_warn("%s: Switching to 1.2V signalling voltage failed\n",
1819 mmc_hostname(mmc));
1820 return -EIO;
1821 }
1822 }
1823 return 0;
1824 default:
1825 /* No signal voltage switch required */
1826 return 0;
1827 }
1828 }
1829
1830 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1831 struct mmc_ios *ios)
1832 {
1833 struct sdhci_host *host = mmc_priv(mmc);
1834
1835 if (host->version < SDHCI_SPEC_300)
1836 return 0;
1837
1838 return sdhci_do_start_signal_voltage_switch(host, ios);
1839 }
1840
1841 static int sdhci_card_busy(struct mmc_host *mmc)
1842 {
1843 struct sdhci_host *host = mmc_priv(mmc);
1844 u32 present_state;
1845
1846 /* Check whether DAT[3:0] is 0000 */
1847 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1848
1849 return !(present_state & SDHCI_DATA_LVL_MASK);
1850 }
1851
1852 static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
1853 {
1854 struct sdhci_host *host = mmc_priv(mmc);
1855 unsigned long flags;
1856
1857 spin_lock_irqsave(&host->lock, flags);
1858 host->flags |= SDHCI_HS400_TUNING;
1859 spin_unlock_irqrestore(&host->lock, flags);
1860
1861 return 0;
1862 }
1863
1864 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1865 {
1866 struct sdhci_host *host = mmc_priv(mmc);
1867 u16 ctrl;
1868 int tuning_loop_counter = MAX_TUNING_LOOP;
1869 int err = 0;
1870 unsigned long flags;
1871 unsigned int tuning_count = 0;
1872 bool hs400_tuning;
1873
1874 spin_lock_irqsave(&host->lock, flags);
1875
1876 hs400_tuning = host->flags & SDHCI_HS400_TUNING;
1877 host->flags &= ~SDHCI_HS400_TUNING;
1878
1879 if (host->tuning_mode == SDHCI_TUNING_MODE_1)
1880 tuning_count = host->tuning_count;
1881
1882 /*
1883 * The Host Controller needs tuning in case of SDR104 and DDR50
1884 * mode, and for SDR50 mode when Use Tuning for SDR50 is set in
1885 * the Capabilities register.
1886 * If the Host Controller supports the HS200 mode then the
1887 * tuning function has to be executed.
1888 */
1889 switch (host->timing) {
1890 /* HS400 tuning is done in HS200 mode */
1891 case MMC_TIMING_MMC_HS400:
1892 err = -EINVAL;
1893 goto out_unlock;
1894
1895 case MMC_TIMING_MMC_HS200:
1896 /*
1897 * Periodic re-tuning for HS400 is not expected to be needed, so
1898 * disable it here.
1899 */
1900 if (hs400_tuning)
1901 tuning_count = 0;
1902 break;
1903
1904 case MMC_TIMING_UHS_SDR104:
1905 case MMC_TIMING_UHS_DDR50:
1906 break;
1907
1908 case MMC_TIMING_UHS_SDR50:
1909 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1910 host->flags & SDHCI_SDR104_NEEDS_TUNING)
1911 break;
1912 /* FALLTHROUGH */
1913
1914 default:
1915 goto out_unlock;
1916 }
1917
1918 if (host->ops->platform_execute_tuning) {
1919 spin_unlock_irqrestore(&host->lock, flags);
1920 err = host->ops->platform_execute_tuning(host, opcode);
1921 return err;
1922 }
1923
1924 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1925 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1926 if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND)
1927 ctrl |= SDHCI_CTRL_TUNED_CLK;
1928 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1929
1930 /*
1931 * As per the Host Controller spec v3.00, tuning command
1932 * generates Buffer Read Ready interrupt, so enable that.
1933 *
1934 * Note: The spec clearly says that when tuning sequence
1935 * is being performed, the controller does not generate
1936 * interrupts other than Buffer Read Ready interrupt. But
1937 * to make sure we don't hit a controller bug, we _only_
1938 * enable Buffer Read Ready interrupt here.
1939 */
1940 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1941 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1942
1943 /*
1944 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1945 * of loops reaches 40 times or a timeout of 150ms occurs.
1946 */
1947 do {
1948 struct mmc_command cmd = {0};
1949 struct mmc_request mrq = {NULL};
1950
1951 cmd.opcode = opcode;
1952 cmd.arg = 0;
1953 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1954 cmd.retries = 0;
1955 cmd.data = NULL;
1956 cmd.error = 0;
1957
1958 if (tuning_loop_counter-- == 0)
1959 break;
1960
1961 mrq.cmd = &cmd;
1962 host->mrq = &mrq;
1963
1964 /*
1965 * In response to CMD19, the card sends 64 bytes of tuning
1966 * block to the Host Controller. So we set the block size
1967 * to 64 here.
1968 */
1969 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1970 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1971 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1972 SDHCI_BLOCK_SIZE);
1973 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1974 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1975 SDHCI_BLOCK_SIZE);
1976 } else {
1977 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1978 SDHCI_BLOCK_SIZE);
1979 }
1980
1981 /*
1982 * The tuning block is sent by the card to the host controller.
1983 * So we set the TRNS_READ bit in the Transfer Mode register.
1984 * This also takes care of setting DMA Enable and Multi Block
1985 * Select in the same register to 0.
1986 */
1987 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1988
1989 sdhci_send_command(host, &cmd);
1990
1991 host->cmd = NULL;
1992 host->mrq = NULL;
1993
1994 spin_unlock_irqrestore(&host->lock, flags);
1995 /* Wait for Buffer Read Ready interrupt */
1996 wait_event_interruptible_timeout(host->buf_ready_int,
1997 (host->tuning_done == 1),
1998 msecs_to_jiffies(50));
1999 spin_lock_irqsave(&host->lock, flags);
2000
2001 if (!host->tuning_done) {
2002 pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n");
2003 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2004 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2005 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
2006 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2007
2008 err = -EIO;
2009 goto out;
2010 }
2011
2012 host->tuning_done = 0;
2013
2014 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2015
2016 /* eMMC spec does not require a delay between tuning cycles */
2017 if (opcode == MMC_SEND_TUNING_BLOCK)
2018 mdelay(1);
2019 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
2020
2021 /*
2022 * The Host Driver has exhausted the maximum number of loops allowed,
2023 * so use fixed sampling frequency.
2024 */
2025 if (tuning_loop_counter < 0) {
2026 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
2027 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2028 }
2029 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2030 pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n");
2031 err = -EIO;
2032 }
2033
2034 out:
2035 if (tuning_count) {
2036 /*
2037 * In case tuning fails, host controllers which support
2038 * re-tuning can try tuning again at a later time, when the
2039 * re-tuning timer expires. So for these controllers, we
2040 * return 0. Since there might be other controllers who do not
2041 * have this capability, we return error for them.
2042 */
2043 err = 0;
2044 }
2045
2046 host->mmc->retune_period = err ? 0 : tuning_count;
2047
2048 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2049 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2050 out_unlock:
2051 spin_unlock_irqrestore(&host->lock, flags);
2052 return err;
2053 }
2054
2055 static int sdhci_select_drive_strength(struct mmc_card *card,
2056 unsigned int max_dtr, int host_drv,
2057 int card_drv, int *drv_type)
2058 {
2059 struct sdhci_host *host = mmc_priv(card->host);
2060
2061 if (!host->ops->select_drive_strength)
2062 return 0;
2063
2064 return host->ops->select_drive_strength(host, card, max_dtr, host_drv,
2065 card_drv, drv_type);
2066 }
2067
2068 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2069 {
2070 /* Host Controller v3.00 defines preset value registers */
2071 if (host->version < SDHCI_SPEC_300)
2072 return;
2073
2074 /*
2075 * We only enable or disable Preset Value if they are not already
2076 * enabled or disabled respectively. Otherwise, we bail out.
2077 */
2078 if (host->preset_enabled != enable) {
2079 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2080
2081 if (enable)
2082 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2083 else
2084 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2085
2086 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2087
2088 if (enable)
2089 host->flags |= SDHCI_PV_ENABLED;
2090 else
2091 host->flags &= ~SDHCI_PV_ENABLED;
2092
2093 host->preset_enabled = enable;
2094 }
2095 }
2096
2097 static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
2098 int err)
2099 {
2100 struct sdhci_host *host = mmc_priv(mmc);
2101 struct mmc_data *data = mrq->data;
2102
2103 if (data->host_cookie != COOKIE_UNMAPPED)
2104 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2105 data->flags & MMC_DATA_WRITE ?
2106 DMA_TO_DEVICE : DMA_FROM_DEVICE);
2107
2108 data->host_cookie = COOKIE_UNMAPPED;
2109 }
2110
2111 static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
2112 bool is_first_req)
2113 {
2114 struct sdhci_host *host = mmc_priv(mmc);
2115
2116 mrq->data->host_cookie = COOKIE_UNMAPPED;
2117
2118 if (host->flags & SDHCI_REQ_USE_DMA)
2119 sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED);
2120 }
2121
2122 static void sdhci_card_event(struct mmc_host *mmc)
2123 {
2124 struct sdhci_host *host = mmc_priv(mmc);
2125 unsigned long flags;
2126 int present;
2127
2128 /* First check if client has provided their own card event */
2129 if (host->ops->card_event)
2130 host->ops->card_event(host);
2131
2132 present = sdhci_do_get_cd(host);
2133
2134 spin_lock_irqsave(&host->lock, flags);
2135
2136 /* Check host->mrq first in case we are runtime suspended */
2137 if (host->mrq && !present) {
2138 pr_err("%s: Card removed during transfer!\n",
2139 mmc_hostname(host->mmc));
2140 pr_err("%s: Resetting controller.\n",
2141 mmc_hostname(host->mmc));
2142
2143 sdhci_do_reset(host, SDHCI_RESET_CMD);
2144 sdhci_do_reset(host, SDHCI_RESET_DATA);
2145
2146 host->mrq->cmd->error = -ENOMEDIUM;
2147 tasklet_schedule(&host->finish_tasklet);
2148 }
2149
2150 spin_unlock_irqrestore(&host->lock, flags);
2151 }
2152
2153 static const struct mmc_host_ops sdhci_ops = {
2154 .request = sdhci_request,
2155 .post_req = sdhci_post_req,
2156 .pre_req = sdhci_pre_req,
2157 .set_ios = sdhci_set_ios,
2158 .get_cd = sdhci_get_cd,
2159 .get_ro = sdhci_get_ro,
2160 .hw_reset = sdhci_hw_reset,
2161 .enable_sdio_irq = sdhci_enable_sdio_irq,
2162 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2163 .prepare_hs400_tuning = sdhci_prepare_hs400_tuning,
2164 .execute_tuning = sdhci_execute_tuning,
2165 .select_drive_strength = sdhci_select_drive_strength,
2166 .card_event = sdhci_card_event,
2167 .card_busy = sdhci_card_busy,
2168 };
2169
2170 /*****************************************************************************\
2171 * *
2172 * Tasklets *
2173 * *
2174 \*****************************************************************************/
2175
2176 static void sdhci_tasklet_finish(unsigned long param)
2177 {
2178 struct sdhci_host *host;
2179 unsigned long flags;
2180 struct mmc_request *mrq;
2181
2182 host = (struct sdhci_host*)param;
2183
2184 spin_lock_irqsave(&host->lock, flags);
2185
2186 /*
2187 * If this tasklet gets rescheduled while running, it will
2188 * be run again afterwards but without any active request.
2189 */
2190 if (!host->mrq) {
2191 spin_unlock_irqrestore(&host->lock, flags);
2192 return;
2193 }
2194
2195 del_timer(&host->timer);
2196
2197 mrq = host->mrq;
2198
2199 /*
2200 * Always unmap the data buffers if they were mapped by
2201 * sdhci_prepare_data() whenever we finish with a request.
2202 * This avoids leaking DMA mappings on error.
2203 */
2204 if (host->flags & SDHCI_REQ_USE_DMA) {
2205 struct mmc_data *data = mrq->data;
2206
2207 if (data && data->host_cookie == COOKIE_MAPPED) {
2208 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
2209 (data->flags & MMC_DATA_READ) ?
2210 DMA_FROM_DEVICE : DMA_TO_DEVICE);
2211 data->host_cookie = COOKIE_UNMAPPED;
2212 }
2213 }
2214
2215 /*
2216 * The controller needs a reset of internal state machines
2217 * upon error conditions.
2218 */
2219 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2220 ((mrq->cmd && mrq->cmd->error) ||
2221 (mrq->sbc && mrq->sbc->error) ||
2222 (mrq->data && ((mrq->data->error && !mrq->data->stop) ||
2223 (mrq->data->stop && mrq->data->stop->error))) ||
2224 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2225
2226 /* Some controllers need this kick or reset won't work here */
2227 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2228 /* This is to force an update */
2229 host->ops->set_clock(host, host->clock);
2230
2231 /* Spec says we should do both at the same time, but Ricoh
2232 controllers do not like that. */
2233 sdhci_do_reset(host, SDHCI_RESET_CMD);
2234 sdhci_do_reset(host, SDHCI_RESET_DATA);
2235 }
2236
2237 host->mrq = NULL;
2238 host->cmd = NULL;
2239 host->data = NULL;
2240
2241 sdhci_led_deactivate(host);
2242
2243 mmiowb();
2244 spin_unlock_irqrestore(&host->lock, flags);
2245
2246 mmc_request_done(host->mmc, mrq);
2247 }
2248
2249 static void sdhci_timeout_timer(unsigned long data)
2250 {
2251 struct sdhci_host *host;
2252 unsigned long flags;
2253
2254 host = (struct sdhci_host*)data;
2255
2256 spin_lock_irqsave(&host->lock, flags);
2257
2258 if (host->mrq) {
2259 pr_err("%s: Timeout waiting for hardware interrupt.\n",
2260 mmc_hostname(host->mmc));
2261 sdhci_dumpregs(host);
2262
2263 if (host->data) {
2264 host->data->error = -ETIMEDOUT;
2265 sdhci_finish_data(host);
2266 } else {
2267 if (host->cmd)
2268 host->cmd->error = -ETIMEDOUT;
2269 else
2270 host->mrq->cmd->error = -ETIMEDOUT;
2271
2272 tasklet_schedule(&host->finish_tasklet);
2273 }
2274 }
2275
2276 mmiowb();
2277 spin_unlock_irqrestore(&host->lock, flags);
2278 }
2279
2280 /*****************************************************************************\
2281 * *
2282 * Interrupt handling *
2283 * *
2284 \*****************************************************************************/
2285
2286 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask)
2287 {
2288 BUG_ON(intmask == 0);
2289
2290 if (!host->cmd) {
2291 pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
2292 mmc_hostname(host->mmc), (unsigned)intmask);
2293 sdhci_dumpregs(host);
2294 return;
2295 }
2296
2297 if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC |
2298 SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) {
2299 if (intmask & SDHCI_INT_TIMEOUT)
2300 host->cmd->error = -ETIMEDOUT;
2301 else
2302 host->cmd->error = -EILSEQ;
2303
2304 /*
2305 * If this command initiates a data phase and a response
2306 * CRC error is signalled, the card can start transferring
2307 * data - the card may have received the command without
2308 * error. We must not terminate the mmc_request early.
2309 *
2310 * If the card did not receive the command or returned an
2311 * error which prevented it sending data, the data phase
2312 * will time out.
2313 */
2314 if (host->cmd->data &&
2315 (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) ==
2316 SDHCI_INT_CRC) {
2317 host->cmd = NULL;
2318 return;
2319 }
2320
2321 tasklet_schedule(&host->finish_tasklet);
2322 return;
2323 }
2324
2325 /*
2326 * The host can send and interrupt when the busy state has
2327 * ended, allowing us to wait without wasting CPU cycles.
2328 * Unfortunately this is overloaded on the "data complete"
2329 * interrupt, so we need to take some care when handling
2330 * it.
2331 *
2332 * Note: The 1.0 specification is a bit ambiguous about this
2333 * feature so there might be some problems with older
2334 * controllers.
2335 */
2336 if (host->cmd->flags & MMC_RSP_BUSY) {
2337 if (host->cmd->data)
2338 DBG("Cannot wait for busy signal when also doing a data transfer");
2339 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)
2340 && !host->busy_handle) {
2341 /* Mark that command complete before busy is ended */
2342 host->busy_handle = 1;
2343 return;
2344 }
2345
2346 /* The controller does not support the end-of-busy IRQ,
2347 * fall through and take the SDHCI_INT_RESPONSE */
2348 } else if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) &&
2349 host->cmd->opcode == MMC_STOP_TRANSMISSION && !host->data) {
2350 *mask &= ~SDHCI_INT_DATA_END;
2351 }
2352
2353 if (intmask & SDHCI_INT_RESPONSE)
2354 sdhci_finish_command(host);
2355 }
2356
2357 #ifdef CONFIG_MMC_DEBUG
2358 static void sdhci_adma_show_error(struct sdhci_host *host)
2359 {
2360 const char *name = mmc_hostname(host->mmc);
2361 void *desc = host->adma_table;
2362
2363 sdhci_dumpregs(host);
2364
2365 while (true) {
2366 struct sdhci_adma2_64_desc *dma_desc = desc;
2367
2368 if (host->flags & SDHCI_USE_64_BIT_DMA)
2369 DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n",
2370 name, desc, le32_to_cpu(dma_desc->addr_hi),
2371 le32_to_cpu(dma_desc->addr_lo),
2372 le16_to_cpu(dma_desc->len),
2373 le16_to_cpu(dma_desc->cmd));
2374 else
2375 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2376 name, desc, le32_to_cpu(dma_desc->addr_lo),
2377 le16_to_cpu(dma_desc->len),
2378 le16_to_cpu(dma_desc->cmd));
2379
2380 desc += host->desc_sz;
2381
2382 if (dma_desc->cmd & cpu_to_le16(ADMA2_END))
2383 break;
2384 }
2385 }
2386 #else
2387 static void sdhci_adma_show_error(struct sdhci_host *host) { }
2388 #endif
2389
2390 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2391 {
2392 u32 command;
2393 BUG_ON(intmask == 0);
2394
2395 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2396 if (intmask & SDHCI_INT_DATA_AVAIL) {
2397 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2398 if (command == MMC_SEND_TUNING_BLOCK ||
2399 command == MMC_SEND_TUNING_BLOCK_HS200) {
2400 host->tuning_done = 1;
2401 wake_up(&host->buf_ready_int);
2402 return;
2403 }
2404 }
2405
2406 if (!host->data) {
2407 /*
2408 * The "data complete" interrupt is also used to
2409 * indicate that a busy state has ended. See comment
2410 * above in sdhci_cmd_irq().
2411 */
2412 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2413 if (intmask & SDHCI_INT_DATA_TIMEOUT) {
2414 host->cmd->error = -ETIMEDOUT;
2415 tasklet_schedule(&host->finish_tasklet);
2416 return;
2417 }
2418 if (intmask & SDHCI_INT_DATA_END) {
2419 /*
2420 * Some cards handle busy-end interrupt
2421 * before the command completed, so make
2422 * sure we do things in the proper order.
2423 */
2424 if (host->busy_handle)
2425 sdhci_finish_command(host);
2426 else
2427 host->busy_handle = 1;
2428 return;
2429 }
2430 }
2431
2432 pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n",
2433 mmc_hostname(host->mmc), (unsigned)intmask);
2434 sdhci_dumpregs(host);
2435
2436 return;
2437 }
2438
2439 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2440 host->data->error = -ETIMEDOUT;
2441 else if (intmask & SDHCI_INT_DATA_END_BIT)
2442 host->data->error = -EILSEQ;
2443 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2444 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2445 != MMC_BUS_TEST_R)
2446 host->data->error = -EILSEQ;
2447 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2448 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2449 sdhci_adma_show_error(host);
2450 host->data->error = -EIO;
2451 if (host->ops->adma_workaround)
2452 host->ops->adma_workaround(host, intmask);
2453 }
2454
2455 if (host->data->error)
2456 sdhci_finish_data(host);
2457 else {
2458 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2459 sdhci_transfer_pio(host);
2460
2461 /*
2462 * We currently don't do anything fancy with DMA
2463 * boundaries, but as we can't disable the feature
2464 * we need to at least restart the transfer.
2465 *
2466 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2467 * should return a valid address to continue from, but as
2468 * some controllers are faulty, don't trust them.
2469 */
2470 if (intmask & SDHCI_INT_DMA_END) {
2471 u32 dmastart, dmanow;
2472 dmastart = sg_dma_address(host->data->sg);
2473 dmanow = dmastart + host->data->bytes_xfered;
2474 /*
2475 * Force update to the next DMA block boundary.
2476 */
2477 dmanow = (dmanow &
2478 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2479 SDHCI_DEFAULT_BOUNDARY_SIZE;
2480 host->data->bytes_xfered = dmanow - dmastart;
2481 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2482 " next 0x%08x\n",
2483 mmc_hostname(host->mmc), dmastart,
2484 host->data->bytes_xfered, dmanow);
2485 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2486 }
2487
2488 if (intmask & SDHCI_INT_DATA_END) {
2489 if (host->cmd) {
2490 /*
2491 * Data managed to finish before the
2492 * command completed. Make sure we do
2493 * things in the proper order.
2494 */
2495 host->data_early = 1;
2496 } else {
2497 sdhci_finish_data(host);
2498 }
2499 }
2500 }
2501 }
2502
2503 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2504 {
2505 irqreturn_t result = IRQ_NONE;
2506 struct sdhci_host *host = dev_id;
2507 u32 intmask, mask, unexpected = 0;
2508 int max_loops = 16;
2509
2510 spin_lock(&host->lock);
2511
2512 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2513 spin_unlock(&host->lock);
2514 return IRQ_NONE;
2515 }
2516
2517 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2518 if (!intmask || intmask == 0xffffffff) {
2519 result = IRQ_NONE;
2520 goto out;
2521 }
2522
2523 do {
2524 /* Clear selected interrupts. */
2525 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2526 SDHCI_INT_BUS_POWER);
2527 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2528
2529 DBG("*** %s got interrupt: 0x%08x\n",
2530 mmc_hostname(host->mmc), intmask);
2531
2532 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2533 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2534 SDHCI_CARD_PRESENT;
2535
2536 /*
2537 * There is a observation on i.mx esdhc. INSERT
2538 * bit will be immediately set again when it gets
2539 * cleared, if a card is inserted. We have to mask
2540 * the irq to prevent interrupt storm which will
2541 * freeze the system. And the REMOVE gets the
2542 * same situation.
2543 *
2544 * More testing are needed here to ensure it works
2545 * for other platforms though.
2546 */
2547 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2548 SDHCI_INT_CARD_REMOVE);
2549 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2550 SDHCI_INT_CARD_INSERT;
2551 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2552 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2553
2554 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2555 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2556
2557 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2558 SDHCI_INT_CARD_REMOVE);
2559 result = IRQ_WAKE_THREAD;
2560 }
2561
2562 if (intmask & SDHCI_INT_CMD_MASK)
2563 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK,
2564 &intmask);
2565
2566 if (intmask & SDHCI_INT_DATA_MASK)
2567 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2568
2569 if (intmask & SDHCI_INT_BUS_POWER)
2570 pr_err("%s: Card is consuming too much power!\n",
2571 mmc_hostname(host->mmc));
2572
2573 if (intmask & SDHCI_INT_CARD_INT) {
2574 sdhci_enable_sdio_irq_nolock(host, false);
2575 host->thread_isr |= SDHCI_INT_CARD_INT;
2576 result = IRQ_WAKE_THREAD;
2577 }
2578
2579 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2580 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2581 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2582 SDHCI_INT_CARD_INT);
2583
2584 if (intmask) {
2585 unexpected |= intmask;
2586 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2587 }
2588
2589 if (result == IRQ_NONE)
2590 result = IRQ_HANDLED;
2591
2592 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2593 } while (intmask && --max_loops);
2594 out:
2595 spin_unlock(&host->lock);
2596
2597 if (unexpected) {
2598 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2599 mmc_hostname(host->mmc), unexpected);
2600 sdhci_dumpregs(host);
2601 }
2602
2603 return result;
2604 }
2605
2606 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2607 {
2608 struct sdhci_host *host = dev_id;
2609 unsigned long flags;
2610 u32 isr;
2611
2612 spin_lock_irqsave(&host->lock, flags);
2613 isr = host->thread_isr;
2614 host->thread_isr = 0;
2615 spin_unlock_irqrestore(&host->lock, flags);
2616
2617 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2618 sdhci_card_event(host->mmc);
2619 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2620 }
2621
2622 if (isr & SDHCI_INT_CARD_INT) {
2623 sdio_run_irqs(host->mmc);
2624
2625 spin_lock_irqsave(&host->lock, flags);
2626 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2627 sdhci_enable_sdio_irq_nolock(host, true);
2628 spin_unlock_irqrestore(&host->lock, flags);
2629 }
2630
2631 return isr ? IRQ_HANDLED : IRQ_NONE;
2632 }
2633
2634 /*****************************************************************************\
2635 * *
2636 * Suspend/resume *
2637 * *
2638 \*****************************************************************************/
2639
2640 #ifdef CONFIG_PM
2641 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2642 {
2643 u8 val;
2644 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2645 | SDHCI_WAKE_ON_INT;
2646
2647 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2648 val |= mask ;
2649 /* Avoid fake wake up */
2650 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2651 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2652 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2653 }
2654 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2655
2656 static void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2657 {
2658 u8 val;
2659 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2660 | SDHCI_WAKE_ON_INT;
2661
2662 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2663 val &= ~mask;
2664 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2665 }
2666
2667 int sdhci_suspend_host(struct sdhci_host *host)
2668 {
2669 sdhci_disable_card_detection(host);
2670
2671 mmc_retune_timer_stop(host->mmc);
2672 mmc_retune_needed(host->mmc);
2673
2674 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2675 host->ier = 0;
2676 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2677 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2678 free_irq(host->irq, host);
2679 } else {
2680 sdhci_enable_irq_wakeups(host);
2681 enable_irq_wake(host->irq);
2682 }
2683 return 0;
2684 }
2685
2686 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2687
2688 int sdhci_resume_host(struct sdhci_host *host)
2689 {
2690 int ret = 0;
2691
2692 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2693 if (host->ops->enable_dma)
2694 host->ops->enable_dma(host);
2695 }
2696
2697 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2698 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2699 /* Card keeps power but host controller does not */
2700 sdhci_init(host, 0);
2701 host->pwr = 0;
2702 host->clock = 0;
2703 sdhci_do_set_ios(host, &host->mmc->ios);
2704 } else {
2705 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2706 mmiowb();
2707 }
2708
2709 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2710 ret = request_threaded_irq(host->irq, sdhci_irq,
2711 sdhci_thread_irq, IRQF_SHARED,
2712 mmc_hostname(host->mmc), host);
2713 if (ret)
2714 return ret;
2715 } else {
2716 sdhci_disable_irq_wakeups(host);
2717 disable_irq_wake(host->irq);
2718 }
2719
2720 sdhci_enable_card_detection(host);
2721
2722 return ret;
2723 }
2724
2725 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2726
2727 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2728 {
2729 unsigned long flags;
2730
2731 mmc_retune_timer_stop(host->mmc);
2732 mmc_retune_needed(host->mmc);
2733
2734 spin_lock_irqsave(&host->lock, flags);
2735 host->ier &= SDHCI_INT_CARD_INT;
2736 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2737 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2738 spin_unlock_irqrestore(&host->lock, flags);
2739
2740 synchronize_hardirq(host->irq);
2741
2742 spin_lock_irqsave(&host->lock, flags);
2743 host->runtime_suspended = true;
2744 spin_unlock_irqrestore(&host->lock, flags);
2745
2746 return 0;
2747 }
2748 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2749
2750 int sdhci_runtime_resume_host(struct sdhci_host *host)
2751 {
2752 unsigned long flags;
2753 int host_flags = host->flags;
2754
2755 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2756 if (host->ops->enable_dma)
2757 host->ops->enable_dma(host);
2758 }
2759
2760 sdhci_init(host, 0);
2761
2762 /* Force clock and power re-program */
2763 host->pwr = 0;
2764 host->clock = 0;
2765 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2766 sdhci_do_set_ios(host, &host->mmc->ios);
2767
2768 if ((host_flags & SDHCI_PV_ENABLED) &&
2769 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2770 spin_lock_irqsave(&host->lock, flags);
2771 sdhci_enable_preset_value(host, true);
2772 spin_unlock_irqrestore(&host->lock, flags);
2773 }
2774
2775 spin_lock_irqsave(&host->lock, flags);
2776
2777 host->runtime_suspended = false;
2778
2779 /* Enable SDIO IRQ */
2780 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2781 sdhci_enable_sdio_irq_nolock(host, true);
2782
2783 /* Enable Card Detection */
2784 sdhci_enable_card_detection(host);
2785
2786 spin_unlock_irqrestore(&host->lock, flags);
2787
2788 return 0;
2789 }
2790 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2791
2792 #endif /* CONFIG_PM */
2793
2794 /*****************************************************************************\
2795 * *
2796 * Device allocation/registration *
2797 * *
2798 \*****************************************************************************/
2799
2800 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2801 size_t priv_size)
2802 {
2803 struct mmc_host *mmc;
2804 struct sdhci_host *host;
2805
2806 WARN_ON(dev == NULL);
2807
2808 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2809 if (!mmc)
2810 return ERR_PTR(-ENOMEM);
2811
2812 host = mmc_priv(mmc);
2813 host->mmc = mmc;
2814 host->mmc_host_ops = sdhci_ops;
2815 mmc->ops = &host->mmc_host_ops;
2816
2817 return host;
2818 }
2819
2820 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2821
2822 static int sdhci_set_dma_mask(struct sdhci_host *host)
2823 {
2824 struct mmc_host *mmc = host->mmc;
2825 struct device *dev = mmc_dev(mmc);
2826 int ret = -EINVAL;
2827
2828 if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA)
2829 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2830
2831 /* Try 64-bit mask if hardware is capable of it */
2832 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2833 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
2834 if (ret) {
2835 pr_warn("%s: Failed to set 64-bit DMA mask.\n",
2836 mmc_hostname(mmc));
2837 host->flags &= ~SDHCI_USE_64_BIT_DMA;
2838 }
2839 }
2840
2841 /* 32-bit mask as default & fallback */
2842 if (ret) {
2843 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
2844 if (ret)
2845 pr_warn("%s: Failed to set 32-bit DMA mask.\n",
2846 mmc_hostname(mmc));
2847 }
2848
2849 return ret;
2850 }
2851
2852 int sdhci_add_host(struct sdhci_host *host)
2853 {
2854 struct mmc_host *mmc;
2855 u32 caps[2] = {0, 0};
2856 u32 max_current_caps;
2857 unsigned int ocr_avail;
2858 unsigned int override_timeout_clk;
2859 u32 max_clk;
2860 int ret;
2861
2862 WARN_ON(host == NULL);
2863 if (host == NULL)
2864 return -EINVAL;
2865
2866 mmc = host->mmc;
2867
2868 if (debug_quirks)
2869 host->quirks = debug_quirks;
2870 if (debug_quirks2)
2871 host->quirks2 = debug_quirks2;
2872
2873 override_timeout_clk = host->timeout_clk;
2874
2875 sdhci_do_reset(host, SDHCI_RESET_ALL);
2876
2877 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2878 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2879 >> SDHCI_SPEC_VER_SHIFT;
2880 if (host->version > SDHCI_SPEC_300) {
2881 pr_err("%s: Unknown controller version (%d). You may experience problems.\n",
2882 mmc_hostname(mmc), host->version);
2883 }
2884
2885 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2886 sdhci_readl(host, SDHCI_CAPABILITIES);
2887
2888 if (host->version >= SDHCI_SPEC_300)
2889 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2890 host->caps1 :
2891 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2892
2893 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2894 host->flags |= SDHCI_USE_SDMA;
2895 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2896 DBG("Controller doesn't have SDMA capability\n");
2897 else
2898 host->flags |= SDHCI_USE_SDMA;
2899
2900 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2901 (host->flags & SDHCI_USE_SDMA)) {
2902 DBG("Disabling DMA as it is marked broken\n");
2903 host->flags &= ~SDHCI_USE_SDMA;
2904 }
2905
2906 if ((host->version >= SDHCI_SPEC_200) &&
2907 (caps[0] & SDHCI_CAN_DO_ADMA2))
2908 host->flags |= SDHCI_USE_ADMA;
2909
2910 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2911 (host->flags & SDHCI_USE_ADMA)) {
2912 DBG("Disabling ADMA as it is marked broken\n");
2913 host->flags &= ~SDHCI_USE_ADMA;
2914 }
2915
2916 /*
2917 * It is assumed that a 64-bit capable device has set a 64-bit DMA mask
2918 * and *must* do 64-bit DMA. A driver has the opportunity to change
2919 * that during the first call to ->enable_dma(). Similarly
2920 * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to
2921 * implement.
2922 */
2923 if (caps[0] & SDHCI_CAN_64BIT)
2924 host->flags |= SDHCI_USE_64_BIT_DMA;
2925
2926 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2927 ret = sdhci_set_dma_mask(host);
2928
2929 if (!ret && host->ops->enable_dma)
2930 ret = host->ops->enable_dma(host);
2931
2932 if (ret) {
2933 pr_warn("%s: No suitable DMA available - falling back to PIO\n",
2934 mmc_hostname(mmc));
2935 host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2936
2937 ret = 0;
2938 }
2939 }
2940
2941 /* SDMA does not support 64-bit DMA */
2942 if (host->flags & SDHCI_USE_64_BIT_DMA)
2943 host->flags &= ~SDHCI_USE_SDMA;
2944
2945 if (host->flags & SDHCI_USE_ADMA) {
2946 dma_addr_t dma;
2947 void *buf;
2948
2949 /*
2950 * The DMA descriptor table size is calculated as the maximum
2951 * number of segments times 2, to allow for an alignment
2952 * descriptor for each segment, plus 1 for a nop end descriptor,
2953 * all multipled by the descriptor size.
2954 */
2955 if (host->flags & SDHCI_USE_64_BIT_DMA) {
2956 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2957 SDHCI_ADMA2_64_DESC_SZ;
2958 host->desc_sz = SDHCI_ADMA2_64_DESC_SZ;
2959 } else {
2960 host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) *
2961 SDHCI_ADMA2_32_DESC_SZ;
2962 host->desc_sz = SDHCI_ADMA2_32_DESC_SZ;
2963 }
2964
2965 host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN;
2966 buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz +
2967 host->adma_table_sz, &dma, GFP_KERNEL);
2968 if (!buf) {
2969 pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n",
2970 mmc_hostname(mmc));
2971 host->flags &= ~SDHCI_USE_ADMA;
2972 } else if ((dma + host->align_buffer_sz) &
2973 (SDHCI_ADMA2_DESC_ALIGN - 1)) {
2974 pr_warn("%s: unable to allocate aligned ADMA descriptor\n",
2975 mmc_hostname(mmc));
2976 host->flags &= ~SDHCI_USE_ADMA;
2977 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
2978 host->adma_table_sz, buf, dma);
2979 } else {
2980 host->align_buffer = buf;
2981 host->align_addr = dma;
2982
2983 host->adma_table = buf + host->align_buffer_sz;
2984 host->adma_addr = dma + host->align_buffer_sz;
2985 }
2986 }
2987
2988 /*
2989 * If we use DMA, then it's up to the caller to set the DMA
2990 * mask, but PIO does not need the hw shim so we set a new
2991 * mask here in that case.
2992 */
2993 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2994 host->dma_mask = DMA_BIT_MASK(64);
2995 mmc_dev(mmc)->dma_mask = &host->dma_mask;
2996 }
2997
2998 if (host->version >= SDHCI_SPEC_300)
2999 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
3000 >> SDHCI_CLOCK_BASE_SHIFT;
3001 else
3002 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
3003 >> SDHCI_CLOCK_BASE_SHIFT;
3004
3005 host->max_clk *= 1000000;
3006 if (host->max_clk == 0 || host->quirks &
3007 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
3008 if (!host->ops->get_max_clock) {
3009 pr_err("%s: Hardware doesn't specify base clock frequency.\n",
3010 mmc_hostname(mmc));
3011 ret = -ENODEV;
3012 goto undma;
3013 }
3014 host->max_clk = host->ops->get_max_clock(host);
3015 }
3016
3017 /*
3018 * In case of Host Controller v3.00, find out whether clock
3019 * multiplier is supported.
3020 */
3021 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
3022 SDHCI_CLOCK_MUL_SHIFT;
3023
3024 /*
3025 * In case the value in Clock Multiplier is 0, then programmable
3026 * clock mode is not supported, otherwise the actual clock
3027 * multiplier is one more than the value of Clock Multiplier
3028 * in the Capabilities Register.
3029 */
3030 if (host->clk_mul)
3031 host->clk_mul += 1;
3032
3033 /*
3034 * Set host parameters.
3035 */
3036 max_clk = host->max_clk;
3037
3038 if (host->ops->get_min_clock)
3039 mmc->f_min = host->ops->get_min_clock(host);
3040 else if (host->version >= SDHCI_SPEC_300) {
3041 if (host->clk_mul) {
3042 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
3043 max_clk = host->max_clk * host->clk_mul;
3044 } else
3045 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
3046 } else
3047 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
3048
3049 if (!mmc->f_max || mmc->f_max > max_clk)
3050 mmc->f_max = max_clk;
3051
3052 if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
3053 host->timeout_clk = (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >>
3054 SDHCI_TIMEOUT_CLK_SHIFT;
3055 if (host->timeout_clk == 0) {
3056 if (host->ops->get_timeout_clock) {
3057 host->timeout_clk =
3058 host->ops->get_timeout_clock(host);
3059 } else {
3060 pr_err("%s: Hardware doesn't specify timeout clock frequency.\n",
3061 mmc_hostname(mmc));
3062 ret = -ENODEV;
3063 goto undma;
3064 }
3065 }
3066
3067 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
3068 host->timeout_clk *= 1000;
3069
3070 if (override_timeout_clk)
3071 host->timeout_clk = override_timeout_clk;
3072
3073 mmc->max_busy_timeout = host->ops->get_max_timeout_count ?
3074 host->ops->get_max_timeout_count(host) : 1 << 27;
3075 mmc->max_busy_timeout /= host->timeout_clk;
3076 }
3077
3078 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
3079 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3080
3081 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
3082 host->flags |= SDHCI_AUTO_CMD12;
3083
3084 /* Auto-CMD23 stuff only works in ADMA or PIO. */
3085 if ((host->version >= SDHCI_SPEC_300) &&
3086 ((host->flags & SDHCI_USE_ADMA) ||
3087 !(host->flags & SDHCI_USE_SDMA)) &&
3088 !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) {
3089 host->flags |= SDHCI_AUTO_CMD23;
3090 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
3091 } else {
3092 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
3093 }
3094
3095 /*
3096 * A controller may support 8-bit width, but the board itself
3097 * might not have the pins brought out. Boards that support
3098 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
3099 * their platform code before calling sdhci_add_host(), and we
3100 * won't assume 8-bit width for hosts without that CAP.
3101 */
3102 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
3103 mmc->caps |= MMC_CAP_4_BIT_DATA;
3104
3105 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
3106 mmc->caps &= ~MMC_CAP_CMD23;
3107
3108 if (caps[0] & SDHCI_CAN_DO_HISPD)
3109 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
3110
3111 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
3112 !(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3113 IS_ERR_VALUE(mmc_gpio_get_cd(host->mmc)))
3114 mmc->caps |= MMC_CAP_NEEDS_POLL;
3115
3116 /* If there are external regulators, get them */
3117 ret = mmc_regulator_get_supply(mmc);
3118 if (ret == -EPROBE_DEFER)
3119 goto undma;
3120
3121 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
3122 if (!IS_ERR(mmc->supply.vqmmc)) {
3123 ret = regulator_enable(mmc->supply.vqmmc);
3124 if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000,
3125 1950000))
3126 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3127 SDHCI_SUPPORT_SDR50 |
3128 SDHCI_SUPPORT_DDR50);
3129 if (ret) {
3130 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3131 mmc_hostname(mmc), ret);
3132 mmc->supply.vqmmc = ERR_PTR(-EINVAL);
3133 }
3134 }
3135
3136 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3137 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3138 SDHCI_SUPPORT_DDR50);
3139
3140 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3141 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3142 SDHCI_SUPPORT_DDR50))
3143 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3144
3145 /* SDR104 supports also implies SDR50 support */
3146 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3147 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3148 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3149 * field can be promoted to support HS200.
3150 */
3151 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3152 mmc->caps2 |= MMC_CAP2_HS200;
3153 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3154 mmc->caps |= MMC_CAP_UHS_SDR50;
3155
3156 if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 &&
3157 (caps[1] & SDHCI_SUPPORT_HS400))
3158 mmc->caps2 |= MMC_CAP2_HS400;
3159
3160 if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) &&
3161 (IS_ERR(mmc->supply.vqmmc) ||
3162 !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000,
3163 1300000)))
3164 mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V;
3165
3166 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3167 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3168 mmc->caps |= MMC_CAP_UHS_DDR50;
3169
3170 /* Does the host need tuning for SDR50? */
3171 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3172 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3173
3174 /* Does the host need tuning for SDR104 / HS200? */
3175 if (mmc->caps2 & MMC_CAP2_HS200)
3176 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3177
3178 /* Driver Type(s) (A, C, D) supported by the host */
3179 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3180 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3181 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3182 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3183 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3184 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3185
3186 /* Initial value for re-tuning timer count */
3187 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3188 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3189
3190 /*
3191 * In case Re-tuning Timer is not disabled, the actual value of
3192 * re-tuning timer will be 2 ^ (n - 1).
3193 */
3194 if (host->tuning_count)
3195 host->tuning_count = 1 << (host->tuning_count - 1);
3196
3197 /* Re-tuning mode supported by the Host Controller */
3198 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3199 SDHCI_RETUNING_MODE_SHIFT;
3200
3201 ocr_avail = 0;
3202
3203 /*
3204 * According to SD Host Controller spec v3.00, if the Host System
3205 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3206 * the value is meaningful only if Voltage Support in the Capabilities
3207 * register is set. The actual current value is 4 times the register
3208 * value.
3209 */
3210 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3211 if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) {
3212 int curr = regulator_get_current_limit(mmc->supply.vmmc);
3213 if (curr > 0) {
3214
3215 /* convert to SDHCI_MAX_CURRENT format */
3216 curr = curr/1000; /* convert to mA */
3217 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3218
3219 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3220 max_current_caps =
3221 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3222 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3223 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3224 }
3225 }
3226
3227 if (caps[0] & SDHCI_CAN_VDD_330) {
3228 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3229
3230 mmc->max_current_330 = ((max_current_caps &
3231 SDHCI_MAX_CURRENT_330_MASK) >>
3232 SDHCI_MAX_CURRENT_330_SHIFT) *
3233 SDHCI_MAX_CURRENT_MULTIPLIER;
3234 }
3235 if (caps[0] & SDHCI_CAN_VDD_300) {
3236 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3237
3238 mmc->max_current_300 = ((max_current_caps &
3239 SDHCI_MAX_CURRENT_300_MASK) >>
3240 SDHCI_MAX_CURRENT_300_SHIFT) *
3241 SDHCI_MAX_CURRENT_MULTIPLIER;
3242 }
3243 if (caps[0] & SDHCI_CAN_VDD_180) {
3244 ocr_avail |= MMC_VDD_165_195;
3245
3246 mmc->max_current_180 = ((max_current_caps &
3247 SDHCI_MAX_CURRENT_180_MASK) >>
3248 SDHCI_MAX_CURRENT_180_SHIFT) *
3249 SDHCI_MAX_CURRENT_MULTIPLIER;
3250 }
3251
3252 /* If OCR set by host, use it instead. */
3253 if (host->ocr_mask)
3254 ocr_avail = host->ocr_mask;
3255
3256 /* If OCR set by external regulators, give it highest prio. */
3257 if (mmc->ocr_avail)
3258 ocr_avail = mmc->ocr_avail;
3259
3260 mmc->ocr_avail = ocr_avail;
3261 mmc->ocr_avail_sdio = ocr_avail;
3262 if (host->ocr_avail_sdio)
3263 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3264 mmc->ocr_avail_sd = ocr_avail;
3265 if (host->ocr_avail_sd)
3266 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3267 else /* normal SD controllers don't support 1.8V */
3268 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3269 mmc->ocr_avail_mmc = ocr_avail;
3270 if (host->ocr_avail_mmc)
3271 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3272
3273 if (mmc->ocr_avail == 0) {
3274 pr_err("%s: Hardware doesn't report any support voltages.\n",
3275 mmc_hostname(mmc));
3276 ret = -ENODEV;
3277 goto unreg;
3278 }
3279
3280 spin_lock_init(&host->lock);
3281
3282 /*
3283 * Maximum number of segments. Depends on if the hardware
3284 * can do scatter/gather or not.
3285 */
3286 if (host->flags & SDHCI_USE_ADMA)
3287 mmc->max_segs = SDHCI_MAX_SEGS;
3288 else if (host->flags & SDHCI_USE_SDMA)
3289 mmc->max_segs = 1;
3290 else /* PIO */
3291 mmc->max_segs = SDHCI_MAX_SEGS;
3292
3293 /*
3294 * Maximum number of sectors in one transfer. Limited by SDMA boundary
3295 * size (512KiB). Note some tuning modes impose a 4MiB limit, but this
3296 * is less anyway.
3297 */
3298 mmc->max_req_size = 524288;
3299
3300 /*
3301 * Maximum segment size. Could be one segment with the maximum number
3302 * of bytes. When doing hardware scatter/gather, each entry cannot
3303 * be larger than 64 KiB though.
3304 */
3305 if (host->flags & SDHCI_USE_ADMA) {
3306 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3307 mmc->max_seg_size = 65535;
3308 else
3309 mmc->max_seg_size = 65536;
3310 } else {
3311 mmc->max_seg_size = mmc->max_req_size;
3312 }
3313
3314 /*
3315 * Maximum block size. This varies from controller to controller and
3316 * is specified in the capabilities register.
3317 */
3318 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3319 mmc->max_blk_size = 2;
3320 } else {
3321 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3322 SDHCI_MAX_BLOCK_SHIFT;
3323 if (mmc->max_blk_size >= 3) {
3324 pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n",
3325 mmc_hostname(mmc));
3326 mmc->max_blk_size = 0;
3327 }
3328 }
3329
3330 mmc->max_blk_size = 512 << mmc->max_blk_size;
3331
3332 /*
3333 * Maximum block count.
3334 */
3335 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3336
3337 /*
3338 * Init tasklets.
3339 */
3340 tasklet_init(&host->finish_tasklet,
3341 sdhci_tasklet_finish, (unsigned long)host);
3342
3343 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3344
3345 init_waitqueue_head(&host->buf_ready_int);
3346
3347 sdhci_init(host, 0);
3348
3349 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3350 IRQF_SHARED, mmc_hostname(mmc), host);
3351 if (ret) {
3352 pr_err("%s: Failed to request IRQ %d: %d\n",
3353 mmc_hostname(mmc), host->irq, ret);
3354 goto untasklet;
3355 }
3356
3357 #ifdef CONFIG_MMC_DEBUG
3358 sdhci_dumpregs(host);
3359 #endif
3360
3361 ret = sdhci_led_register(host);
3362 if (ret) {
3363 pr_err("%s: Failed to register LED device: %d\n",
3364 mmc_hostname(mmc), ret);
3365 goto unirq;
3366 }
3367
3368 mmiowb();
3369
3370 ret = mmc_add_host(mmc);
3371 if (ret)
3372 goto unled;
3373
3374 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3375 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3376 (host->flags & SDHCI_USE_ADMA) ?
3377 (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" :
3378 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3379
3380 sdhci_enable_card_detection(host);
3381
3382 return 0;
3383
3384 unled:
3385 sdhci_led_unregister(host);
3386 unirq:
3387 sdhci_do_reset(host, SDHCI_RESET_ALL);
3388 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3389 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3390 free_irq(host->irq, host);
3391 untasklet:
3392 tasklet_kill(&host->finish_tasklet);
3393 unreg:
3394 if (!IS_ERR(mmc->supply.vqmmc))
3395 regulator_disable(mmc->supply.vqmmc);
3396 undma:
3397 if (host->align_buffer)
3398 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3399 host->adma_table_sz, host->align_buffer,
3400 host->align_addr);
3401 host->adma_table = NULL;
3402 host->align_buffer = NULL;
3403
3404 return ret;
3405 }
3406
3407 EXPORT_SYMBOL_GPL(sdhci_add_host);
3408
3409 void sdhci_remove_host(struct sdhci_host *host, int dead)
3410 {
3411 struct mmc_host *mmc = host->mmc;
3412 unsigned long flags;
3413
3414 if (dead) {
3415 spin_lock_irqsave(&host->lock, flags);
3416
3417 host->flags |= SDHCI_DEVICE_DEAD;
3418
3419 if (host->mrq) {
3420 pr_err("%s: Controller removed during "
3421 " transfer!\n", mmc_hostname(mmc));
3422
3423 host->mrq->cmd->error = -ENOMEDIUM;
3424 tasklet_schedule(&host->finish_tasklet);
3425 }
3426
3427 spin_unlock_irqrestore(&host->lock, flags);
3428 }
3429
3430 sdhci_disable_card_detection(host);
3431
3432 mmc_remove_host(mmc);
3433
3434 sdhci_led_unregister(host);
3435
3436 if (!dead)
3437 sdhci_do_reset(host, SDHCI_RESET_ALL);
3438
3439 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3440 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3441 free_irq(host->irq, host);
3442
3443 del_timer_sync(&host->timer);
3444
3445 tasklet_kill(&host->finish_tasklet);
3446
3447 if (!IS_ERR(mmc->supply.vqmmc))
3448 regulator_disable(mmc->supply.vqmmc);
3449
3450 if (host->align_buffer)
3451 dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz +
3452 host->adma_table_sz, host->align_buffer,
3453 host->align_addr);
3454
3455 host->adma_table = NULL;
3456 host->align_buffer = NULL;
3457 }
3458
3459 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3460
3461 void sdhci_free_host(struct sdhci_host *host)
3462 {
3463 mmc_free_host(host->mmc);
3464 }
3465
3466 EXPORT_SYMBOL_GPL(sdhci_free_host);
3467
3468 /*****************************************************************************\
3469 * *
3470 * Driver init/exit *
3471 * *
3472 \*****************************************************************************/
3473
3474 static int __init sdhci_drv_init(void)
3475 {
3476 pr_info(DRIVER_NAME
3477 ": Secure Digital Host Controller Interface driver\n");
3478 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3479
3480 return 0;
3481 }
3482
3483 static void __exit sdhci_drv_exit(void)
3484 {
3485 }
3486
3487 module_init(sdhci_drv_init);
3488 module_exit(sdhci_drv_exit);
3489
3490 module_param(debug_quirks, uint, 0444);
3491 module_param(debug_quirks2, uint, 0444);
3492
3493 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3494 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3495 MODULE_LICENSE("GPL");
3496
3497 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3498 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");
Linux kernel - Deliverables
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