2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/scatterlist.h>
22 #include <linux/leds.h>
24 #include <linux/mmc/host.h>
28 #define DRIVER_NAME "sdhci"
30 #define DBG(f, x...) \
31 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
33 static unsigned int debug_quirks
= 0;
35 static void sdhci_prepare_data(struct sdhci_host
*, struct mmc_data
*);
36 static void sdhci_finish_data(struct sdhci_host
*);
38 static void sdhci_send_command(struct sdhci_host
*, struct mmc_command
*);
39 static void sdhci_finish_command(struct sdhci_host
*);
41 static void sdhci_dumpregs(struct sdhci_host
*host
)
43 printk(KERN_DEBUG DRIVER_NAME
": ============== REGISTER DUMP ==============\n");
45 printk(KERN_DEBUG DRIVER_NAME
": Sys addr: 0x%08x | Version: 0x%08x\n",
46 readl(host
->ioaddr
+ SDHCI_DMA_ADDRESS
),
47 readw(host
->ioaddr
+ SDHCI_HOST_VERSION
));
48 printk(KERN_DEBUG DRIVER_NAME
": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
49 readw(host
->ioaddr
+ SDHCI_BLOCK_SIZE
),
50 readw(host
->ioaddr
+ SDHCI_BLOCK_COUNT
));
51 printk(KERN_DEBUG DRIVER_NAME
": Argument: 0x%08x | Trn mode: 0x%08x\n",
52 readl(host
->ioaddr
+ SDHCI_ARGUMENT
),
53 readw(host
->ioaddr
+ SDHCI_TRANSFER_MODE
));
54 printk(KERN_DEBUG DRIVER_NAME
": Present: 0x%08x | Host ctl: 0x%08x\n",
55 readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
),
56 readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
));
57 printk(KERN_DEBUG DRIVER_NAME
": Power: 0x%08x | Blk gap: 0x%08x\n",
58 readb(host
->ioaddr
+ SDHCI_POWER_CONTROL
),
59 readb(host
->ioaddr
+ SDHCI_BLOCK_GAP_CONTROL
));
60 printk(KERN_DEBUG DRIVER_NAME
": Wake-up: 0x%08x | Clock: 0x%08x\n",
61 readb(host
->ioaddr
+ SDHCI_WAKE_UP_CONTROL
),
62 readw(host
->ioaddr
+ SDHCI_CLOCK_CONTROL
));
63 printk(KERN_DEBUG DRIVER_NAME
": Timeout: 0x%08x | Int stat: 0x%08x\n",
64 readb(host
->ioaddr
+ SDHCI_TIMEOUT_CONTROL
),
65 readl(host
->ioaddr
+ SDHCI_INT_STATUS
));
66 printk(KERN_DEBUG DRIVER_NAME
": Int enab: 0x%08x | Sig enab: 0x%08x\n",
67 readl(host
->ioaddr
+ SDHCI_INT_ENABLE
),
68 readl(host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
));
69 printk(KERN_DEBUG DRIVER_NAME
": AC12 err: 0x%08x | Slot int: 0x%08x\n",
70 readw(host
->ioaddr
+ SDHCI_ACMD12_ERR
),
71 readw(host
->ioaddr
+ SDHCI_SLOT_INT_STATUS
));
72 printk(KERN_DEBUG DRIVER_NAME
": Caps: 0x%08x | Max curr: 0x%08x\n",
73 readl(host
->ioaddr
+ SDHCI_CAPABILITIES
),
74 readl(host
->ioaddr
+ SDHCI_MAX_CURRENT
));
76 printk(KERN_DEBUG DRIVER_NAME
": ===========================================\n");
79 /*****************************************************************************\
81 * Low level functions *
83 \*****************************************************************************/
85 static void sdhci_reset(struct sdhci_host
*host
, u8 mask
)
87 unsigned long timeout
;
89 if (host
->quirks
& SDHCI_QUIRK_NO_CARD_NO_RESET
) {
90 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) &
95 writeb(mask
, host
->ioaddr
+ SDHCI_SOFTWARE_RESET
);
97 if (mask
& SDHCI_RESET_ALL
)
100 /* Wait max 100 ms */
103 /* hw clears the bit when it's done */
104 while (readb(host
->ioaddr
+ SDHCI_SOFTWARE_RESET
) & mask
) {
106 printk(KERN_ERR
"%s: Reset 0x%x never completed.\n",
107 mmc_hostname(host
->mmc
), (int)mask
);
108 sdhci_dumpregs(host
);
116 static void sdhci_init(struct sdhci_host
*host
)
120 sdhci_reset(host
, SDHCI_RESET_ALL
);
122 intmask
= SDHCI_INT_BUS_POWER
| SDHCI_INT_DATA_END_BIT
|
123 SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_TIMEOUT
| SDHCI_INT_INDEX
|
124 SDHCI_INT_END_BIT
| SDHCI_INT_CRC
| SDHCI_INT_TIMEOUT
|
125 SDHCI_INT_CARD_REMOVE
| SDHCI_INT_CARD_INSERT
|
126 SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
|
127 SDHCI_INT_DMA_END
| SDHCI_INT_DATA_END
| SDHCI_INT_RESPONSE
|
128 SDHCI_INT_ADMA_ERROR
;
130 writel(intmask
, host
->ioaddr
+ SDHCI_INT_ENABLE
);
131 writel(intmask
, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
134 static void sdhci_activate_led(struct sdhci_host
*host
)
138 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
139 ctrl
|= SDHCI_CTRL_LED
;
140 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
143 static void sdhci_deactivate_led(struct sdhci_host
*host
)
147 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
148 ctrl
&= ~SDHCI_CTRL_LED
;
149 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
152 #ifdef CONFIG_LEDS_CLASS
153 static void sdhci_led_control(struct led_classdev
*led
,
154 enum led_brightness brightness
)
156 struct sdhci_host
*host
= container_of(led
, struct sdhci_host
, led
);
159 spin_lock_irqsave(&host
->lock
, flags
);
161 if (brightness
== LED_OFF
)
162 sdhci_deactivate_led(host
);
164 sdhci_activate_led(host
);
166 spin_unlock_irqrestore(&host
->lock
, flags
);
170 /*****************************************************************************\
174 \*****************************************************************************/
176 static inline char* sdhci_sg_to_buffer(struct sdhci_host
* host
)
178 return sg_virt(host
->cur_sg
);
181 static inline int sdhci_next_sg(struct sdhci_host
* host
)
184 * Skip to next SG entry.
192 if (host
->num_sg
> 0) {
194 host
->remain
= host
->cur_sg
->length
;
200 static void sdhci_read_block_pio(struct sdhci_host
*host
)
202 int blksize
, chunk_remain
;
207 DBG("PIO reading\n");
209 blksize
= host
->data
->blksz
;
213 buffer
= sdhci_sg_to_buffer(host
) + host
->offset
;
216 if (chunk_remain
== 0) {
217 data
= readl(host
->ioaddr
+ SDHCI_BUFFER
);
218 chunk_remain
= min(blksize
, 4);
221 size
= min(host
->remain
, chunk_remain
);
223 chunk_remain
-= size
;
225 host
->offset
+= size
;
226 host
->remain
-= size
;
229 *buffer
= data
& 0xFF;
235 if (host
->remain
== 0) {
236 if (sdhci_next_sg(host
) == 0) {
237 BUG_ON(blksize
!= 0);
240 buffer
= sdhci_sg_to_buffer(host
);
245 static void sdhci_write_block_pio(struct sdhci_host
*host
)
247 int blksize
, chunk_remain
;
252 DBG("PIO writing\n");
254 blksize
= host
->data
->blksz
;
259 buffer
= sdhci_sg_to_buffer(host
) + host
->offset
;
262 size
= min(host
->remain
, chunk_remain
);
264 chunk_remain
-= size
;
266 host
->offset
+= size
;
267 host
->remain
-= size
;
271 data
|= (u32
)*buffer
<< 24;
276 if (chunk_remain
== 0) {
277 writel(data
, host
->ioaddr
+ SDHCI_BUFFER
);
278 chunk_remain
= min(blksize
, 4);
281 if (host
->remain
== 0) {
282 if (sdhci_next_sg(host
) == 0) {
283 BUG_ON(blksize
!= 0);
286 buffer
= sdhci_sg_to_buffer(host
);
291 static void sdhci_transfer_pio(struct sdhci_host
*host
)
297 if (host
->num_sg
== 0)
300 if (host
->data
->flags
& MMC_DATA_READ
)
301 mask
= SDHCI_DATA_AVAILABLE
;
303 mask
= SDHCI_SPACE_AVAILABLE
;
305 while (readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & mask
) {
306 if (host
->data
->flags
& MMC_DATA_READ
)
307 sdhci_read_block_pio(host
);
309 sdhci_write_block_pio(host
);
311 if (host
->num_sg
== 0)
315 DBG("PIO transfer complete.\n");
318 static char *sdhci_kmap_atomic(struct scatterlist
*sg
, unsigned long *flags
)
320 local_irq_save(*flags
);
321 return kmap_atomic(sg_page(sg
), KM_BIO_SRC_IRQ
) + sg
->offset
;
324 static void sdhci_kunmap_atomic(void *buffer
, unsigned long *flags
)
326 kunmap_atomic(buffer
, KM_BIO_SRC_IRQ
);
327 local_irq_restore(*flags
);
330 static int sdhci_adma_table_pre(struct sdhci_host
*host
,
331 struct mmc_data
*data
)
338 dma_addr_t align_addr
;
341 struct scatterlist
*sg
;
347 * The spec does not specify endianness of descriptor table.
348 * We currently guess that it is LE.
351 if (data
->flags
& MMC_DATA_READ
)
352 direction
= DMA_FROM_DEVICE
;
354 direction
= DMA_TO_DEVICE
;
357 * The ADMA descriptor table is mapped further down as we
358 * need to fill it with data first.
361 host
->align_addr
= dma_map_single(mmc_dev(host
->mmc
),
362 host
->align_buffer
, 128 * 4, direction
);
363 if (dma_mapping_error(host
->align_addr
))
365 BUG_ON(host
->align_addr
& 0x3);
367 host
->sg_count
= dma_map_sg(mmc_dev(host
->mmc
),
368 data
->sg
, data
->sg_len
, direction
);
369 if (host
->sg_count
== 0)
372 desc
= host
->adma_desc
;
373 align
= host
->align_buffer
;
375 align_addr
= host
->align_addr
;
377 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
378 addr
= sg_dma_address(sg
);
379 len
= sg_dma_len(sg
);
382 * The SDHCI specification states that ADMA
383 * addresses must be 32-bit aligned. If they
384 * aren't, then we use a bounce buffer for
385 * the (up to three) bytes that screw up the
388 offset
= (4 - (addr
& 0x3)) & 0x3;
390 if (data
->flags
& MMC_DATA_WRITE
) {
391 buffer
= sdhci_kmap_atomic(sg
, &flags
);
392 memcpy(align
, buffer
, offset
);
393 sdhci_kunmap_atomic(buffer
, &flags
);
396 desc
[7] = (align_addr
>> 24) & 0xff;
397 desc
[6] = (align_addr
>> 16) & 0xff;
398 desc
[5] = (align_addr
>> 8) & 0xff;
399 desc
[4] = (align_addr
>> 0) & 0xff;
401 BUG_ON(offset
> 65536);
403 desc
[3] = (offset
>> 8) & 0xff;
404 desc
[2] = (offset
>> 0) & 0xff;
407 desc
[0] = 0x21; /* tran, valid */
418 desc
[7] = (addr
>> 24) & 0xff;
419 desc
[6] = (addr
>> 16) & 0xff;
420 desc
[5] = (addr
>> 8) & 0xff;
421 desc
[4] = (addr
>> 0) & 0xff;
425 desc
[3] = (len
>> 8) & 0xff;
426 desc
[2] = (len
>> 0) & 0xff;
429 desc
[0] = 0x21; /* tran, valid */
434 * If this triggers then we have a calculation bug
437 WARN_ON((desc
- host
->adma_desc
) > (128 * 2 + 1) * 4);
441 * Add a terminating entry.
452 desc
[0] = 0x03; /* nop, end, valid */
455 * Resync align buffer as we might have changed it.
457 if (data
->flags
& MMC_DATA_WRITE
) {
458 dma_sync_single_for_device(mmc_dev(host
->mmc
),
459 host
->align_addr
, 128 * 4, direction
);
462 host
->adma_addr
= dma_map_single(mmc_dev(host
->mmc
),
463 host
->adma_desc
, (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
464 if (dma_mapping_error(host
->align_addr
))
466 BUG_ON(host
->adma_addr
& 0x3);
471 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
472 data
->sg_len
, direction
);
474 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
480 static void sdhci_adma_table_post(struct sdhci_host
*host
,
481 struct mmc_data
*data
)
485 struct scatterlist
*sg
;
491 if (data
->flags
& MMC_DATA_READ
)
492 direction
= DMA_FROM_DEVICE
;
494 direction
= DMA_TO_DEVICE
;
496 dma_unmap_single(mmc_dev(host
->mmc
), host
->adma_addr
,
497 (128 * 2 + 1) * 4, DMA_TO_DEVICE
);
499 dma_unmap_single(mmc_dev(host
->mmc
), host
->align_addr
,
502 if (data
->flags
& MMC_DATA_READ
) {
503 dma_sync_sg_for_cpu(mmc_dev(host
->mmc
), data
->sg
,
504 data
->sg_len
, direction
);
506 align
= host
->align_buffer
;
508 for_each_sg(data
->sg
, sg
, host
->sg_count
, i
) {
509 if (sg_dma_address(sg
) & 0x3) {
510 size
= 4 - (sg_dma_address(sg
) & 0x3);
512 buffer
= sdhci_kmap_atomic(sg
, &flags
);
513 memcpy(buffer
, align
, size
);
514 sdhci_kunmap_atomic(buffer
, &flags
);
521 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
522 data
->sg_len
, direction
);
525 static u8
sdhci_calc_timeout(struct sdhci_host
*host
, struct mmc_data
*data
)
528 unsigned target_timeout
, current_timeout
;
531 * If the host controller provides us with an incorrect timeout
532 * value, just skip the check and use 0xE. The hardware may take
533 * longer to time out, but that's much better than having a too-short
536 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
))
540 target_timeout
= data
->timeout_ns
/ 1000 +
541 data
->timeout_clks
/ host
->clock
;
544 * Figure out needed cycles.
545 * We do this in steps in order to fit inside a 32 bit int.
546 * The first step is the minimum timeout, which will have a
547 * minimum resolution of 6 bits:
548 * (1) 2^13*1000 > 2^22,
549 * (2) host->timeout_clk < 2^16
554 current_timeout
= (1 << 13) * 1000 / host
->timeout_clk
;
555 while (current_timeout
< target_timeout
) {
557 current_timeout
<<= 1;
563 printk(KERN_WARNING
"%s: Too large timeout requested!\n",
564 mmc_hostname(host
->mmc
));
571 static void sdhci_prepare_data(struct sdhci_host
*host
, struct mmc_data
*data
)
583 BUG_ON(data
->blksz
* data
->blocks
> 524288);
584 BUG_ON(data
->blksz
> host
->mmc
->max_blk_size
);
585 BUG_ON(data
->blocks
> 65535);
588 host
->data_early
= 0;
590 count
= sdhci_calc_timeout(host
, data
);
591 writeb(count
, host
->ioaddr
+ SDHCI_TIMEOUT_CONTROL
);
593 if (host
->flags
& SDHCI_USE_DMA
)
594 host
->flags
|= SDHCI_REQ_USE_DMA
;
597 * FIXME: This doesn't account for merging when mapping the
600 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
602 struct scatterlist
*sg
;
605 if (host
->flags
& SDHCI_USE_ADMA
) {
606 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
609 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_SIZE
)
613 if (unlikely(broken
)) {
614 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
615 if (sg
->length
& 0x3) {
616 DBG("Reverting to PIO because of "
617 "transfer size (%d)\n",
619 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
627 * The assumption here being that alignment is the same after
628 * translation to device address space.
630 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
632 struct scatterlist
*sg
;
635 if (host
->flags
& SDHCI_USE_ADMA
) {
637 * As we use 3 byte chunks to work around
638 * alignment problems, we need to check this
641 if (host
->quirks
& SDHCI_QUIRK_32BIT_ADMA_SIZE
)
644 if (host
->quirks
& SDHCI_QUIRK_32BIT_DMA_ADDR
)
648 if (unlikely(broken
)) {
649 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
650 if (sg
->offset
& 0x3) {
651 DBG("Reverting to PIO because of "
653 host
->flags
&= ~SDHCI_REQ_USE_DMA
;
660 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
661 if (host
->flags
& SDHCI_USE_ADMA
) {
662 ret
= sdhci_adma_table_pre(host
, data
);
665 * This only happens when someone fed
666 * us an invalid request.
669 host
->flags
&= ~SDHCI_USE_DMA
;
671 writel(host
->adma_addr
,
672 host
->ioaddr
+ SDHCI_ADMA_ADDRESS
);
677 sg_cnt
= dma_map_sg(mmc_dev(host
->mmc
),
678 data
->sg
, data
->sg_len
,
679 (data
->flags
& MMC_DATA_READ
) ?
684 * This only happens when someone fed
685 * us an invalid request.
688 host
->flags
&= ~SDHCI_USE_DMA
;
691 writel(sg_dma_address(data
->sg
),
692 host
->ioaddr
+ SDHCI_DMA_ADDRESS
);
698 * Always adjust the DMA selection as some controllers
699 * (e.g. JMicron) can't do PIO properly when the selection
702 if (host
->version
>= SDHCI_SPEC_200
) {
703 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
704 ctrl
&= ~SDHCI_CTRL_DMA_MASK
;
705 if ((host
->flags
& SDHCI_REQ_USE_DMA
) &&
706 (host
->flags
& SDHCI_USE_ADMA
))
707 ctrl
|= SDHCI_CTRL_ADMA32
;
709 ctrl
|= SDHCI_CTRL_SDMA
;
710 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
713 if (!(host
->flags
& SDHCI_REQ_USE_DMA
)) {
714 host
->cur_sg
= data
->sg
;
715 host
->num_sg
= data
->sg_len
;
718 host
->remain
= host
->cur_sg
->length
;
721 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
722 writew(SDHCI_MAKE_BLKSZ(7, data
->blksz
),
723 host
->ioaddr
+ SDHCI_BLOCK_SIZE
);
724 writew(data
->blocks
, host
->ioaddr
+ SDHCI_BLOCK_COUNT
);
727 static void sdhci_set_transfer_mode(struct sdhci_host
*host
,
728 struct mmc_data
*data
)
735 WARN_ON(!host
->data
);
737 mode
= SDHCI_TRNS_BLK_CNT_EN
;
738 if (data
->blocks
> 1)
739 mode
|= SDHCI_TRNS_MULTI
;
740 if (data
->flags
& MMC_DATA_READ
)
741 mode
|= SDHCI_TRNS_READ
;
742 if (host
->flags
& SDHCI_REQ_USE_DMA
)
743 mode
|= SDHCI_TRNS_DMA
;
745 writew(mode
, host
->ioaddr
+ SDHCI_TRANSFER_MODE
);
748 static void sdhci_finish_data(struct sdhci_host
*host
)
750 struct mmc_data
*data
;
757 if (host
->flags
& SDHCI_REQ_USE_DMA
) {
758 if (host
->flags
& SDHCI_USE_ADMA
)
759 sdhci_adma_table_post(host
, data
);
761 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
,
762 data
->sg_len
, (data
->flags
& MMC_DATA_READ
) ?
763 DMA_FROM_DEVICE
: DMA_TO_DEVICE
);
768 * The specification states that the block count register must
769 * be updated, but it does not specify at what point in the
770 * data flow. That makes the register entirely useless to read
771 * back so we have to assume that nothing made it to the card
772 * in the event of an error.
775 data
->bytes_xfered
= 0;
777 data
->bytes_xfered
= data
->blksz
* data
->blocks
;
781 * The controller needs a reset of internal state machines
782 * upon error conditions.
785 sdhci_reset(host
, SDHCI_RESET_CMD
);
786 sdhci_reset(host
, SDHCI_RESET_DATA
);
789 sdhci_send_command(host
, data
->stop
);
791 tasklet_schedule(&host
->finish_tasklet
);
794 static void sdhci_send_command(struct sdhci_host
*host
, struct mmc_command
*cmd
)
798 unsigned long timeout
;
805 mask
= SDHCI_CMD_INHIBIT
;
806 if ((cmd
->data
!= NULL
) || (cmd
->flags
& MMC_RSP_BUSY
))
807 mask
|= SDHCI_DATA_INHIBIT
;
809 /* We shouldn't wait for data inihibit for stop commands, even
810 though they might use busy signaling */
811 if (host
->mrq
->data
&& (cmd
== host
->mrq
->data
->stop
))
812 mask
&= ~SDHCI_DATA_INHIBIT
;
814 while (readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & mask
) {
816 printk(KERN_ERR
"%s: Controller never released "
817 "inhibit bit(s).\n", mmc_hostname(host
->mmc
));
818 sdhci_dumpregs(host
);
820 tasklet_schedule(&host
->finish_tasklet
);
827 mod_timer(&host
->timer
, jiffies
+ 10 * HZ
);
831 sdhci_prepare_data(host
, cmd
->data
);
833 writel(cmd
->arg
, host
->ioaddr
+ SDHCI_ARGUMENT
);
835 sdhci_set_transfer_mode(host
, cmd
->data
);
837 if ((cmd
->flags
& MMC_RSP_136
) && (cmd
->flags
& MMC_RSP_BUSY
)) {
838 printk(KERN_ERR
"%s: Unsupported response type!\n",
839 mmc_hostname(host
->mmc
));
840 cmd
->error
= -EINVAL
;
841 tasklet_schedule(&host
->finish_tasklet
);
845 if (!(cmd
->flags
& MMC_RSP_PRESENT
))
846 flags
= SDHCI_CMD_RESP_NONE
;
847 else if (cmd
->flags
& MMC_RSP_136
)
848 flags
= SDHCI_CMD_RESP_LONG
;
849 else if (cmd
->flags
& MMC_RSP_BUSY
)
850 flags
= SDHCI_CMD_RESP_SHORT_BUSY
;
852 flags
= SDHCI_CMD_RESP_SHORT
;
854 if (cmd
->flags
& MMC_RSP_CRC
)
855 flags
|= SDHCI_CMD_CRC
;
856 if (cmd
->flags
& MMC_RSP_OPCODE
)
857 flags
|= SDHCI_CMD_INDEX
;
859 flags
|= SDHCI_CMD_DATA
;
861 writew(SDHCI_MAKE_CMD(cmd
->opcode
, flags
),
862 host
->ioaddr
+ SDHCI_COMMAND
);
865 static void sdhci_finish_command(struct sdhci_host
*host
)
869 BUG_ON(host
->cmd
== NULL
);
871 if (host
->cmd
->flags
& MMC_RSP_PRESENT
) {
872 if (host
->cmd
->flags
& MMC_RSP_136
) {
873 /* CRC is stripped so we need to do some shifting. */
874 for (i
= 0;i
< 4;i
++) {
875 host
->cmd
->resp
[i
] = readl(host
->ioaddr
+
876 SDHCI_RESPONSE
+ (3-i
)*4) << 8;
878 host
->cmd
->resp
[i
] |=
880 SDHCI_RESPONSE
+ (3-i
)*4-1);
883 host
->cmd
->resp
[0] = readl(host
->ioaddr
+ SDHCI_RESPONSE
);
887 host
->cmd
->error
= 0;
889 if (host
->data
&& host
->data_early
)
890 sdhci_finish_data(host
);
892 if (!host
->cmd
->data
)
893 tasklet_schedule(&host
->finish_tasklet
);
898 static void sdhci_set_clock(struct sdhci_host
*host
, unsigned int clock
)
902 unsigned long timeout
;
904 if (clock
== host
->clock
)
907 writew(0, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
912 for (div
= 1;div
< 256;div
*= 2) {
913 if ((host
->max_clk
/ div
) <= clock
)
918 clk
= div
<< SDHCI_DIVIDER_SHIFT
;
919 clk
|= SDHCI_CLOCK_INT_EN
;
920 writew(clk
, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
924 while (!((clk
= readw(host
->ioaddr
+ SDHCI_CLOCK_CONTROL
))
925 & SDHCI_CLOCK_INT_STABLE
)) {
927 printk(KERN_ERR
"%s: Internal clock never "
928 "stabilised.\n", mmc_hostname(host
->mmc
));
929 sdhci_dumpregs(host
);
936 clk
|= SDHCI_CLOCK_CARD_EN
;
937 writew(clk
, host
->ioaddr
+ SDHCI_CLOCK_CONTROL
);
943 static void sdhci_set_power(struct sdhci_host
*host
, unsigned short power
)
947 if (host
->power
== power
)
950 if (power
== (unsigned short)-1) {
951 writeb(0, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
956 * Spec says that we should clear the power reg before setting
957 * a new value. Some controllers don't seem to like this though.
959 if (!(host
->quirks
& SDHCI_QUIRK_SINGLE_POWER_WRITE
))
960 writeb(0, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
962 pwr
= SDHCI_POWER_ON
;
964 switch (1 << power
) {
965 case MMC_VDD_165_195
:
966 pwr
|= SDHCI_POWER_180
;
970 pwr
|= SDHCI_POWER_300
;
974 pwr
|= SDHCI_POWER_330
;
981 * At least the Marvell CaFe chip gets confused if we set the voltage
982 * and set turn on power at the same time, so set the voltage first.
984 if ((host
->quirks
& SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER
))
985 writeb(pwr
& ~SDHCI_POWER_ON
,
986 host
->ioaddr
+ SDHCI_POWER_CONTROL
);
988 writeb(pwr
, host
->ioaddr
+ SDHCI_POWER_CONTROL
);
994 /*****************************************************************************\
998 \*****************************************************************************/
1000 static void sdhci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
1002 struct sdhci_host
*host
;
1003 unsigned long flags
;
1005 host
= mmc_priv(mmc
);
1007 spin_lock_irqsave(&host
->lock
, flags
);
1009 WARN_ON(host
->mrq
!= NULL
);
1011 #ifndef CONFIG_LEDS_CLASS
1012 sdhci_activate_led(host
);
1017 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)
1018 || (host
->flags
& SDHCI_DEVICE_DEAD
)) {
1019 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1020 tasklet_schedule(&host
->finish_tasklet
);
1022 sdhci_send_command(host
, mrq
->cmd
);
1025 spin_unlock_irqrestore(&host
->lock
, flags
);
1028 static void sdhci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1030 struct sdhci_host
*host
;
1031 unsigned long flags
;
1034 host
= mmc_priv(mmc
);
1036 spin_lock_irqsave(&host
->lock
, flags
);
1038 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1042 * Reset the chip on each power off.
1043 * Should clear out any weird states.
1045 if (ios
->power_mode
== MMC_POWER_OFF
) {
1046 writel(0, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
1050 sdhci_set_clock(host
, ios
->clock
);
1052 if (ios
->power_mode
== MMC_POWER_OFF
)
1053 sdhci_set_power(host
, -1);
1055 sdhci_set_power(host
, ios
->vdd
);
1057 ctrl
= readb(host
->ioaddr
+ SDHCI_HOST_CONTROL
);
1059 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
1060 ctrl
|= SDHCI_CTRL_4BITBUS
;
1062 ctrl
&= ~SDHCI_CTRL_4BITBUS
;
1064 if (ios
->timing
== MMC_TIMING_SD_HS
)
1065 ctrl
|= SDHCI_CTRL_HISPD
;
1067 ctrl
&= ~SDHCI_CTRL_HISPD
;
1069 writeb(ctrl
, host
->ioaddr
+ SDHCI_HOST_CONTROL
);
1072 * Some (ENE) controllers go apeshit on some ios operation,
1073 * signalling timeout and CRC errors even on CMD0. Resetting
1074 * it on each ios seems to solve the problem.
1076 if(host
->quirks
& SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS
)
1077 sdhci_reset(host
, SDHCI_RESET_CMD
| SDHCI_RESET_DATA
);
1081 spin_unlock_irqrestore(&host
->lock
, flags
);
1084 static int sdhci_get_ro(struct mmc_host
*mmc
)
1086 struct sdhci_host
*host
;
1087 unsigned long flags
;
1090 host
= mmc_priv(mmc
);
1092 spin_lock_irqsave(&host
->lock
, flags
);
1094 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1097 present
= readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
);
1099 spin_unlock_irqrestore(&host
->lock
, flags
);
1101 return !(present
& SDHCI_WRITE_PROTECT
);
1104 static void sdhci_enable_sdio_irq(struct mmc_host
*mmc
, int enable
)
1106 struct sdhci_host
*host
;
1107 unsigned long flags
;
1110 host
= mmc_priv(mmc
);
1112 spin_lock_irqsave(&host
->lock
, flags
);
1114 if (host
->flags
& SDHCI_DEVICE_DEAD
)
1117 ier
= readl(host
->ioaddr
+ SDHCI_INT_ENABLE
);
1119 ier
&= ~SDHCI_INT_CARD_INT
;
1121 ier
|= SDHCI_INT_CARD_INT
;
1123 writel(ier
, host
->ioaddr
+ SDHCI_INT_ENABLE
);
1124 writel(ier
, host
->ioaddr
+ SDHCI_SIGNAL_ENABLE
);
1129 spin_unlock_irqrestore(&host
->lock
, flags
);
1132 static const struct mmc_host_ops sdhci_ops
= {
1133 .request
= sdhci_request
,
1134 .set_ios
= sdhci_set_ios
,
1135 .get_ro
= sdhci_get_ro
,
1136 .enable_sdio_irq
= sdhci_enable_sdio_irq
,
1139 /*****************************************************************************\
1143 \*****************************************************************************/
1145 static void sdhci_tasklet_card(unsigned long param
)
1147 struct sdhci_host
*host
;
1148 unsigned long flags
;
1150 host
= (struct sdhci_host
*)param
;
1152 spin_lock_irqsave(&host
->lock
, flags
);
1154 if (!(readl(host
->ioaddr
+ SDHCI_PRESENT_STATE
) & SDHCI_CARD_PRESENT
)) {
1156 printk(KERN_ERR
"%s: Card removed during transfer!\n",
1157 mmc_hostname(host
->mmc
));
1158 printk(KERN_ERR
"%s: Resetting controller.\n",
1159 mmc_hostname(host
->mmc
));
1161 sdhci_reset(host
, SDHCI_RESET_CMD
);
1162 sdhci_reset(host
, SDHCI_RESET_DATA
);
1164 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1165 tasklet_schedule(&host
->finish_tasklet
);
1169 spin_unlock_irqrestore(&host
->lock
, flags
);
1171 mmc_detect_change(host
->mmc
, msecs_to_jiffies(500));
1174 static void sdhci_tasklet_finish(unsigned long param
)
1176 struct sdhci_host
*host
;
1177 unsigned long flags
;
1178 struct mmc_request
*mrq
;
1180 host
= (struct sdhci_host
*)param
;
1182 spin_lock_irqsave(&host
->lock
, flags
);
1184 del_timer(&host
->timer
);
1189 * The controller needs a reset of internal state machines
1190 * upon error conditions.
1192 if (!(host
->flags
& SDHCI_DEVICE_DEAD
) &&
1194 (mrq
->data
&& (mrq
->data
->error
||
1195 (mrq
->data
->stop
&& mrq
->data
->stop
->error
))) ||
1196 (host
->quirks
& SDHCI_QUIRK_RESET_AFTER_REQUEST
))) {
1198 /* Some controllers need this kick or reset won't work here */
1199 if (host
->quirks
& SDHCI_QUIRK_CLOCK_BEFORE_RESET
) {
1202 /* This is to force an update */
1203 clock
= host
->clock
;
1205 sdhci_set_clock(host
, clock
);
1208 /* Spec says we should do both at the same time, but Ricoh
1209 controllers do not like that. */
1210 sdhci_reset(host
, SDHCI_RESET_CMD
);
1211 sdhci_reset(host
, SDHCI_RESET_DATA
);
1218 #ifndef CONFIG_LEDS_CLASS
1219 sdhci_deactivate_led(host
);
1223 spin_unlock_irqrestore(&host
->lock
, flags
);
1225 mmc_request_done(host
->mmc
, mrq
);
1228 static void sdhci_timeout_timer(unsigned long data
)
1230 struct sdhci_host
*host
;
1231 unsigned long flags
;
1233 host
= (struct sdhci_host
*)data
;
1235 spin_lock_irqsave(&host
->lock
, flags
);
1238 printk(KERN_ERR
"%s: Timeout waiting for hardware "
1239 "interrupt.\n", mmc_hostname(host
->mmc
));
1240 sdhci_dumpregs(host
);
1243 host
->data
->error
= -ETIMEDOUT
;
1244 sdhci_finish_data(host
);
1247 host
->cmd
->error
= -ETIMEDOUT
;
1249 host
->mrq
->cmd
->error
= -ETIMEDOUT
;
1251 tasklet_schedule(&host
->finish_tasklet
);
1256 spin_unlock_irqrestore(&host
->lock
, flags
);
1259 /*****************************************************************************\
1261 * Interrupt handling *
1263 \*****************************************************************************/
1265 static void sdhci_cmd_irq(struct sdhci_host
*host
, u32 intmask
)
1267 BUG_ON(intmask
== 0);
1270 printk(KERN_ERR
"%s: Got command interrupt 0x%08x even "
1271 "though no command operation was in progress.\n",
1272 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1273 sdhci_dumpregs(host
);
1277 if (intmask
& SDHCI_INT_TIMEOUT
)
1278 host
->cmd
->error
= -ETIMEDOUT
;
1279 else if (intmask
& (SDHCI_INT_CRC
| SDHCI_INT_END_BIT
|
1281 host
->cmd
->error
= -EILSEQ
;
1283 if (host
->cmd
->error
)
1284 tasklet_schedule(&host
->finish_tasklet
);
1285 else if (intmask
& SDHCI_INT_RESPONSE
)
1286 sdhci_finish_command(host
);
1289 static void sdhci_data_irq(struct sdhci_host
*host
, u32 intmask
)
1291 BUG_ON(intmask
== 0);
1295 * A data end interrupt is sent together with the response
1296 * for the stop command.
1298 if (intmask
& SDHCI_INT_DATA_END
)
1301 printk(KERN_ERR
"%s: Got data interrupt 0x%08x even "
1302 "though no data operation was in progress.\n",
1303 mmc_hostname(host
->mmc
), (unsigned)intmask
);
1304 sdhci_dumpregs(host
);
1309 if (intmask
& SDHCI_INT_DATA_TIMEOUT
)
1310 host
->data
->error
= -ETIMEDOUT
;
1311 else if (intmask
& (SDHCI_INT_DATA_CRC
| SDHCI_INT_DATA_END_BIT
))
1312 host
->data
->error
= -EILSEQ
;
1313 else if (intmask
& SDHCI_INT_ADMA_ERROR
)
1314 host
->data
->error
= -EIO
;
1316 if (host
->data
->error
)
1317 sdhci_finish_data(host
);
1319 if (intmask
& (SDHCI_INT_DATA_AVAIL
| SDHCI_INT_SPACE_AVAIL
))
1320 sdhci_transfer_pio(host
);
1323 * We currently don't do anything fancy with DMA
1324 * boundaries, but as we can't disable the feature
1325 * we need to at least restart the transfer.
1327 if (intmask
& SDHCI_INT_DMA_END
)
1328 writel(readl(host
->ioaddr
+ SDHCI_DMA_ADDRESS
),
1329 host
->ioaddr
+ SDHCI_DMA_ADDRESS
);
1331 if (intmask
& SDHCI_INT_DATA_END
) {
1334 * Data managed to finish before the
1335 * command completed. Make sure we do
1336 * things in the proper order.
1338 host
->data_early
= 1;
1340 sdhci_finish_data(host
);
1346 static irqreturn_t
sdhci_irq(int irq
, void *dev_id
)
1349 struct sdhci_host
* host
= dev_id
;
1353 spin_lock(&host
->lock
);
1355 intmask
= readl(host
->ioaddr
+ SDHCI_INT_STATUS
);
1357 if (!intmask
|| intmask
== 0xffffffff) {
1362 DBG("*** %s got interrupt: 0x%08x\n",
1363 mmc_hostname(host
->mmc
), intmask
);
1365 if (intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
)) {
1366 writel(intmask
& (SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
),
1367 host
->ioaddr
+ SDHCI_INT_STATUS
);
1368 tasklet_schedule(&host
->card_tasklet
);
1371 intmask
&= ~(SDHCI_INT_CARD_INSERT
| SDHCI_INT_CARD_REMOVE
);
1373 if (intmask
& SDHCI_INT_CMD_MASK
) {
1374 writel(intmask
& SDHCI_INT_CMD_MASK
,
1375 host
->ioaddr
+ SDHCI_INT_STATUS
);
1376 sdhci_cmd_irq(host
, intmask
& SDHCI_INT_CMD_MASK
);
1379 if (intmask
& SDHCI_INT_DATA_MASK
) {
1380 writel(intmask
& SDHCI_INT_DATA_MASK
,
1381 host
->ioaddr
+ SDHCI_INT_STATUS
);
1382 sdhci_data_irq(host
, intmask
& SDHCI_INT_DATA_MASK
);
1385 intmask
&= ~(SDHCI_INT_CMD_MASK
| SDHCI_INT_DATA_MASK
);
1387 intmask
&= ~SDHCI_INT_ERROR
;
1389 if (intmask
& SDHCI_INT_BUS_POWER
) {
1390 printk(KERN_ERR
"%s: Card is consuming too much power!\n",
1391 mmc_hostname(host
->mmc
));
1392 writel(SDHCI_INT_BUS_POWER
, host
->ioaddr
+ SDHCI_INT_STATUS
);
1395 intmask
&= ~SDHCI_INT_BUS_POWER
;
1397 if (intmask
& SDHCI_INT_CARD_INT
)
1400 intmask
&= ~SDHCI_INT_CARD_INT
;
1403 printk(KERN_ERR
"%s: Unexpected interrupt 0x%08x.\n",
1404 mmc_hostname(host
->mmc
), intmask
);
1405 sdhci_dumpregs(host
);
1407 writel(intmask
, host
->ioaddr
+ SDHCI_INT_STATUS
);
1410 result
= IRQ_HANDLED
;
1414 spin_unlock(&host
->lock
);
1417 * We have to delay this as it calls back into the driver.
1420 mmc_signal_sdio_irq(host
->mmc
);
1425 /*****************************************************************************\
1429 \*****************************************************************************/
1433 int sdhci_suspend_host(struct sdhci_host
*host
, pm_message_t state
)
1437 ret
= mmc_suspend_host(host
->mmc
, state
);
1441 free_irq(host
->irq
, host
);
1446 EXPORT_SYMBOL_GPL(sdhci_suspend_host
);
1448 int sdhci_resume_host(struct sdhci_host
*host
)
1452 if (host
->flags
& SDHCI_USE_DMA
) {
1453 if (host
->ops
->enable_dma
)
1454 host
->ops
->enable_dma(host
);
1457 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
1458 mmc_hostname(host
->mmc
), host
);
1465 ret
= mmc_resume_host(host
->mmc
);
1472 EXPORT_SYMBOL_GPL(sdhci_resume_host
);
1474 #endif /* CONFIG_PM */
1476 /*****************************************************************************\
1478 * Device allocation/registration *
1480 \*****************************************************************************/
1482 struct sdhci_host
*sdhci_alloc_host(struct device
*dev
,
1485 struct mmc_host
*mmc
;
1486 struct sdhci_host
*host
;
1488 WARN_ON(dev
== NULL
);
1490 mmc
= mmc_alloc_host(sizeof(struct sdhci_host
) + priv_size
, dev
);
1492 return ERR_PTR(-ENOMEM
);
1494 host
= mmc_priv(mmc
);
1500 EXPORT_SYMBOL_GPL(sdhci_alloc_host
);
1502 int sdhci_add_host(struct sdhci_host
*host
)
1504 struct mmc_host
*mmc
;
1508 WARN_ON(host
== NULL
);
1515 host
->quirks
= debug_quirks
;
1517 sdhci_reset(host
, SDHCI_RESET_ALL
);
1519 host
->version
= readw(host
->ioaddr
+ SDHCI_HOST_VERSION
);
1520 host
->version
= (host
->version
& SDHCI_SPEC_VER_MASK
)
1521 >> SDHCI_SPEC_VER_SHIFT
;
1522 if (host
->version
> SDHCI_SPEC_200
) {
1523 printk(KERN_ERR
"%s: Unknown controller version (%d). "
1524 "You may experience problems.\n", mmc_hostname(mmc
),
1528 caps
= readl(host
->ioaddr
+ SDHCI_CAPABILITIES
);
1530 if (host
->quirks
& SDHCI_QUIRK_FORCE_DMA
)
1531 host
->flags
|= SDHCI_USE_DMA
;
1532 else if (!(caps
& SDHCI_CAN_DO_DMA
))
1533 DBG("Controller doesn't have DMA capability\n");
1535 host
->flags
|= SDHCI_USE_DMA
;
1537 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_DMA
) &&
1538 (host
->flags
& SDHCI_USE_DMA
)) {
1539 DBG("Disabling DMA as it is marked broken\n");
1540 host
->flags
&= ~SDHCI_USE_DMA
;
1543 if (host
->flags
& SDHCI_USE_DMA
) {
1544 if ((host
->version
>= SDHCI_SPEC_200
) &&
1545 (caps
& SDHCI_CAN_DO_ADMA2
))
1546 host
->flags
|= SDHCI_USE_ADMA
;
1549 if ((host
->quirks
& SDHCI_QUIRK_BROKEN_ADMA
) &&
1550 (host
->flags
& SDHCI_USE_ADMA
)) {
1551 DBG("Disabling ADMA as it is marked broken\n");
1552 host
->flags
&= ~SDHCI_USE_ADMA
;
1555 if (host
->flags
& SDHCI_USE_DMA
) {
1556 if (host
->ops
->enable_dma
) {
1557 if (host
->ops
->enable_dma(host
)) {
1558 printk(KERN_WARNING
"%s: No suitable DMA "
1559 "available. Falling back to PIO.\n",
1561 host
->flags
&= ~(SDHCI_USE_DMA
| SDHCI_USE_ADMA
);
1566 if (host
->flags
& SDHCI_USE_ADMA
) {
1568 * We need to allocate descriptors for all sg entries
1569 * (128) and potentially one alignment transfer for
1570 * each of those entries.
1572 host
->adma_desc
= kmalloc((128 * 2 + 1) * 4, GFP_KERNEL
);
1573 host
->align_buffer
= kmalloc(128 * 4, GFP_KERNEL
);
1574 if (!host
->adma_desc
|| !host
->align_buffer
) {
1575 kfree(host
->adma_desc
);
1576 kfree(host
->align_buffer
);
1577 printk(KERN_WARNING
"%s: Unable to allocate ADMA "
1578 "buffers. Falling back to standard DMA.\n",
1580 host
->flags
&= ~SDHCI_USE_ADMA
;
1584 /* XXX: Hack to get MMC layer to avoid highmem */
1585 if (!(host
->flags
& SDHCI_USE_DMA
))
1586 mmc_dev(host
->mmc
)->dma_mask
= NULL
;
1589 (caps
& SDHCI_CLOCK_BASE_MASK
) >> SDHCI_CLOCK_BASE_SHIFT
;
1590 if (host
->max_clk
== 0) {
1591 printk(KERN_ERR
"%s: Hardware doesn't specify base clock "
1592 "frequency.\n", mmc_hostname(mmc
));
1595 host
->max_clk
*= 1000000;
1598 (caps
& SDHCI_TIMEOUT_CLK_MASK
) >> SDHCI_TIMEOUT_CLK_SHIFT
;
1599 if (host
->timeout_clk
== 0) {
1600 printk(KERN_ERR
"%s: Hardware doesn't specify timeout clock "
1601 "frequency.\n", mmc_hostname(mmc
));
1604 if (caps
& SDHCI_TIMEOUT_CLK_UNIT
)
1605 host
->timeout_clk
*= 1000;
1608 * Set host parameters.
1610 mmc
->ops
= &sdhci_ops
;
1611 mmc
->f_min
= host
->max_clk
/ 256;
1612 mmc
->f_max
= host
->max_clk
;
1613 mmc
->caps
= MMC_CAP_4_BIT_DATA
| MMC_CAP_SDIO_IRQ
;
1615 if (caps
& SDHCI_CAN_DO_HISPD
)
1616 mmc
->caps
|= MMC_CAP_SD_HIGHSPEED
;
1619 if (caps
& SDHCI_CAN_VDD_330
)
1620 mmc
->ocr_avail
|= MMC_VDD_32_33
|MMC_VDD_33_34
;
1621 if (caps
& SDHCI_CAN_VDD_300
)
1622 mmc
->ocr_avail
|= MMC_VDD_29_30
|MMC_VDD_30_31
;
1623 if (caps
& SDHCI_CAN_VDD_180
)
1624 mmc
->ocr_avail
|= MMC_VDD_165_195
;
1626 if (mmc
->ocr_avail
== 0) {
1627 printk(KERN_ERR
"%s: Hardware doesn't report any "
1628 "support voltages.\n", mmc_hostname(mmc
));
1632 spin_lock_init(&host
->lock
);
1635 * Maximum number of segments. Depends on if the hardware
1636 * can do scatter/gather or not.
1638 if (host
->flags
& SDHCI_USE_ADMA
)
1639 mmc
->max_hw_segs
= 128;
1640 else if (host
->flags
& SDHCI_USE_DMA
)
1641 mmc
->max_hw_segs
= 1;
1643 mmc
->max_hw_segs
= 128;
1644 mmc
->max_phys_segs
= 128;
1647 * Maximum number of sectors in one transfer. Limited by DMA boundary
1650 mmc
->max_req_size
= 524288;
1653 * Maximum segment size. Could be one segment with the maximum number
1654 * of bytes. When doing hardware scatter/gather, each entry cannot
1655 * be larger than 64 KiB though.
1657 if (host
->flags
& SDHCI_USE_ADMA
)
1658 mmc
->max_seg_size
= 65536;
1660 mmc
->max_seg_size
= mmc
->max_req_size
;
1663 * Maximum block size. This varies from controller to controller and
1664 * is specified in the capabilities register.
1666 mmc
->max_blk_size
= (caps
& SDHCI_MAX_BLOCK_MASK
) >> SDHCI_MAX_BLOCK_SHIFT
;
1667 if (mmc
->max_blk_size
>= 3) {
1668 printk(KERN_WARNING
"%s: Invalid maximum block size, "
1669 "assuming 512 bytes\n", mmc_hostname(mmc
));
1670 mmc
->max_blk_size
= 512;
1672 mmc
->max_blk_size
= 512 << mmc
->max_blk_size
;
1675 * Maximum block count.
1677 mmc
->max_blk_count
= 65535;
1682 tasklet_init(&host
->card_tasklet
,
1683 sdhci_tasklet_card
, (unsigned long)host
);
1684 tasklet_init(&host
->finish_tasklet
,
1685 sdhci_tasklet_finish
, (unsigned long)host
);
1687 setup_timer(&host
->timer
, sdhci_timeout_timer
, (unsigned long)host
);
1689 ret
= request_irq(host
->irq
, sdhci_irq
, IRQF_SHARED
,
1690 mmc_hostname(mmc
), host
);
1696 #ifdef CONFIG_MMC_DEBUG
1697 sdhci_dumpregs(host
);
1700 #ifdef CONFIG_LEDS_CLASS
1701 host
->led
.name
= mmc_hostname(mmc
);
1702 host
->led
.brightness
= LED_OFF
;
1703 host
->led
.default_trigger
= mmc_hostname(mmc
);
1704 host
->led
.brightness_set
= sdhci_led_control
;
1706 ret
= led_classdev_register(mmc_dev(mmc
), &host
->led
);
1715 printk(KERN_INFO
"%s: SDHCI controller on %s [%s] using %s%s\n",
1716 mmc_hostname(mmc
), host
->hw_name
, mmc_dev(mmc
)->bus_id
,
1717 (host
->flags
& SDHCI_USE_ADMA
)?"A":"",
1718 (host
->flags
& SDHCI_USE_DMA
)?"DMA":"PIO");
1722 #ifdef CONFIG_LEDS_CLASS
1724 sdhci_reset(host
, SDHCI_RESET_ALL
);
1725 free_irq(host
->irq
, host
);
1728 tasklet_kill(&host
->card_tasklet
);
1729 tasklet_kill(&host
->finish_tasklet
);
1734 EXPORT_SYMBOL_GPL(sdhci_add_host
);
1736 void sdhci_remove_host(struct sdhci_host
*host
, int dead
)
1738 unsigned long flags
;
1741 spin_lock_irqsave(&host
->lock
, flags
);
1743 host
->flags
|= SDHCI_DEVICE_DEAD
;
1746 printk(KERN_ERR
"%s: Controller removed during "
1747 " transfer!\n", mmc_hostname(host
->mmc
));
1749 host
->mrq
->cmd
->error
= -ENOMEDIUM
;
1750 tasklet_schedule(&host
->finish_tasklet
);
1753 spin_unlock_irqrestore(&host
->lock
, flags
);
1756 mmc_remove_host(host
->mmc
);
1758 #ifdef CONFIG_LEDS_CLASS
1759 led_classdev_unregister(&host
->led
);
1763 sdhci_reset(host
, SDHCI_RESET_ALL
);
1765 free_irq(host
->irq
, host
);
1767 del_timer_sync(&host
->timer
);
1769 tasklet_kill(&host
->card_tasklet
);
1770 tasklet_kill(&host
->finish_tasklet
);
1772 kfree(host
->adma_desc
);
1773 kfree(host
->align_buffer
);
1775 host
->adma_desc
= NULL
;
1776 host
->align_buffer
= NULL
;
1779 EXPORT_SYMBOL_GPL(sdhci_remove_host
);
1781 void sdhci_free_host(struct sdhci_host
*host
)
1783 mmc_free_host(host
->mmc
);
1786 EXPORT_SYMBOL_GPL(sdhci_free_host
);
1788 /*****************************************************************************\
1790 * Driver init/exit *
1792 \*****************************************************************************/
1794 static int __init
sdhci_drv_init(void)
1796 printk(KERN_INFO DRIVER_NAME
1797 ": Secure Digital Host Controller Interface driver\n");
1798 printk(KERN_INFO DRIVER_NAME
": Copyright(c) Pierre Ossman\n");
1803 static void __exit
sdhci_drv_exit(void)
1807 module_init(sdhci_drv_init
);
1808 module_exit(sdhci_drv_exit
);
1810 module_param(debug_quirks
, uint
, 0444);
1812 MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
1813 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
1814 MODULE_LICENSE("GPL");
1816 MODULE_PARM_DESC(debug_quirks
, "Force certain quirks.");