drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11
  12 #include <linux/scatterlist.h>
  13
  14 /*
  15  * Controller registers
  16  */
  17
  18 #define SDHCI_DMA_ADDRESS       0x00
  19
  20 #define SDHCI_BLOCK_SIZE        0x04
  21 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  22
  23 #define SDHCI_BLOCK_COUNT       0x06
  24
  25 #define SDHCI_ARGUMENT          0x08
  26
  27 #define SDHCI_TRANSFER_MODE     0x0C
  28 #define  SDHCI_TRNS_DMA         0x01
  29 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  30 #define  SDHCI_TRNS_ACMD12      0x04
  31 #define  SDHCI_TRNS_READ        0x10
  32 #define  SDHCI_TRNS_MULTI       0x20
  33
  34 #define SDHCI_COMMAND           0x0E
  35 #define  SDHCI_CMD_RESP_MASK    0x03
  36 #define  SDHCI_CMD_CRC          0x08
  37 #define  SDHCI_CMD_INDEX        0x10
  38 #define  SDHCI_CMD_DATA         0x20
  39
  40 #define  SDHCI_CMD_RESP_NONE    0x00
  41 #define  SDHCI_CMD_RESP_LONG    0x01
  42 #define  SDHCI_CMD_RESP_SHORT   0x02
  43 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  44
  45 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  46
  47 #define SDHCI_RESPONSE          0x10
  48
  49 #define SDHCI_BUFFER            0x20
  50
  51 #define SDHCI_PRESENT_STATE     0x24
  52 #define  SDHCI_CMD_INHIBIT      0x00000001
  53 #define  SDHCI_DATA_INHIBIT     0x00000002
  54 #define  SDHCI_DOING_WRITE      0x00000100
  55 #define  SDHCI_DOING_READ       0x00000200
  56 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  57 #define  SDHCI_DATA_AVAILABLE   0x00000800
  58 #define  SDHCI_CARD_PRESENT     0x00010000
  59 #define  SDHCI_WRITE_PROTECT    0x00080000
  60
  61 #define SDHCI_HOST_CONTROL      0x28
  62 #define  SDHCI_CTRL_LED         0x01
  63 #define  SDHCI_CTRL_4BITBUS     0x02
  64 #define  SDHCI_CTRL_HISPD       0x04
  65 #define  SDHCI_CTRL_DMA_MASK    0x18
  66 #define   SDHCI_CTRL_SDMA       0x00
  67 #define   SDHCI_CTRL_ADMA1      0x08
  68 #define   SDHCI_CTRL_ADMA32     0x10
  69 #define   SDHCI_CTRL_ADMA64     0x18
  70
  71 #define SDHCI_POWER_CONTROL     0x29
  72 #define  SDHCI_POWER_ON         0x01
  73 #define  SDHCI_POWER_180        0x0A
  74 #define  SDHCI_POWER_300        0x0C
  75 #define  SDHCI_POWER_330        0x0E
  76
  77 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  78
  79 #define SDHCI_WAKE_UP_CONTROL   0x2B
  80
  81 #define SDHCI_CLOCK_CONTROL     0x2C
  82 #define  SDHCI_DIVIDER_SHIFT    8
  83 #define  SDHCI_CLOCK_CARD_EN    0x0004
  84 #define  SDHCI_CLOCK_INT_STABLE 0x0002
  85 #define  SDHCI_CLOCK_INT_EN     0x0001
  86
  87 #define SDHCI_TIMEOUT_CONTROL   0x2E
  88
  89 #define SDHCI_SOFTWARE_RESET    0x2F
  90 #define  SDHCI_RESET_ALL        0x01
  91 #define  SDHCI_RESET_CMD        0x02
  92 #define  SDHCI_RESET_DATA       0x04
  93
  94 #define SDHCI_INT_STATUS        0x30
  95 #define SDHCI_INT_ENABLE        0x34
  96 #define SDHCI_SIGNAL_ENABLE     0x38
  97 #define  SDHCI_INT_RESPONSE     0x00000001
  98 #define  SDHCI_INT_DATA_END     0x00000002
  99 #define  SDHCI_INT_DMA_END      0x00000008
 100 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 101 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 102 #define  SDHCI_INT_CARD_INSERT  0x00000040
 103 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 104 #define  SDHCI_INT_CARD_INT     0x00000100
 105 #define  SDHCI_INT_ERROR        0x00008000
 106 #define  SDHCI_INT_TIMEOUT      0x00010000
 107 #define  SDHCI_INT_CRC          0x00020000
 108 #define  SDHCI_INT_END_BIT      0x00040000
 109 #define  SDHCI_INT_INDEX        0x00080000
 110 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 111 #define  SDHCI_INT_DATA_CRC     0x00200000
 112 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 113 #define  SDHCI_INT_BUS_POWER    0x00800000
 114 #define  SDHCI_INT_ACMD12ERR    0x01000000
 115 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 116
 117 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 118 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 119
 120 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 121                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 122 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 123                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 124                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 125                 SDHCI_INT_DATA_END_BIT)
 126
 127 #define SDHCI_ACMD12_ERR        0x3C
 128
 129 /* 3E-3F reserved */
 130
 131 #define SDHCI_CAPABILITIES      0x40
 132 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 133 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 134 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 135 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 136 #define  SDHCI_CLOCK_BASE_SHIFT 8
 137 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 138 #define  SDHCI_MAX_BLOCK_SHIFT  16
 139 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 140 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 141 #define  SDHCI_CAN_DO_HISPD     0x00200000
 142 #define  SDHCI_CAN_DO_DMA       0x00400000
 143 #define  SDHCI_CAN_VDD_330      0x01000000
 144 #define  SDHCI_CAN_VDD_300      0x02000000
 145 #define  SDHCI_CAN_VDD_180      0x04000000
 146 #define  SDHCI_CAN_64BIT        0x10000000
 147
 148 /* 44-47 reserved for more caps */
 149
 150 #define SDHCI_MAX_CURRENT       0x48
 151
 152 /* 4C-4F reserved for more max current */
 153
 154 #define SDHCI_SET_ACMD12_ERROR  0x50
 155 #define SDHCI_SET_INT_ERROR     0x52
 156
 157 #define SDHCI_ADMA_ERROR        0x54
 158
 159 /* 55-57 reserved */
 160
 161 #define SDHCI_ADMA_ADDRESS      0x58
 162
 163 /* 60-FB reserved */
 164
 165 #define SDHCI_SLOT_INT_STATUS   0xFC
 166
 167 #define SDHCI_HOST_VERSION      0xFE
 168 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 169 #define  SDHCI_VENDOR_VER_SHIFT 8
 170 #define  SDHCI_SPEC_VER_MASK    0x00FF
 171 #define  SDHCI_SPEC_VER_SHIFT   0
 172 #define   SDHCI_SPEC_100        0
 173 #define   SDHCI_SPEC_200        1
 174
 175 struct sdhci_ops;
 176
 177 struct sdhci_host {
 178         /* Data set by hardware interface driver */
 179         const char              *hw_name;       /* Hardware bus name */
 180
 181         unsigned int            quirks;         /* Deviations from spec. */
 182
 183 /* Controller doesn't honor resets unless we touch the clock register */
 184 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
 185 /* Controller has bad caps bits, but really supports DMA */
 186 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
 187 /* Controller doesn't like to be reset when there is no card inserted. */
 188 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
 189 /* Controller doesn't like clearing the power reg before a change */
 190 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
 191 /* Controller has flaky internal state so reset it on each ios change */
 192 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
 193 /* Controller has an unusable DMA engine */
 194 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
 195 /* Controller has an unusable ADMA engine */
 196 #define SDHCI_QUIRK_BROKEN_ADMA                         (1<<6)
 197 /* Controller can only DMA from 32-bit aligned addresses */
 198 #define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<7)
 199 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
 200 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<8)
 201 /* Controller can only ADMA chunks that are a multiple of 32 bits */
 202 #define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1<<9)
 203 /* Controller needs to be reset after each request to stay stable */
 204 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<10)
 205 /* Controller needs voltage and power writes to happen separately */
 206 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<11)
 207 /* Controller provides an incorrect timeout value for transfers */
 208 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<12)
 209 /* Controller has an issue with buffer bits for small transfers */
 210 #define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1<<13)
 211 /* Controller does not provide transfer-complete interrupt when not busy */
 212 #define SDHCI_QUIRK_NO_BUSY_IRQ                         (1<<14)
 213
 214         int                     irq;            /* Device IRQ */
 215         void __iomem *          ioaddr;         /* Mapped address */
 216
 217         const struct sdhci_ops  *ops;           /* Low level hw interface */
 218
 219         /* Internal data */
 220         struct mmc_host         *mmc;           /* MMC structure */
 221         u64                     dma_mask;       /* custom DMA mask */
 222
 223 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
 224         struct led_classdev     led;            /* LED control */
 225         char   led_name[32];
 226 #endif
 227
 228         spinlock_t              lock;           /* Mutex */
 229
 230         int                     flags;          /* Host attributes */
 231 #define SDHCI_USE_DMA           (1<<0)          /* Host is DMA capable */
 232 #define SDHCI_USE_ADMA          (1<<1)          /* Host is ADMA capable */
 233 #define SDHCI_REQ_USE_DMA       (1<<2)          /* Use DMA for this req. */
 234 #define SDHCI_DEVICE_DEAD       (1<<3)          /* Device unresponsive */
 235
 236         unsigned int            version;        /* SDHCI spec. version */
 237
 238         unsigned int            max_clk;        /* Max possible freq (MHz) */
 239         unsigned int            timeout_clk;    /* Timeout freq (KHz) */
 240
 241         unsigned int            clock;          /* Current clock (MHz) */
 242         unsigned short          power;          /* Current voltage */
 243
 244         struct mmc_request      *mrq;           /* Current request */
 245         struct mmc_command      *cmd;           /* Current command */
 246         struct mmc_data         *data;          /* Current data request */
 247         unsigned int            data_early:1;   /* Data finished before cmd */
 248
 249         struct sg_mapping_iter  sg_miter;       /* SG state for PIO */
 250         unsigned int            blocks;         /* remaining PIO blocks */
 251
 252         int                     sg_count;       /* Mapped sg entries */
 253
 254         u8                      *adma_desc;     /* ADMA descriptor table */
 255         u8                      *align_buffer;  /* Bounce buffer */
 256
 257         dma_addr_t              adma_addr;      /* Mapped ADMA descr. table */
 258         dma_addr_t              align_addr;     /* Mapped bounce buffer */
 259
 260         struct tasklet_struct   card_tasklet;   /* Tasklet structures */
 261         struct tasklet_struct   finish_tasklet;
 262
 263         struct timer_list       timer;          /* Timer for timeouts */
 264
 265         unsigned long           private[0] ____cacheline_aligned;
 266 };
 267
 268
 269 struct sdhci_ops {
 270         int             (*enable_dma)(struct sdhci_host *host);
 271 };
 272
 273
 274 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 275         size_t priv_size);
 276 extern void sdhci_free_host(struct sdhci_host *host);
 277
 278 static inline void *sdhci_priv(struct sdhci_host *host)
 279 {
 280         return (void *)host->private;
 281 }
 282
 283 extern int sdhci_add_host(struct sdhci_host *host);
 284 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 285
 286 #ifdef CONFIG_PM
 287 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
 288 extern int sdhci_resume_host(struct sdhci_host *host);
 289 #endif