4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Yusuke Goda <yusuke.goda.sx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
15 * 3. Handle MMC errors better
20 * The MMCIF driver is now processing MMC requests asynchronously, according
21 * to the Linux MMC API requirement.
23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
24 * data, and optional stop. To achieve asynchronous processing each of these
25 * stages is split into two halves: a top and a bottom half. The top half
26 * initialises the hardware, installs a timeout handler to handle completion
27 * timeouts, and returns. In case of the command stage this immediately returns
28 * control to the caller, leaving all further processing to run asynchronously.
29 * All further request processing is performed by the bottom halves.
31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
32 * thread, a DMA completion callback, if DMA is used, a timeout work, and
33 * request- and stage-specific handler methods.
35 * Each bottom half run begins with either a hardware interrupt, a DMA callback
36 * invocation, or a timeout work run. In case of an error or a successful
37 * processing completion, the MMC core is informed and the request processing is
38 * finished. In case processing has to continue, i.e., if data has to be read
39 * from or written to the card, or if a stop command has to be sent, the next
40 * top half is called, which performs the necessary hardware handling and
41 * reschedules the timeout work. This returns the driver state machine into the
42 * bottom half waiting state.
45 #include <linux/bitops.h>
46 #include <linux/clk.h>
47 #include <linux/completion.h>
48 #include <linux/delay.h>
49 #include <linux/dma-mapping.h>
50 #include <linux/dmaengine.h>
51 #include <linux/mmc/card.h>
52 #include <linux/mmc/core.h>
53 #include <linux/mmc/host.h>
54 #include <linux/mmc/mmc.h>
55 #include <linux/mmc/sdio.h>
56 #include <linux/mmc/sh_mmcif.h>
57 #include <linux/mmc/slot-gpio.h>
58 #include <linux/mod_devicetable.h>
59 #include <linux/pagemap.h>
60 #include <linux/platform_device.h>
61 #include <linux/pm_qos.h>
62 #include <linux/pm_runtime.h>
63 #include <linux/spinlock.h>
64 #include <linux/module.h>
66 #define DRIVER_NAME "sh_mmcif"
67 #define DRIVER_VERSION "2010-04-28"
70 #define CMD_MASK 0x3f000000
71 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
72 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
73 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
74 #define CMD_SET_RBSY (1 << 21) /* R1b */
75 #define CMD_SET_CCSEN (1 << 20)
76 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
77 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
78 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
79 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
80 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
81 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
82 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
83 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
84 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
85 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
86 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
87 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
88 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
89 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
90 #define CMD_SET_CCSH (1 << 5)
91 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
92 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
93 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
96 #define CMD_CTRL_BREAK (1 << 0)
99 #define BLOCK_SIZE_MASK 0x0000ffff
102 #define INT_CCSDE (1 << 29)
103 #define INT_CMD12DRE (1 << 26)
104 #define INT_CMD12RBE (1 << 25)
105 #define INT_CMD12CRE (1 << 24)
106 #define INT_DTRANE (1 << 23)
107 #define INT_BUFRE (1 << 22)
108 #define INT_BUFWEN (1 << 21)
109 #define INT_BUFREN (1 << 20)
110 #define INT_CCSRCV (1 << 19)
111 #define INT_RBSYE (1 << 17)
112 #define INT_CRSPE (1 << 16)
113 #define INT_CMDVIO (1 << 15)
114 #define INT_BUFVIO (1 << 14)
115 #define INT_WDATERR (1 << 11)
116 #define INT_RDATERR (1 << 10)
117 #define INT_RIDXERR (1 << 9)
118 #define INT_RSPERR (1 << 8)
119 #define INT_CCSTO (1 << 5)
120 #define INT_CRCSTO (1 << 4)
121 #define INT_WDATTO (1 << 3)
122 #define INT_RDATTO (1 << 2)
123 #define INT_RBSYTO (1 << 1)
124 #define INT_RSPTO (1 << 0)
125 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
126 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
127 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
128 INT_RDATTO | INT_RBSYTO | INT_RSPTO)
131 #define MASK_ALL 0x00000000
132 #define MASK_MCCSDE (1 << 29)
133 #define MASK_MCMD12DRE (1 << 26)
134 #define MASK_MCMD12RBE (1 << 25)
135 #define MASK_MCMD12CRE (1 << 24)
136 #define MASK_MDTRANE (1 << 23)
137 #define MASK_MBUFRE (1 << 22)
138 #define MASK_MBUFWEN (1 << 21)
139 #define MASK_MBUFREN (1 << 20)
140 #define MASK_MCCSRCV (1 << 19)
141 #define MASK_MRBSYE (1 << 17)
142 #define MASK_MCRSPE (1 << 16)
143 #define MASK_MCMDVIO (1 << 15)
144 #define MASK_MBUFVIO (1 << 14)
145 #define MASK_MWDATERR (1 << 11)
146 #define MASK_MRDATERR (1 << 10)
147 #define MASK_MRIDXERR (1 << 9)
148 #define MASK_MRSPERR (1 << 8)
149 #define MASK_MCCSTO (1 << 5)
150 #define MASK_MCRCSTO (1 << 4)
151 #define MASK_MWDATTO (1 << 3)
152 #define MASK_MRDATTO (1 << 2)
153 #define MASK_MRBSYTO (1 << 1)
154 #define MASK_MRSPTO (1 << 0)
156 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
157 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
158 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \
159 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
162 #define STS1_CMDSEQ (1 << 31)
165 #define STS2_CRCSTE (1 << 31)
166 #define STS2_CRC16E (1 << 30)
167 #define STS2_AC12CRCE (1 << 29)
168 #define STS2_RSPCRC7E (1 << 28)
169 #define STS2_CRCSTEBE (1 << 27)
170 #define STS2_RDATEBE (1 << 26)
171 #define STS2_AC12REBE (1 << 25)
172 #define STS2_RSPEBE (1 << 24)
173 #define STS2_AC12IDXE (1 << 23)
174 #define STS2_RSPIDXE (1 << 22)
175 #define STS2_CCSTO (1 << 15)
176 #define STS2_RDATTO (1 << 14)
177 #define STS2_DATBSYTO (1 << 13)
178 #define STS2_CRCSTTO (1 << 12)
179 #define STS2_AC12BSYTO (1 << 11)
180 #define STS2_RSPBSYTO (1 << 10)
181 #define STS2_AC12RSPTO (1 << 9)
182 #define STS2_RSPTO (1 << 8)
183 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
184 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
185 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
186 STS2_DATBSYTO | STS2_CRCSTTO | \
187 STS2_AC12BSYTO | STS2_RSPBSYTO | \
188 STS2_AC12RSPTO | STS2_RSPTO)
190 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */
191 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
192 #define CLKDEV_INIT 400000 /* 400 KHz */
200 enum mmcif_wait_for
{
201 MMCIF_WAIT_FOR_REQUEST
,
203 MMCIF_WAIT_FOR_MREAD
,
204 MMCIF_WAIT_FOR_MWRITE
,
206 MMCIF_WAIT_FOR_WRITE
,
207 MMCIF_WAIT_FOR_READ_END
,
208 MMCIF_WAIT_FOR_WRITE_END
,
212 struct sh_mmcif_host
{
213 struct mmc_host
*mmc
;
214 struct mmc_request
*mrq
;
215 struct platform_device
*pd
;
216 struct sh_dmae_slave dma_slave_tx
;
217 struct sh_dmae_slave dma_slave_rx
;
226 spinlock_t lock
; /* protect sh_mmcif_host::state */
227 enum mmcif_state state
;
228 enum mmcif_wait_for wait_for
;
229 struct delayed_work timeout_work
;
237 struct dma_chan
*chan_rx
;
238 struct dma_chan
*chan_tx
;
239 struct completion dma_complete
;
243 static inline void sh_mmcif_bitset(struct sh_mmcif_host
*host
,
244 unsigned int reg
, u32 val
)
246 writel(val
| readl(host
->addr
+ reg
), host
->addr
+ reg
);
249 static inline void sh_mmcif_bitclr(struct sh_mmcif_host
*host
,
250 unsigned int reg
, u32 val
)
252 writel(~val
& readl(host
->addr
+ reg
), host
->addr
+ reg
);
255 static void mmcif_dma_complete(void *arg
)
257 struct sh_mmcif_host
*host
= arg
;
258 struct mmc_data
*data
= host
->mrq
->data
;
260 dev_dbg(&host
->pd
->dev
, "Command completed\n");
262 if (WARN(!data
, "%s: NULL data in DMA completion!\n",
263 dev_name(&host
->pd
->dev
)))
266 if (data
->flags
& MMC_DATA_READ
)
267 dma_unmap_sg(host
->chan_rx
->device
->dev
,
268 data
->sg
, data
->sg_len
,
271 dma_unmap_sg(host
->chan_tx
->device
->dev
,
272 data
->sg
, data
->sg_len
,
275 complete(&host
->dma_complete
);
278 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host
*host
)
280 struct mmc_data
*data
= host
->mrq
->data
;
281 struct scatterlist
*sg
= data
->sg
;
282 struct dma_async_tx_descriptor
*desc
= NULL
;
283 struct dma_chan
*chan
= host
->chan_rx
;
284 dma_cookie_t cookie
= -EINVAL
;
287 ret
= dma_map_sg(chan
->device
->dev
, sg
, data
->sg_len
,
290 host
->dma_active
= true;
291 desc
= dmaengine_prep_slave_sg(chan
, sg
, ret
,
292 DMA_DEV_TO_MEM
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
296 desc
->callback
= mmcif_dma_complete
;
297 desc
->callback_param
= host
;
298 cookie
= dmaengine_submit(desc
);
299 sh_mmcif_bitset(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_DMAREN
);
300 dma_async_issue_pending(chan
);
302 dev_dbg(&host
->pd
->dev
, "%s(): mapped %d -> %d, cookie %d\n",
303 __func__
, data
->sg_len
, ret
, cookie
);
306 /* DMA failed, fall back to PIO */
309 host
->chan_rx
= NULL
;
310 host
->dma_active
= false;
311 dma_release_channel(chan
);
312 /* Free the Tx channel too */
313 chan
= host
->chan_tx
;
315 host
->chan_tx
= NULL
;
316 dma_release_channel(chan
);
318 dev_warn(&host
->pd
->dev
,
319 "DMA failed: %d, falling back to PIO\n", ret
);
320 sh_mmcif_bitclr(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_DMAREN
| BUF_ACC_DMAWEN
);
323 dev_dbg(&host
->pd
->dev
, "%s(): desc %p, cookie %d, sg[%d]\n", __func__
,
324 desc
, cookie
, data
->sg_len
);
327 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host
*host
)
329 struct mmc_data
*data
= host
->mrq
->data
;
330 struct scatterlist
*sg
= data
->sg
;
331 struct dma_async_tx_descriptor
*desc
= NULL
;
332 struct dma_chan
*chan
= host
->chan_tx
;
333 dma_cookie_t cookie
= -EINVAL
;
336 ret
= dma_map_sg(chan
->device
->dev
, sg
, data
->sg_len
,
339 host
->dma_active
= true;
340 desc
= dmaengine_prep_slave_sg(chan
, sg
, ret
,
341 DMA_MEM_TO_DEV
, DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
345 desc
->callback
= mmcif_dma_complete
;
346 desc
->callback_param
= host
;
347 cookie
= dmaengine_submit(desc
);
348 sh_mmcif_bitset(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_DMAWEN
);
349 dma_async_issue_pending(chan
);
351 dev_dbg(&host
->pd
->dev
, "%s(): mapped %d -> %d, cookie %d\n",
352 __func__
, data
->sg_len
, ret
, cookie
);
355 /* DMA failed, fall back to PIO */
358 host
->chan_tx
= NULL
;
359 host
->dma_active
= false;
360 dma_release_channel(chan
);
361 /* Free the Rx channel too */
362 chan
= host
->chan_rx
;
364 host
->chan_rx
= NULL
;
365 dma_release_channel(chan
);
367 dev_warn(&host
->pd
->dev
,
368 "DMA failed: %d, falling back to PIO\n", ret
);
369 sh_mmcif_bitclr(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_DMAREN
| BUF_ACC_DMAWEN
);
372 dev_dbg(&host
->pd
->dev
, "%s(): desc %p, cookie %d\n", __func__
,
376 static bool sh_mmcif_filter(struct dma_chan
*chan
, void *arg
)
378 dev_dbg(chan
->device
->dev
, "%s: slave data %p\n", __func__
, arg
);
383 static void sh_mmcif_request_dma(struct sh_mmcif_host
*host
,
384 struct sh_mmcif_plat_data
*pdata
)
386 struct sh_dmae_slave
*tx
, *rx
;
387 host
->dma_active
= false;
392 /* We can only either use DMA for both Tx and Rx or not use it at all */
394 dev_warn(&host
->pd
->dev
,
395 "Update your platform to use embedded DMA slave IDs\n");
396 tx
= &pdata
->dma
->chan_priv_tx
;
397 rx
= &pdata
->dma
->chan_priv_rx
;
399 tx
= &host
->dma_slave_tx
;
400 tx
->slave_id
= pdata
->slave_id_tx
;
401 rx
= &host
->dma_slave_rx
;
402 rx
->slave_id
= pdata
->slave_id_rx
;
404 if (tx
->slave_id
> 0 && rx
->slave_id
> 0) {
408 dma_cap_set(DMA_SLAVE
, mask
);
410 host
->chan_tx
= dma_request_channel(mask
, sh_mmcif_filter
, tx
);
411 dev_dbg(&host
->pd
->dev
, "%s: TX: got channel %p\n", __func__
,
417 host
->chan_rx
= dma_request_channel(mask
, sh_mmcif_filter
, rx
);
418 dev_dbg(&host
->pd
->dev
, "%s: RX: got channel %p\n", __func__
,
421 if (!host
->chan_rx
) {
422 dma_release_channel(host
->chan_tx
);
423 host
->chan_tx
= NULL
;
427 init_completion(&host
->dma_complete
);
431 static void sh_mmcif_release_dma(struct sh_mmcif_host
*host
)
433 sh_mmcif_bitclr(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_DMAREN
| BUF_ACC_DMAWEN
);
434 /* Descriptors are freed automatically */
436 struct dma_chan
*chan
= host
->chan_tx
;
437 host
->chan_tx
= NULL
;
438 dma_release_channel(chan
);
441 struct dma_chan
*chan
= host
->chan_rx
;
442 host
->chan_rx
= NULL
;
443 dma_release_channel(chan
);
446 host
->dma_active
= false;
449 static void sh_mmcif_clock_control(struct sh_mmcif_host
*host
, unsigned int clk
)
451 struct sh_mmcif_plat_data
*p
= host
->pd
->dev
.platform_data
;
452 bool sup_pclk
= p
? p
->sup_pclk
: false;
454 sh_mmcif_bitclr(host
, MMCIF_CE_CLK_CTRL
, CLK_ENABLE
);
455 sh_mmcif_bitclr(host
, MMCIF_CE_CLK_CTRL
, CLK_CLEAR
);
459 if (sup_pclk
&& clk
== host
->clk
)
460 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, CLK_SUP_PCLK
);
462 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, CLK_CLEAR
&
463 ((fls(DIV_ROUND_UP(host
->clk
,
464 clk
) - 1) - 1) << 16));
466 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, CLK_ENABLE
);
469 static void sh_mmcif_sync_reset(struct sh_mmcif_host
*host
)
473 tmp
= 0x010f0000 & sh_mmcif_readl(host
->addr
, MMCIF_CE_CLK_CTRL
);
475 sh_mmcif_writel(host
->addr
, MMCIF_CE_VERSION
, SOFT_RST_ON
);
476 sh_mmcif_writel(host
->addr
, MMCIF_CE_VERSION
, SOFT_RST_OFF
);
477 sh_mmcif_bitset(host
, MMCIF_CE_CLK_CTRL
, tmp
|
478 SRSPTO_256
| SRBSYTO_29
| SRWDTO_29
| SCCSTO_29
);
480 sh_mmcif_bitset(host
, MMCIF_CE_BUF_ACC
, BUF_ACC_ATYP
);
483 static int sh_mmcif_error_manage(struct sh_mmcif_host
*host
)
488 host
->sd_error
= false;
490 state1
= sh_mmcif_readl(host
->addr
, MMCIF_CE_HOST_STS1
);
491 state2
= sh_mmcif_readl(host
->addr
, MMCIF_CE_HOST_STS2
);
492 dev_dbg(&host
->pd
->dev
, "ERR HOST_STS1 = %08x\n", state1
);
493 dev_dbg(&host
->pd
->dev
, "ERR HOST_STS2 = %08x\n", state2
);
495 if (state1
& STS1_CMDSEQ
) {
496 sh_mmcif_bitset(host
, MMCIF_CE_CMD_CTRL
, CMD_CTRL_BREAK
);
497 sh_mmcif_bitset(host
, MMCIF_CE_CMD_CTRL
, ~CMD_CTRL_BREAK
);
498 for (timeout
= 10000000; timeout
; timeout
--) {
499 if (!(sh_mmcif_readl(host
->addr
, MMCIF_CE_HOST_STS1
)
505 dev_err(&host
->pd
->dev
,
506 "Forced end of command sequence timeout err\n");
509 sh_mmcif_sync_reset(host
);
510 dev_dbg(&host
->pd
->dev
, "Forced end of command sequence\n");
514 if (state2
& STS2_CRC_ERR
) {
515 dev_dbg(&host
->pd
->dev
, ": CRC error\n");
517 } else if (state2
& STS2_TIMEOUT_ERR
) {
518 dev_dbg(&host
->pd
->dev
, ": Timeout\n");
521 dev_dbg(&host
->pd
->dev
, ": End/Index error\n");
527 static bool sh_mmcif_next_block(struct sh_mmcif_host
*host
, u32
*p
)
529 struct mmc_data
*data
= host
->mrq
->data
;
531 host
->sg_blkidx
+= host
->blocksize
;
533 /* data->sg->length must be a multiple of host->blocksize? */
534 BUG_ON(host
->sg_blkidx
> data
->sg
->length
);
536 if (host
->sg_blkidx
== data
->sg
->length
) {
538 if (++host
->sg_idx
< data
->sg_len
)
539 host
->pio_ptr
= sg_virt(++data
->sg
);
544 if (host
->sg_idx
== data
->sg_len
)
550 static void sh_mmcif_single_read(struct sh_mmcif_host
*host
,
551 struct mmc_request
*mrq
)
553 host
->blocksize
= (sh_mmcif_readl(host
->addr
, MMCIF_CE_BLOCK_SET
) &
554 BLOCK_SIZE_MASK
) + 3;
556 host
->wait_for
= MMCIF_WAIT_FOR_READ
;
557 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
559 /* buf read enable */
560 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
563 static bool sh_mmcif_read_block(struct sh_mmcif_host
*host
)
565 struct mmc_data
*data
= host
->mrq
->data
;
566 u32
*p
= sg_virt(data
->sg
);
569 if (host
->sd_error
) {
570 data
->error
= sh_mmcif_error_manage(host
);
574 for (i
= 0; i
< host
->blocksize
/ 4; i
++)
575 *p
++ = sh_mmcif_readl(host
->addr
, MMCIF_CE_DATA
);
577 /* buffer read end */
578 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFRE
);
579 host
->wait_for
= MMCIF_WAIT_FOR_READ_END
;
584 static void sh_mmcif_multi_read(struct sh_mmcif_host
*host
,
585 struct mmc_request
*mrq
)
587 struct mmc_data
*data
= mrq
->data
;
589 if (!data
->sg_len
|| !data
->sg
->length
)
592 host
->blocksize
= sh_mmcif_readl(host
->addr
, MMCIF_CE_BLOCK_SET
) &
595 host
->wait_for
= MMCIF_WAIT_FOR_MREAD
;
598 host
->pio_ptr
= sg_virt(data
->sg
);
599 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
600 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
603 static bool sh_mmcif_mread_block(struct sh_mmcif_host
*host
)
605 struct mmc_data
*data
= host
->mrq
->data
;
606 u32
*p
= host
->pio_ptr
;
609 if (host
->sd_error
) {
610 data
->error
= sh_mmcif_error_manage(host
);
614 BUG_ON(!data
->sg
->length
);
616 for (i
= 0; i
< host
->blocksize
/ 4; i
++)
617 *p
++ = sh_mmcif_readl(host
->addr
, MMCIF_CE_DATA
);
619 if (!sh_mmcif_next_block(host
, p
))
622 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
623 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
628 static void sh_mmcif_single_write(struct sh_mmcif_host
*host
,
629 struct mmc_request
*mrq
)
631 host
->blocksize
= (sh_mmcif_readl(host
->addr
, MMCIF_CE_BLOCK_SET
) &
632 BLOCK_SIZE_MASK
) + 3;
634 host
->wait_for
= MMCIF_WAIT_FOR_WRITE
;
635 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
637 /* buf write enable */
638 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
641 static bool sh_mmcif_write_block(struct sh_mmcif_host
*host
)
643 struct mmc_data
*data
= host
->mrq
->data
;
644 u32
*p
= sg_virt(data
->sg
);
647 if (host
->sd_error
) {
648 data
->error
= sh_mmcif_error_manage(host
);
652 for (i
= 0; i
< host
->blocksize
/ 4; i
++)
653 sh_mmcif_writel(host
->addr
, MMCIF_CE_DATA
, *p
++);
655 /* buffer write end */
656 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MDTRANE
);
657 host
->wait_for
= MMCIF_WAIT_FOR_WRITE_END
;
662 static void sh_mmcif_multi_write(struct sh_mmcif_host
*host
,
663 struct mmc_request
*mrq
)
665 struct mmc_data
*data
= mrq
->data
;
667 if (!data
->sg_len
|| !data
->sg
->length
)
670 host
->blocksize
= sh_mmcif_readl(host
->addr
, MMCIF_CE_BLOCK_SET
) &
673 host
->wait_for
= MMCIF_WAIT_FOR_MWRITE
;
676 host
->pio_ptr
= sg_virt(data
->sg
);
677 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
678 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
681 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host
*host
)
683 struct mmc_data
*data
= host
->mrq
->data
;
684 u32
*p
= host
->pio_ptr
;
687 if (host
->sd_error
) {
688 data
->error
= sh_mmcif_error_manage(host
);
692 BUG_ON(!data
->sg
->length
);
694 for (i
= 0; i
< host
->blocksize
/ 4; i
++)
695 sh_mmcif_writel(host
->addr
, MMCIF_CE_DATA
, *p
++);
697 if (!sh_mmcif_next_block(host
, p
))
700 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
701 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
706 static void sh_mmcif_get_response(struct sh_mmcif_host
*host
,
707 struct mmc_command
*cmd
)
709 if (cmd
->flags
& MMC_RSP_136
) {
710 cmd
->resp
[0] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP3
);
711 cmd
->resp
[1] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP2
);
712 cmd
->resp
[2] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP1
);
713 cmd
->resp
[3] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP0
);
715 cmd
->resp
[0] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP0
);
718 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host
*host
,
719 struct mmc_command
*cmd
)
721 cmd
->resp
[0] = sh_mmcif_readl(host
->addr
, MMCIF_CE_RESP_CMD12
);
724 static u32
sh_mmcif_set_cmd(struct sh_mmcif_host
*host
,
725 struct mmc_request
*mrq
)
727 struct mmc_data
*data
= mrq
->data
;
728 struct mmc_command
*cmd
= mrq
->cmd
;
729 u32 opc
= cmd
->opcode
;
732 /* Response Type check */
733 switch (mmc_resp_type(cmd
)) {
735 tmp
|= CMD_SET_RTYP_NO
;
740 tmp
|= CMD_SET_RTYP_6B
;
743 tmp
|= CMD_SET_RTYP_17B
;
746 dev_err(&host
->pd
->dev
, "Unsupported response type.\n");
752 case MMC_STOP_TRANSMISSION
:
753 case MMC_SET_WRITE_PROT
:
754 case MMC_CLR_WRITE_PROT
:
762 switch (host
->bus_width
) {
763 case MMC_BUS_WIDTH_1
:
764 tmp
|= CMD_SET_DATW_1
;
766 case MMC_BUS_WIDTH_4
:
767 tmp
|= CMD_SET_DATW_4
;
769 case MMC_BUS_WIDTH_8
:
770 tmp
|= CMD_SET_DATW_8
;
773 dev_err(&host
->pd
->dev
, "Unsupported bus width.\n");
778 if (opc
== MMC_WRITE_BLOCK
|| opc
== MMC_WRITE_MULTIPLE_BLOCK
)
781 if (opc
== MMC_READ_MULTIPLE_BLOCK
|| opc
== MMC_WRITE_MULTIPLE_BLOCK
) {
782 tmp
|= CMD_SET_CMLTE
| CMD_SET_CMD12EN
;
783 sh_mmcif_bitset(host
, MMCIF_CE_BLOCK_SET
,
786 /* RIDXC[1:0] check bits */
787 if (opc
== MMC_SEND_OP_COND
|| opc
== MMC_ALL_SEND_CID
||
788 opc
== MMC_SEND_CSD
|| opc
== MMC_SEND_CID
)
789 tmp
|= CMD_SET_RIDXC_BITS
;
790 /* RCRC7C[1:0] check bits */
791 if (opc
== MMC_SEND_OP_COND
)
792 tmp
|= CMD_SET_CRC7C_BITS
;
793 /* RCRC7C[1:0] internal CRC7 */
794 if (opc
== MMC_ALL_SEND_CID
||
795 opc
== MMC_SEND_CSD
|| opc
== MMC_SEND_CID
)
796 tmp
|= CMD_SET_CRC7C_INTERNAL
;
798 return (opc
<< 24) | tmp
;
801 static int sh_mmcif_data_trans(struct sh_mmcif_host
*host
,
802 struct mmc_request
*mrq
, u32 opc
)
805 case MMC_READ_MULTIPLE_BLOCK
:
806 sh_mmcif_multi_read(host
, mrq
);
808 case MMC_WRITE_MULTIPLE_BLOCK
:
809 sh_mmcif_multi_write(host
, mrq
);
811 case MMC_WRITE_BLOCK
:
812 sh_mmcif_single_write(host
, mrq
);
814 case MMC_READ_SINGLE_BLOCK
:
815 case MMC_SEND_EXT_CSD
:
816 sh_mmcif_single_read(host
, mrq
);
819 dev_err(&host
->pd
->dev
, "UNSUPPORTED CMD = d'%08d\n", opc
);
824 static void sh_mmcif_start_cmd(struct sh_mmcif_host
*host
,
825 struct mmc_request
*mrq
)
827 struct mmc_command
*cmd
= mrq
->cmd
;
828 u32 opc
= cmd
->opcode
;
832 /* response busy check */
834 case MMC_STOP_TRANSMISSION
:
835 case MMC_SET_WRITE_PROT
:
836 case MMC_CLR_WRITE_PROT
:
838 mask
= MASK_START_CMD
| MASK_MRBSYE
;
841 mask
= MASK_START_CMD
| MASK_MCRSPE
;
846 sh_mmcif_writel(host
->addr
, MMCIF_CE_BLOCK_SET
, 0);
847 sh_mmcif_writel(host
->addr
, MMCIF_CE_BLOCK_SET
,
850 opc
= sh_mmcif_set_cmd(host
, mrq
);
852 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, 0xD80430C0);
853 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, mask
);
855 sh_mmcif_writel(host
->addr
, MMCIF_CE_ARG
, cmd
->arg
);
857 sh_mmcif_writel(host
->addr
, MMCIF_CE_CMD_SET
, opc
);
859 host
->wait_for
= MMCIF_WAIT_FOR_CMD
;
860 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
863 static void sh_mmcif_stop_cmd(struct sh_mmcif_host
*host
,
864 struct mmc_request
*mrq
)
866 switch (mrq
->cmd
->opcode
) {
867 case MMC_READ_MULTIPLE_BLOCK
:
868 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12DRE
);
870 case MMC_WRITE_MULTIPLE_BLOCK
:
871 sh_mmcif_bitset(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12RBE
);
874 dev_err(&host
->pd
->dev
, "unsupported stop cmd\n");
875 mrq
->stop
->error
= sh_mmcif_error_manage(host
);
879 host
->wait_for
= MMCIF_WAIT_FOR_STOP
;
880 schedule_delayed_work(&host
->timeout_work
, host
->timeout
);
883 static void sh_mmcif_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
885 struct sh_mmcif_host
*host
= mmc_priv(mmc
);
888 spin_lock_irqsave(&host
->lock
, flags
);
889 if (host
->state
!= STATE_IDLE
) {
890 spin_unlock_irqrestore(&host
->lock
, flags
);
891 mrq
->cmd
->error
= -EAGAIN
;
892 mmc_request_done(mmc
, mrq
);
896 host
->state
= STATE_REQUEST
;
897 spin_unlock_irqrestore(&host
->lock
, flags
);
899 switch (mrq
->cmd
->opcode
) {
900 /* MMCIF does not support SD/SDIO command */
901 case MMC_SLEEP_AWAKE
: /* = SD_IO_SEND_OP_COND (5) */
902 case MMC_SEND_EXT_CSD
: /* = SD_SEND_IF_COND (8) */
903 if ((mrq
->cmd
->flags
& MMC_CMD_MASK
) != MMC_CMD_BCR
)
906 host
->state
= STATE_IDLE
;
907 mrq
->cmd
->error
= -ETIMEDOUT
;
908 mmc_request_done(mmc
, mrq
);
916 sh_mmcif_start_cmd(host
, mrq
);
919 static int sh_mmcif_clk_update(struct sh_mmcif_host
*host
)
921 int ret
= clk_enable(host
->hclk
);
924 host
->clk
= clk_get_rate(host
->hclk
);
925 host
->mmc
->f_max
= host
->clk
/ 2;
926 host
->mmc
->f_min
= host
->clk
/ 512;
932 static void sh_mmcif_set_power(struct sh_mmcif_host
*host
, struct mmc_ios
*ios
)
934 struct sh_mmcif_plat_data
*pd
= host
->pd
->dev
.platform_data
;
935 struct mmc_host
*mmc
= host
->mmc
;
937 if (pd
&& pd
->set_pwr
)
938 pd
->set_pwr(host
->pd
, ios
->power_mode
!= MMC_POWER_OFF
);
939 if (!IS_ERR(mmc
->supply
.vmmc
))
940 /* Errors ignored... */
941 mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
,
942 ios
->power_mode
? ios
->vdd
: 0);
945 static void sh_mmcif_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
947 struct sh_mmcif_host
*host
= mmc_priv(mmc
);
950 spin_lock_irqsave(&host
->lock
, flags
);
951 if (host
->state
!= STATE_IDLE
) {
952 spin_unlock_irqrestore(&host
->lock
, flags
);
956 host
->state
= STATE_IOS
;
957 spin_unlock_irqrestore(&host
->lock
, flags
);
959 if (ios
->power_mode
== MMC_POWER_UP
) {
960 if (!host
->card_present
) {
961 /* See if we also get DMA */
962 sh_mmcif_request_dma(host
, host
->pd
->dev
.platform_data
);
963 host
->card_present
= true;
965 sh_mmcif_set_power(host
, ios
);
966 } else if (ios
->power_mode
== MMC_POWER_OFF
|| !ios
->clock
) {
968 sh_mmcif_clock_control(host
, 0);
969 if (ios
->power_mode
== MMC_POWER_OFF
) {
970 if (host
->card_present
) {
971 sh_mmcif_release_dma(host
);
972 host
->card_present
= false;
976 pm_runtime_put(&host
->pd
->dev
);
977 clk_disable(host
->hclk
);
979 if (ios
->power_mode
== MMC_POWER_OFF
)
980 sh_mmcif_set_power(host
, ios
);
982 host
->state
= STATE_IDLE
;
988 sh_mmcif_clk_update(host
);
989 pm_runtime_get_sync(&host
->pd
->dev
);
991 sh_mmcif_sync_reset(host
);
993 sh_mmcif_clock_control(host
, ios
->clock
);
996 host
->bus_width
= ios
->bus_width
;
997 host
->state
= STATE_IDLE
;
1000 static int sh_mmcif_get_cd(struct mmc_host
*mmc
)
1002 struct sh_mmcif_host
*host
= mmc_priv(mmc
);
1003 struct sh_mmcif_plat_data
*p
= host
->pd
->dev
.platform_data
;
1004 int ret
= mmc_gpio_get_cd(mmc
);
1009 if (!p
|| !p
->get_cd
)
1012 return p
->get_cd(host
->pd
);
1015 static struct mmc_host_ops sh_mmcif_ops
= {
1016 .request
= sh_mmcif_request
,
1017 .set_ios
= sh_mmcif_set_ios
,
1018 .get_cd
= sh_mmcif_get_cd
,
1021 static bool sh_mmcif_end_cmd(struct sh_mmcif_host
*host
)
1023 struct mmc_command
*cmd
= host
->mrq
->cmd
;
1024 struct mmc_data
*data
= host
->mrq
->data
;
1027 if (host
->sd_error
) {
1028 switch (cmd
->opcode
) {
1029 case MMC_ALL_SEND_CID
:
1030 case MMC_SELECT_CARD
:
1032 cmd
->error
= -ETIMEDOUT
;
1033 host
->sd_error
= false;
1036 cmd
->error
= sh_mmcif_error_manage(host
);
1037 dev_dbg(&host
->pd
->dev
, "Cmd(d'%d) error %d\n",
1038 cmd
->opcode
, cmd
->error
);
1043 if (!(cmd
->flags
& MMC_RSP_PRESENT
)) {
1048 sh_mmcif_get_response(host
, cmd
);
1053 if (data
->flags
& MMC_DATA_READ
) {
1055 sh_mmcif_start_dma_rx(host
);
1058 sh_mmcif_start_dma_tx(host
);
1061 if (!host
->dma_active
) {
1062 data
->error
= sh_mmcif_data_trans(host
, host
->mrq
, cmd
->opcode
);
1068 /* Running in the IRQ thread, can sleep */
1069 time
= wait_for_completion_interruptible_timeout(&host
->dma_complete
,
1071 if (host
->sd_error
) {
1072 dev_err(host
->mmc
->parent
,
1073 "Error IRQ while waiting for DMA completion!\n");
1074 /* Woken up by an error IRQ: abort DMA */
1075 if (data
->flags
& MMC_DATA_READ
)
1076 dmaengine_terminate_all(host
->chan_rx
);
1078 dmaengine_terminate_all(host
->chan_tx
);
1079 data
->error
= sh_mmcif_error_manage(host
);
1081 data
->error
= -ETIMEDOUT
;
1082 } else if (time
< 0) {
1085 sh_mmcif_bitclr(host
, MMCIF_CE_BUF_ACC
,
1086 BUF_ACC_DMAREN
| BUF_ACC_DMAWEN
);
1087 host
->dma_active
= false;
1090 data
->bytes_xfered
= 0;
1095 static irqreturn_t
sh_mmcif_irqt(int irq
, void *dev_id
)
1097 struct sh_mmcif_host
*host
= dev_id
;
1098 struct mmc_request
*mrq
= host
->mrq
;
1099 struct mmc_data
*data
= mrq
->data
;
1101 cancel_delayed_work_sync(&host
->timeout_work
);
1104 * All handlers return true, if processing continues, and false, if the
1105 * request has to be completed - successfully or not
1107 switch (host
->wait_for
) {
1108 case MMCIF_WAIT_FOR_REQUEST
:
1109 /* We're too late, the timeout has already kicked in */
1111 case MMCIF_WAIT_FOR_CMD
:
1112 if (sh_mmcif_end_cmd(host
))
1116 case MMCIF_WAIT_FOR_MREAD
:
1117 if (sh_mmcif_mread_block(host
))
1118 /* Wait for more data */
1121 case MMCIF_WAIT_FOR_READ
:
1122 if (sh_mmcif_read_block(host
))
1123 /* Wait for data end */
1126 case MMCIF_WAIT_FOR_MWRITE
:
1127 if (sh_mmcif_mwrite_block(host
))
1128 /* Wait data to write */
1131 case MMCIF_WAIT_FOR_WRITE
:
1132 if (sh_mmcif_write_block(host
))
1133 /* Wait for data end */
1136 case MMCIF_WAIT_FOR_STOP
:
1137 if (host
->sd_error
) {
1138 mrq
->stop
->error
= sh_mmcif_error_manage(host
);
1141 sh_mmcif_get_cmd12response(host
, mrq
->stop
);
1142 mrq
->stop
->error
= 0;
1144 case MMCIF_WAIT_FOR_READ_END
:
1145 case MMCIF_WAIT_FOR_WRITE_END
:
1147 data
->error
= sh_mmcif_error_manage(host
);
1153 if (host
->wait_for
!= MMCIF_WAIT_FOR_STOP
) {
1154 if (!mrq
->cmd
->error
&& data
&& !data
->error
)
1155 data
->bytes_xfered
=
1156 data
->blocks
* data
->blksz
;
1158 if (mrq
->stop
&& !mrq
->cmd
->error
&& (!data
|| !data
->error
)) {
1159 sh_mmcif_stop_cmd(host
, mrq
);
1160 if (!mrq
->stop
->error
)
1165 host
->wait_for
= MMCIF_WAIT_FOR_REQUEST
;
1166 host
->state
= STATE_IDLE
;
1168 mmc_request_done(host
->mmc
, mrq
);
1173 static irqreturn_t
sh_mmcif_intr(int irq
, void *dev_id
)
1175 struct sh_mmcif_host
*host
= dev_id
;
1179 state
= sh_mmcif_readl(host
->addr
, MMCIF_CE_INT
);
1181 if (state
& INT_ERR_STS
) {
1182 /* error interrupts - process first */
1183 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~state
);
1184 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, state
);
1186 } else if (state
& INT_RBSYE
) {
1187 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
,
1188 ~(INT_RBSYE
| INT_CRSPE
));
1189 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MRBSYE
);
1190 } else if (state
& INT_CRSPE
) {
1191 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_CRSPE
);
1192 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MCRSPE
);
1193 } else if (state
& INT_BUFREN
) {
1194 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_BUFREN
);
1195 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MBUFREN
);
1196 } else if (state
& INT_BUFWEN
) {
1197 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_BUFWEN
);
1198 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MBUFWEN
);
1199 } else if (state
& INT_CMD12DRE
) {
1200 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
,
1201 ~(INT_CMD12DRE
| INT_CMD12RBE
|
1202 INT_CMD12CRE
| INT_BUFRE
));
1203 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12DRE
);
1204 } else if (state
& INT_BUFRE
) {
1205 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_BUFRE
);
1206 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MBUFRE
);
1207 } else if (state
& INT_DTRANE
) {
1208 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~INT_DTRANE
);
1209 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MDTRANE
);
1210 } else if (state
& INT_CMD12RBE
) {
1211 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
,
1212 ~(INT_CMD12RBE
| INT_CMD12CRE
));
1213 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, MASK_MCMD12RBE
);
1215 dev_dbg(&host
->pd
->dev
, "Unsupported interrupt: 0x%x\n", state
);
1216 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT
, ~state
);
1217 sh_mmcif_bitclr(host
, MMCIF_CE_INT_MASK
, state
);
1221 host
->sd_error
= true;
1222 dev_dbg(&host
->pd
->dev
, "int err state = %08x\n", state
);
1224 if (state
& ~(INT_CMD12RBE
| INT_CMD12CRE
)) {
1225 if (!host
->dma_active
)
1226 return IRQ_WAKE_THREAD
;
1227 else if (host
->sd_error
)
1228 mmcif_dma_complete(host
);
1230 dev_dbg(&host
->pd
->dev
, "Unexpected IRQ 0x%x\n", state
);
1236 static void mmcif_timeout_work(struct work_struct
*work
)
1238 struct delayed_work
*d
= container_of(work
, struct delayed_work
, work
);
1239 struct sh_mmcif_host
*host
= container_of(d
, struct sh_mmcif_host
, timeout_work
);
1240 struct mmc_request
*mrq
= host
->mrq
;
1243 /* Don't run after mmc_remove_host() */
1247 * Handle races with cancel_delayed_work(), unless
1248 * cancel_delayed_work_sync() is used
1250 switch (host
->wait_for
) {
1251 case MMCIF_WAIT_FOR_CMD
:
1252 mrq
->cmd
->error
= sh_mmcif_error_manage(host
);
1254 case MMCIF_WAIT_FOR_STOP
:
1255 mrq
->stop
->error
= sh_mmcif_error_manage(host
);
1257 case MMCIF_WAIT_FOR_MREAD
:
1258 case MMCIF_WAIT_FOR_MWRITE
:
1259 case MMCIF_WAIT_FOR_READ
:
1260 case MMCIF_WAIT_FOR_WRITE
:
1261 case MMCIF_WAIT_FOR_READ_END
:
1262 case MMCIF_WAIT_FOR_WRITE_END
:
1263 mrq
->data
->error
= sh_mmcif_error_manage(host
);
1269 host
->state
= STATE_IDLE
;
1270 host
->wait_for
= MMCIF_WAIT_FOR_REQUEST
;
1272 mmc_request_done(host
->mmc
, mrq
);
1275 static void sh_mmcif_init_ocr(struct sh_mmcif_host
*host
)
1277 struct sh_mmcif_plat_data
*pd
= host
->pd
->dev
.platform_data
;
1278 struct mmc_host
*mmc
= host
->mmc
;
1280 mmc_regulator_get_supply(mmc
);
1285 if (!mmc
->ocr_avail
)
1286 mmc
->ocr_avail
= pd
->ocr
;
1288 dev_warn(mmc_dev(mmc
), "Platform OCR mask is ignored\n");
1291 static int __devinit
sh_mmcif_probe(struct platform_device
*pdev
)
1293 int ret
= 0, irq
[2];
1294 struct mmc_host
*mmc
;
1295 struct sh_mmcif_host
*host
;
1296 struct sh_mmcif_plat_data
*pd
= pdev
->dev
.platform_data
;
1297 struct resource
*res
;
1301 irq
[0] = platform_get_irq(pdev
, 0);
1302 irq
[1] = platform_get_irq(pdev
, 1);
1303 if (irq
[0] < 0 || irq
[1] < 0) {
1304 dev_err(&pdev
->dev
, "Get irq error\n");
1307 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1309 dev_err(&pdev
->dev
, "platform_get_resource error.\n");
1312 reg
= ioremap(res
->start
, resource_size(res
));
1314 dev_err(&pdev
->dev
, "ioremap error.\n");
1318 mmc
= mmc_alloc_host(sizeof(struct sh_mmcif_host
), &pdev
->dev
);
1323 host
= mmc_priv(mmc
);
1326 host
->timeout
= 1000;
1330 spin_lock_init(&host
->lock
);
1332 mmc
->ops
= &sh_mmcif_ops
;
1333 sh_mmcif_init_ocr(host
);
1335 mmc
->caps
= MMC_CAP_MMC_HIGHSPEED
;
1337 mmc
->caps
|= pd
->caps
;
1339 mmc
->max_blk_size
= 512;
1340 mmc
->max_req_size
= PAGE_CACHE_SIZE
* mmc
->max_segs
;
1341 mmc
->max_blk_count
= mmc
->max_req_size
/ mmc
->max_blk_size
;
1342 mmc
->max_seg_size
= mmc
->max_req_size
;
1344 platform_set_drvdata(pdev
, host
);
1346 pm_runtime_enable(&pdev
->dev
);
1347 host
->power
= false;
1349 snprintf(clk_name
, sizeof(clk_name
), "mmc%d", pdev
->id
);
1350 host
->hclk
= clk_get(&pdev
->dev
, clk_name
);
1351 if (IS_ERR(host
->hclk
)) {
1352 ret
= PTR_ERR(host
->hclk
);
1353 dev_err(&pdev
->dev
, "cannot get clock \"%s\": %d\n", clk_name
, ret
);
1356 ret
= sh_mmcif_clk_update(host
);
1360 ret
= pm_runtime_resume(&pdev
->dev
);
1364 INIT_DELAYED_WORK(&host
->timeout_work
, mmcif_timeout_work
);
1366 sh_mmcif_sync_reset(host
);
1367 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, MASK_ALL
);
1369 ret
= request_threaded_irq(irq
[0], sh_mmcif_intr
, sh_mmcif_irqt
, 0, "sh_mmc:error", host
);
1371 dev_err(&pdev
->dev
, "request_irq error (sh_mmc:error)\n");
1374 ret
= request_threaded_irq(irq
[1], sh_mmcif_intr
, sh_mmcif_irqt
, 0, "sh_mmc:int", host
);
1376 dev_err(&pdev
->dev
, "request_irq error (sh_mmc:int)\n");
1380 if (pd
&& pd
->use_cd_gpio
) {
1381 ret
= mmc_gpio_request_cd(mmc
, pd
->cd_gpio
);
1386 clk_disable(host
->hclk
);
1387 ret
= mmc_add_host(mmc
);
1391 dev_pm_qos_expose_latency_limit(&pdev
->dev
, 100);
1393 dev_info(&pdev
->dev
, "driver version %s\n", DRIVER_VERSION
);
1394 dev_dbg(&pdev
->dev
, "chip ver H'%04x\n",
1395 sh_mmcif_readl(host
->addr
, MMCIF_CE_VERSION
) & 0x0000ffff);
1399 if (pd
&& pd
->use_cd_gpio
)
1400 mmc_gpio_free_cd(mmc
);
1402 free_irq(irq
[1], host
);
1404 free_irq(irq
[0], host
);
1406 pm_runtime_suspend(&pdev
->dev
);
1408 clk_disable(host
->hclk
);
1410 clk_put(host
->hclk
);
1412 pm_runtime_disable(&pdev
->dev
);
1419 static int __devexit
sh_mmcif_remove(struct platform_device
*pdev
)
1421 struct sh_mmcif_host
*host
= platform_get_drvdata(pdev
);
1422 struct sh_mmcif_plat_data
*pd
= pdev
->dev
.platform_data
;
1426 clk_enable(host
->hclk
);
1427 pm_runtime_get_sync(&pdev
->dev
);
1429 dev_pm_qos_hide_latency_limit(&pdev
->dev
);
1431 if (pd
&& pd
->use_cd_gpio
)
1432 mmc_gpio_free_cd(host
->mmc
);
1434 mmc_remove_host(host
->mmc
);
1435 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, MASK_ALL
);
1438 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1439 * mmc_remove_host() call above. But swapping order doesn't help either
1440 * (a query on the linux-mmc mailing list didn't bring any replies).
1442 cancel_delayed_work_sync(&host
->timeout_work
);
1445 iounmap(host
->addr
);
1447 irq
[0] = platform_get_irq(pdev
, 0);
1448 irq
[1] = platform_get_irq(pdev
, 1);
1450 free_irq(irq
[0], host
);
1451 free_irq(irq
[1], host
);
1453 platform_set_drvdata(pdev
, NULL
);
1455 mmc_free_host(host
->mmc
);
1456 pm_runtime_put_sync(&pdev
->dev
);
1457 clk_disable(host
->hclk
);
1458 pm_runtime_disable(&pdev
->dev
);
1464 static int sh_mmcif_suspend(struct device
*dev
)
1466 struct sh_mmcif_host
*host
= dev_get_drvdata(dev
);
1467 int ret
= mmc_suspend_host(host
->mmc
);
1470 sh_mmcif_writel(host
->addr
, MMCIF_CE_INT_MASK
, MASK_ALL
);
1475 static int sh_mmcif_resume(struct device
*dev
)
1477 struct sh_mmcif_host
*host
= dev_get_drvdata(dev
);
1479 return mmc_resume_host(host
->mmc
);
1482 #define sh_mmcif_suspend NULL
1483 #define sh_mmcif_resume NULL
1484 #endif /* CONFIG_PM */
1486 static const struct of_device_id mmcif_of_match
[] = {
1487 { .compatible
= "renesas,sh-mmcif" },
1490 MODULE_DEVICE_TABLE(of
, mmcif_of_match
);
1492 static const struct dev_pm_ops sh_mmcif_dev_pm_ops
= {
1493 .suspend
= sh_mmcif_suspend
,
1494 .resume
= sh_mmcif_resume
,
1497 static struct platform_driver sh_mmcif_driver
= {
1498 .probe
= sh_mmcif_probe
,
1499 .remove
= sh_mmcif_remove
,
1501 .name
= DRIVER_NAME
,
1502 .pm
= &sh_mmcif_dev_pm_ops
,
1503 .owner
= THIS_MODULE
,
1504 .of_match_table
= mmcif_of_match
,
1508 module_platform_driver(sh_mmcif_driver
);
1510 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1511 MODULE_LICENSE("GPL");
1512 MODULE_ALIAS("platform:" DRIVER_NAME
);
1513 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");