2 * linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #include <linux/config.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/interrupt.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/highmem.h>
20 #include <linux/mmc/host.h>
21 #include <linux/mmc/protocol.h>
22 #include <linux/amba/bus.h>
23 #include <linux/clk.h>
25 #include <asm/cacheflush.h>
26 #include <asm/div64.h>
28 #include <asm/scatterlist.h>
29 #include <asm/sizes.h>
30 #include <asm/mach/mmc.h>
34 #define DRIVER_NAME "mmci-pl18x"
36 #ifdef CONFIG_MMC_DEBUG
37 #define DBG(host,fmt,args...) \
38 pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
40 #define DBG(host,fmt,args...) do { } while (0)
43 static unsigned int fmax
= 515633;
46 mmci_request_end(struct mmci_host
*host
, struct mmc_request
*mrq
)
48 writel(0, host
->base
+ MMCICOMMAND
);
54 mrq
->data
->bytes_xfered
= host
->data_xfered
;
57 * Need to drop the host lock here; mmc_request_done may call
58 * back into the driver...
60 spin_unlock(&host
->lock
);
61 mmc_request_done(host
->mmc
, mrq
);
62 spin_lock(&host
->lock
);
65 static void mmci_stop_data(struct mmci_host
*host
)
67 writel(0, host
->base
+ MMCIDATACTRL
);
68 writel(0, host
->base
+ MMCIMASK1
);
72 static void mmci_start_data(struct mmci_host
*host
, struct mmc_data
*data
)
74 unsigned int datactrl
, timeout
, irqmask
;
75 unsigned long long clks
;
78 DBG(host
, "blksz %04x blks %04x flags %08x\n",
79 1 << data
->blksz_bits
, data
->blocks
, data
->flags
);
82 host
->size
= data
->blocks
<< data
->blksz_bits
;
83 host
->data_xfered
= 0;
85 mmci_init_sg(host
, data
);
87 clks
= (unsigned long long)data
->timeout_ns
* host
->cclk
;
88 do_div(clks
, 1000000000UL);
90 timeout
= data
->timeout_clks
+ (unsigned int)clks
;
93 writel(timeout
, base
+ MMCIDATATIMER
);
94 writel(host
->size
, base
+ MMCIDATALENGTH
);
96 datactrl
= MCI_DPSM_ENABLE
| data
->blksz_bits
<< 4;
97 if (data
->flags
& MMC_DATA_READ
) {
98 datactrl
|= MCI_DPSM_DIRECTION
;
99 irqmask
= MCI_RXFIFOHALFFULLMASK
;
102 * If we have less than a FIFOSIZE of bytes to transfer,
103 * trigger a PIO interrupt as soon as any data is available.
105 if (host
->size
< MCI_FIFOSIZE
)
106 irqmask
|= MCI_RXDATAAVLBLMASK
;
109 * We don't actually need to include "FIFO empty" here
110 * since its implicit in "FIFO half empty".
112 irqmask
= MCI_TXFIFOHALFEMPTYMASK
;
115 writel(datactrl
, base
+ MMCIDATACTRL
);
116 writel(readl(base
+ MMCIMASK0
) & ~MCI_DATAENDMASK
, base
+ MMCIMASK0
);
117 writel(irqmask
, base
+ MMCIMASK1
);
121 mmci_start_command(struct mmci_host
*host
, struct mmc_command
*cmd
, u32 c
)
123 void __iomem
*base
= host
->base
;
125 DBG(host
, "op %02x arg %08x flags %08x\n",
126 cmd
->opcode
, cmd
->arg
, cmd
->flags
);
128 if (readl(base
+ MMCICOMMAND
) & MCI_CPSM_ENABLE
) {
129 writel(0, base
+ MMCICOMMAND
);
133 c
|= cmd
->opcode
| MCI_CPSM_ENABLE
;
134 if (cmd
->flags
& MMC_RSP_PRESENT
) {
135 if (cmd
->flags
& MMC_RSP_136
)
136 c
|= MCI_CPSM_LONGRSP
;
137 c
|= MCI_CPSM_RESPONSE
;
140 c
|= MCI_CPSM_INTERRUPT
;
144 writel(cmd
->arg
, base
+ MMCIARGUMENT
);
145 writel(c
, base
+ MMCICOMMAND
);
149 mmci_data_irq(struct mmci_host
*host
, struct mmc_data
*data
,
152 if (status
& MCI_DATABLOCKEND
) {
153 host
->data_xfered
+= 1 << data
->blksz_bits
;
155 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_TXUNDERRUN
|MCI_RXOVERRUN
)) {
156 if (status
& MCI_DATACRCFAIL
)
157 data
->error
= MMC_ERR_BADCRC
;
158 else if (status
& MCI_DATATIMEOUT
)
159 data
->error
= MMC_ERR_TIMEOUT
;
160 else if (status
& (MCI_TXUNDERRUN
|MCI_RXOVERRUN
))
161 data
->error
= MMC_ERR_FIFO
;
162 status
|= MCI_DATAEND
;
165 * We hit an error condition. Ensure that any data
166 * partially written to a page is properly coherent.
168 if (host
->sg_len
&& data
->flags
& MMC_DATA_READ
)
169 flush_dcache_page(host
->sg_ptr
->page
);
171 if (status
& MCI_DATAEND
) {
172 mmci_stop_data(host
);
175 mmci_request_end(host
, data
->mrq
);
177 mmci_start_command(host
, data
->stop
, 0);
183 mmci_cmd_irq(struct mmci_host
*host
, struct mmc_command
*cmd
,
186 void __iomem
*base
= host
->base
;
190 cmd
->resp
[0] = readl(base
+ MMCIRESPONSE0
);
191 cmd
->resp
[1] = readl(base
+ MMCIRESPONSE1
);
192 cmd
->resp
[2] = readl(base
+ MMCIRESPONSE2
);
193 cmd
->resp
[3] = readl(base
+ MMCIRESPONSE3
);
195 if (status
& MCI_CMDTIMEOUT
) {
196 cmd
->error
= MMC_ERR_TIMEOUT
;
197 } else if (status
& MCI_CMDCRCFAIL
&& cmd
->flags
& MMC_RSP_CRC
) {
198 cmd
->error
= MMC_ERR_BADCRC
;
201 if (!cmd
->data
|| cmd
->error
!= MMC_ERR_NONE
) {
202 mmci_request_end(host
, cmd
->mrq
);
203 } else if (!(cmd
->data
->flags
& MMC_DATA_READ
)) {
204 mmci_start_data(host
, cmd
->data
);
208 static int mmci_pio_read(struct mmci_host
*host
, char *buffer
, unsigned int remain
)
210 void __iomem
*base
= host
->base
;
215 int count
= host
->size
- (readl(base
+ MMCIFIFOCNT
) << 2);
223 readsl(base
+ MMCIFIFO
, ptr
, count
>> 2);
231 status
= readl(base
+ MMCISTATUS
);
232 } while (status
& MCI_RXDATAAVLBL
);
237 static int mmci_pio_write(struct mmci_host
*host
, char *buffer
, unsigned int remain
, u32 status
)
239 void __iomem
*base
= host
->base
;
243 unsigned int count
, maxcnt
;
245 maxcnt
= status
& MCI_TXFIFOEMPTY
? MCI_FIFOSIZE
: MCI_FIFOHALFSIZE
;
246 count
= min(remain
, maxcnt
);
248 writesl(base
+ MMCIFIFO
, ptr
, count
>> 2);
256 status
= readl(base
+ MMCISTATUS
);
257 } while (status
& MCI_TXFIFOHALFEMPTY
);
263 * PIO data transfer IRQ handler.
265 static irqreturn_t
mmci_pio_irq(int irq
, void *dev_id
, struct pt_regs
*regs
)
267 struct mmci_host
*host
= dev_id
;
268 void __iomem
*base
= host
->base
;
271 status
= readl(base
+ MMCISTATUS
);
273 DBG(host
, "irq1 %08x\n", status
);
277 unsigned int remain
, len
;
281 * For write, we only need to test the half-empty flag
282 * here - if the FIFO is completely empty, then by
283 * definition it is more than half empty.
285 * For read, check for data available.
287 if (!(status
& (MCI_TXFIFOHALFEMPTY
|MCI_RXDATAAVLBL
)))
291 * Map the current scatter buffer.
293 buffer
= mmci_kmap_atomic(host
, &flags
) + host
->sg_off
;
294 remain
= host
->sg_ptr
->length
- host
->sg_off
;
297 if (status
& MCI_RXACTIVE
)
298 len
= mmci_pio_read(host
, buffer
, remain
);
299 if (status
& MCI_TXACTIVE
)
300 len
= mmci_pio_write(host
, buffer
, remain
, status
);
305 mmci_kunmap_atomic(host
, buffer
, &flags
);
315 * If we were reading, and we have completed this
316 * page, ensure that the data cache is coherent.
318 if (status
& MCI_RXACTIVE
)
319 flush_dcache_page(host
->sg_ptr
->page
);
321 if (!mmci_next_sg(host
))
324 status
= readl(base
+ MMCISTATUS
);
328 * If we're nearing the end of the read, switch to
329 * "any data available" mode.
331 if (status
& MCI_RXACTIVE
&& host
->size
< MCI_FIFOSIZE
)
332 writel(MCI_RXDATAAVLBLMASK
, base
+ MMCIMASK1
);
335 * If we run out of data, disable the data IRQs; this
336 * prevents a race where the FIFO becomes empty before
337 * the chip itself has disabled the data path, and
338 * stops us racing with our data end IRQ.
340 if (host
->size
== 0) {
341 writel(0, base
+ MMCIMASK1
);
342 writel(readl(base
+ MMCIMASK0
) | MCI_DATAENDMASK
, base
+ MMCIMASK0
);
349 * Handle completion of command and data transfers.
351 static irqreturn_t
mmci_irq(int irq
, void *dev_id
, struct pt_regs
*regs
)
353 struct mmci_host
*host
= dev_id
;
357 spin_lock(&host
->lock
);
360 struct mmc_command
*cmd
;
361 struct mmc_data
*data
;
363 status
= readl(host
->base
+ MMCISTATUS
);
364 status
&= readl(host
->base
+ MMCIMASK0
);
365 writel(status
, host
->base
+ MMCICLEAR
);
367 DBG(host
, "irq0 %08x\n", status
);
370 if (status
& (MCI_DATACRCFAIL
|MCI_DATATIMEOUT
|MCI_TXUNDERRUN
|
371 MCI_RXOVERRUN
|MCI_DATAEND
|MCI_DATABLOCKEND
) && data
)
372 mmci_data_irq(host
, data
, status
);
375 if (status
& (MCI_CMDCRCFAIL
|MCI_CMDTIMEOUT
|MCI_CMDSENT
|MCI_CMDRESPEND
) && cmd
)
376 mmci_cmd_irq(host
, cmd
, status
);
381 spin_unlock(&host
->lock
);
383 return IRQ_RETVAL(ret
);
386 static void mmci_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
388 struct mmci_host
*host
= mmc_priv(mmc
);
390 WARN_ON(host
->mrq
!= NULL
);
392 spin_lock_irq(&host
->lock
);
396 if (mrq
->data
&& mrq
->data
->flags
& MMC_DATA_READ
)
397 mmci_start_data(host
, mrq
->data
);
399 mmci_start_command(host
, mrq
->cmd
, 0);
401 spin_unlock_irq(&host
->lock
);
404 static void mmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
406 struct mmci_host
*host
= mmc_priv(mmc
);
407 u32 clk
= 0, pwr
= 0;
409 DBG(host
, "clock %uHz busmode %u powermode %u Vdd %u\n",
410 ios
->clock
, ios
->bus_mode
, ios
->power_mode
, ios
->vdd
);
413 if (ios
->clock
>= host
->mclk
) {
414 clk
= MCI_CLK_BYPASS
;
415 host
->cclk
= host
->mclk
;
417 clk
= host
->mclk
/ (2 * ios
->clock
) - 1;
420 host
->cclk
= host
->mclk
/ (2 * (clk
+ 1));
422 clk
|= MCI_CLK_ENABLE
;
425 if (host
->plat
->translate_vdd
)
426 pwr
|= host
->plat
->translate_vdd(mmc_dev(mmc
), ios
->vdd
);
428 switch (ios
->power_mode
) {
439 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
442 writel(clk
, host
->base
+ MMCICLOCK
);
444 if (host
->pwr
!= pwr
) {
446 writel(pwr
, host
->base
+ MMCIPOWER
);
450 static struct mmc_host_ops mmci_ops
= {
451 .request
= mmci_request
,
452 .set_ios
= mmci_set_ios
,
455 static void mmci_check_status(unsigned long data
)
457 struct mmci_host
*host
= (struct mmci_host
*)data
;
460 status
= host
->plat
->status(mmc_dev(host
->mmc
));
461 if (status
^ host
->oldstat
)
462 mmc_detect_change(host
->mmc
, 0);
464 host
->oldstat
= status
;
465 mod_timer(&host
->timer
, jiffies
+ HZ
);
468 static int mmci_probe(struct amba_device
*dev
, void *id
)
470 struct mmc_platform_data
*plat
= dev
->dev
.platform_data
;
471 struct mmci_host
*host
;
472 struct mmc_host
*mmc
;
475 /* must have platform data */
481 ret
= amba_request_regions(dev
, DRIVER_NAME
);
485 mmc
= mmc_alloc_host(sizeof(struct mmci_host
), &dev
->dev
);
491 host
= mmc_priv(mmc
);
492 host
->clk
= clk_get(&dev
->dev
, "MCLK");
493 if (IS_ERR(host
->clk
)) {
494 ret
= PTR_ERR(host
->clk
);
499 ret
= clk_enable(host
->clk
);
504 host
->mclk
= clk_get_rate(host
->clk
);
506 host
->base
= ioremap(dev
->res
.start
, SZ_4K
);
512 mmc
->ops
= &mmci_ops
;
513 mmc
->f_min
= (host
->mclk
+ 511) / 512;
514 mmc
->f_max
= min(host
->mclk
, fmax
);
515 mmc
->ocr_avail
= plat
->ocr_mask
;
520 mmc
->max_hw_segs
= 16;
521 mmc
->max_phys_segs
= NR_SG
;
524 * Since we only have a 16-bit data length register, we must
525 * ensure that we don't exceed 2^16-1 bytes in a single request.
526 * Choose 64 (512-byte) sectors as the limit.
528 mmc
->max_sectors
= 64;
531 * Set the maximum segment size. Since we aren't doing DMA
532 * (yet) we are only limited by the data length register.
534 mmc
->max_seg_size
= mmc
->max_sectors
<< 9;
536 spin_lock_init(&host
->lock
);
538 writel(0, host
->base
+ MMCIMASK0
);
539 writel(0, host
->base
+ MMCIMASK1
);
540 writel(0xfff, host
->base
+ MMCICLEAR
);
542 ret
= request_irq(dev
->irq
[0], mmci_irq
, SA_SHIRQ
, DRIVER_NAME
" (cmd)", host
);
546 ret
= request_irq(dev
->irq
[1], mmci_pio_irq
, SA_SHIRQ
, DRIVER_NAME
" (pio)", host
);
550 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
552 amba_set_drvdata(dev
, mmc
);
556 printk(KERN_INFO
"%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
557 mmc_hostname(mmc
), amba_rev(dev
), amba_config(dev
),
558 dev
->res
.start
, dev
->irq
[0], dev
->irq
[1]);
560 init_timer(&host
->timer
);
561 host
->timer
.data
= (unsigned long)host
;
562 host
->timer
.function
= mmci_check_status
;
563 host
->timer
.expires
= jiffies
+ HZ
;
564 add_timer(&host
->timer
);
569 free_irq(dev
->irq
[0], host
);
573 clk_disable(host
->clk
);
579 amba_release_regions(dev
);
584 static int mmci_remove(struct amba_device
*dev
)
586 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
588 amba_set_drvdata(dev
, NULL
);
591 struct mmci_host
*host
= mmc_priv(mmc
);
593 del_timer_sync(&host
->timer
);
595 mmc_remove_host(mmc
);
597 writel(0, host
->base
+ MMCIMASK0
);
598 writel(0, host
->base
+ MMCIMASK1
);
600 writel(0, host
->base
+ MMCICOMMAND
);
601 writel(0, host
->base
+ MMCIDATACTRL
);
603 free_irq(dev
->irq
[0], host
);
604 free_irq(dev
->irq
[1], host
);
607 clk_disable(host
->clk
);
612 amba_release_regions(dev
);
619 static int mmci_suspend(struct amba_device
*dev
, pm_message_t state
)
621 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
625 struct mmci_host
*host
= mmc_priv(mmc
);
627 ret
= mmc_suspend_host(mmc
, state
);
629 writel(0, host
->base
+ MMCIMASK0
);
635 static int mmci_resume(struct amba_device
*dev
)
637 struct mmc_host
*mmc
= amba_get_drvdata(dev
);
641 struct mmci_host
*host
= mmc_priv(mmc
);
643 writel(MCI_IRQENABLE
, host
->base
+ MMCIMASK0
);
645 ret
= mmc_resume_host(mmc
);
651 #define mmci_suspend NULL
652 #define mmci_resume NULL
655 static struct amba_id mmci_ids
[] = {
667 static struct amba_driver mmci_driver
= {
672 .remove
= mmci_remove
,
673 .suspend
= mmci_suspend
,
674 .resume
= mmci_resume
,
675 .id_table
= mmci_ids
,
678 static int __init
mmci_init(void)
680 return amba_driver_register(&mmci_driver
);
683 static void __exit
mmci_exit(void)
685 amba_driver_unregister(&mmci_driver
);
688 module_init(mmci_init
);
689 module_exit(mmci_exit
);
690 module_param(fmax
, uint
, 0444);
692 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
693 MODULE_LICENSE("GPL");
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