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Merge branch 'for-linus' of master.kernel.org:/pub/scm/linux/kernel/git/roland/infiniband
[deliverable/linux.git] / drivers / mmc / pxamci.c
1 /*
2 * linux/drivers/mmc/pxa.c - PXA MMCI driver
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This hardware is really sick:
11 * - No way to clear interrupts.
12 * - Have to turn off the clock whenever we touch the device.
13 * - Doesn't tell you how many data blocks were transferred.
14 * Yuck!
15 *
16 * 1 and 3 byte data transfers not supported
17 * max block length up to 1023
18 */
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/mmc/host.h>
28 #include <linux/mmc/protocol.h>
29
30 #include <asm/dma.h>
31 #include <asm/io.h>
32 #include <asm/scatterlist.h>
33 #include <asm/sizes.h>
34
35 #include <asm/arch/pxa-regs.h>
36 #include <asm/arch/mmc.h>
37
38 #include "pxamci.h"
39
40 #define DRIVER_NAME "pxa2xx-mci"
41
42 #define NR_SG 1
43
44 struct pxamci_host {
45 struct mmc_host *mmc;
46 spinlock_t lock;
47 struct resource *res;
48 void __iomem *base;
49 int irq;
50 int dma;
51 unsigned int clkrt;
52 unsigned int cmdat;
53 unsigned int imask;
54 unsigned int power_mode;
55 struct pxamci_platform_data *pdata;
56
57 struct mmc_request *mrq;
58 struct mmc_command *cmd;
59 struct mmc_data *data;
60
61 dma_addr_t sg_dma;
62 struct pxa_dma_desc *sg_cpu;
63 unsigned int dma_len;
64
65 unsigned int dma_dir;
66 };
67
68 static inline unsigned int ns_to_clocks(unsigned int ns)
69 {
70 return (ns * (CLOCKRATE / 1000000) + 999) / 1000;
71 }
72
73 static void pxamci_stop_clock(struct pxamci_host *host)
74 {
75 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) {
76 unsigned long timeout = 10000;
77 unsigned int v;
78
79 writel(STOP_CLOCK, host->base + MMC_STRPCL);
80
81 do {
82 v = readl(host->base + MMC_STAT);
83 if (!(v & STAT_CLK_EN))
84 break;
85 udelay(1);
86 } while (timeout--);
87
88 if (v & STAT_CLK_EN)
89 dev_err(mmc_dev(host->mmc), "unable to stop clock\n");
90 }
91 }
92
93 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask)
94 {
95 unsigned long flags;
96
97 spin_lock_irqsave(&host->lock, flags);
98 host->imask &= ~mask;
99 writel(host->imask, host->base + MMC_I_MASK);
100 spin_unlock_irqrestore(&host->lock, flags);
101 }
102
103 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask)
104 {
105 unsigned long flags;
106
107 spin_lock_irqsave(&host->lock, flags);
108 host->imask |= mask;
109 writel(host->imask, host->base + MMC_I_MASK);
110 spin_unlock_irqrestore(&host->lock, flags);
111 }
112
113 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data)
114 {
115 unsigned int nob = data->blocks;
116 unsigned int timeout;
117 u32 dcmd;
118 int i;
119
120 host->data = data;
121
122 if (data->flags & MMC_DATA_STREAM)
123 nob = 0xffff;
124
125 writel(nob, host->base + MMC_NOB);
126 writel(1 << data->blksz_bits, host->base + MMC_BLKLEN);
127
128 timeout = ns_to_clocks(data->timeout_ns) + data->timeout_clks;
129 writel((timeout + 255) / 256, host->base + MMC_RDTO);
130
131 if (data->flags & MMC_DATA_READ) {
132 host->dma_dir = DMA_FROM_DEVICE;
133 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG;
134 DRCMRTXMMC = 0;
135 DRCMRRXMMC = host->dma | DRCMR_MAPVLD;
136 } else {
137 host->dma_dir = DMA_TO_DEVICE;
138 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC;
139 DRCMRRXMMC = 0;
140 DRCMRTXMMC = host->dma | DRCMR_MAPVLD;
141 }
142
143 dcmd |= DCMD_BURST32 | DCMD_WIDTH1;
144
145 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
146 host->dma_dir);
147
148 for (i = 0; i < host->dma_len; i++) {
149 if (data->flags & MMC_DATA_READ) {
150 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO;
151 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]);
152 } else {
153 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]);
154 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO;
155 }
156 host->sg_cpu[i].dcmd = dcmd | sg_dma_len(&data->sg[i]);
157 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) *
158 sizeof(struct pxa_dma_desc);
159 }
160 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP;
161 wmb();
162
163 DDADR(host->dma) = host->sg_dma;
164 DCSR(host->dma) = DCSR_RUN;
165 }
166
167 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat)
168 {
169 WARN_ON(host->cmd != NULL);
170 host->cmd = cmd;
171
172 if (cmd->flags & MMC_RSP_BUSY)
173 cmdat |= CMDAT_BUSY;
174
175 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE))
176 switch (RSP_TYPE(mmc_resp_type(cmd))) {
177 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6 */
178 cmdat |= CMDAT_RESP_SHORT;
179 break;
180 case RSP_TYPE(MMC_RSP_R3):
181 cmdat |= CMDAT_RESP_R3;
182 break;
183 case RSP_TYPE(MMC_RSP_R2):
184 cmdat |= CMDAT_RESP_R2;
185 break;
186 default:
187 break;
188 }
189
190 writel(cmd->opcode, host->base + MMC_CMD);
191 writel(cmd->arg >> 16, host->base + MMC_ARGH);
192 writel(cmd->arg & 0xffff, host->base + MMC_ARGL);
193 writel(cmdat, host->base + MMC_CMDAT);
194 writel(host->clkrt, host->base + MMC_CLKRT);
195
196 writel(START_CLOCK, host->base + MMC_STRPCL);
197
198 pxamci_enable_irq(host, END_CMD_RES);
199 }
200
201 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq)
202 {
203 pr_debug("PXAMCI: request done\n");
204 host->mrq = NULL;
205 host->cmd = NULL;
206 host->data = NULL;
207 mmc_request_done(host->mmc, mrq);
208 }
209
210 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat)
211 {
212 struct mmc_command *cmd = host->cmd;
213 int i;
214 u32 v;
215
216 if (!cmd)
217 return 0;
218
219 host->cmd = NULL;
220
221 /*
222 * Did I mention this is Sick. We always need to
223 * discard the upper 8 bits of the first 16-bit word.
224 */
225 v = readl(host->base + MMC_RES) & 0xffff;
226 for (i = 0; i < 4; i++) {
227 u32 w1 = readl(host->base + MMC_RES) & 0xffff;
228 u32 w2 = readl(host->base + MMC_RES) & 0xffff;
229 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8;
230 v = w2;
231 }
232
233 if (stat & STAT_TIME_OUT_RESPONSE) {
234 cmd->error = MMC_ERR_TIMEOUT;
235 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
236 #ifdef CONFIG_PXA27x
237 /*
238 * workaround for erratum #42:
239 * Intel PXA27x Family Processor Specification Update Rev 001
240 */
241 if (cmd->opcode == MMC_ALL_SEND_CID ||
242 cmd->opcode == MMC_SEND_CSD ||
243 cmd->opcode == MMC_SEND_CID) {
244 /* a bogus CRC error can appear if the msb of
245 the 15 byte response is a one */
246 if ((cmd->resp[0] & 0x80000000) == 0)
247 cmd->error = MMC_ERR_BADCRC;
248 } else {
249 pr_debug("ignoring CRC from command %d - *risky*\n",cmd->opcode);
250 }
251 #else
252 cmd->error = MMC_ERR_BADCRC;
253 #endif
254 }
255
256 pxamci_disable_irq(host, END_CMD_RES);
257 if (host->data && cmd->error == MMC_ERR_NONE) {
258 pxamci_enable_irq(host, DATA_TRAN_DONE);
259 } else {
260 pxamci_finish_request(host, host->mrq);
261 }
262
263 return 1;
264 }
265
266 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat)
267 {
268 struct mmc_data *data = host->data;
269
270 if (!data)
271 return 0;
272
273 DCSR(host->dma) = 0;
274 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
275 host->dma_dir);
276
277 if (stat & STAT_READ_TIME_OUT)
278 data->error = MMC_ERR_TIMEOUT;
279 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR))
280 data->error = MMC_ERR_BADCRC;
281
282 /*
283 * There appears to be a hardware design bug here. There seems to
284 * be no way to find out how much data was transferred to the card.
285 * This means that if there was an error on any block, we mark all
286 * data blocks as being in error.
287 */
288 if (data->error == MMC_ERR_NONE)
289 data->bytes_xfered = data->blocks << data->blksz_bits;
290 else
291 data->bytes_xfered = 0;
292
293 pxamci_disable_irq(host, DATA_TRAN_DONE);
294
295 host->data = NULL;
296 if (host->mrq->stop && data->error == MMC_ERR_NONE) {
297 pxamci_stop_clock(host);
298 pxamci_start_cmd(host, host->mrq->stop, 0);
299 } else {
300 pxamci_finish_request(host, host->mrq);
301 }
302
303 return 1;
304 }
305
306 static irqreturn_t pxamci_irq(int irq, void *devid, struct pt_regs *regs)
307 {
308 struct pxamci_host *host = devid;
309 unsigned int ireg;
310 int handled = 0;
311
312 ireg = readl(host->base + MMC_I_REG);
313
314 pr_debug("PXAMCI: irq %08x\n", ireg);
315
316 if (ireg) {
317 unsigned stat = readl(host->base + MMC_STAT);
318
319 pr_debug("PXAMCI: stat %08x\n", stat);
320
321 if (ireg & END_CMD_RES)
322 handled |= pxamci_cmd_done(host, stat);
323 if (ireg & DATA_TRAN_DONE)
324 handled |= pxamci_data_done(host, stat);
325 }
326
327 return IRQ_RETVAL(handled);
328 }
329
330 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq)
331 {
332 struct pxamci_host *host = mmc_priv(mmc);
333 unsigned int cmdat;
334
335 WARN_ON(host->mrq != NULL);
336
337 host->mrq = mrq;
338
339 pxamci_stop_clock(host);
340
341 cmdat = host->cmdat;
342 host->cmdat &= ~CMDAT_INIT;
343
344 if (mrq->data) {
345 pxamci_setup_data(host, mrq->data);
346
347 cmdat &= ~CMDAT_BUSY;
348 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN;
349 if (mrq->data->flags & MMC_DATA_WRITE)
350 cmdat |= CMDAT_WRITE;
351
352 if (mrq->data->flags & MMC_DATA_STREAM)
353 cmdat |= CMDAT_STREAM;
354 }
355
356 pxamci_start_cmd(host, mrq->cmd, cmdat);
357 }
358
359 static int pxamci_get_ro(struct mmc_host *mmc)
360 {
361 struct pxamci_host *host = mmc_priv(mmc);
362
363 if (host->pdata && host->pdata->get_ro)
364 return host->pdata->get_ro(mmc->dev);
365 /* Host doesn't support read only detection so assume writeable */
366 return 0;
367 }
368
369 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
370 {
371 struct pxamci_host *host = mmc_priv(mmc);
372
373 pr_debug("pxamci_set_ios: clock %u power %u vdd %u.%02u\n",
374 ios->clock, ios->power_mode, ios->vdd / 100,
375 ios->vdd % 100);
376
377 if (ios->clock) {
378 unsigned int clk = CLOCKRATE / ios->clock;
379 if (CLOCKRATE / clk > ios->clock)
380 clk <<= 1;
381 host->clkrt = fls(clk) - 1;
382 pxa_set_cken(CKEN12_MMC, 1);
383
384 /*
385 * we write clkrt on the next command
386 */
387 } else {
388 pxamci_stop_clock(host);
389 pxa_set_cken(CKEN12_MMC, 0);
390 }
391
392 if (host->power_mode != ios->power_mode) {
393 host->power_mode = ios->power_mode;
394
395 if (host->pdata && host->pdata->setpower)
396 host->pdata->setpower(mmc->dev, ios->vdd);
397
398 if (ios->power_mode == MMC_POWER_ON)
399 host->cmdat |= CMDAT_INIT;
400 }
401
402 pr_debug("pxamci_set_ios: clkrt = %x cmdat = %x\n",
403 host->clkrt, host->cmdat);
404 }
405
406 static struct mmc_host_ops pxamci_ops = {
407 .request = pxamci_request,
408 .get_ro = pxamci_get_ro,
409 .set_ios = pxamci_set_ios,
410 };
411
412 static void pxamci_dma_irq(int dma, void *devid, struct pt_regs *regs)
413 {
414 printk(KERN_ERR "DMA%d: IRQ???\n", dma);
415 DCSR(dma) = DCSR_STARTINTR|DCSR_ENDINTR|DCSR_BUSERR;
416 }
417
418 static irqreturn_t pxamci_detect_irq(int irq, void *devid, struct pt_regs *regs)
419 {
420 struct pxamci_host *host = mmc_priv(devid);
421
422 mmc_detect_change(devid, host->pdata->detect_delay);
423 return IRQ_HANDLED;
424 }
425
426 static int pxamci_probe(struct platform_device *pdev)
427 {
428 struct mmc_host *mmc;
429 struct pxamci_host *host = NULL;
430 struct resource *r;
431 int ret, irq;
432
433 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434 irq = platform_get_irq(pdev, 0);
435 if (!r || irq < 0)
436 return -ENXIO;
437
438 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME);
439 if (!r)
440 return -EBUSY;
441
442 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev);
443 if (!mmc) {
444 ret = -ENOMEM;
445 goto out;
446 }
447
448 mmc->ops = &pxamci_ops;
449 mmc->f_min = CLOCKRATE_MIN;
450 mmc->f_max = CLOCKRATE_MAX;
451
452 /*
453 * We can do SG-DMA, but we don't because we never know how much
454 * data we successfully wrote to the card.
455 */
456 mmc->max_phys_segs = NR_SG;
457
458 /*
459 * Our hardware DMA can handle a maximum of one page per SG entry.
460 */
461 mmc->max_seg_size = PAGE_SIZE;
462
463 host = mmc_priv(mmc);
464 host->mmc = mmc;
465 host->dma = -1;
466 host->pdata = pdev->dev.platform_data;
467 mmc->ocr_avail = host->pdata ?
468 host->pdata->ocr_mask :
469 MMC_VDD_32_33|MMC_VDD_33_34;
470
471 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL);
472 if (!host->sg_cpu) {
473 ret = -ENOMEM;
474 goto out;
475 }
476
477 spin_lock_init(&host->lock);
478 host->res = r;
479 host->irq = irq;
480 host->imask = MMC_I_MASK_ALL;
481
482 host->base = ioremap(r->start, SZ_4K);
483 if (!host->base) {
484 ret = -ENOMEM;
485 goto out;
486 }
487
488 /*
489 * Ensure that the host controller is shut down, and setup
490 * with our defaults.
491 */
492 pxamci_stop_clock(host);
493 writel(0, host->base + MMC_SPI);
494 writel(64, host->base + MMC_RESTO);
495 writel(host->imask, host->base + MMC_I_MASK);
496
497 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW,
498 pxamci_dma_irq, host);
499 if (host->dma < 0) {
500 ret = -EBUSY;
501 goto out;
502 }
503
504 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host);
505 if (ret)
506 goto out;
507
508 platform_set_drvdata(pdev, mmc);
509
510 if (host->pdata && host->pdata->init)
511 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc);
512
513 mmc_add_host(mmc);
514
515 return 0;
516
517 out:
518 if (host) {
519 if (host->dma >= 0)
520 pxa_free_dma(host->dma);
521 if (host->base)
522 iounmap(host->base);
523 if (host->sg_cpu)
524 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
525 }
526 if (mmc)
527 mmc_free_host(mmc);
528 release_resource(r);
529 return ret;
530 }
531
532 static int pxamci_remove(struct platform_device *pdev)
533 {
534 struct mmc_host *mmc = platform_get_drvdata(pdev);
535
536 platform_set_drvdata(pdev, NULL);
537
538 if (mmc) {
539 struct pxamci_host *host = mmc_priv(mmc);
540
541 if (host->pdata && host->pdata->exit)
542 host->pdata->exit(&pdev->dev, mmc);
543
544 mmc_remove_host(mmc);
545
546 pxamci_stop_clock(host);
547 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD|
548 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE,
549 host->base + MMC_I_MASK);
550
551 DRCMRRXMMC = 0;
552 DRCMRTXMMC = 0;
553
554 free_irq(host->irq, host);
555 pxa_free_dma(host->dma);
556 iounmap(host->base);
557 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
558
559 release_resource(host->res);
560
561 mmc_free_host(mmc);
562 }
563 return 0;
564 }
565
566 #ifdef CONFIG_PM
567 static int pxamci_suspend(struct platform_device *dev, pm_message_t state)
568 {
569 struct mmc_host *mmc = platform_get_drvdata(dev);
570 int ret = 0;
571
572 if (mmc)
573 ret = mmc_suspend_host(mmc, state);
574
575 return ret;
576 }
577
578 static int pxamci_resume(struct platform_device *dev)
579 {
580 struct mmc_host *mmc = platform_get_drvdata(dev);
581 int ret = 0;
582
583 if (mmc)
584 ret = mmc_resume_host(mmc);
585
586 return ret;
587 }
588 #else
589 #define pxamci_suspend NULL
590 #define pxamci_resume NULL
591 #endif
592
593 static struct platform_driver pxamci_driver = {
594 .probe = pxamci_probe,
595 .remove = pxamci_remove,
596 .suspend = pxamci_suspend,
597 .resume = pxamci_resume,
598 .driver = {
599 .name = DRIVER_NAME,
600 },
601 };
602
603 static int __init pxamci_init(void)
604 {
605 return platform_driver_register(&pxamci_driver);
606 }
607
608 static void __exit pxamci_exit(void)
609 {
610 platform_driver_unregister(&pxamci_driver);
611 }
612
613 module_init(pxamci_init);
614 module_exit(pxamci_exit);
615
616 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver");
617 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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