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MTD: Convert Atmel PRI information to AMD format
[deliverable/linux.git] / drivers / mtd / chips / cfi_cmdset_0002.c
1 /*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
17 *
18 * This code is GPL
19 *
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
29 #include <asm/io.h>
30 #include <asm/byteorder.h>
31
32 #include <linux/errno.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
41
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
44
45 #define MAX_WORD_RETRIES 3
46
47 #define MANUFACTURER_AMD 0x0001
48 #define MANUFACTURER_SST 0x00BF
49 #define SST49LF004B 0x0060
50 #define SST49LF008A 0x005a
51
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
61
62 static void cfi_amdstd_destroy(struct mtd_info *);
63
64 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
65 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
66
67 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
68 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
69 #include "fwh_lock.h"
70
71 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
72 .probe = NULL, /* Not usable directly */
73 .destroy = cfi_amdstd_destroy,
74 .name = "cfi_cmdset_0002",
75 .module = THIS_MODULE
76 };
77
78
79 /* #define DEBUG_CFI_FEATURES */
80
81
82 #ifdef DEBUG_CFI_FEATURES
83 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
84 {
85 const char* erase_suspend[3] = {
86 "Not supported", "Read only", "Read/write"
87 };
88 const char* top_bottom[6] = {
89 "No WP", "8x8KiB sectors at top & bottom, no WP",
90 "Bottom boot", "Top boot",
91 "Uniform, Bottom WP", "Uniform, Top WP"
92 };
93
94 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
95 printk(" Address sensitive unlock: %s\n",
96 (extp->SiliconRevision & 1) ? "Not required" : "Required");
97
98 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
99 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
100 else
101 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
102
103 if (extp->BlkProt == 0)
104 printk(" Block protection: Not supported\n");
105 else
106 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
107
108
109 printk(" Temporary block unprotect: %s\n",
110 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
111 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
112 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
113 printk(" Burst mode: %s\n",
114 extp->BurstMode ? "Supported" : "Not supported");
115 if (extp->PageMode == 0)
116 printk(" Page mode: Not supported\n");
117 else
118 printk(" Page mode: %d word page\n", extp->PageMode << 2);
119
120 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
121 extp->VppMin >> 4, extp->VppMin & 0xf);
122 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
123 extp->VppMax >> 4, extp->VppMax & 0xf);
124
125 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
126 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
127 else
128 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
129 }
130 #endif
131
132 #ifdef AMD_BOOTLOC_BUG
133 /* Wheee. Bring me the head of someone at AMD. */
134 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
135 {
136 struct map_info *map = mtd->priv;
137 struct cfi_private *cfi = map->fldrv_priv;
138 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
139 __u8 major = extp->MajorVersion;
140 __u8 minor = extp->MinorVersion;
141
142 if (((major << 8) | minor) < 0x3131) {
143 /* CFI version 1.0 => don't trust bootloc */
144 if (cfi->id & 0x80) {
145 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
146 extp->TopBottom = 3; /* top boot */
147 } else {
148 extp->TopBottom = 2; /* bottom boot */
149 }
150 }
151 }
152 #endif
153
154 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
155 {
156 struct map_info *map = mtd->priv;
157 struct cfi_private *cfi = map->fldrv_priv;
158 if (cfi->cfiq->BufWriteTimeoutTyp) {
159 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
160 mtd->write = cfi_amdstd_write_buffers;
161 }
162 }
163
164 /* Atmel chips don't use the same PRI format as AMD chips */
165 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
166 {
167 struct map_info *map = mtd->priv;
168 struct cfi_private *cfi = map->fldrv_priv;
169 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
170 struct cfi_pri_atmel atmel_pri;
171
172 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
173 memset(extp + 5, 0, sizeof(*extp) - 5);
174
175 if (atmel_pri.Features & 0x02)
176 extp->EraseSuspend = 2;
177
178 if (atmel_pri.BottomBoot)
179 extp->TopBottom = 2;
180 else
181 extp->TopBottom = 3;
182 }
183
184 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
185 {
186 /* Setup for chips with a secsi area */
187 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
188 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
189 }
190
191 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
192 {
193 struct map_info *map = mtd->priv;
194 struct cfi_private *cfi = map->fldrv_priv;
195 if ((cfi->cfiq->NumEraseRegions == 1) &&
196 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
197 mtd->erase = cfi_amdstd_erase_chip;
198 }
199
200 }
201
202 static struct cfi_fixup cfi_fixup_table[] = {
203 #ifdef AMD_BOOTLOC_BUG
204 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
205 #endif
206 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
207 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
208 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
209 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
210 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
211 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
212 #if !FORCE_WORD_WRITE
213 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
214 #endif
215 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
216 { 0, 0, NULL, NULL }
217 };
218 static struct cfi_fixup jedec_fixup_table[] = {
219 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
220 { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
221 { 0, 0, NULL, NULL }
222 };
223
224 static struct cfi_fixup fixup_table[] = {
225 /* The CFI vendor ids and the JEDEC vendor IDs appear
226 * to be common. It is like the devices id's are as
227 * well. This table is to pick all cases where
228 * we know that is the case.
229 */
230 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
231 { 0, 0, NULL, NULL }
232 };
233
234
235 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
236 {
237 struct cfi_private *cfi = map->fldrv_priv;
238 struct mtd_info *mtd;
239 int i;
240
241 mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
242 if (!mtd) {
243 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
244 return NULL;
245 }
246 memset(mtd, 0, sizeof(*mtd));
247 mtd->priv = map;
248 mtd->type = MTD_NORFLASH;
249
250 /* Fill in the default mtd operations */
251 mtd->erase = cfi_amdstd_erase_varsize;
252 mtd->write = cfi_amdstd_write_words;
253 mtd->read = cfi_amdstd_read;
254 mtd->sync = cfi_amdstd_sync;
255 mtd->suspend = cfi_amdstd_suspend;
256 mtd->resume = cfi_amdstd_resume;
257 mtd->flags = MTD_CAP_NORFLASH;
258 mtd->name = map->name;
259 mtd->writesize = 1;
260
261 if (cfi->cfi_mode==CFI_MODE_CFI){
262 unsigned char bootloc;
263 /*
264 * It's a real CFI chip, not one for which the probe
265 * routine faked a CFI structure. So we read the feature
266 * table from it.
267 */
268 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
269 struct cfi_pri_amdstd *extp;
270
271 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
272 if (!extp) {
273 kfree(mtd);
274 return NULL;
275 }
276
277 if (extp->MajorVersion != '1' ||
278 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
279 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
280 "version %c.%c.\n", extp->MajorVersion,
281 extp->MinorVersion);
282 kfree(extp);
283 kfree(mtd);
284 return NULL;
285 }
286
287 /* Install our own private info structure */
288 cfi->cmdset_priv = extp;
289
290 /* Apply cfi device specific fixups */
291 cfi_fixup(mtd, cfi_fixup_table);
292
293 #ifdef DEBUG_CFI_FEATURES
294 /* Tell the user about it in lots of lovely detail */
295 cfi_tell_features(extp);
296 #endif
297
298 bootloc = extp->TopBottom;
299 if ((bootloc != 2) && (bootloc != 3)) {
300 printk(KERN_WARNING "%s: CFI does not contain boot "
301 "bank location. Assuming top.\n", map->name);
302 bootloc = 2;
303 }
304
305 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
306 printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name);
307
308 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
309 int j = (cfi->cfiq->NumEraseRegions-1)-i;
310 __u32 swap;
311
312 swap = cfi->cfiq->EraseRegionInfo[i];
313 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
314 cfi->cfiq->EraseRegionInfo[j] = swap;
315 }
316 }
317 /* Set the default CFI lock/unlock addresses */
318 cfi->addr_unlock1 = 0x555;
319 cfi->addr_unlock2 = 0x2aa;
320 /* Modify the unlock address if we are in compatibility mode */
321 if ( /* x16 in x8 mode */
322 ((cfi->device_type == CFI_DEVICETYPE_X8) &&
323 (cfi->cfiq->InterfaceDesc == 2)) ||
324 /* x32 in x16 mode */
325 ((cfi->device_type == CFI_DEVICETYPE_X16) &&
326 (cfi->cfiq->InterfaceDesc == 4)))
327 {
328 cfi->addr_unlock1 = 0xaaa;
329 cfi->addr_unlock2 = 0x555;
330 }
331
332 } /* CFI mode */
333 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
334 /* Apply jedec specific fixups */
335 cfi_fixup(mtd, jedec_fixup_table);
336 }
337 /* Apply generic fixups */
338 cfi_fixup(mtd, fixup_table);
339
340 for (i=0; i< cfi->numchips; i++) {
341 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
342 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
343 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
344 }
345
346 map->fldrv = &cfi_amdstd_chipdrv;
347
348 return cfi_amdstd_setup(mtd);
349 }
350 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
351
352 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
353 {
354 struct map_info *map = mtd->priv;
355 struct cfi_private *cfi = map->fldrv_priv;
356 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
357 unsigned long offset = 0;
358 int i,j;
359
360 printk(KERN_NOTICE "number of %s chips: %d\n",
361 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
362 /* Select the correct geometry setup */
363 mtd->size = devsize * cfi->numchips;
364
365 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
366 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
367 * mtd->numeraseregions, GFP_KERNEL);
368 if (!mtd->eraseregions) {
369 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
370 goto setup_err;
371 }
372
373 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
374 unsigned long ernum, ersize;
375 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
376 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
377
378 if (mtd->erasesize < ersize) {
379 mtd->erasesize = ersize;
380 }
381 for (j=0; j<cfi->numchips; j++) {
382 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
383 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
384 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
385 }
386 offset += (ersize * ernum);
387 }
388 if (offset != devsize) {
389 /* Argh */
390 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
391 goto setup_err;
392 }
393 #if 0
394 // debug
395 for (i=0; i<mtd->numeraseregions;i++){
396 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
397 i,mtd->eraseregions[i].offset,
398 mtd->eraseregions[i].erasesize,
399 mtd->eraseregions[i].numblocks);
400 }
401 #endif
402
403 /* FIXME: erase-suspend-program is broken. See
404 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
405 printk(KERN_NOTICE "cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
406
407 __module_get(THIS_MODULE);
408 return mtd;
409
410 setup_err:
411 if(mtd) {
412 kfree(mtd->eraseregions);
413 kfree(mtd);
414 }
415 kfree(cfi->cmdset_priv);
416 kfree(cfi->cfiq);
417 return NULL;
418 }
419
420 /*
421 * Return true if the chip is ready.
422 *
423 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
424 * non-suspended sector) and is indicated by no toggle bits toggling.
425 *
426 * Note that anything more complicated than checking if no bits are toggling
427 * (including checking DQ5 for an error status) is tricky to get working
428 * correctly and is therefore not done (particulary with interleaved chips
429 * as each chip must be checked independantly of the others).
430 */
431 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
432 {
433 map_word d, t;
434
435 d = map_read(map, addr);
436 t = map_read(map, addr);
437
438 return map_word_equal(map, d, t);
439 }
440
441 /*
442 * Return true if the chip is ready and has the correct value.
443 *
444 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
445 * non-suspended sector) and it is indicated by no bits toggling.
446 *
447 * Error are indicated by toggling bits or bits held with the wrong value,
448 * or with bits toggling.
449 *
450 * Note that anything more complicated than checking if no bits are toggling
451 * (including checking DQ5 for an error status) is tricky to get working
452 * correctly and is therefore not done (particulary with interleaved chips
453 * as each chip must be checked independantly of the others).
454 *
455 */
456 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
457 {
458 map_word oldd, curd;
459
460 oldd = map_read(map, addr);
461 curd = map_read(map, addr);
462
463 return map_word_equal(map, oldd, curd) &&
464 map_word_equal(map, curd, expected);
465 }
466
467 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
468 {
469 DECLARE_WAITQUEUE(wait, current);
470 struct cfi_private *cfi = map->fldrv_priv;
471 unsigned long timeo;
472 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
473
474 resettime:
475 timeo = jiffies + HZ;
476 retry:
477 switch (chip->state) {
478
479 case FL_STATUS:
480 for (;;) {
481 if (chip_ready(map, adr))
482 break;
483
484 if (time_after(jiffies, timeo)) {
485 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
486 spin_unlock(chip->mutex);
487 return -EIO;
488 }
489 spin_unlock(chip->mutex);
490 cfi_udelay(1);
491 spin_lock(chip->mutex);
492 /* Someone else might have been playing with it. */
493 goto retry;
494 }
495
496 case FL_READY:
497 case FL_CFI_QUERY:
498 case FL_JEDEC_QUERY:
499 return 0;
500
501 case FL_ERASING:
502 if (mode == FL_WRITING) /* FIXME: Erase-suspend-program appears broken. */
503 goto sleep;
504
505 if (!(mode == FL_READY || mode == FL_POINT
506 || !cfip
507 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))
508 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x1))))
509 goto sleep;
510
511 /* We could check to see if we're trying to access the sector
512 * that is currently being erased. However, no user will try
513 * anything like that so we just wait for the timeout. */
514
515 /* Erase suspend */
516 /* It's harmless to issue the Erase-Suspend and Erase-Resume
517 * commands when the erase algorithm isn't in progress. */
518 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
519 chip->oldstate = FL_ERASING;
520 chip->state = FL_ERASE_SUSPENDING;
521 chip->erase_suspended = 1;
522 for (;;) {
523 if (chip_ready(map, adr))
524 break;
525
526 if (time_after(jiffies, timeo)) {
527 /* Should have suspended the erase by now.
528 * Send an Erase-Resume command as either
529 * there was an error (so leave the erase
530 * routine to recover from it) or we trying to
531 * use the erase-in-progress sector. */
532 map_write(map, CMD(0x30), chip->in_progress_block_addr);
533 chip->state = FL_ERASING;
534 chip->oldstate = FL_READY;
535 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
536 return -EIO;
537 }
538
539 spin_unlock(chip->mutex);
540 cfi_udelay(1);
541 spin_lock(chip->mutex);
542 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
543 So we can just loop here. */
544 }
545 chip->state = FL_READY;
546 return 0;
547
548 case FL_XIP_WHILE_ERASING:
549 if (mode != FL_READY && mode != FL_POINT &&
550 (!cfip || !(cfip->EraseSuspend&2)))
551 goto sleep;
552 chip->oldstate = chip->state;
553 chip->state = FL_READY;
554 return 0;
555
556 case FL_POINT:
557 /* Only if there's no operation suspended... */
558 if (mode == FL_READY && chip->oldstate == FL_READY)
559 return 0;
560
561 default:
562 sleep:
563 set_current_state(TASK_UNINTERRUPTIBLE);
564 add_wait_queue(&chip->wq, &wait);
565 spin_unlock(chip->mutex);
566 schedule();
567 remove_wait_queue(&chip->wq, &wait);
568 spin_lock(chip->mutex);
569 goto resettime;
570 }
571 }
572
573
574 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
575 {
576 struct cfi_private *cfi = map->fldrv_priv;
577
578 switch(chip->oldstate) {
579 case FL_ERASING:
580 chip->state = chip->oldstate;
581 map_write(map, CMD(0x30), chip->in_progress_block_addr);
582 chip->oldstate = FL_READY;
583 chip->state = FL_ERASING;
584 break;
585
586 case FL_XIP_WHILE_ERASING:
587 chip->state = chip->oldstate;
588 chip->oldstate = FL_READY;
589 break;
590
591 case FL_READY:
592 case FL_STATUS:
593 /* We should really make set_vpp() count, rather than doing this */
594 DISABLE_VPP(map);
595 break;
596 default:
597 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
598 }
599 wake_up(&chip->wq);
600 }
601
602 #ifdef CONFIG_MTD_XIP
603
604 /*
605 * No interrupt what so ever can be serviced while the flash isn't in array
606 * mode. This is ensured by the xip_disable() and xip_enable() functions
607 * enclosing any code path where the flash is known not to be in array mode.
608 * And within a XIP disabled code path, only functions marked with __xipram
609 * may be called and nothing else (it's a good thing to inspect generated
610 * assembly to make sure inline functions were actually inlined and that gcc
611 * didn't emit calls to its own support functions). Also configuring MTD CFI
612 * support to a single buswidth and a single interleave is also recommended.
613 */
614
615 static void xip_disable(struct map_info *map, struct flchip *chip,
616 unsigned long adr)
617 {
618 /* TODO: chips with no XIP use should ignore and return */
619 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
620 local_irq_disable();
621 }
622
623 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
624 unsigned long adr)
625 {
626 struct cfi_private *cfi = map->fldrv_priv;
627
628 if (chip->state != FL_POINT && chip->state != FL_READY) {
629 map_write(map, CMD(0xf0), adr);
630 chip->state = FL_READY;
631 }
632 (void) map_read(map, adr);
633 xip_iprefetch();
634 local_irq_enable();
635 }
636
637 /*
638 * When a delay is required for the flash operation to complete, the
639 * xip_udelay() function is polling for both the given timeout and pending
640 * (but still masked) hardware interrupts. Whenever there is an interrupt
641 * pending then the flash erase operation is suspended, array mode restored
642 * and interrupts unmasked. Task scheduling might also happen at that
643 * point. The CPU eventually returns from the interrupt or the call to
644 * schedule() and the suspended flash operation is resumed for the remaining
645 * of the delay period.
646 *
647 * Warning: this function _will_ fool interrupt latency tracing tools.
648 */
649
650 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
651 unsigned long adr, int usec)
652 {
653 struct cfi_private *cfi = map->fldrv_priv;
654 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
655 map_word status, OK = CMD(0x80);
656 unsigned long suspended, start = xip_currtime();
657 flstate_t oldstate;
658
659 do {
660 cpu_relax();
661 if (xip_irqpending() && extp &&
662 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
663 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
664 /*
665 * Let's suspend the erase operation when supported.
666 * Note that we currently don't try to suspend
667 * interleaved chips if there is already another
668 * operation suspended (imagine what happens
669 * when one chip was already done with the current
670 * operation while another chip suspended it, then
671 * we resume the whole thing at once). Yes, it
672 * can happen!
673 */
674 map_write(map, CMD(0xb0), adr);
675 usec -= xip_elapsed_since(start);
676 suspended = xip_currtime();
677 do {
678 if (xip_elapsed_since(suspended) > 100000) {
679 /*
680 * The chip doesn't want to suspend
681 * after waiting for 100 msecs.
682 * This is a critical error but there
683 * is not much we can do here.
684 */
685 return;
686 }
687 status = map_read(map, adr);
688 } while (!map_word_andequal(map, status, OK, OK));
689
690 /* Suspend succeeded */
691 oldstate = chip->state;
692 if (!map_word_bitsset(map, status, CMD(0x40)))
693 break;
694 chip->state = FL_XIP_WHILE_ERASING;
695 chip->erase_suspended = 1;
696 map_write(map, CMD(0xf0), adr);
697 (void) map_read(map, adr);
698 asm volatile (".rep 8; nop; .endr");
699 local_irq_enable();
700 spin_unlock(chip->mutex);
701 asm volatile (".rep 8; nop; .endr");
702 cond_resched();
703
704 /*
705 * We're back. However someone else might have
706 * decided to go write to the chip if we are in
707 * a suspended erase state. If so let's wait
708 * until it's done.
709 */
710 spin_lock(chip->mutex);
711 while (chip->state != FL_XIP_WHILE_ERASING) {
712 DECLARE_WAITQUEUE(wait, current);
713 set_current_state(TASK_UNINTERRUPTIBLE);
714 add_wait_queue(&chip->wq, &wait);
715 spin_unlock(chip->mutex);
716 schedule();
717 remove_wait_queue(&chip->wq, &wait);
718 spin_lock(chip->mutex);
719 }
720 /* Disallow XIP again */
721 local_irq_disable();
722
723 /* Resume the write or erase operation */
724 map_write(map, CMD(0x30), adr);
725 chip->state = oldstate;
726 start = xip_currtime();
727 } else if (usec >= 1000000/HZ) {
728 /*
729 * Try to save on CPU power when waiting delay
730 * is at least a system timer tick period.
731 * No need to be extremely accurate here.
732 */
733 xip_cpu_idle();
734 }
735 status = map_read(map, adr);
736 } while (!map_word_andequal(map, status, OK, OK)
737 && xip_elapsed_since(start) < usec);
738 }
739
740 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
741
742 /*
743 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
744 * the flash is actively programming or erasing since we have to poll for
745 * the operation to complete anyway. We can't do that in a generic way with
746 * a XIP setup so do it before the actual flash operation in this case
747 * and stub it out from INVALIDATE_CACHE_UDELAY.
748 */
749 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
750 INVALIDATE_CACHED_RANGE(map, from, size)
751
752 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
753 UDELAY(map, chip, adr, usec)
754
755 /*
756 * Extra notes:
757 *
758 * Activating this XIP support changes the way the code works a bit. For
759 * example the code to suspend the current process when concurrent access
760 * happens is never executed because xip_udelay() will always return with the
761 * same chip state as it was entered with. This is why there is no care for
762 * the presence of add_wait_queue() or schedule() calls from within a couple
763 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
764 * The queueing and scheduling are always happening within xip_udelay().
765 *
766 * Similarly, get_chip() and put_chip() just happen to always be executed
767 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
768 * is in array mode, therefore never executing many cases therein and not
769 * causing any problem with XIP.
770 */
771
772 #else
773
774 #define xip_disable(map, chip, adr)
775 #define xip_enable(map, chip, adr)
776 #define XIP_INVAL_CACHED_RANGE(x...)
777
778 #define UDELAY(map, chip, adr, usec) \
779 do { \
780 spin_unlock(chip->mutex); \
781 cfi_udelay(usec); \
782 spin_lock(chip->mutex); \
783 } while (0)
784
785 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
786 do { \
787 spin_unlock(chip->mutex); \
788 INVALIDATE_CACHED_RANGE(map, adr, len); \
789 cfi_udelay(usec); \
790 spin_lock(chip->mutex); \
791 } while (0)
792
793 #endif
794
795 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
796 {
797 unsigned long cmd_addr;
798 struct cfi_private *cfi = map->fldrv_priv;
799 int ret;
800
801 adr += chip->start;
802
803 /* Ensure cmd read/writes are aligned. */
804 cmd_addr = adr & ~(map_bankwidth(map)-1);
805
806 spin_lock(chip->mutex);
807 ret = get_chip(map, chip, cmd_addr, FL_READY);
808 if (ret) {
809 spin_unlock(chip->mutex);
810 return ret;
811 }
812
813 if (chip->state != FL_POINT && chip->state != FL_READY) {
814 map_write(map, CMD(0xf0), cmd_addr);
815 chip->state = FL_READY;
816 }
817
818 map_copy_from(map, buf, adr, len);
819
820 put_chip(map, chip, cmd_addr);
821
822 spin_unlock(chip->mutex);
823 return 0;
824 }
825
826
827 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
828 {
829 struct map_info *map = mtd->priv;
830 struct cfi_private *cfi = map->fldrv_priv;
831 unsigned long ofs;
832 int chipnum;
833 int ret = 0;
834
835 /* ofs: offset within the first chip that the first read should start */
836
837 chipnum = (from >> cfi->chipshift);
838 ofs = from - (chipnum << cfi->chipshift);
839
840
841 *retlen = 0;
842
843 while (len) {
844 unsigned long thislen;
845
846 if (chipnum >= cfi->numchips)
847 break;
848
849 if ((len + ofs -1) >> cfi->chipshift)
850 thislen = (1<<cfi->chipshift) - ofs;
851 else
852 thislen = len;
853
854 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
855 if (ret)
856 break;
857
858 *retlen += thislen;
859 len -= thislen;
860 buf += thislen;
861
862 ofs = 0;
863 chipnum++;
864 }
865 return ret;
866 }
867
868
869 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
870 {
871 DECLARE_WAITQUEUE(wait, current);
872 unsigned long timeo = jiffies + HZ;
873 struct cfi_private *cfi = map->fldrv_priv;
874
875 retry:
876 spin_lock(chip->mutex);
877
878 if (chip->state != FL_READY){
879 #if 0
880 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
881 #endif
882 set_current_state(TASK_UNINTERRUPTIBLE);
883 add_wait_queue(&chip->wq, &wait);
884
885 spin_unlock(chip->mutex);
886
887 schedule();
888 remove_wait_queue(&chip->wq, &wait);
889 #if 0
890 if(signal_pending(current))
891 return -EINTR;
892 #endif
893 timeo = jiffies + HZ;
894
895 goto retry;
896 }
897
898 adr += chip->start;
899
900 chip->state = FL_READY;
901
902 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
903 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
904 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
905
906 map_copy_from(map, buf, adr, len);
907
908 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
909 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
910 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
911 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
912
913 wake_up(&chip->wq);
914 spin_unlock(chip->mutex);
915
916 return 0;
917 }
918
919 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
920 {
921 struct map_info *map = mtd->priv;
922 struct cfi_private *cfi = map->fldrv_priv;
923 unsigned long ofs;
924 int chipnum;
925 int ret = 0;
926
927
928 /* ofs: offset within the first chip that the first read should start */
929
930 /* 8 secsi bytes per chip */
931 chipnum=from>>3;
932 ofs=from & 7;
933
934
935 *retlen = 0;
936
937 while (len) {
938 unsigned long thislen;
939
940 if (chipnum >= cfi->numchips)
941 break;
942
943 if ((len + ofs -1) >> 3)
944 thislen = (1<<3) - ofs;
945 else
946 thislen = len;
947
948 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
949 if (ret)
950 break;
951
952 *retlen += thislen;
953 len -= thislen;
954 buf += thislen;
955
956 ofs = 0;
957 chipnum++;
958 }
959 return ret;
960 }
961
962
963 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
964 {
965 struct cfi_private *cfi = map->fldrv_priv;
966 unsigned long timeo = jiffies + HZ;
967 /*
968 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
969 * have a max write time of a few hundreds usec). However, we should
970 * use the maximum timeout value given by the chip at probe time
971 * instead. Unfortunately, struct flchip does have a field for
972 * maximum timeout, only for typical which can be far too short
973 * depending of the conditions. The ' + 1' is to avoid having a
974 * timeout of 0 jiffies if HZ is smaller than 1000.
975 */
976 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
977 int ret = 0;
978 map_word oldd;
979 int retry_cnt = 0;
980
981 adr += chip->start;
982
983 spin_lock(chip->mutex);
984 ret = get_chip(map, chip, adr, FL_WRITING);
985 if (ret) {
986 spin_unlock(chip->mutex);
987 return ret;
988 }
989
990 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
991 __func__, adr, datum.x[0] );
992
993 /*
994 * Check for a NOP for the case when the datum to write is already
995 * present - it saves time and works around buggy chips that corrupt
996 * data at other locations when 0xff is written to a location that
997 * already contains 0xff.
998 */
999 oldd = map_read(map, adr);
1000 if (map_word_equal(map, oldd, datum)) {
1001 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1002 __func__);
1003 goto op_done;
1004 }
1005
1006 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1007 ENABLE_VPP(map);
1008 xip_disable(map, chip, adr);
1009 retry:
1010 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1011 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1012 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1013 map_write(map, datum, adr);
1014 chip->state = FL_WRITING;
1015
1016 INVALIDATE_CACHE_UDELAY(map, chip,
1017 adr, map_bankwidth(map),
1018 chip->word_write_time);
1019
1020 /* See comment above for timeout value. */
1021 timeo = jiffies + uWriteTimeout;
1022 for (;;) {
1023 if (chip->state != FL_WRITING) {
1024 /* Someone's suspended the write. Sleep */
1025 DECLARE_WAITQUEUE(wait, current);
1026
1027 set_current_state(TASK_UNINTERRUPTIBLE);
1028 add_wait_queue(&chip->wq, &wait);
1029 spin_unlock(chip->mutex);
1030 schedule();
1031 remove_wait_queue(&chip->wq, &wait);
1032 timeo = jiffies + (HZ / 2); /* FIXME */
1033 spin_lock(chip->mutex);
1034 continue;
1035 }
1036
1037 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1038 xip_enable(map, chip, adr);
1039 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1040 xip_disable(map, chip, adr);
1041 break;
1042 }
1043
1044 if (chip_ready(map, adr))
1045 break;
1046
1047 /* Latency issues. Drop the lock, wait a while and retry */
1048 UDELAY(map, chip, adr, 1);
1049 }
1050 /* Did we succeed? */
1051 if (!chip_good(map, adr, datum)) {
1052 /* reset on all failures. */
1053 map_write( map, CMD(0xF0), chip->start );
1054 /* FIXME - should have reset delay before continuing */
1055
1056 if (++retry_cnt <= MAX_WORD_RETRIES)
1057 goto retry;
1058
1059 ret = -EIO;
1060 }
1061 xip_enable(map, chip, adr);
1062 op_done:
1063 chip->state = FL_READY;
1064 put_chip(map, chip, adr);
1065 spin_unlock(chip->mutex);
1066
1067 return ret;
1068 }
1069
1070
1071 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1072 size_t *retlen, const u_char *buf)
1073 {
1074 struct map_info *map = mtd->priv;
1075 struct cfi_private *cfi = map->fldrv_priv;
1076 int ret = 0;
1077 int chipnum;
1078 unsigned long ofs, chipstart;
1079 DECLARE_WAITQUEUE(wait, current);
1080
1081 *retlen = 0;
1082 if (!len)
1083 return 0;
1084
1085 chipnum = to >> cfi->chipshift;
1086 ofs = to - (chipnum << cfi->chipshift);
1087 chipstart = cfi->chips[chipnum].start;
1088
1089 /* If it's not bus-aligned, do the first byte write */
1090 if (ofs & (map_bankwidth(map)-1)) {
1091 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1092 int i = ofs - bus_ofs;
1093 int n = 0;
1094 map_word tmp_buf;
1095
1096 retry:
1097 spin_lock(cfi->chips[chipnum].mutex);
1098
1099 if (cfi->chips[chipnum].state != FL_READY) {
1100 #if 0
1101 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1102 #endif
1103 set_current_state(TASK_UNINTERRUPTIBLE);
1104 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1105
1106 spin_unlock(cfi->chips[chipnum].mutex);
1107
1108 schedule();
1109 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1110 #if 0
1111 if(signal_pending(current))
1112 return -EINTR;
1113 #endif
1114 goto retry;
1115 }
1116
1117 /* Load 'tmp_buf' with old contents of flash */
1118 tmp_buf = map_read(map, bus_ofs+chipstart);
1119
1120 spin_unlock(cfi->chips[chipnum].mutex);
1121
1122 /* Number of bytes to copy from buffer */
1123 n = min_t(int, len, map_bankwidth(map)-i);
1124
1125 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1126
1127 ret = do_write_oneword(map, &cfi->chips[chipnum],
1128 bus_ofs, tmp_buf);
1129 if (ret)
1130 return ret;
1131
1132 ofs += n;
1133 buf += n;
1134 (*retlen) += n;
1135 len -= n;
1136
1137 if (ofs >> cfi->chipshift) {
1138 chipnum ++;
1139 ofs = 0;
1140 if (chipnum == cfi->numchips)
1141 return 0;
1142 }
1143 }
1144
1145 /* We are now aligned, write as much as possible */
1146 while(len >= map_bankwidth(map)) {
1147 map_word datum;
1148
1149 datum = map_word_load(map, buf);
1150
1151 ret = do_write_oneword(map, &cfi->chips[chipnum],
1152 ofs, datum);
1153 if (ret)
1154 return ret;
1155
1156 ofs += map_bankwidth(map);
1157 buf += map_bankwidth(map);
1158 (*retlen) += map_bankwidth(map);
1159 len -= map_bankwidth(map);
1160
1161 if (ofs >> cfi->chipshift) {
1162 chipnum ++;
1163 ofs = 0;
1164 if (chipnum == cfi->numchips)
1165 return 0;
1166 chipstart = cfi->chips[chipnum].start;
1167 }
1168 }
1169
1170 /* Write the trailing bytes if any */
1171 if (len & (map_bankwidth(map)-1)) {
1172 map_word tmp_buf;
1173
1174 retry1:
1175 spin_lock(cfi->chips[chipnum].mutex);
1176
1177 if (cfi->chips[chipnum].state != FL_READY) {
1178 #if 0
1179 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1180 #endif
1181 set_current_state(TASK_UNINTERRUPTIBLE);
1182 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1183
1184 spin_unlock(cfi->chips[chipnum].mutex);
1185
1186 schedule();
1187 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1188 #if 0
1189 if(signal_pending(current))
1190 return -EINTR;
1191 #endif
1192 goto retry1;
1193 }
1194
1195 tmp_buf = map_read(map, ofs + chipstart);
1196
1197 spin_unlock(cfi->chips[chipnum].mutex);
1198
1199 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1200
1201 ret = do_write_oneword(map, &cfi->chips[chipnum],
1202 ofs, tmp_buf);
1203 if (ret)
1204 return ret;
1205
1206 (*retlen) += len;
1207 }
1208
1209 return 0;
1210 }
1211
1212
1213 /*
1214 * FIXME: interleaved mode not tested, and probably not supported!
1215 */
1216 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1217 unsigned long adr, const u_char *buf,
1218 int len)
1219 {
1220 struct cfi_private *cfi = map->fldrv_priv;
1221 unsigned long timeo = jiffies + HZ;
1222 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1223 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1224 int ret = -EIO;
1225 unsigned long cmd_adr;
1226 int z, words;
1227 map_word datum;
1228
1229 adr += chip->start;
1230 cmd_adr = adr;
1231
1232 spin_lock(chip->mutex);
1233 ret = get_chip(map, chip, adr, FL_WRITING);
1234 if (ret) {
1235 spin_unlock(chip->mutex);
1236 return ret;
1237 }
1238
1239 datum = map_word_load(map, buf);
1240
1241 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1242 __func__, adr, datum.x[0] );
1243
1244 XIP_INVAL_CACHED_RANGE(map, adr, len);
1245 ENABLE_VPP(map);
1246 xip_disable(map, chip, cmd_adr);
1247
1248 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1249 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1250 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1251
1252 /* Write Buffer Load */
1253 map_write(map, CMD(0x25), cmd_adr);
1254
1255 chip->state = FL_WRITING_TO_BUFFER;
1256
1257 /* Write length of data to come */
1258 words = len / map_bankwidth(map);
1259 map_write(map, CMD(words - 1), cmd_adr);
1260 /* Write data */
1261 z = 0;
1262 while(z < words * map_bankwidth(map)) {
1263 datum = map_word_load(map, buf);
1264 map_write(map, datum, adr + z);
1265
1266 z += map_bankwidth(map);
1267 buf += map_bankwidth(map);
1268 }
1269 z -= map_bankwidth(map);
1270
1271 adr += z;
1272
1273 /* Write Buffer Program Confirm: GO GO GO */
1274 map_write(map, CMD(0x29), cmd_adr);
1275 chip->state = FL_WRITING;
1276
1277 INVALIDATE_CACHE_UDELAY(map, chip,
1278 adr, map_bankwidth(map),
1279 chip->word_write_time);
1280
1281 timeo = jiffies + uWriteTimeout;
1282
1283 for (;;) {
1284 if (chip->state != FL_WRITING) {
1285 /* Someone's suspended the write. Sleep */
1286 DECLARE_WAITQUEUE(wait, current);
1287
1288 set_current_state(TASK_UNINTERRUPTIBLE);
1289 add_wait_queue(&chip->wq, &wait);
1290 spin_unlock(chip->mutex);
1291 schedule();
1292 remove_wait_queue(&chip->wq, &wait);
1293 timeo = jiffies + (HZ / 2); /* FIXME */
1294 spin_lock(chip->mutex);
1295 continue;
1296 }
1297
1298 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1299 break;
1300
1301 if (chip_ready(map, adr)) {
1302 xip_enable(map, chip, adr);
1303 goto op_done;
1304 }
1305
1306 /* Latency issues. Drop the lock, wait a while and retry */
1307 UDELAY(map, chip, adr, 1);
1308 }
1309
1310 /* reset on all failures. */
1311 map_write( map, CMD(0xF0), chip->start );
1312 xip_enable(map, chip, adr);
1313 /* FIXME - should have reset delay before continuing */
1314
1315 printk(KERN_WARNING "MTD %s(): software timeout\n",
1316 __func__ );
1317
1318 ret = -EIO;
1319 op_done:
1320 chip->state = FL_READY;
1321 put_chip(map, chip, adr);
1322 spin_unlock(chip->mutex);
1323
1324 return ret;
1325 }
1326
1327
1328 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1329 size_t *retlen, const u_char *buf)
1330 {
1331 struct map_info *map = mtd->priv;
1332 struct cfi_private *cfi = map->fldrv_priv;
1333 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1334 int ret = 0;
1335 int chipnum;
1336 unsigned long ofs;
1337
1338 *retlen = 0;
1339 if (!len)
1340 return 0;
1341
1342 chipnum = to >> cfi->chipshift;
1343 ofs = to - (chipnum << cfi->chipshift);
1344
1345 /* If it's not bus-aligned, do the first word write */
1346 if (ofs & (map_bankwidth(map)-1)) {
1347 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1348 if (local_len > len)
1349 local_len = len;
1350 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1351 local_len, retlen, buf);
1352 if (ret)
1353 return ret;
1354 ofs += local_len;
1355 buf += local_len;
1356 len -= local_len;
1357
1358 if (ofs >> cfi->chipshift) {
1359 chipnum ++;
1360 ofs = 0;
1361 if (chipnum == cfi->numchips)
1362 return 0;
1363 }
1364 }
1365
1366 /* Write buffer is worth it only if more than one word to write... */
1367 while (len >= map_bankwidth(map) * 2) {
1368 /* We must not cross write block boundaries */
1369 int size = wbufsize - (ofs & (wbufsize-1));
1370
1371 if (size > len)
1372 size = len;
1373 if (size % map_bankwidth(map))
1374 size -= size % map_bankwidth(map);
1375
1376 ret = do_write_buffer(map, &cfi->chips[chipnum],
1377 ofs, buf, size);
1378 if (ret)
1379 return ret;
1380
1381 ofs += size;
1382 buf += size;
1383 (*retlen) += size;
1384 len -= size;
1385
1386 if (ofs >> cfi->chipshift) {
1387 chipnum ++;
1388 ofs = 0;
1389 if (chipnum == cfi->numchips)
1390 return 0;
1391 }
1392 }
1393
1394 if (len) {
1395 size_t retlen_dregs = 0;
1396
1397 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1398 len, &retlen_dregs, buf);
1399
1400 *retlen += retlen_dregs;
1401 return ret;
1402 }
1403
1404 return 0;
1405 }
1406
1407
1408 /*
1409 * Handle devices with one erase region, that only implement
1410 * the chip erase command.
1411 */
1412 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1413 {
1414 struct cfi_private *cfi = map->fldrv_priv;
1415 unsigned long timeo = jiffies + HZ;
1416 unsigned long int adr;
1417 DECLARE_WAITQUEUE(wait, current);
1418 int ret = 0;
1419
1420 adr = cfi->addr_unlock1;
1421
1422 spin_lock(chip->mutex);
1423 ret = get_chip(map, chip, adr, FL_WRITING);
1424 if (ret) {
1425 spin_unlock(chip->mutex);
1426 return ret;
1427 }
1428
1429 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1430 __func__, chip->start );
1431
1432 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1433 ENABLE_VPP(map);
1434 xip_disable(map, chip, adr);
1435
1436 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1437 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1438 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1439 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1440 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1441 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1442
1443 chip->state = FL_ERASING;
1444 chip->erase_suspended = 0;
1445 chip->in_progress_block_addr = adr;
1446
1447 INVALIDATE_CACHE_UDELAY(map, chip,
1448 adr, map->size,
1449 chip->erase_time*500);
1450
1451 timeo = jiffies + (HZ*20);
1452
1453 for (;;) {
1454 if (chip->state != FL_ERASING) {
1455 /* Someone's suspended the erase. Sleep */
1456 set_current_state(TASK_UNINTERRUPTIBLE);
1457 add_wait_queue(&chip->wq, &wait);
1458 spin_unlock(chip->mutex);
1459 schedule();
1460 remove_wait_queue(&chip->wq, &wait);
1461 spin_lock(chip->mutex);
1462 continue;
1463 }
1464 if (chip->erase_suspended) {
1465 /* This erase was suspended and resumed.
1466 Adjust the timeout */
1467 timeo = jiffies + (HZ*20); /* FIXME */
1468 chip->erase_suspended = 0;
1469 }
1470
1471 if (chip_ready(map, adr))
1472 break;
1473
1474 if (time_after(jiffies, timeo)) {
1475 printk(KERN_WARNING "MTD %s(): software timeout\n",
1476 __func__ );
1477 break;
1478 }
1479
1480 /* Latency issues. Drop the lock, wait a while and retry */
1481 UDELAY(map, chip, adr, 1000000/HZ);
1482 }
1483 /* Did we succeed? */
1484 if (!chip_good(map, adr, map_word_ff(map))) {
1485 /* reset on all failures. */
1486 map_write( map, CMD(0xF0), chip->start );
1487 /* FIXME - should have reset delay before continuing */
1488
1489 ret = -EIO;
1490 }
1491
1492 chip->state = FL_READY;
1493 xip_enable(map, chip, adr);
1494 put_chip(map, chip, adr);
1495 spin_unlock(chip->mutex);
1496
1497 return ret;
1498 }
1499
1500
1501 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1502 {
1503 struct cfi_private *cfi = map->fldrv_priv;
1504 unsigned long timeo = jiffies + HZ;
1505 DECLARE_WAITQUEUE(wait, current);
1506 int ret = 0;
1507
1508 adr += chip->start;
1509
1510 spin_lock(chip->mutex);
1511 ret = get_chip(map, chip, adr, FL_ERASING);
1512 if (ret) {
1513 spin_unlock(chip->mutex);
1514 return ret;
1515 }
1516
1517 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1518 __func__, adr );
1519
1520 XIP_INVAL_CACHED_RANGE(map, adr, len);
1521 ENABLE_VPP(map);
1522 xip_disable(map, chip, adr);
1523
1524 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1525 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1526 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1527 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1528 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1529 map_write(map, CMD(0x30), adr);
1530
1531 chip->state = FL_ERASING;
1532 chip->erase_suspended = 0;
1533 chip->in_progress_block_addr = adr;
1534
1535 INVALIDATE_CACHE_UDELAY(map, chip,
1536 adr, len,
1537 chip->erase_time*500);
1538
1539 timeo = jiffies + (HZ*20);
1540
1541 for (;;) {
1542 if (chip->state != FL_ERASING) {
1543 /* Someone's suspended the erase. Sleep */
1544 set_current_state(TASK_UNINTERRUPTIBLE);
1545 add_wait_queue(&chip->wq, &wait);
1546 spin_unlock(chip->mutex);
1547 schedule();
1548 remove_wait_queue(&chip->wq, &wait);
1549 spin_lock(chip->mutex);
1550 continue;
1551 }
1552 if (chip->erase_suspended) {
1553 /* This erase was suspended and resumed.
1554 Adjust the timeout */
1555 timeo = jiffies + (HZ*20); /* FIXME */
1556 chip->erase_suspended = 0;
1557 }
1558
1559 if (chip_ready(map, adr)) {
1560 xip_enable(map, chip, adr);
1561 break;
1562 }
1563
1564 if (time_after(jiffies, timeo)) {
1565 xip_enable(map, chip, adr);
1566 printk(KERN_WARNING "MTD %s(): software timeout\n",
1567 __func__ );
1568 break;
1569 }
1570
1571 /* Latency issues. Drop the lock, wait a while and retry */
1572 UDELAY(map, chip, adr, 1000000/HZ);
1573 }
1574 /* Did we succeed? */
1575 if (!chip_good(map, adr, map_word_ff(map))) {
1576 /* reset on all failures. */
1577 map_write( map, CMD(0xF0), chip->start );
1578 /* FIXME - should have reset delay before continuing */
1579
1580 ret = -EIO;
1581 }
1582
1583 chip->state = FL_READY;
1584 put_chip(map, chip, adr);
1585 spin_unlock(chip->mutex);
1586 return ret;
1587 }
1588
1589
1590 int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1591 {
1592 unsigned long ofs, len;
1593 int ret;
1594
1595 ofs = instr->addr;
1596 len = instr->len;
1597
1598 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1599 if (ret)
1600 return ret;
1601
1602 instr->state = MTD_ERASE_DONE;
1603 mtd_erase_callback(instr);
1604
1605 return 0;
1606 }
1607
1608
1609 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1610 {
1611 struct map_info *map = mtd->priv;
1612 struct cfi_private *cfi = map->fldrv_priv;
1613 int ret = 0;
1614
1615 if (instr->addr != 0)
1616 return -EINVAL;
1617
1618 if (instr->len != mtd->size)
1619 return -EINVAL;
1620
1621 ret = do_erase_chip(map, &cfi->chips[0]);
1622 if (ret)
1623 return ret;
1624
1625 instr->state = MTD_ERASE_DONE;
1626 mtd_erase_callback(instr);
1627
1628 return 0;
1629 }
1630
1631
1632 static void cfi_amdstd_sync (struct mtd_info *mtd)
1633 {
1634 struct map_info *map = mtd->priv;
1635 struct cfi_private *cfi = map->fldrv_priv;
1636 int i;
1637 struct flchip *chip;
1638 int ret = 0;
1639 DECLARE_WAITQUEUE(wait, current);
1640
1641 for (i=0; !ret && i<cfi->numchips; i++) {
1642 chip = &cfi->chips[i];
1643
1644 retry:
1645 spin_lock(chip->mutex);
1646
1647 switch(chip->state) {
1648 case FL_READY:
1649 case FL_STATUS:
1650 case FL_CFI_QUERY:
1651 case FL_JEDEC_QUERY:
1652 chip->oldstate = chip->state;
1653 chip->state = FL_SYNCING;
1654 /* No need to wake_up() on this state change -
1655 * as the whole point is that nobody can do anything
1656 * with the chip now anyway.
1657 */
1658 case FL_SYNCING:
1659 spin_unlock(chip->mutex);
1660 break;
1661
1662 default:
1663 /* Not an idle state */
1664 add_wait_queue(&chip->wq, &wait);
1665
1666 spin_unlock(chip->mutex);
1667
1668 schedule();
1669
1670 remove_wait_queue(&chip->wq, &wait);
1671
1672 goto retry;
1673 }
1674 }
1675
1676 /* Unlock the chips again */
1677
1678 for (i--; i >=0; i--) {
1679 chip = &cfi->chips[i];
1680
1681 spin_lock(chip->mutex);
1682
1683 if (chip->state == FL_SYNCING) {
1684 chip->state = chip->oldstate;
1685 wake_up(&chip->wq);
1686 }
1687 spin_unlock(chip->mutex);
1688 }
1689 }
1690
1691
1692 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1693 {
1694 struct map_info *map = mtd->priv;
1695 struct cfi_private *cfi = map->fldrv_priv;
1696 int i;
1697 struct flchip *chip;
1698 int ret = 0;
1699
1700 for (i=0; !ret && i<cfi->numchips; i++) {
1701 chip = &cfi->chips[i];
1702
1703 spin_lock(chip->mutex);
1704
1705 switch(chip->state) {
1706 case FL_READY:
1707 case FL_STATUS:
1708 case FL_CFI_QUERY:
1709 case FL_JEDEC_QUERY:
1710 chip->oldstate = chip->state;
1711 chip->state = FL_PM_SUSPENDED;
1712 /* No need to wake_up() on this state change -
1713 * as the whole point is that nobody can do anything
1714 * with the chip now anyway.
1715 */
1716 case FL_PM_SUSPENDED:
1717 break;
1718
1719 default:
1720 ret = -EAGAIN;
1721 break;
1722 }
1723 spin_unlock(chip->mutex);
1724 }
1725
1726 /* Unlock the chips again */
1727
1728 if (ret) {
1729 for (i--; i >=0; i--) {
1730 chip = &cfi->chips[i];
1731
1732 spin_lock(chip->mutex);
1733
1734 if (chip->state == FL_PM_SUSPENDED) {
1735 chip->state = chip->oldstate;
1736 wake_up(&chip->wq);
1737 }
1738 spin_unlock(chip->mutex);
1739 }
1740 }
1741
1742 return ret;
1743 }
1744
1745
1746 static void cfi_amdstd_resume(struct mtd_info *mtd)
1747 {
1748 struct map_info *map = mtd->priv;
1749 struct cfi_private *cfi = map->fldrv_priv;
1750 int i;
1751 struct flchip *chip;
1752
1753 for (i=0; i<cfi->numchips; i++) {
1754
1755 chip = &cfi->chips[i];
1756
1757 spin_lock(chip->mutex);
1758
1759 if (chip->state == FL_PM_SUSPENDED) {
1760 chip->state = FL_READY;
1761 map_write(map, CMD(0xF0), chip->start);
1762 wake_up(&chip->wq);
1763 }
1764 else
1765 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1766
1767 spin_unlock(chip->mutex);
1768 }
1769 }
1770
1771 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1772 {
1773 struct map_info *map = mtd->priv;
1774 struct cfi_private *cfi = map->fldrv_priv;
1775
1776 kfree(cfi->cmdset_priv);
1777 kfree(cfi->cfiq);
1778 kfree(cfi);
1779 kfree(mtd->eraseregions);
1780 }
1781
1782 MODULE_LICENSE("GPL");
1783 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1784 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
Linux kernel - Deliverables
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