2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
24 #include <linux/config.h>
25 #include <linux/module.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
31 #include <asm/byteorder.h>
33 #include <linux/errno.h>
34 #include <linux/slab.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/mtd/compatmac.h>
38 #include <linux/mtd/map.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/cfi.h>
41 #include <linux/mtd/xip.h>
43 #define AMD_BOOTLOC_BUG
44 #define FORCE_WORD_WRITE 0
46 #define MAX_WORD_RETRIES 3
48 #define MANUFACTURER_AMD 0x0001
49 #define MANUFACTURER_SST 0x00BF
50 #define SST49LF004B 0x0060
51 #define SST49LF008A 0x005a
53 static int cfi_amdstd_read (struct mtd_info
*, loff_t
, size_t, size_t *, u_char
*);
54 static int cfi_amdstd_write_words(struct mtd_info
*, loff_t
, size_t, size_t *, const u_char
*);
55 static int cfi_amdstd_write_buffers(struct mtd_info
*, loff_t
, size_t, size_t *, const u_char
*);
56 static int cfi_amdstd_erase_chip(struct mtd_info
*, struct erase_info
*);
57 static int cfi_amdstd_erase_varsize(struct mtd_info
*, struct erase_info
*);
58 static void cfi_amdstd_sync (struct mtd_info
*);
59 static int cfi_amdstd_suspend (struct mtd_info
*);
60 static void cfi_amdstd_resume (struct mtd_info
*);
61 static int cfi_amdstd_secsi_read (struct mtd_info
*, loff_t
, size_t, size_t *, u_char
*);
63 static void cfi_amdstd_destroy(struct mtd_info
*);
65 struct mtd_info
*cfi_cmdset_0002(struct map_info
*, int);
66 static struct mtd_info
*cfi_amdstd_setup (struct mtd_info
*);
68 static int get_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int mode
);
69 static void put_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
);
72 static struct mtd_chip_driver cfi_amdstd_chipdrv
= {
73 .probe
= NULL
, /* Not usable directly */
74 .destroy
= cfi_amdstd_destroy
,
75 .name
= "cfi_cmdset_0002",
80 /* #define DEBUG_CFI_FEATURES */
83 #ifdef DEBUG_CFI_FEATURES
84 static void cfi_tell_features(struct cfi_pri_amdstd
*extp
)
86 const char* erase_suspend
[3] = {
87 "Not supported", "Read only", "Read/write"
89 const char* top_bottom
[6] = {
90 "No WP", "8x8KiB sectors at top & bottom, no WP",
91 "Bottom boot", "Top boot",
92 "Uniform, Bottom WP", "Uniform, Top WP"
95 printk(" Silicon revision: %d\n", extp
->SiliconRevision
>> 1);
96 printk(" Address sensitive unlock: %s\n",
97 (extp
->SiliconRevision
& 1) ? "Not required" : "Required");
99 if (extp
->EraseSuspend
< ARRAY_SIZE(erase_suspend
))
100 printk(" Erase Suspend: %s\n", erase_suspend
[extp
->EraseSuspend
]);
102 printk(" Erase Suspend: Unknown value %d\n", extp
->EraseSuspend
);
104 if (extp
->BlkProt
== 0)
105 printk(" Block protection: Not supported\n");
107 printk(" Block protection: %d sectors per group\n", extp
->BlkProt
);
110 printk(" Temporary block unprotect: %s\n",
111 extp
->TmpBlkUnprotect
? "Supported" : "Not supported");
112 printk(" Block protect/unprotect scheme: %d\n", extp
->BlkProtUnprot
);
113 printk(" Number of simultaneous operations: %d\n", extp
->SimultaneousOps
);
114 printk(" Burst mode: %s\n",
115 extp
->BurstMode
? "Supported" : "Not supported");
116 if (extp
->PageMode
== 0)
117 printk(" Page mode: Not supported\n");
119 printk(" Page mode: %d word page\n", extp
->PageMode
<< 2);
121 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
122 extp
->VppMin
>> 4, extp
->VppMin
& 0xf);
123 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
124 extp
->VppMax
>> 4, extp
->VppMax
& 0xf);
126 if (extp
->TopBottom
< ARRAY_SIZE(top_bottom
))
127 printk(" Top/Bottom Boot Block: %s\n", top_bottom
[extp
->TopBottom
]);
129 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp
->TopBottom
);
133 #ifdef AMD_BOOTLOC_BUG
134 /* Wheee. Bring me the head of someone at AMD. */
135 static void fixup_amd_bootblock(struct mtd_info
*mtd
, void* param
)
137 struct map_info
*map
= mtd
->priv
;
138 struct cfi_private
*cfi
= map
->fldrv_priv
;
139 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
140 __u8 major
= extp
->MajorVersion
;
141 __u8 minor
= extp
->MinorVersion
;
143 if (((major
<< 8) | minor
) < 0x3131) {
144 /* CFI version 1.0 => don't trust bootloc */
145 if (cfi
->id
& 0x80) {
146 printk(KERN_WARNING
"%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map
->name
, cfi
->id
);
147 extp
->TopBottom
= 3; /* top boot */
149 extp
->TopBottom
= 2; /* bottom boot */
155 static void fixup_use_write_buffers(struct mtd_info
*mtd
, void *param
)
157 struct map_info
*map
= mtd
->priv
;
158 struct cfi_private
*cfi
= map
->fldrv_priv
;
159 if (cfi
->cfiq
->BufWriteTimeoutTyp
) {
160 DEBUG(MTD_DEBUG_LEVEL1
, "Using buffer write method\n" );
161 mtd
->write
= cfi_amdstd_write_buffers
;
165 static void fixup_use_secsi(struct mtd_info
*mtd
, void *param
)
167 /* Setup for chips with a secsi area */
168 mtd
->read_user_prot_reg
= cfi_amdstd_secsi_read
;
169 mtd
->read_fact_prot_reg
= cfi_amdstd_secsi_read
;
172 static void fixup_use_erase_chip(struct mtd_info
*mtd
, void *param
)
174 struct map_info
*map
= mtd
->priv
;
175 struct cfi_private
*cfi
= map
->fldrv_priv
;
176 if ((cfi
->cfiq
->NumEraseRegions
== 1) &&
177 ((cfi
->cfiq
->EraseRegionInfo
[0] & 0xffff) == 0)) {
178 mtd
->erase
= cfi_amdstd_erase_chip
;
183 static struct cfi_fixup cfi_fixup_table
[] = {
184 #ifdef AMD_BOOTLOC_BUG
185 { CFI_MFR_AMD
, CFI_ID_ANY
, fixup_amd_bootblock
, NULL
},
187 { CFI_MFR_AMD
, 0x0050, fixup_use_secsi
, NULL
, },
188 { CFI_MFR_AMD
, 0x0053, fixup_use_secsi
, NULL
, },
189 { CFI_MFR_AMD
, 0x0055, fixup_use_secsi
, NULL
, },
190 { CFI_MFR_AMD
, 0x0056, fixup_use_secsi
, NULL
, },
191 { CFI_MFR_AMD
, 0x005C, fixup_use_secsi
, NULL
, },
192 { CFI_MFR_AMD
, 0x005F, fixup_use_secsi
, NULL
, },
193 #if !FORCE_WORD_WRITE
194 { CFI_MFR_ANY
, CFI_ID_ANY
, fixup_use_write_buffers
, NULL
, },
198 static struct cfi_fixup jedec_fixup_table
[] = {
199 { MANUFACTURER_SST
, SST49LF004B
, fixup_use_fwh_lock
, NULL
, },
200 { MANUFACTURER_SST
, SST49LF008A
, fixup_use_fwh_lock
, NULL
, },
204 static struct cfi_fixup fixup_table
[] = {
205 /* The CFI vendor ids and the JEDEC vendor IDs appear
206 * to be common. It is like the devices id's are as
207 * well. This table is to pick all cases where
208 * we know that is the case.
210 { CFI_MFR_ANY
, CFI_ID_ANY
, fixup_use_erase_chip
, NULL
},
215 struct mtd_info
*cfi_cmdset_0002(struct map_info
*map
, int primary
)
217 struct cfi_private
*cfi
= map
->fldrv_priv
;
218 struct mtd_info
*mtd
;
221 mtd
= kmalloc(sizeof(*mtd
), GFP_KERNEL
);
223 printk(KERN_WARNING
"Failed to allocate memory for MTD device\n");
226 memset(mtd
, 0, sizeof(*mtd
));
228 mtd
->type
= MTD_NORFLASH
;
230 /* Fill in the default mtd operations */
231 mtd
->erase
= cfi_amdstd_erase_varsize
;
232 mtd
->write
= cfi_amdstd_write_words
;
233 mtd
->read
= cfi_amdstd_read
;
234 mtd
->sync
= cfi_amdstd_sync
;
235 mtd
->suspend
= cfi_amdstd_suspend
;
236 mtd
->resume
= cfi_amdstd_resume
;
237 mtd
->flags
= MTD_CAP_NORFLASH
;
238 mtd
->name
= map
->name
;
241 if (cfi
->cfi_mode
==CFI_MODE_CFI
){
242 unsigned char bootloc
;
244 * It's a real CFI chip, not one for which the probe
245 * routine faked a CFI structure. So we read the feature
248 __u16 adr
= primary
?cfi
->cfiq
->P_ADR
:cfi
->cfiq
->A_ADR
;
249 struct cfi_pri_amdstd
*extp
;
251 extp
= (struct cfi_pri_amdstd
*)cfi_read_pri(map
, adr
, sizeof(*extp
), "Amd/Fujitsu");
257 if (extp
->MajorVersion
!= '1' ||
258 (extp
->MinorVersion
< '0' || extp
->MinorVersion
> '4')) {
259 printk(KERN_ERR
" Unknown Amd/Fujitsu Extended Query "
260 "version %c.%c.\n", extp
->MajorVersion
,
267 /* Install our own private info structure */
268 cfi
->cmdset_priv
= extp
;
270 /* Apply cfi device specific fixups */
271 cfi_fixup(mtd
, cfi_fixup_table
);
273 #ifdef DEBUG_CFI_FEATURES
274 /* Tell the user about it in lots of lovely detail */
275 cfi_tell_features(extp
);
278 bootloc
= extp
->TopBottom
;
279 if ((bootloc
!= 2) && (bootloc
!= 3)) {
280 printk(KERN_WARNING
"%s: CFI does not contain boot "
281 "bank location. Assuming top.\n", map
->name
);
285 if (bootloc
== 3 && cfi
->cfiq
->NumEraseRegions
> 1) {
286 printk(KERN_WARNING
"%s: Swapping erase regions for broken CFI table.\n", map
->name
);
288 for (i
=0; i
<cfi
->cfiq
->NumEraseRegions
/ 2; i
++) {
289 int j
= (cfi
->cfiq
->NumEraseRegions
-1)-i
;
292 swap
= cfi
->cfiq
->EraseRegionInfo
[i
];
293 cfi
->cfiq
->EraseRegionInfo
[i
] = cfi
->cfiq
->EraseRegionInfo
[j
];
294 cfi
->cfiq
->EraseRegionInfo
[j
] = swap
;
297 /* Set the default CFI lock/unlock addresses */
298 cfi
->addr_unlock1
= 0x555;
299 cfi
->addr_unlock2
= 0x2aa;
300 /* Modify the unlock address if we are in compatibility mode */
301 if ( /* x16 in x8 mode */
302 ((cfi
->device_type
== CFI_DEVICETYPE_X8
) &&
303 (cfi
->cfiq
->InterfaceDesc
== 2)) ||
304 /* x32 in x16 mode */
305 ((cfi
->device_type
== CFI_DEVICETYPE_X16
) &&
306 (cfi
->cfiq
->InterfaceDesc
== 4)))
308 cfi
->addr_unlock1
= 0xaaa;
309 cfi
->addr_unlock2
= 0x555;
313 else if (cfi
->cfi_mode
== CFI_MODE_JEDEC
) {
314 /* Apply jedec specific fixups */
315 cfi_fixup(mtd
, jedec_fixup_table
);
317 /* Apply generic fixups */
318 cfi_fixup(mtd
, fixup_table
);
320 for (i
=0; i
< cfi
->numchips
; i
++) {
321 cfi
->chips
[i
].word_write_time
= 1<<cfi
->cfiq
->WordWriteTimeoutTyp
;
322 cfi
->chips
[i
].buffer_write_time
= 1<<cfi
->cfiq
->BufWriteTimeoutTyp
;
323 cfi
->chips
[i
].erase_time
= 1<<cfi
->cfiq
->BlockEraseTimeoutTyp
;
326 map
->fldrv
= &cfi_amdstd_chipdrv
;
328 return cfi_amdstd_setup(mtd
);
330 EXPORT_SYMBOL_GPL(cfi_cmdset_0002
);
332 static struct mtd_info
*cfi_amdstd_setup(struct mtd_info
*mtd
)
334 struct map_info
*map
= mtd
->priv
;
335 struct cfi_private
*cfi
= map
->fldrv_priv
;
336 unsigned long devsize
= (1<<cfi
->cfiq
->DevSize
) * cfi
->interleave
;
337 unsigned long offset
= 0;
340 printk(KERN_NOTICE
"number of %s chips: %d\n",
341 (cfi
->cfi_mode
== CFI_MODE_CFI
)?"CFI":"JEDEC",cfi
->numchips
);
342 /* Select the correct geometry setup */
343 mtd
->size
= devsize
* cfi
->numchips
;
345 mtd
->numeraseregions
= cfi
->cfiq
->NumEraseRegions
* cfi
->numchips
;
346 mtd
->eraseregions
= kmalloc(sizeof(struct mtd_erase_region_info
)
347 * mtd
->numeraseregions
, GFP_KERNEL
);
348 if (!mtd
->eraseregions
) {
349 printk(KERN_WARNING
"Failed to allocate memory for MTD erase region info\n");
353 for (i
=0; i
<cfi
->cfiq
->NumEraseRegions
; i
++) {
354 unsigned long ernum
, ersize
;
355 ersize
= ((cfi
->cfiq
->EraseRegionInfo
[i
] >> 8) & ~0xff) * cfi
->interleave
;
356 ernum
= (cfi
->cfiq
->EraseRegionInfo
[i
] & 0xffff) + 1;
358 if (mtd
->erasesize
< ersize
) {
359 mtd
->erasesize
= ersize
;
361 for (j
=0; j
<cfi
->numchips
; j
++) {
362 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].offset
= (j
*devsize
)+offset
;
363 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].erasesize
= ersize
;
364 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].numblocks
= ernum
;
366 offset
+= (ersize
* ernum
);
368 if (offset
!= devsize
) {
370 printk(KERN_WARNING
"Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset
, devsize
);
375 for (i
=0; i
<mtd
->numeraseregions
;i
++){
376 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
377 i
,mtd
->eraseregions
[i
].offset
,
378 mtd
->eraseregions
[i
].erasesize
,
379 mtd
->eraseregions
[i
].numblocks
);
383 /* FIXME: erase-suspend-program is broken. See
384 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
385 printk(KERN_NOTICE
"cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
387 __module_get(THIS_MODULE
);
392 kfree(mtd
->eraseregions
);
395 kfree(cfi
->cmdset_priv
);
401 * Return true if the chip is ready.
403 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
404 * non-suspended sector) and is indicated by no toggle bits toggling.
406 * Note that anything more complicated than checking if no bits are toggling
407 * (including checking DQ5 for an error status) is tricky to get working
408 * correctly and is therefore not done (particulary with interleaved chips
409 * as each chip must be checked independantly of the others).
411 static int __xipram
chip_ready(struct map_info
*map
, unsigned long addr
)
415 d
= map_read(map
, addr
);
416 t
= map_read(map
, addr
);
418 return map_word_equal(map
, d
, t
);
422 * Return true if the chip is ready and has the correct value.
424 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
425 * non-suspended sector) and it is indicated by no bits toggling.
427 * Error are indicated by toggling bits or bits held with the wrong value,
428 * or with bits toggling.
430 * Note that anything more complicated than checking if no bits are toggling
431 * (including checking DQ5 for an error status) is tricky to get working
432 * correctly and is therefore not done (particulary with interleaved chips
433 * as each chip must be checked independantly of the others).
436 static int __xipram
chip_good(struct map_info
*map
, unsigned long addr
, map_word expected
)
440 oldd
= map_read(map
, addr
);
441 curd
= map_read(map
, addr
);
443 return map_word_equal(map
, oldd
, curd
) &&
444 map_word_equal(map
, curd
, expected
);
447 static int get_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int mode
)
449 DECLARE_WAITQUEUE(wait
, current
);
450 struct cfi_private
*cfi
= map
->fldrv_priv
;
452 struct cfi_pri_amdstd
*cfip
= (struct cfi_pri_amdstd
*)cfi
->cmdset_priv
;
455 timeo
= jiffies
+ HZ
;
457 switch (chip
->state
) {
461 if (chip_ready(map
, adr
))
464 if (time_after(jiffies
, timeo
)) {
465 printk(KERN_ERR
"Waiting for chip to be ready timed out.\n");
466 spin_unlock(chip
->mutex
);
469 spin_unlock(chip
->mutex
);
471 spin_lock(chip
->mutex
);
472 /* Someone else might have been playing with it. */
482 if (mode
== FL_WRITING
) /* FIXME: Erase-suspend-program appears broken. */
485 if (!(mode
== FL_READY
|| mode
== FL_POINT
487 || (mode
== FL_WRITING
&& (cfip
->EraseSuspend
& 0x2))
488 || (mode
== FL_WRITING
&& (cfip
->EraseSuspend
& 0x1))))
491 /* We could check to see if we're trying to access the sector
492 * that is currently being erased. However, no user will try
493 * anything like that so we just wait for the timeout. */
496 /* It's harmless to issue the Erase-Suspend and Erase-Resume
497 * commands when the erase algorithm isn't in progress. */
498 map_write(map
, CMD(0xB0), chip
->in_progress_block_addr
);
499 chip
->oldstate
= FL_ERASING
;
500 chip
->state
= FL_ERASE_SUSPENDING
;
501 chip
->erase_suspended
= 1;
503 if (chip_ready(map
, adr
))
506 if (time_after(jiffies
, timeo
)) {
507 /* Should have suspended the erase by now.
508 * Send an Erase-Resume command as either
509 * there was an error (so leave the erase
510 * routine to recover from it) or we trying to
511 * use the erase-in-progress sector. */
512 map_write(map
, CMD(0x30), chip
->in_progress_block_addr
);
513 chip
->state
= FL_ERASING
;
514 chip
->oldstate
= FL_READY
;
515 printk(KERN_ERR
"MTD %s(): chip not ready after erase suspend\n", __func__
);
519 spin_unlock(chip
->mutex
);
521 spin_lock(chip
->mutex
);
522 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
523 So we can just loop here. */
525 chip
->state
= FL_READY
;
528 case FL_XIP_WHILE_ERASING
:
529 if (mode
!= FL_READY
&& mode
!= FL_POINT
&&
530 (!cfip
|| !(cfip
->EraseSuspend
&2)))
532 chip
->oldstate
= chip
->state
;
533 chip
->state
= FL_READY
;
537 /* Only if there's no operation suspended... */
538 if (mode
== FL_READY
&& chip
->oldstate
== FL_READY
)
543 set_current_state(TASK_UNINTERRUPTIBLE
);
544 add_wait_queue(&chip
->wq
, &wait
);
545 spin_unlock(chip
->mutex
);
547 remove_wait_queue(&chip
->wq
, &wait
);
548 spin_lock(chip
->mutex
);
554 static void put_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
)
556 struct cfi_private
*cfi
= map
->fldrv_priv
;
558 switch(chip
->oldstate
) {
560 chip
->state
= chip
->oldstate
;
561 map_write(map
, CMD(0x30), chip
->in_progress_block_addr
);
562 chip
->oldstate
= FL_READY
;
563 chip
->state
= FL_ERASING
;
566 case FL_XIP_WHILE_ERASING
:
567 chip
->state
= chip
->oldstate
;
568 chip
->oldstate
= FL_READY
;
573 /* We should really make set_vpp() count, rather than doing this */
577 printk(KERN_ERR
"MTD: put_chip() called with oldstate %d!!\n", chip
->oldstate
);
582 #ifdef CONFIG_MTD_XIP
585 * No interrupt what so ever can be serviced while the flash isn't in array
586 * mode. This is ensured by the xip_disable() and xip_enable() functions
587 * enclosing any code path where the flash is known not to be in array mode.
588 * And within a XIP disabled code path, only functions marked with __xipram
589 * may be called and nothing else (it's a good thing to inspect generated
590 * assembly to make sure inline functions were actually inlined and that gcc
591 * didn't emit calls to its own support functions). Also configuring MTD CFI
592 * support to a single buswidth and a single interleave is also recommended.
595 static void xip_disable(struct map_info
*map
, struct flchip
*chip
,
598 /* TODO: chips with no XIP use should ignore and return */
599 (void) map_read(map
, adr
); /* ensure mmu mapping is up to date */
603 static void __xipram
xip_enable(struct map_info
*map
, struct flchip
*chip
,
606 struct cfi_private
*cfi
= map
->fldrv_priv
;
608 if (chip
->state
!= FL_POINT
&& chip
->state
!= FL_READY
) {
609 map_write(map
, CMD(0xf0), adr
);
610 chip
->state
= FL_READY
;
612 (void) map_read(map
, adr
);
618 * When a delay is required for the flash operation to complete, the
619 * xip_udelay() function is polling for both the given timeout and pending
620 * (but still masked) hardware interrupts. Whenever there is an interrupt
621 * pending then the flash erase operation is suspended, array mode restored
622 * and interrupts unmasked. Task scheduling might also happen at that
623 * point. The CPU eventually returns from the interrupt or the call to
624 * schedule() and the suspended flash operation is resumed for the remaining
625 * of the delay period.
627 * Warning: this function _will_ fool interrupt latency tracing tools.
630 static void __xipram
xip_udelay(struct map_info
*map
, struct flchip
*chip
,
631 unsigned long adr
, int usec
)
633 struct cfi_private
*cfi
= map
->fldrv_priv
;
634 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
635 map_word status
, OK
= CMD(0x80);
636 unsigned long suspended
, start
= xip_currtime();
641 if (xip_irqpending() && extp
&&
642 ((chip
->state
== FL_ERASING
&& (extp
->EraseSuspend
& 2))) &&
643 (cfi_interleave_is_1(cfi
) || chip
->oldstate
== FL_READY
)) {
645 * Let's suspend the erase operation when supported.
646 * Note that we currently don't try to suspend
647 * interleaved chips if there is already another
648 * operation suspended (imagine what happens
649 * when one chip was already done with the current
650 * operation while another chip suspended it, then
651 * we resume the whole thing at once). Yes, it
654 map_write(map
, CMD(0xb0), adr
);
655 usec
-= xip_elapsed_since(start
);
656 suspended
= xip_currtime();
658 if (xip_elapsed_since(suspended
) > 100000) {
660 * The chip doesn't want to suspend
661 * after waiting for 100 msecs.
662 * This is a critical error but there
663 * is not much we can do here.
667 status
= map_read(map
, adr
);
668 } while (!map_word_andequal(map
, status
, OK
, OK
));
670 /* Suspend succeeded */
671 oldstate
= chip
->state
;
672 if (!map_word_bitsset(map
, status
, CMD(0x40)))
674 chip
->state
= FL_XIP_WHILE_ERASING
;
675 chip
->erase_suspended
= 1;
676 map_write(map
, CMD(0xf0), adr
);
677 (void) map_read(map
, adr
);
678 asm volatile (".rep 8; nop; .endr");
680 spin_unlock(chip
->mutex
);
681 asm volatile (".rep 8; nop; .endr");
685 * We're back. However someone else might have
686 * decided to go write to the chip if we are in
687 * a suspended erase state. If so let's wait
690 spin_lock(chip
->mutex
);
691 while (chip
->state
!= FL_XIP_WHILE_ERASING
) {
692 DECLARE_WAITQUEUE(wait
, current
);
693 set_current_state(TASK_UNINTERRUPTIBLE
);
694 add_wait_queue(&chip
->wq
, &wait
);
695 spin_unlock(chip
->mutex
);
697 remove_wait_queue(&chip
->wq
, &wait
);
698 spin_lock(chip
->mutex
);
700 /* Disallow XIP again */
703 /* Resume the write or erase operation */
704 map_write(map
, CMD(0x30), adr
);
705 chip
->state
= oldstate
;
706 start
= xip_currtime();
707 } else if (usec
>= 1000000/HZ
) {
709 * Try to save on CPU power when waiting delay
710 * is at least a system timer tick period.
711 * No need to be extremely accurate here.
715 status
= map_read(map
, adr
);
716 } while (!map_word_andequal(map
, status
, OK
, OK
)
717 && xip_elapsed_since(start
) < usec
);
720 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
723 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
724 * the flash is actively programming or erasing since we have to poll for
725 * the operation to complete anyway. We can't do that in a generic way with
726 * a XIP setup so do it before the actual flash operation in this case
727 * and stub it out from INVALIDATE_CACHE_UDELAY.
729 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
730 INVALIDATE_CACHED_RANGE(map, from, size)
732 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
733 UDELAY(map, chip, adr, usec)
738 * Activating this XIP support changes the way the code works a bit. For
739 * example the code to suspend the current process when concurrent access
740 * happens is never executed because xip_udelay() will always return with the
741 * same chip state as it was entered with. This is why there is no care for
742 * the presence of add_wait_queue() or schedule() calls from within a couple
743 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
744 * The queueing and scheduling are always happening within xip_udelay().
746 * Similarly, get_chip() and put_chip() just happen to always be executed
747 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
748 * is in array mode, therefore never executing many cases therein and not
749 * causing any problem with XIP.
754 #define xip_disable(map, chip, adr)
755 #define xip_enable(map, chip, adr)
756 #define XIP_INVAL_CACHED_RANGE(x...)
758 #define UDELAY(map, chip, adr, usec) \
760 spin_unlock(chip->mutex); \
762 spin_lock(chip->mutex); \
765 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
767 spin_unlock(chip->mutex); \
768 INVALIDATE_CACHED_RANGE(map, adr, len); \
770 spin_lock(chip->mutex); \
775 static inline int do_read_onechip(struct map_info
*map
, struct flchip
*chip
, loff_t adr
, size_t len
, u_char
*buf
)
777 unsigned long cmd_addr
;
778 struct cfi_private
*cfi
= map
->fldrv_priv
;
783 /* Ensure cmd read/writes are aligned. */
784 cmd_addr
= adr
& ~(map_bankwidth(map
)-1);
786 spin_lock(chip
->mutex
);
787 ret
= get_chip(map
, chip
, cmd_addr
, FL_READY
);
789 spin_unlock(chip
->mutex
);
793 if (chip
->state
!= FL_POINT
&& chip
->state
!= FL_READY
) {
794 map_write(map
, CMD(0xf0), cmd_addr
);
795 chip
->state
= FL_READY
;
798 map_copy_from(map
, buf
, adr
, len
);
800 put_chip(map
, chip
, cmd_addr
);
802 spin_unlock(chip
->mutex
);
807 static int cfi_amdstd_read (struct mtd_info
*mtd
, loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
809 struct map_info
*map
= mtd
->priv
;
810 struct cfi_private
*cfi
= map
->fldrv_priv
;
815 /* ofs: offset within the first chip that the first read should start */
817 chipnum
= (from
>> cfi
->chipshift
);
818 ofs
= from
- (chipnum
<< cfi
->chipshift
);
824 unsigned long thislen
;
826 if (chipnum
>= cfi
->numchips
)
829 if ((len
+ ofs
-1) >> cfi
->chipshift
)
830 thislen
= (1<<cfi
->chipshift
) - ofs
;
834 ret
= do_read_onechip(map
, &cfi
->chips
[chipnum
], ofs
, thislen
, buf
);
849 static inline int do_read_secsi_onechip(struct map_info
*map
, struct flchip
*chip
, loff_t adr
, size_t len
, u_char
*buf
)
851 DECLARE_WAITQUEUE(wait
, current
);
852 unsigned long timeo
= jiffies
+ HZ
;
853 struct cfi_private
*cfi
= map
->fldrv_priv
;
856 spin_lock(chip
->mutex
);
858 if (chip
->state
!= FL_READY
){
860 printk(KERN_DEBUG
"Waiting for chip to read, status = %d\n", chip
->state
);
862 set_current_state(TASK_UNINTERRUPTIBLE
);
863 add_wait_queue(&chip
->wq
, &wait
);
865 spin_unlock(chip
->mutex
);
868 remove_wait_queue(&chip
->wq
, &wait
);
870 if(signal_pending(current
))
873 timeo
= jiffies
+ HZ
;
880 chip
->state
= FL_READY
;
882 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
883 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
884 cfi_send_gen_cmd(0x88, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
886 map_copy_from(map
, buf
, adr
, len
);
888 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
889 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
890 cfi_send_gen_cmd(0x90, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
891 cfi_send_gen_cmd(0x00, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
894 spin_unlock(chip
->mutex
);
899 static int cfi_amdstd_secsi_read (struct mtd_info
*mtd
, loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
901 struct map_info
*map
= mtd
->priv
;
902 struct cfi_private
*cfi
= map
->fldrv_priv
;
908 /* ofs: offset within the first chip that the first read should start */
910 /* 8 secsi bytes per chip */
918 unsigned long thislen
;
920 if (chipnum
>= cfi
->numchips
)
923 if ((len
+ ofs
-1) >> 3)
924 thislen
= (1<<3) - ofs
;
928 ret
= do_read_secsi_onechip(map
, &cfi
->chips
[chipnum
], ofs
, thislen
, buf
);
943 static int __xipram
do_write_oneword(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, map_word datum
)
945 struct cfi_private
*cfi
= map
->fldrv_priv
;
946 unsigned long timeo
= jiffies
+ HZ
;
948 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
949 * have a max write time of a few hundreds usec). However, we should
950 * use the maximum timeout value given by the chip at probe time
951 * instead. Unfortunately, struct flchip does have a field for
952 * maximum timeout, only for typical which can be far too short
953 * depending of the conditions. The ' + 1' is to avoid having a
954 * timeout of 0 jiffies if HZ is smaller than 1000.
956 unsigned long uWriteTimeout
= ( HZ
/ 1000 ) + 1;
963 spin_lock(chip
->mutex
);
964 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
966 spin_unlock(chip
->mutex
);
970 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
971 __func__
, adr
, datum
.x
[0] );
974 * Check for a NOP for the case when the datum to write is already
975 * present - it saves time and works around buggy chips that corrupt
976 * data at other locations when 0xff is written to a location that
977 * already contains 0xff.
979 oldd
= map_read(map
, adr
);
980 if (map_word_equal(map
, oldd
, datum
)) {
981 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): NOP\n",
986 XIP_INVAL_CACHED_RANGE(map
, adr
, map_bankwidth(map
));
988 xip_disable(map
, chip
, adr
);
990 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
991 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
992 cfi_send_gen_cmd(0xA0, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
993 map_write(map
, datum
, adr
);
994 chip
->state
= FL_WRITING
;
996 INVALIDATE_CACHE_UDELAY(map
, chip
,
997 adr
, map_bankwidth(map
),
998 chip
->word_write_time
);
1000 /* See comment above for timeout value. */
1001 timeo
= jiffies
+ uWriteTimeout
;
1003 if (chip
->state
!= FL_WRITING
) {
1004 /* Someone's suspended the write. Sleep */
1005 DECLARE_WAITQUEUE(wait
, current
);
1007 set_current_state(TASK_UNINTERRUPTIBLE
);
1008 add_wait_queue(&chip
->wq
, &wait
);
1009 spin_unlock(chip
->mutex
);
1011 remove_wait_queue(&chip
->wq
, &wait
);
1012 timeo
= jiffies
+ (HZ
/ 2); /* FIXME */
1013 spin_lock(chip
->mutex
);
1017 if (time_after(jiffies
, timeo
) && !chip_ready(map
, adr
)){
1018 xip_enable(map
, chip
, adr
);
1019 printk(KERN_WARNING
"MTD %s(): software timeout\n", __func__
);
1020 xip_disable(map
, chip
, adr
);
1024 if (chip_ready(map
, adr
))
1027 /* Latency issues. Drop the lock, wait a while and retry */
1028 UDELAY(map
, chip
, adr
, 1);
1030 /* Did we succeed? */
1031 if (!chip_good(map
, adr
, datum
)) {
1032 /* reset on all failures. */
1033 map_write( map
, CMD(0xF0), chip
->start
);
1034 /* FIXME - should have reset delay before continuing */
1036 if (++retry_cnt
<= MAX_WORD_RETRIES
)
1041 xip_enable(map
, chip
, adr
);
1043 chip
->state
= FL_READY
;
1044 put_chip(map
, chip
, adr
);
1045 spin_unlock(chip
->mutex
);
1051 static int cfi_amdstd_write_words(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1052 size_t *retlen
, const u_char
*buf
)
1054 struct map_info
*map
= mtd
->priv
;
1055 struct cfi_private
*cfi
= map
->fldrv_priv
;
1058 unsigned long ofs
, chipstart
;
1059 DECLARE_WAITQUEUE(wait
, current
);
1065 chipnum
= to
>> cfi
->chipshift
;
1066 ofs
= to
- (chipnum
<< cfi
->chipshift
);
1067 chipstart
= cfi
->chips
[chipnum
].start
;
1069 /* If it's not bus-aligned, do the first byte write */
1070 if (ofs
& (map_bankwidth(map
)-1)) {
1071 unsigned long bus_ofs
= ofs
& ~(map_bankwidth(map
)-1);
1072 int i
= ofs
- bus_ofs
;
1077 spin_lock(cfi
->chips
[chipnum
].mutex
);
1079 if (cfi
->chips
[chipnum
].state
!= FL_READY
) {
1081 printk(KERN_DEBUG
"Waiting for chip to write, status = %d\n", cfi
->chips
[chipnum
].state
);
1083 set_current_state(TASK_UNINTERRUPTIBLE
);
1084 add_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1086 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1089 remove_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1091 if(signal_pending(current
))
1097 /* Load 'tmp_buf' with old contents of flash */
1098 tmp_buf
= map_read(map
, bus_ofs
+chipstart
);
1100 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1102 /* Number of bytes to copy from buffer */
1103 n
= min_t(int, len
, map_bankwidth(map
)-i
);
1105 tmp_buf
= map_word_load_partial(map
, tmp_buf
, buf
, i
, n
);
1107 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1117 if (ofs
>> cfi
->chipshift
) {
1120 if (chipnum
== cfi
->numchips
)
1125 /* We are now aligned, write as much as possible */
1126 while(len
>= map_bankwidth(map
)) {
1129 datum
= map_word_load(map
, buf
);
1131 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1136 ofs
+= map_bankwidth(map
);
1137 buf
+= map_bankwidth(map
);
1138 (*retlen
) += map_bankwidth(map
);
1139 len
-= map_bankwidth(map
);
1141 if (ofs
>> cfi
->chipshift
) {
1144 if (chipnum
== cfi
->numchips
)
1146 chipstart
= cfi
->chips
[chipnum
].start
;
1150 /* Write the trailing bytes if any */
1151 if (len
& (map_bankwidth(map
)-1)) {
1155 spin_lock(cfi
->chips
[chipnum
].mutex
);
1157 if (cfi
->chips
[chipnum
].state
!= FL_READY
) {
1159 printk(KERN_DEBUG
"Waiting for chip to write, status = %d\n", cfi
->chips
[chipnum
].state
);
1161 set_current_state(TASK_UNINTERRUPTIBLE
);
1162 add_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1164 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1167 remove_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1169 if(signal_pending(current
))
1175 tmp_buf
= map_read(map
, ofs
+ chipstart
);
1177 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1179 tmp_buf
= map_word_load_partial(map
, tmp_buf
, buf
, 0, len
);
1181 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1194 * FIXME: interleaved mode not tested, and probably not supported!
1196 static int __xipram
do_write_buffer(struct map_info
*map
, struct flchip
*chip
,
1197 unsigned long adr
, const u_char
*buf
,
1200 struct cfi_private
*cfi
= map
->fldrv_priv
;
1201 unsigned long timeo
= jiffies
+ HZ
;
1202 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1203 unsigned long uWriteTimeout
= ( HZ
/ 1000 ) + 1;
1205 unsigned long cmd_adr
;
1212 spin_lock(chip
->mutex
);
1213 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1215 spin_unlock(chip
->mutex
);
1219 datum
= map_word_load(map
, buf
);
1221 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1222 __func__
, adr
, datum
.x
[0] );
1224 XIP_INVAL_CACHED_RANGE(map
, adr
, len
);
1226 xip_disable(map
, chip
, cmd_adr
);
1228 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1229 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1230 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1232 /* Write Buffer Load */
1233 map_write(map
, CMD(0x25), cmd_adr
);
1235 chip
->state
= FL_WRITING_TO_BUFFER
;
1237 /* Write length of data to come */
1238 words
= len
/ map_bankwidth(map
);
1239 map_write(map
, CMD(words
- 1), cmd_adr
);
1242 while(z
< words
* map_bankwidth(map
)) {
1243 datum
= map_word_load(map
, buf
);
1244 map_write(map
, datum
, adr
+ z
);
1246 z
+= map_bankwidth(map
);
1247 buf
+= map_bankwidth(map
);
1249 z
-= map_bankwidth(map
);
1253 /* Write Buffer Program Confirm: GO GO GO */
1254 map_write(map
, CMD(0x29), cmd_adr
);
1255 chip
->state
= FL_WRITING
;
1257 INVALIDATE_CACHE_UDELAY(map
, chip
,
1258 adr
, map_bankwidth(map
),
1259 chip
->word_write_time
);
1261 timeo
= jiffies
+ uWriteTimeout
;
1264 if (chip
->state
!= FL_WRITING
) {
1265 /* Someone's suspended the write. Sleep */
1266 DECLARE_WAITQUEUE(wait
, current
);
1268 set_current_state(TASK_UNINTERRUPTIBLE
);
1269 add_wait_queue(&chip
->wq
, &wait
);
1270 spin_unlock(chip
->mutex
);
1272 remove_wait_queue(&chip
->wq
, &wait
);
1273 timeo
= jiffies
+ (HZ
/ 2); /* FIXME */
1274 spin_lock(chip
->mutex
);
1278 if (time_after(jiffies
, timeo
) && !chip_ready(map
, adr
))
1281 if (chip_ready(map
, adr
)) {
1282 xip_enable(map
, chip
, adr
);
1286 /* Latency issues. Drop the lock, wait a while and retry */
1287 UDELAY(map
, chip
, adr
, 1);
1290 /* reset on all failures. */
1291 map_write( map
, CMD(0xF0), chip
->start
);
1292 xip_enable(map
, chip
, adr
);
1293 /* FIXME - should have reset delay before continuing */
1295 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1300 chip
->state
= FL_READY
;
1301 put_chip(map
, chip
, adr
);
1302 spin_unlock(chip
->mutex
);
1308 static int cfi_amdstd_write_buffers(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1309 size_t *retlen
, const u_char
*buf
)
1311 struct map_info
*map
= mtd
->priv
;
1312 struct cfi_private
*cfi
= map
->fldrv_priv
;
1313 int wbufsize
= cfi_interleave(cfi
) << cfi
->cfiq
->MaxBufWriteSize
;
1322 chipnum
= to
>> cfi
->chipshift
;
1323 ofs
= to
- (chipnum
<< cfi
->chipshift
);
1325 /* If it's not bus-aligned, do the first word write */
1326 if (ofs
& (map_bankwidth(map
)-1)) {
1327 size_t local_len
= (-ofs
)&(map_bankwidth(map
)-1);
1328 if (local_len
> len
)
1330 ret
= cfi_amdstd_write_words(mtd
, ofs
+ (chipnum
<<cfi
->chipshift
),
1331 local_len
, retlen
, buf
);
1338 if (ofs
>> cfi
->chipshift
) {
1341 if (chipnum
== cfi
->numchips
)
1346 /* Write buffer is worth it only if more than one word to write... */
1347 while (len
>= map_bankwidth(map
) * 2) {
1348 /* We must not cross write block boundaries */
1349 int size
= wbufsize
- (ofs
& (wbufsize
-1));
1353 if (size
% map_bankwidth(map
))
1354 size
-= size
% map_bankwidth(map
);
1356 ret
= do_write_buffer(map
, &cfi
->chips
[chipnum
],
1366 if (ofs
>> cfi
->chipshift
) {
1369 if (chipnum
== cfi
->numchips
)
1375 size_t retlen_dregs
= 0;
1377 ret
= cfi_amdstd_write_words(mtd
, ofs
+ (chipnum
<<cfi
->chipshift
),
1378 len
, &retlen_dregs
, buf
);
1380 *retlen
+= retlen_dregs
;
1389 * Handle devices with one erase region, that only implement
1390 * the chip erase command.
1392 static int __xipram
do_erase_chip(struct map_info
*map
, struct flchip
*chip
)
1394 struct cfi_private
*cfi
= map
->fldrv_priv
;
1395 unsigned long timeo
= jiffies
+ HZ
;
1396 unsigned long int adr
;
1397 DECLARE_WAITQUEUE(wait
, current
);
1400 adr
= cfi
->addr_unlock1
;
1402 spin_lock(chip
->mutex
);
1403 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1405 spin_unlock(chip
->mutex
);
1409 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): ERASE 0x%.8lx\n",
1410 __func__
, chip
->start
);
1412 XIP_INVAL_CACHED_RANGE(map
, adr
, map
->size
);
1414 xip_disable(map
, chip
, adr
);
1416 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1417 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1418 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1419 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1420 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1421 cfi_send_gen_cmd(0x10, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1423 chip
->state
= FL_ERASING
;
1424 chip
->erase_suspended
= 0;
1425 chip
->in_progress_block_addr
= adr
;
1427 INVALIDATE_CACHE_UDELAY(map
, chip
,
1429 chip
->erase_time
*500);
1431 timeo
= jiffies
+ (HZ
*20);
1434 if (chip
->state
!= FL_ERASING
) {
1435 /* Someone's suspended the erase. Sleep */
1436 set_current_state(TASK_UNINTERRUPTIBLE
);
1437 add_wait_queue(&chip
->wq
, &wait
);
1438 spin_unlock(chip
->mutex
);
1440 remove_wait_queue(&chip
->wq
, &wait
);
1441 spin_lock(chip
->mutex
);
1444 if (chip
->erase_suspended
) {
1445 /* This erase was suspended and resumed.
1446 Adjust the timeout */
1447 timeo
= jiffies
+ (HZ
*20); /* FIXME */
1448 chip
->erase_suspended
= 0;
1451 if (chip_ready(map
, adr
))
1454 if (time_after(jiffies
, timeo
)) {
1455 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1460 /* Latency issues. Drop the lock, wait a while and retry */
1461 UDELAY(map
, chip
, adr
, 1000000/HZ
);
1463 /* Did we succeed? */
1464 if (!chip_good(map
, adr
, map_word_ff(map
))) {
1465 /* reset on all failures. */
1466 map_write( map
, CMD(0xF0), chip
->start
);
1467 /* FIXME - should have reset delay before continuing */
1472 chip
->state
= FL_READY
;
1473 xip_enable(map
, chip
, adr
);
1474 put_chip(map
, chip
, adr
);
1475 spin_unlock(chip
->mutex
);
1481 static int __xipram
do_erase_oneblock(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int len
, void *thunk
)
1483 struct cfi_private
*cfi
= map
->fldrv_priv
;
1484 unsigned long timeo
= jiffies
+ HZ
;
1485 DECLARE_WAITQUEUE(wait
, current
);
1490 spin_lock(chip
->mutex
);
1491 ret
= get_chip(map
, chip
, adr
, FL_ERASING
);
1493 spin_unlock(chip
->mutex
);
1497 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): ERASE 0x%.8lx\n",
1500 XIP_INVAL_CACHED_RANGE(map
, adr
, len
);
1502 xip_disable(map
, chip
, adr
);
1504 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1505 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1506 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1507 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1508 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1509 map_write(map
, CMD(0x30), adr
);
1511 chip
->state
= FL_ERASING
;
1512 chip
->erase_suspended
= 0;
1513 chip
->in_progress_block_addr
= adr
;
1515 INVALIDATE_CACHE_UDELAY(map
, chip
,
1517 chip
->erase_time
*500);
1519 timeo
= jiffies
+ (HZ
*20);
1522 if (chip
->state
!= FL_ERASING
) {
1523 /* Someone's suspended the erase. Sleep */
1524 set_current_state(TASK_UNINTERRUPTIBLE
);
1525 add_wait_queue(&chip
->wq
, &wait
);
1526 spin_unlock(chip
->mutex
);
1528 remove_wait_queue(&chip
->wq
, &wait
);
1529 spin_lock(chip
->mutex
);
1532 if (chip
->erase_suspended
) {
1533 /* This erase was suspended and resumed.
1534 Adjust the timeout */
1535 timeo
= jiffies
+ (HZ
*20); /* FIXME */
1536 chip
->erase_suspended
= 0;
1539 if (chip_ready(map
, adr
)) {
1540 xip_enable(map
, chip
, adr
);
1544 if (time_after(jiffies
, timeo
)) {
1545 xip_enable(map
, chip
, adr
);
1546 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1551 /* Latency issues. Drop the lock, wait a while and retry */
1552 UDELAY(map
, chip
, adr
, 1000000/HZ
);
1554 /* Did we succeed? */
1555 if (!chip_good(map
, adr
, map_word_ff(map
))) {
1556 /* reset on all failures. */
1557 map_write( map
, CMD(0xF0), chip
->start
);
1558 /* FIXME - should have reset delay before continuing */
1563 chip
->state
= FL_READY
;
1564 put_chip(map
, chip
, adr
);
1565 spin_unlock(chip
->mutex
);
1570 int cfi_amdstd_erase_varsize(struct mtd_info
*mtd
, struct erase_info
*instr
)
1572 unsigned long ofs
, len
;
1578 ret
= cfi_varsize_frob(mtd
, do_erase_oneblock
, ofs
, len
, NULL
);
1582 instr
->state
= MTD_ERASE_DONE
;
1583 mtd_erase_callback(instr
);
1589 static int cfi_amdstd_erase_chip(struct mtd_info
*mtd
, struct erase_info
*instr
)
1591 struct map_info
*map
= mtd
->priv
;
1592 struct cfi_private
*cfi
= map
->fldrv_priv
;
1595 if (instr
->addr
!= 0)
1598 if (instr
->len
!= mtd
->size
)
1601 ret
= do_erase_chip(map
, &cfi
->chips
[0]);
1605 instr
->state
= MTD_ERASE_DONE
;
1606 mtd_erase_callback(instr
);
1612 static void cfi_amdstd_sync (struct mtd_info
*mtd
)
1614 struct map_info
*map
= mtd
->priv
;
1615 struct cfi_private
*cfi
= map
->fldrv_priv
;
1617 struct flchip
*chip
;
1619 DECLARE_WAITQUEUE(wait
, current
);
1621 for (i
=0; !ret
&& i
<cfi
->numchips
; i
++) {
1622 chip
= &cfi
->chips
[i
];
1625 spin_lock(chip
->mutex
);
1627 switch(chip
->state
) {
1631 case FL_JEDEC_QUERY
:
1632 chip
->oldstate
= chip
->state
;
1633 chip
->state
= FL_SYNCING
;
1634 /* No need to wake_up() on this state change -
1635 * as the whole point is that nobody can do anything
1636 * with the chip now anyway.
1639 spin_unlock(chip
->mutex
);
1643 /* Not an idle state */
1644 add_wait_queue(&chip
->wq
, &wait
);
1646 spin_unlock(chip
->mutex
);
1650 remove_wait_queue(&chip
->wq
, &wait
);
1656 /* Unlock the chips again */
1658 for (i
--; i
>=0; i
--) {
1659 chip
= &cfi
->chips
[i
];
1661 spin_lock(chip
->mutex
);
1663 if (chip
->state
== FL_SYNCING
) {
1664 chip
->state
= chip
->oldstate
;
1667 spin_unlock(chip
->mutex
);
1672 static int cfi_amdstd_suspend(struct mtd_info
*mtd
)
1674 struct map_info
*map
= mtd
->priv
;
1675 struct cfi_private
*cfi
= map
->fldrv_priv
;
1677 struct flchip
*chip
;
1680 for (i
=0; !ret
&& i
<cfi
->numchips
; i
++) {
1681 chip
= &cfi
->chips
[i
];
1683 spin_lock(chip
->mutex
);
1685 switch(chip
->state
) {
1689 case FL_JEDEC_QUERY
:
1690 chip
->oldstate
= chip
->state
;
1691 chip
->state
= FL_PM_SUSPENDED
;
1692 /* No need to wake_up() on this state change -
1693 * as the whole point is that nobody can do anything
1694 * with the chip now anyway.
1696 case FL_PM_SUSPENDED
:
1703 spin_unlock(chip
->mutex
);
1706 /* Unlock the chips again */
1709 for (i
--; i
>=0; i
--) {
1710 chip
= &cfi
->chips
[i
];
1712 spin_lock(chip
->mutex
);
1714 if (chip
->state
== FL_PM_SUSPENDED
) {
1715 chip
->state
= chip
->oldstate
;
1718 spin_unlock(chip
->mutex
);
1726 static void cfi_amdstd_resume(struct mtd_info
*mtd
)
1728 struct map_info
*map
= mtd
->priv
;
1729 struct cfi_private
*cfi
= map
->fldrv_priv
;
1731 struct flchip
*chip
;
1733 for (i
=0; i
<cfi
->numchips
; i
++) {
1735 chip
= &cfi
->chips
[i
];
1737 spin_lock(chip
->mutex
);
1739 if (chip
->state
== FL_PM_SUSPENDED
) {
1740 chip
->state
= FL_READY
;
1741 map_write(map
, CMD(0xF0), chip
->start
);
1745 printk(KERN_ERR
"Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1747 spin_unlock(chip
->mutex
);
1751 static void cfi_amdstd_destroy(struct mtd_info
*mtd
)
1753 struct map_info
*map
= mtd
->priv
;
1754 struct cfi_private
*cfi
= map
->fldrv_priv
;
1756 kfree(cfi
->cmdset_priv
);
1759 kfree(mtd
->eraseregions
);
1762 MODULE_LICENSE("GPL");
1763 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1764 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");