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[MTD] CHIPS: Support for SST 49LF040B flash chip
[deliverable/linux.git] / drivers / mtd / chips / cfi_cmdset_0002.c
1 /*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
17 *
18 * This code is GPL
19 *
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
29 #include <asm/io.h>
30 #include <asm/byteorder.h>
31
32 #include <linux/errno.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
41
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
44
45 #define MAX_WORD_RETRIES 3
46
47 #define MANUFACTURER_AMD 0x0001
48 #define MANUFACTURER_ATMEL 0x001F
49 #define MANUFACTURER_SST 0x00BF
50 #define SST49LF004B 0x0060
51 #define SST49LF040B 0x0050
52 #define SST49LF008A 0x005a
53 #define AT49BV6416 0x00d6
54
55 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
56 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
57 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
58 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
59 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
60 static void cfi_amdstd_sync (struct mtd_info *);
61 static int cfi_amdstd_suspend (struct mtd_info *);
62 static void cfi_amdstd_resume (struct mtd_info *);
63 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
64
65 static void cfi_amdstd_destroy(struct mtd_info *);
66
67 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
68 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
69
70 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
71 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
72 #include "fwh_lock.h"
73
74 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len);
75 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len);
76
77 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
78 .probe = NULL, /* Not usable directly */
79 .destroy = cfi_amdstd_destroy,
80 .name = "cfi_cmdset_0002",
81 .module = THIS_MODULE
82 };
83
84
85 /* #define DEBUG_CFI_FEATURES */
86
87
88 #ifdef DEBUG_CFI_FEATURES
89 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
90 {
91 const char* erase_suspend[3] = {
92 "Not supported", "Read only", "Read/write"
93 };
94 const char* top_bottom[6] = {
95 "No WP", "8x8KiB sectors at top & bottom, no WP",
96 "Bottom boot", "Top boot",
97 "Uniform, Bottom WP", "Uniform, Top WP"
98 };
99
100 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
101 printk(" Address sensitive unlock: %s\n",
102 (extp->SiliconRevision & 1) ? "Not required" : "Required");
103
104 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
105 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
106 else
107 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
108
109 if (extp->BlkProt == 0)
110 printk(" Block protection: Not supported\n");
111 else
112 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
113
114
115 printk(" Temporary block unprotect: %s\n",
116 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
117 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
118 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
119 printk(" Burst mode: %s\n",
120 extp->BurstMode ? "Supported" : "Not supported");
121 if (extp->PageMode == 0)
122 printk(" Page mode: Not supported\n");
123 else
124 printk(" Page mode: %d word page\n", extp->PageMode << 2);
125
126 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
127 extp->VppMin >> 4, extp->VppMin & 0xf);
128 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
129 extp->VppMax >> 4, extp->VppMax & 0xf);
130
131 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
132 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
133 else
134 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
135 }
136 #endif
137
138 #ifdef AMD_BOOTLOC_BUG
139 /* Wheee. Bring me the head of someone at AMD. */
140 static void fixup_amd_bootblock(struct mtd_info *mtd, void* param)
141 {
142 struct map_info *map = mtd->priv;
143 struct cfi_private *cfi = map->fldrv_priv;
144 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
145 __u8 major = extp->MajorVersion;
146 __u8 minor = extp->MinorVersion;
147
148 if (((major << 8) | minor) < 0x3131) {
149 /* CFI version 1.0 => don't trust bootloc */
150 if (cfi->id & 0x80) {
151 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
152 extp->TopBottom = 3; /* top boot */
153 } else {
154 extp->TopBottom = 2; /* bottom boot */
155 }
156 }
157 }
158 #endif
159
160 static void fixup_use_write_buffers(struct mtd_info *mtd, void *param)
161 {
162 struct map_info *map = mtd->priv;
163 struct cfi_private *cfi = map->fldrv_priv;
164 if (cfi->cfiq->BufWriteTimeoutTyp) {
165 DEBUG(MTD_DEBUG_LEVEL1, "Using buffer write method\n" );
166 mtd->write = cfi_amdstd_write_buffers;
167 }
168 }
169
170 /* Atmel chips don't use the same PRI format as AMD chips */
171 static void fixup_convert_atmel_pri(struct mtd_info *mtd, void *param)
172 {
173 struct map_info *map = mtd->priv;
174 struct cfi_private *cfi = map->fldrv_priv;
175 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
176 struct cfi_pri_atmel atmel_pri;
177
178 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
179 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
180
181 if (atmel_pri.Features & 0x02)
182 extp->EraseSuspend = 2;
183
184 if (atmel_pri.BottomBoot)
185 extp->TopBottom = 2;
186 else
187 extp->TopBottom = 3;
188 }
189
190 static void fixup_use_secsi(struct mtd_info *mtd, void *param)
191 {
192 /* Setup for chips with a secsi area */
193 mtd->read_user_prot_reg = cfi_amdstd_secsi_read;
194 mtd->read_fact_prot_reg = cfi_amdstd_secsi_read;
195 }
196
197 static void fixup_use_erase_chip(struct mtd_info *mtd, void *param)
198 {
199 struct map_info *map = mtd->priv;
200 struct cfi_private *cfi = map->fldrv_priv;
201 if ((cfi->cfiq->NumEraseRegions == 1) &&
202 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
203 mtd->erase = cfi_amdstd_erase_chip;
204 }
205
206 }
207
208 /*
209 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
210 * locked by default.
211 */
212 static void fixup_use_atmel_lock(struct mtd_info *mtd, void *param)
213 {
214 mtd->lock = cfi_atmel_lock;
215 mtd->unlock = cfi_atmel_unlock;
216 mtd->flags |= MTD_STUPID_LOCK;
217 }
218
219 static struct cfi_fixup cfi_fixup_table[] = {
220 #ifdef AMD_BOOTLOC_BUG
221 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock, NULL },
222 #endif
223 { CFI_MFR_AMD, 0x0050, fixup_use_secsi, NULL, },
224 { CFI_MFR_AMD, 0x0053, fixup_use_secsi, NULL, },
225 { CFI_MFR_AMD, 0x0055, fixup_use_secsi, NULL, },
226 { CFI_MFR_AMD, 0x0056, fixup_use_secsi, NULL, },
227 { CFI_MFR_AMD, 0x005C, fixup_use_secsi, NULL, },
228 { CFI_MFR_AMD, 0x005F, fixup_use_secsi, NULL, },
229 #if !FORCE_WORD_WRITE
230 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers, NULL, },
231 #endif
232 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri, NULL },
233 { 0, 0, NULL, NULL }
234 };
235 static struct cfi_fixup jedec_fixup_table[] = {
236 { MANUFACTURER_SST, SST49LF004B, fixup_use_fwh_lock, NULL, },
237 { MANUFACTURER_SST, SST49LF040B, fixup_use_fwh_lock, NULL, },
238 { MANUFACTURER_SST, SST49LF008A, fixup_use_fwh_lock, NULL, },
239 { 0, 0, NULL, NULL }
240 };
241
242 static struct cfi_fixup fixup_table[] = {
243 /* The CFI vendor ids and the JEDEC vendor IDs appear
244 * to be common. It is like the devices id's are as
245 * well. This table is to pick all cases where
246 * we know that is the case.
247 */
248 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip, NULL },
249 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock, NULL },
250 { 0, 0, NULL, NULL }
251 };
252
253
254 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
255 {
256 struct cfi_private *cfi = map->fldrv_priv;
257 struct mtd_info *mtd;
258 int i;
259
260 mtd = kmalloc(sizeof(*mtd), GFP_KERNEL);
261 if (!mtd) {
262 printk(KERN_WARNING "Failed to allocate memory for MTD device\n");
263 return NULL;
264 }
265 memset(mtd, 0, sizeof(*mtd));
266 mtd->priv = map;
267 mtd->type = MTD_NORFLASH;
268
269 /* Fill in the default mtd operations */
270 mtd->erase = cfi_amdstd_erase_varsize;
271 mtd->write = cfi_amdstd_write_words;
272 mtd->read = cfi_amdstd_read;
273 mtd->sync = cfi_amdstd_sync;
274 mtd->suspend = cfi_amdstd_suspend;
275 mtd->resume = cfi_amdstd_resume;
276 mtd->flags = MTD_CAP_NORFLASH;
277 mtd->name = map->name;
278 mtd->writesize = 1;
279
280 if (cfi->cfi_mode==CFI_MODE_CFI){
281 unsigned char bootloc;
282 /*
283 * It's a real CFI chip, not one for which the probe
284 * routine faked a CFI structure. So we read the feature
285 * table from it.
286 */
287 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
288 struct cfi_pri_amdstd *extp;
289
290 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
291 if (!extp) {
292 kfree(mtd);
293 return NULL;
294 }
295
296 if (extp->MajorVersion != '1' ||
297 (extp->MinorVersion < '0' || extp->MinorVersion > '4')) {
298 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
299 "version %c.%c.\n", extp->MajorVersion,
300 extp->MinorVersion);
301 kfree(extp);
302 kfree(mtd);
303 return NULL;
304 }
305
306 /* Install our own private info structure */
307 cfi->cmdset_priv = extp;
308
309 /* Apply cfi device specific fixups */
310 cfi_fixup(mtd, cfi_fixup_table);
311
312 #ifdef DEBUG_CFI_FEATURES
313 /* Tell the user about it in lots of lovely detail */
314 cfi_tell_features(extp);
315 #endif
316
317 bootloc = extp->TopBottom;
318 if ((bootloc != 2) && (bootloc != 3)) {
319 printk(KERN_WARNING "%s: CFI does not contain boot "
320 "bank location. Assuming top.\n", map->name);
321 bootloc = 2;
322 }
323
324 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
325 printk(KERN_WARNING "%s: Swapping erase regions for broken CFI table.\n", map->name);
326
327 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
328 int j = (cfi->cfiq->NumEraseRegions-1)-i;
329 __u32 swap;
330
331 swap = cfi->cfiq->EraseRegionInfo[i];
332 cfi->cfiq->EraseRegionInfo[i] = cfi->cfiq->EraseRegionInfo[j];
333 cfi->cfiq->EraseRegionInfo[j] = swap;
334 }
335 }
336 /* Set the default CFI lock/unlock addresses */
337 cfi->addr_unlock1 = 0x555;
338 cfi->addr_unlock2 = 0x2aa;
339 /* Modify the unlock address if we are in compatibility mode */
340 if ( /* x16 in x8 mode */
341 ((cfi->device_type == CFI_DEVICETYPE_X8) &&
342 (cfi->cfiq->InterfaceDesc == 2)) ||
343 /* x32 in x16 mode */
344 ((cfi->device_type == CFI_DEVICETYPE_X16) &&
345 (cfi->cfiq->InterfaceDesc == 4)))
346 {
347 cfi->addr_unlock1 = 0xaaa;
348 cfi->addr_unlock2 = 0x555;
349 }
350
351 } /* CFI mode */
352 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
353 /* Apply jedec specific fixups */
354 cfi_fixup(mtd, jedec_fixup_table);
355 }
356 /* Apply generic fixups */
357 cfi_fixup(mtd, fixup_table);
358
359 for (i=0; i< cfi->numchips; i++) {
360 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
361 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
362 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
363 }
364
365 map->fldrv = &cfi_amdstd_chipdrv;
366
367 return cfi_amdstd_setup(mtd);
368 }
369 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
370
371 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
372 {
373 struct map_info *map = mtd->priv;
374 struct cfi_private *cfi = map->fldrv_priv;
375 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
376 unsigned long offset = 0;
377 int i,j;
378
379 printk(KERN_NOTICE "number of %s chips: %d\n",
380 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
381 /* Select the correct geometry setup */
382 mtd->size = devsize * cfi->numchips;
383
384 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
385 mtd->eraseregions = kmalloc(sizeof(struct mtd_erase_region_info)
386 * mtd->numeraseregions, GFP_KERNEL);
387 if (!mtd->eraseregions) {
388 printk(KERN_WARNING "Failed to allocate memory for MTD erase region info\n");
389 goto setup_err;
390 }
391
392 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
393 unsigned long ernum, ersize;
394 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
395 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
396
397 if (mtd->erasesize < ersize) {
398 mtd->erasesize = ersize;
399 }
400 for (j=0; j<cfi->numchips; j++) {
401 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
402 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
403 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
404 }
405 offset += (ersize * ernum);
406 }
407 if (offset != devsize) {
408 /* Argh */
409 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
410 goto setup_err;
411 }
412 #if 0
413 // debug
414 for (i=0; i<mtd->numeraseregions;i++){
415 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
416 i,mtd->eraseregions[i].offset,
417 mtd->eraseregions[i].erasesize,
418 mtd->eraseregions[i].numblocks);
419 }
420 #endif
421
422 /* FIXME: erase-suspend-program is broken. See
423 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
424 printk(KERN_NOTICE "cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
425
426 __module_get(THIS_MODULE);
427 return mtd;
428
429 setup_err:
430 if(mtd) {
431 kfree(mtd->eraseregions);
432 kfree(mtd);
433 }
434 kfree(cfi->cmdset_priv);
435 kfree(cfi->cfiq);
436 return NULL;
437 }
438
439 /*
440 * Return true if the chip is ready.
441 *
442 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
443 * non-suspended sector) and is indicated by no toggle bits toggling.
444 *
445 * Note that anything more complicated than checking if no bits are toggling
446 * (including checking DQ5 for an error status) is tricky to get working
447 * correctly and is therefore not done (particulary with interleaved chips
448 * as each chip must be checked independantly of the others).
449 */
450 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
451 {
452 map_word d, t;
453
454 d = map_read(map, addr);
455 t = map_read(map, addr);
456
457 return map_word_equal(map, d, t);
458 }
459
460 /*
461 * Return true if the chip is ready and has the correct value.
462 *
463 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
464 * non-suspended sector) and it is indicated by no bits toggling.
465 *
466 * Error are indicated by toggling bits or bits held with the wrong value,
467 * or with bits toggling.
468 *
469 * Note that anything more complicated than checking if no bits are toggling
470 * (including checking DQ5 for an error status) is tricky to get working
471 * correctly and is therefore not done (particulary with interleaved chips
472 * as each chip must be checked independantly of the others).
473 *
474 */
475 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
476 {
477 map_word oldd, curd;
478
479 oldd = map_read(map, addr);
480 curd = map_read(map, addr);
481
482 return map_word_equal(map, oldd, curd) &&
483 map_word_equal(map, curd, expected);
484 }
485
486 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
487 {
488 DECLARE_WAITQUEUE(wait, current);
489 struct cfi_private *cfi = map->fldrv_priv;
490 unsigned long timeo;
491 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
492
493 resettime:
494 timeo = jiffies + HZ;
495 retry:
496 switch (chip->state) {
497
498 case FL_STATUS:
499 for (;;) {
500 if (chip_ready(map, adr))
501 break;
502
503 if (time_after(jiffies, timeo)) {
504 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
505 spin_unlock(chip->mutex);
506 return -EIO;
507 }
508 spin_unlock(chip->mutex);
509 cfi_udelay(1);
510 spin_lock(chip->mutex);
511 /* Someone else might have been playing with it. */
512 goto retry;
513 }
514
515 case FL_READY:
516 case FL_CFI_QUERY:
517 case FL_JEDEC_QUERY:
518 return 0;
519
520 case FL_ERASING:
521 if (mode == FL_WRITING) /* FIXME: Erase-suspend-program appears broken. */
522 goto sleep;
523
524 if (!( mode == FL_READY
525 || mode == FL_POINT
526 || !cfip
527 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))
528 || (mode == FL_WRITING && (cfip->EraseSuspend & 0x1)
529 )))
530 goto sleep;
531
532 /* We could check to see if we're trying to access the sector
533 * that is currently being erased. However, no user will try
534 * anything like that so we just wait for the timeout. */
535
536 /* Erase suspend */
537 /* It's harmless to issue the Erase-Suspend and Erase-Resume
538 * commands when the erase algorithm isn't in progress. */
539 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
540 chip->oldstate = FL_ERASING;
541 chip->state = FL_ERASE_SUSPENDING;
542 chip->erase_suspended = 1;
543 for (;;) {
544 if (chip_ready(map, adr))
545 break;
546
547 if (time_after(jiffies, timeo)) {
548 /* Should have suspended the erase by now.
549 * Send an Erase-Resume command as either
550 * there was an error (so leave the erase
551 * routine to recover from it) or we trying to
552 * use the erase-in-progress sector. */
553 map_write(map, CMD(0x30), chip->in_progress_block_addr);
554 chip->state = FL_ERASING;
555 chip->oldstate = FL_READY;
556 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
557 return -EIO;
558 }
559
560 spin_unlock(chip->mutex);
561 cfi_udelay(1);
562 spin_lock(chip->mutex);
563 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
564 So we can just loop here. */
565 }
566 chip->state = FL_READY;
567 return 0;
568
569 case FL_XIP_WHILE_ERASING:
570 if (mode != FL_READY && mode != FL_POINT &&
571 (!cfip || !(cfip->EraseSuspend&2)))
572 goto sleep;
573 chip->oldstate = chip->state;
574 chip->state = FL_READY;
575 return 0;
576
577 case FL_POINT:
578 /* Only if there's no operation suspended... */
579 if (mode == FL_READY && chip->oldstate == FL_READY)
580 return 0;
581
582 default:
583 sleep:
584 set_current_state(TASK_UNINTERRUPTIBLE);
585 add_wait_queue(&chip->wq, &wait);
586 spin_unlock(chip->mutex);
587 schedule();
588 remove_wait_queue(&chip->wq, &wait);
589 spin_lock(chip->mutex);
590 goto resettime;
591 }
592 }
593
594
595 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
596 {
597 struct cfi_private *cfi = map->fldrv_priv;
598
599 switch(chip->oldstate) {
600 case FL_ERASING:
601 chip->state = chip->oldstate;
602 map_write(map, CMD(0x30), chip->in_progress_block_addr);
603 chip->oldstate = FL_READY;
604 chip->state = FL_ERASING;
605 break;
606
607 case FL_XIP_WHILE_ERASING:
608 chip->state = chip->oldstate;
609 chip->oldstate = FL_READY;
610 break;
611
612 case FL_READY:
613 case FL_STATUS:
614 /* We should really make set_vpp() count, rather than doing this */
615 DISABLE_VPP(map);
616 break;
617 default:
618 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
619 }
620 wake_up(&chip->wq);
621 }
622
623 #ifdef CONFIG_MTD_XIP
624
625 /*
626 * No interrupt what so ever can be serviced while the flash isn't in array
627 * mode. This is ensured by the xip_disable() and xip_enable() functions
628 * enclosing any code path where the flash is known not to be in array mode.
629 * And within a XIP disabled code path, only functions marked with __xipram
630 * may be called and nothing else (it's a good thing to inspect generated
631 * assembly to make sure inline functions were actually inlined and that gcc
632 * didn't emit calls to its own support functions). Also configuring MTD CFI
633 * support to a single buswidth and a single interleave is also recommended.
634 */
635
636 static void xip_disable(struct map_info *map, struct flchip *chip,
637 unsigned long adr)
638 {
639 /* TODO: chips with no XIP use should ignore and return */
640 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
641 local_irq_disable();
642 }
643
644 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
645 unsigned long adr)
646 {
647 struct cfi_private *cfi = map->fldrv_priv;
648
649 if (chip->state != FL_POINT && chip->state != FL_READY) {
650 map_write(map, CMD(0xf0), adr);
651 chip->state = FL_READY;
652 }
653 (void) map_read(map, adr);
654 xip_iprefetch();
655 local_irq_enable();
656 }
657
658 /*
659 * When a delay is required for the flash operation to complete, the
660 * xip_udelay() function is polling for both the given timeout and pending
661 * (but still masked) hardware interrupts. Whenever there is an interrupt
662 * pending then the flash erase operation is suspended, array mode restored
663 * and interrupts unmasked. Task scheduling might also happen at that
664 * point. The CPU eventually returns from the interrupt or the call to
665 * schedule() and the suspended flash operation is resumed for the remaining
666 * of the delay period.
667 *
668 * Warning: this function _will_ fool interrupt latency tracing tools.
669 */
670
671 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
672 unsigned long adr, int usec)
673 {
674 struct cfi_private *cfi = map->fldrv_priv;
675 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
676 map_word status, OK = CMD(0x80);
677 unsigned long suspended, start = xip_currtime();
678 flstate_t oldstate;
679
680 do {
681 cpu_relax();
682 if (xip_irqpending() && extp &&
683 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
684 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
685 /*
686 * Let's suspend the erase operation when supported.
687 * Note that we currently don't try to suspend
688 * interleaved chips if there is already another
689 * operation suspended (imagine what happens
690 * when one chip was already done with the current
691 * operation while another chip suspended it, then
692 * we resume the whole thing at once). Yes, it
693 * can happen!
694 */
695 map_write(map, CMD(0xb0), adr);
696 usec -= xip_elapsed_since(start);
697 suspended = xip_currtime();
698 do {
699 if (xip_elapsed_since(suspended) > 100000) {
700 /*
701 * The chip doesn't want to suspend
702 * after waiting for 100 msecs.
703 * This is a critical error but there
704 * is not much we can do here.
705 */
706 return;
707 }
708 status = map_read(map, adr);
709 } while (!map_word_andequal(map, status, OK, OK));
710
711 /* Suspend succeeded */
712 oldstate = chip->state;
713 if (!map_word_bitsset(map, status, CMD(0x40)))
714 break;
715 chip->state = FL_XIP_WHILE_ERASING;
716 chip->erase_suspended = 1;
717 map_write(map, CMD(0xf0), adr);
718 (void) map_read(map, adr);
719 asm volatile (".rep 8; nop; .endr");
720 local_irq_enable();
721 spin_unlock(chip->mutex);
722 asm volatile (".rep 8; nop; .endr");
723 cond_resched();
724
725 /*
726 * We're back. However someone else might have
727 * decided to go write to the chip if we are in
728 * a suspended erase state. If so let's wait
729 * until it's done.
730 */
731 spin_lock(chip->mutex);
732 while (chip->state != FL_XIP_WHILE_ERASING) {
733 DECLARE_WAITQUEUE(wait, current);
734 set_current_state(TASK_UNINTERRUPTIBLE);
735 add_wait_queue(&chip->wq, &wait);
736 spin_unlock(chip->mutex);
737 schedule();
738 remove_wait_queue(&chip->wq, &wait);
739 spin_lock(chip->mutex);
740 }
741 /* Disallow XIP again */
742 local_irq_disable();
743
744 /* Resume the write or erase operation */
745 map_write(map, CMD(0x30), adr);
746 chip->state = oldstate;
747 start = xip_currtime();
748 } else if (usec >= 1000000/HZ) {
749 /*
750 * Try to save on CPU power when waiting delay
751 * is at least a system timer tick period.
752 * No need to be extremely accurate here.
753 */
754 xip_cpu_idle();
755 }
756 status = map_read(map, adr);
757 } while (!map_word_andequal(map, status, OK, OK)
758 && xip_elapsed_since(start) < usec);
759 }
760
761 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
762
763 /*
764 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
765 * the flash is actively programming or erasing since we have to poll for
766 * the operation to complete anyway. We can't do that in a generic way with
767 * a XIP setup so do it before the actual flash operation in this case
768 * and stub it out from INVALIDATE_CACHE_UDELAY.
769 */
770 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
771 INVALIDATE_CACHED_RANGE(map, from, size)
772
773 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
774 UDELAY(map, chip, adr, usec)
775
776 /*
777 * Extra notes:
778 *
779 * Activating this XIP support changes the way the code works a bit. For
780 * example the code to suspend the current process when concurrent access
781 * happens is never executed because xip_udelay() will always return with the
782 * same chip state as it was entered with. This is why there is no care for
783 * the presence of add_wait_queue() or schedule() calls from within a couple
784 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
785 * The queueing and scheduling are always happening within xip_udelay().
786 *
787 * Similarly, get_chip() and put_chip() just happen to always be executed
788 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
789 * is in array mode, therefore never executing many cases therein and not
790 * causing any problem with XIP.
791 */
792
793 #else
794
795 #define xip_disable(map, chip, adr)
796 #define xip_enable(map, chip, adr)
797 #define XIP_INVAL_CACHED_RANGE(x...)
798
799 #define UDELAY(map, chip, adr, usec) \
800 do { \
801 spin_unlock(chip->mutex); \
802 cfi_udelay(usec); \
803 spin_lock(chip->mutex); \
804 } while (0)
805
806 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
807 do { \
808 spin_unlock(chip->mutex); \
809 INVALIDATE_CACHED_RANGE(map, adr, len); \
810 cfi_udelay(usec); \
811 spin_lock(chip->mutex); \
812 } while (0)
813
814 #endif
815
816 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
817 {
818 unsigned long cmd_addr;
819 struct cfi_private *cfi = map->fldrv_priv;
820 int ret;
821
822 adr += chip->start;
823
824 /* Ensure cmd read/writes are aligned. */
825 cmd_addr = adr & ~(map_bankwidth(map)-1);
826
827 spin_lock(chip->mutex);
828 ret = get_chip(map, chip, cmd_addr, FL_READY);
829 if (ret) {
830 spin_unlock(chip->mutex);
831 return ret;
832 }
833
834 if (chip->state != FL_POINT && chip->state != FL_READY) {
835 map_write(map, CMD(0xf0), cmd_addr);
836 chip->state = FL_READY;
837 }
838
839 map_copy_from(map, buf, adr, len);
840
841 put_chip(map, chip, cmd_addr);
842
843 spin_unlock(chip->mutex);
844 return 0;
845 }
846
847
848 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
849 {
850 struct map_info *map = mtd->priv;
851 struct cfi_private *cfi = map->fldrv_priv;
852 unsigned long ofs;
853 int chipnum;
854 int ret = 0;
855
856 /* ofs: offset within the first chip that the first read should start */
857
858 chipnum = (from >> cfi->chipshift);
859 ofs = from - (chipnum << cfi->chipshift);
860
861
862 *retlen = 0;
863
864 while (len) {
865 unsigned long thislen;
866
867 if (chipnum >= cfi->numchips)
868 break;
869
870 if ((len + ofs -1) >> cfi->chipshift)
871 thislen = (1<<cfi->chipshift) - ofs;
872 else
873 thislen = len;
874
875 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
876 if (ret)
877 break;
878
879 *retlen += thislen;
880 len -= thislen;
881 buf += thislen;
882
883 ofs = 0;
884 chipnum++;
885 }
886 return ret;
887 }
888
889
890 static inline int do_read_secsi_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
891 {
892 DECLARE_WAITQUEUE(wait, current);
893 unsigned long timeo = jiffies + HZ;
894 struct cfi_private *cfi = map->fldrv_priv;
895
896 retry:
897 spin_lock(chip->mutex);
898
899 if (chip->state != FL_READY){
900 #if 0
901 printk(KERN_DEBUG "Waiting for chip to read, status = %d\n", chip->state);
902 #endif
903 set_current_state(TASK_UNINTERRUPTIBLE);
904 add_wait_queue(&chip->wq, &wait);
905
906 spin_unlock(chip->mutex);
907
908 schedule();
909 remove_wait_queue(&chip->wq, &wait);
910 #if 0
911 if(signal_pending(current))
912 return -EINTR;
913 #endif
914 timeo = jiffies + HZ;
915
916 goto retry;
917 }
918
919 adr += chip->start;
920
921 chip->state = FL_READY;
922
923 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
924 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
925 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
926
927 map_copy_from(map, buf, adr, len);
928
929 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
930 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
931 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
932 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
933
934 wake_up(&chip->wq);
935 spin_unlock(chip->mutex);
936
937 return 0;
938 }
939
940 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
941 {
942 struct map_info *map = mtd->priv;
943 struct cfi_private *cfi = map->fldrv_priv;
944 unsigned long ofs;
945 int chipnum;
946 int ret = 0;
947
948
949 /* ofs: offset within the first chip that the first read should start */
950
951 /* 8 secsi bytes per chip */
952 chipnum=from>>3;
953 ofs=from & 7;
954
955
956 *retlen = 0;
957
958 while (len) {
959 unsigned long thislen;
960
961 if (chipnum >= cfi->numchips)
962 break;
963
964 if ((len + ofs -1) >> 3)
965 thislen = (1<<3) - ofs;
966 else
967 thislen = len;
968
969 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
970 if (ret)
971 break;
972
973 *retlen += thislen;
974 len -= thislen;
975 buf += thislen;
976
977 ofs = 0;
978 chipnum++;
979 }
980 return ret;
981 }
982
983
984 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip, unsigned long adr, map_word datum)
985 {
986 struct cfi_private *cfi = map->fldrv_priv;
987 unsigned long timeo = jiffies + HZ;
988 /*
989 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
990 * have a max write time of a few hundreds usec). However, we should
991 * use the maximum timeout value given by the chip at probe time
992 * instead. Unfortunately, struct flchip does have a field for
993 * maximum timeout, only for typical which can be far too short
994 * depending of the conditions. The ' + 1' is to avoid having a
995 * timeout of 0 jiffies if HZ is smaller than 1000.
996 */
997 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
998 int ret = 0;
999 map_word oldd;
1000 int retry_cnt = 0;
1001
1002 adr += chip->start;
1003
1004 spin_lock(chip->mutex);
1005 ret = get_chip(map, chip, adr, FL_WRITING);
1006 if (ret) {
1007 spin_unlock(chip->mutex);
1008 return ret;
1009 }
1010
1011 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1012 __func__, adr, datum.x[0] );
1013
1014 /*
1015 * Check for a NOP for the case when the datum to write is already
1016 * present - it saves time and works around buggy chips that corrupt
1017 * data at other locations when 0xff is written to a location that
1018 * already contains 0xff.
1019 */
1020 oldd = map_read(map, adr);
1021 if (map_word_equal(map, oldd, datum)) {
1022 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): NOP\n",
1023 __func__);
1024 goto op_done;
1025 }
1026
1027 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1028 ENABLE_VPP(map);
1029 xip_disable(map, chip, adr);
1030 retry:
1031 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1032 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1033 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1034 map_write(map, datum, adr);
1035 chip->state = FL_WRITING;
1036
1037 INVALIDATE_CACHE_UDELAY(map, chip,
1038 adr, map_bankwidth(map),
1039 chip->word_write_time);
1040
1041 /* See comment above for timeout value. */
1042 timeo = jiffies + uWriteTimeout;
1043 for (;;) {
1044 if (chip->state != FL_WRITING) {
1045 /* Someone's suspended the write. Sleep */
1046 DECLARE_WAITQUEUE(wait, current);
1047
1048 set_current_state(TASK_UNINTERRUPTIBLE);
1049 add_wait_queue(&chip->wq, &wait);
1050 spin_unlock(chip->mutex);
1051 schedule();
1052 remove_wait_queue(&chip->wq, &wait);
1053 timeo = jiffies + (HZ / 2); /* FIXME */
1054 spin_lock(chip->mutex);
1055 continue;
1056 }
1057
1058 if (time_after(jiffies, timeo) && !chip_ready(map, adr)){
1059 xip_enable(map, chip, adr);
1060 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1061 xip_disable(map, chip, adr);
1062 break;
1063 }
1064
1065 if (chip_ready(map, adr))
1066 break;
1067
1068 /* Latency issues. Drop the lock, wait a while and retry */
1069 UDELAY(map, chip, adr, 1);
1070 }
1071 /* Did we succeed? */
1072 if (!chip_good(map, adr, datum)) {
1073 /* reset on all failures. */
1074 map_write( map, CMD(0xF0), chip->start );
1075 /* FIXME - should have reset delay before continuing */
1076
1077 if (++retry_cnt <= MAX_WORD_RETRIES)
1078 goto retry;
1079
1080 ret = -EIO;
1081 }
1082 xip_enable(map, chip, adr);
1083 op_done:
1084 chip->state = FL_READY;
1085 put_chip(map, chip, adr);
1086 spin_unlock(chip->mutex);
1087
1088 return ret;
1089 }
1090
1091
1092 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1093 size_t *retlen, const u_char *buf)
1094 {
1095 struct map_info *map = mtd->priv;
1096 struct cfi_private *cfi = map->fldrv_priv;
1097 int ret = 0;
1098 int chipnum;
1099 unsigned long ofs, chipstart;
1100 DECLARE_WAITQUEUE(wait, current);
1101
1102 *retlen = 0;
1103 if (!len)
1104 return 0;
1105
1106 chipnum = to >> cfi->chipshift;
1107 ofs = to - (chipnum << cfi->chipshift);
1108 chipstart = cfi->chips[chipnum].start;
1109
1110 /* If it's not bus-aligned, do the first byte write */
1111 if (ofs & (map_bankwidth(map)-1)) {
1112 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1113 int i = ofs - bus_ofs;
1114 int n = 0;
1115 map_word tmp_buf;
1116
1117 retry:
1118 spin_lock(cfi->chips[chipnum].mutex);
1119
1120 if (cfi->chips[chipnum].state != FL_READY) {
1121 #if 0
1122 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1123 #endif
1124 set_current_state(TASK_UNINTERRUPTIBLE);
1125 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1126
1127 spin_unlock(cfi->chips[chipnum].mutex);
1128
1129 schedule();
1130 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1131 #if 0
1132 if(signal_pending(current))
1133 return -EINTR;
1134 #endif
1135 goto retry;
1136 }
1137
1138 /* Load 'tmp_buf' with old contents of flash */
1139 tmp_buf = map_read(map, bus_ofs+chipstart);
1140
1141 spin_unlock(cfi->chips[chipnum].mutex);
1142
1143 /* Number of bytes to copy from buffer */
1144 n = min_t(int, len, map_bankwidth(map)-i);
1145
1146 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1147
1148 ret = do_write_oneword(map, &cfi->chips[chipnum],
1149 bus_ofs, tmp_buf);
1150 if (ret)
1151 return ret;
1152
1153 ofs += n;
1154 buf += n;
1155 (*retlen) += n;
1156 len -= n;
1157
1158 if (ofs >> cfi->chipshift) {
1159 chipnum ++;
1160 ofs = 0;
1161 if (chipnum == cfi->numchips)
1162 return 0;
1163 }
1164 }
1165
1166 /* We are now aligned, write as much as possible */
1167 while(len >= map_bankwidth(map)) {
1168 map_word datum;
1169
1170 datum = map_word_load(map, buf);
1171
1172 ret = do_write_oneword(map, &cfi->chips[chipnum],
1173 ofs, datum);
1174 if (ret)
1175 return ret;
1176
1177 ofs += map_bankwidth(map);
1178 buf += map_bankwidth(map);
1179 (*retlen) += map_bankwidth(map);
1180 len -= map_bankwidth(map);
1181
1182 if (ofs >> cfi->chipshift) {
1183 chipnum ++;
1184 ofs = 0;
1185 if (chipnum == cfi->numchips)
1186 return 0;
1187 chipstart = cfi->chips[chipnum].start;
1188 }
1189 }
1190
1191 /* Write the trailing bytes if any */
1192 if (len & (map_bankwidth(map)-1)) {
1193 map_word tmp_buf;
1194
1195 retry1:
1196 spin_lock(cfi->chips[chipnum].mutex);
1197
1198 if (cfi->chips[chipnum].state != FL_READY) {
1199 #if 0
1200 printk(KERN_DEBUG "Waiting for chip to write, status = %d\n", cfi->chips[chipnum].state);
1201 #endif
1202 set_current_state(TASK_UNINTERRUPTIBLE);
1203 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1204
1205 spin_unlock(cfi->chips[chipnum].mutex);
1206
1207 schedule();
1208 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1209 #if 0
1210 if(signal_pending(current))
1211 return -EINTR;
1212 #endif
1213 goto retry1;
1214 }
1215
1216 tmp_buf = map_read(map, ofs + chipstart);
1217
1218 spin_unlock(cfi->chips[chipnum].mutex);
1219
1220 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1221
1222 ret = do_write_oneword(map, &cfi->chips[chipnum],
1223 ofs, tmp_buf);
1224 if (ret)
1225 return ret;
1226
1227 (*retlen) += len;
1228 }
1229
1230 return 0;
1231 }
1232
1233
1234 /*
1235 * FIXME: interleaved mode not tested, and probably not supported!
1236 */
1237 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1238 unsigned long adr, const u_char *buf,
1239 int len)
1240 {
1241 struct cfi_private *cfi = map->fldrv_priv;
1242 unsigned long timeo = jiffies + HZ;
1243 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1244 unsigned long uWriteTimeout = ( HZ / 1000 ) + 1;
1245 int ret = -EIO;
1246 unsigned long cmd_adr;
1247 int z, words;
1248 map_word datum;
1249
1250 adr += chip->start;
1251 cmd_adr = adr;
1252
1253 spin_lock(chip->mutex);
1254 ret = get_chip(map, chip, adr, FL_WRITING);
1255 if (ret) {
1256 spin_unlock(chip->mutex);
1257 return ret;
1258 }
1259
1260 datum = map_word_load(map, buf);
1261
1262 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1263 __func__, adr, datum.x[0] );
1264
1265 XIP_INVAL_CACHED_RANGE(map, adr, len);
1266 ENABLE_VPP(map);
1267 xip_disable(map, chip, cmd_adr);
1268
1269 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1270 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1271 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1272
1273 /* Write Buffer Load */
1274 map_write(map, CMD(0x25), cmd_adr);
1275
1276 chip->state = FL_WRITING_TO_BUFFER;
1277
1278 /* Write length of data to come */
1279 words = len / map_bankwidth(map);
1280 map_write(map, CMD(words - 1), cmd_adr);
1281 /* Write data */
1282 z = 0;
1283 while(z < words * map_bankwidth(map)) {
1284 datum = map_word_load(map, buf);
1285 map_write(map, datum, adr + z);
1286
1287 z += map_bankwidth(map);
1288 buf += map_bankwidth(map);
1289 }
1290 z -= map_bankwidth(map);
1291
1292 adr += z;
1293
1294 /* Write Buffer Program Confirm: GO GO GO */
1295 map_write(map, CMD(0x29), cmd_adr);
1296 chip->state = FL_WRITING;
1297
1298 INVALIDATE_CACHE_UDELAY(map, chip,
1299 adr, map_bankwidth(map),
1300 chip->word_write_time);
1301
1302 timeo = jiffies + uWriteTimeout;
1303
1304 for (;;) {
1305 if (chip->state != FL_WRITING) {
1306 /* Someone's suspended the write. Sleep */
1307 DECLARE_WAITQUEUE(wait, current);
1308
1309 set_current_state(TASK_UNINTERRUPTIBLE);
1310 add_wait_queue(&chip->wq, &wait);
1311 spin_unlock(chip->mutex);
1312 schedule();
1313 remove_wait_queue(&chip->wq, &wait);
1314 timeo = jiffies + (HZ / 2); /* FIXME */
1315 spin_lock(chip->mutex);
1316 continue;
1317 }
1318
1319 if (time_after(jiffies, timeo) && !chip_ready(map, adr))
1320 break;
1321
1322 if (chip_ready(map, adr)) {
1323 xip_enable(map, chip, adr);
1324 goto op_done;
1325 }
1326
1327 /* Latency issues. Drop the lock, wait a while and retry */
1328 UDELAY(map, chip, adr, 1);
1329 }
1330
1331 /* reset on all failures. */
1332 map_write( map, CMD(0xF0), chip->start );
1333 xip_enable(map, chip, adr);
1334 /* FIXME - should have reset delay before continuing */
1335
1336 printk(KERN_WARNING "MTD %s(): software timeout\n",
1337 __func__ );
1338
1339 ret = -EIO;
1340 op_done:
1341 chip->state = FL_READY;
1342 put_chip(map, chip, adr);
1343 spin_unlock(chip->mutex);
1344
1345 return ret;
1346 }
1347
1348
1349 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1350 size_t *retlen, const u_char *buf)
1351 {
1352 struct map_info *map = mtd->priv;
1353 struct cfi_private *cfi = map->fldrv_priv;
1354 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1355 int ret = 0;
1356 int chipnum;
1357 unsigned long ofs;
1358
1359 *retlen = 0;
1360 if (!len)
1361 return 0;
1362
1363 chipnum = to >> cfi->chipshift;
1364 ofs = to - (chipnum << cfi->chipshift);
1365
1366 /* If it's not bus-aligned, do the first word write */
1367 if (ofs & (map_bankwidth(map)-1)) {
1368 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1369 if (local_len > len)
1370 local_len = len;
1371 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1372 local_len, retlen, buf);
1373 if (ret)
1374 return ret;
1375 ofs += local_len;
1376 buf += local_len;
1377 len -= local_len;
1378
1379 if (ofs >> cfi->chipshift) {
1380 chipnum ++;
1381 ofs = 0;
1382 if (chipnum == cfi->numchips)
1383 return 0;
1384 }
1385 }
1386
1387 /* Write buffer is worth it only if more than one word to write... */
1388 while (len >= map_bankwidth(map) * 2) {
1389 /* We must not cross write block boundaries */
1390 int size = wbufsize - (ofs & (wbufsize-1));
1391
1392 if (size > len)
1393 size = len;
1394 if (size % map_bankwidth(map))
1395 size -= size % map_bankwidth(map);
1396
1397 ret = do_write_buffer(map, &cfi->chips[chipnum],
1398 ofs, buf, size);
1399 if (ret)
1400 return ret;
1401
1402 ofs += size;
1403 buf += size;
1404 (*retlen) += size;
1405 len -= size;
1406
1407 if (ofs >> cfi->chipshift) {
1408 chipnum ++;
1409 ofs = 0;
1410 if (chipnum == cfi->numchips)
1411 return 0;
1412 }
1413 }
1414
1415 if (len) {
1416 size_t retlen_dregs = 0;
1417
1418 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1419 len, &retlen_dregs, buf);
1420
1421 *retlen += retlen_dregs;
1422 return ret;
1423 }
1424
1425 return 0;
1426 }
1427
1428
1429 /*
1430 * Handle devices with one erase region, that only implement
1431 * the chip erase command.
1432 */
1433 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
1434 {
1435 struct cfi_private *cfi = map->fldrv_priv;
1436 unsigned long timeo = jiffies + HZ;
1437 unsigned long int adr;
1438 DECLARE_WAITQUEUE(wait, current);
1439 int ret = 0;
1440
1441 adr = cfi->addr_unlock1;
1442
1443 spin_lock(chip->mutex);
1444 ret = get_chip(map, chip, adr, FL_WRITING);
1445 if (ret) {
1446 spin_unlock(chip->mutex);
1447 return ret;
1448 }
1449
1450 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1451 __func__, chip->start );
1452
1453 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
1454 ENABLE_VPP(map);
1455 xip_disable(map, chip, adr);
1456
1457 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1458 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1459 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1460 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1461 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1462 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1463
1464 chip->state = FL_ERASING;
1465 chip->erase_suspended = 0;
1466 chip->in_progress_block_addr = adr;
1467
1468 INVALIDATE_CACHE_UDELAY(map, chip,
1469 adr, map->size,
1470 chip->erase_time*500);
1471
1472 timeo = jiffies + (HZ*20);
1473
1474 for (;;) {
1475 if (chip->state != FL_ERASING) {
1476 /* Someone's suspended the erase. Sleep */
1477 set_current_state(TASK_UNINTERRUPTIBLE);
1478 add_wait_queue(&chip->wq, &wait);
1479 spin_unlock(chip->mutex);
1480 schedule();
1481 remove_wait_queue(&chip->wq, &wait);
1482 spin_lock(chip->mutex);
1483 continue;
1484 }
1485 if (chip->erase_suspended) {
1486 /* This erase was suspended and resumed.
1487 Adjust the timeout */
1488 timeo = jiffies + (HZ*20); /* FIXME */
1489 chip->erase_suspended = 0;
1490 }
1491
1492 if (chip_ready(map, adr))
1493 break;
1494
1495 if (time_after(jiffies, timeo)) {
1496 printk(KERN_WARNING "MTD %s(): software timeout\n",
1497 __func__ );
1498 break;
1499 }
1500
1501 /* Latency issues. Drop the lock, wait a while and retry */
1502 UDELAY(map, chip, adr, 1000000/HZ);
1503 }
1504 /* Did we succeed? */
1505 if (!chip_good(map, adr, map_word_ff(map))) {
1506 /* reset on all failures. */
1507 map_write( map, CMD(0xF0), chip->start );
1508 /* FIXME - should have reset delay before continuing */
1509
1510 ret = -EIO;
1511 }
1512
1513 chip->state = FL_READY;
1514 xip_enable(map, chip, adr);
1515 put_chip(map, chip, adr);
1516 spin_unlock(chip->mutex);
1517
1518 return ret;
1519 }
1520
1521
1522 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
1523 {
1524 struct cfi_private *cfi = map->fldrv_priv;
1525 unsigned long timeo = jiffies + HZ;
1526 DECLARE_WAITQUEUE(wait, current);
1527 int ret = 0;
1528
1529 adr += chip->start;
1530
1531 spin_lock(chip->mutex);
1532 ret = get_chip(map, chip, adr, FL_ERASING);
1533 if (ret) {
1534 spin_unlock(chip->mutex);
1535 return ret;
1536 }
1537
1538 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): ERASE 0x%.8lx\n",
1539 __func__, adr );
1540
1541 XIP_INVAL_CACHED_RANGE(map, adr, len);
1542 ENABLE_VPP(map);
1543 xip_disable(map, chip, adr);
1544
1545 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1546 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1547 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1548 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1549 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1550 map_write(map, CMD(0x30), adr);
1551
1552 chip->state = FL_ERASING;
1553 chip->erase_suspended = 0;
1554 chip->in_progress_block_addr = adr;
1555
1556 INVALIDATE_CACHE_UDELAY(map, chip,
1557 adr, len,
1558 chip->erase_time*500);
1559
1560 timeo = jiffies + (HZ*20);
1561
1562 for (;;) {
1563 if (chip->state != FL_ERASING) {
1564 /* Someone's suspended the erase. Sleep */
1565 set_current_state(TASK_UNINTERRUPTIBLE);
1566 add_wait_queue(&chip->wq, &wait);
1567 spin_unlock(chip->mutex);
1568 schedule();
1569 remove_wait_queue(&chip->wq, &wait);
1570 spin_lock(chip->mutex);
1571 continue;
1572 }
1573 if (chip->erase_suspended) {
1574 /* This erase was suspended and resumed.
1575 Adjust the timeout */
1576 timeo = jiffies + (HZ*20); /* FIXME */
1577 chip->erase_suspended = 0;
1578 }
1579
1580 if (chip_ready(map, adr)) {
1581 xip_enable(map, chip, adr);
1582 break;
1583 }
1584
1585 if (time_after(jiffies, timeo)) {
1586 xip_enable(map, chip, adr);
1587 printk(KERN_WARNING "MTD %s(): software timeout\n",
1588 __func__ );
1589 break;
1590 }
1591
1592 /* Latency issues. Drop the lock, wait a while and retry */
1593 UDELAY(map, chip, adr, 1000000/HZ);
1594 }
1595 /* Did we succeed? */
1596 if (!chip_good(map, adr, map_word_ff(map))) {
1597 /* reset on all failures. */
1598 map_write( map, CMD(0xF0), chip->start );
1599 /* FIXME - should have reset delay before continuing */
1600
1601 ret = -EIO;
1602 }
1603
1604 chip->state = FL_READY;
1605 put_chip(map, chip, adr);
1606 spin_unlock(chip->mutex);
1607 return ret;
1608 }
1609
1610
1611 int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
1612 {
1613 unsigned long ofs, len;
1614 int ret;
1615
1616 ofs = instr->addr;
1617 len = instr->len;
1618
1619 ret = cfi_varsize_frob(mtd, do_erase_oneblock, ofs, len, NULL);
1620 if (ret)
1621 return ret;
1622
1623 instr->state = MTD_ERASE_DONE;
1624 mtd_erase_callback(instr);
1625
1626 return 0;
1627 }
1628
1629
1630 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
1631 {
1632 struct map_info *map = mtd->priv;
1633 struct cfi_private *cfi = map->fldrv_priv;
1634 int ret = 0;
1635
1636 if (instr->addr != 0)
1637 return -EINVAL;
1638
1639 if (instr->len != mtd->size)
1640 return -EINVAL;
1641
1642 ret = do_erase_chip(map, &cfi->chips[0]);
1643 if (ret)
1644 return ret;
1645
1646 instr->state = MTD_ERASE_DONE;
1647 mtd_erase_callback(instr);
1648
1649 return 0;
1650 }
1651
1652 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
1653 unsigned long adr, int len, void *thunk)
1654 {
1655 struct cfi_private *cfi = map->fldrv_priv;
1656 int ret;
1657
1658 spin_lock(chip->mutex);
1659 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
1660 if (ret)
1661 goto out_unlock;
1662 chip->state = FL_LOCKING;
1663
1664 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1665 __func__, adr, len);
1666
1667 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1668 cfi->device_type, NULL);
1669 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1670 cfi->device_type, NULL);
1671 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
1672 cfi->device_type, NULL);
1673 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1674 cfi->device_type, NULL);
1675 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1676 cfi->device_type, NULL);
1677 map_write(map, CMD(0x40), chip->start + adr);
1678
1679 chip->state = FL_READY;
1680 put_chip(map, chip, adr + chip->start);
1681 ret = 0;
1682
1683 out_unlock:
1684 spin_unlock(chip->mutex);
1685 return ret;
1686 }
1687
1688 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
1689 unsigned long adr, int len, void *thunk)
1690 {
1691 struct cfi_private *cfi = map->fldrv_priv;
1692 int ret;
1693
1694 spin_lock(chip->mutex);
1695 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
1696 if (ret)
1697 goto out_unlock;
1698 chip->state = FL_UNLOCKING;
1699
1700 DEBUG(MTD_DEBUG_LEVEL3, "MTD %s(): LOCK 0x%08lx len %d\n",
1701 __func__, adr, len);
1702
1703 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1704 cfi->device_type, NULL);
1705 map_write(map, CMD(0x70), adr);
1706
1707 chip->state = FL_READY;
1708 put_chip(map, chip, adr + chip->start);
1709 ret = 0;
1710
1711 out_unlock:
1712 spin_unlock(chip->mutex);
1713 return ret;
1714 }
1715
1716 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
1717 {
1718 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
1719 }
1720
1721 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
1722 {
1723 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
1724 }
1725
1726
1727 static void cfi_amdstd_sync (struct mtd_info *mtd)
1728 {
1729 struct map_info *map = mtd->priv;
1730 struct cfi_private *cfi = map->fldrv_priv;
1731 int i;
1732 struct flchip *chip;
1733 int ret = 0;
1734 DECLARE_WAITQUEUE(wait, current);
1735
1736 for (i=0; !ret && i<cfi->numchips; i++) {
1737 chip = &cfi->chips[i];
1738
1739 retry:
1740 spin_lock(chip->mutex);
1741
1742 switch(chip->state) {
1743 case FL_READY:
1744 case FL_STATUS:
1745 case FL_CFI_QUERY:
1746 case FL_JEDEC_QUERY:
1747 chip->oldstate = chip->state;
1748 chip->state = FL_SYNCING;
1749 /* No need to wake_up() on this state change -
1750 * as the whole point is that nobody can do anything
1751 * with the chip now anyway.
1752 */
1753 case FL_SYNCING:
1754 spin_unlock(chip->mutex);
1755 break;
1756
1757 default:
1758 /* Not an idle state */
1759 add_wait_queue(&chip->wq, &wait);
1760
1761 spin_unlock(chip->mutex);
1762
1763 schedule();
1764
1765 remove_wait_queue(&chip->wq, &wait);
1766
1767 goto retry;
1768 }
1769 }
1770
1771 /* Unlock the chips again */
1772
1773 for (i--; i >=0; i--) {
1774 chip = &cfi->chips[i];
1775
1776 spin_lock(chip->mutex);
1777
1778 if (chip->state == FL_SYNCING) {
1779 chip->state = chip->oldstate;
1780 wake_up(&chip->wq);
1781 }
1782 spin_unlock(chip->mutex);
1783 }
1784 }
1785
1786
1787 static int cfi_amdstd_suspend(struct mtd_info *mtd)
1788 {
1789 struct map_info *map = mtd->priv;
1790 struct cfi_private *cfi = map->fldrv_priv;
1791 int i;
1792 struct flchip *chip;
1793 int ret = 0;
1794
1795 for (i=0; !ret && i<cfi->numchips; i++) {
1796 chip = &cfi->chips[i];
1797
1798 spin_lock(chip->mutex);
1799
1800 switch(chip->state) {
1801 case FL_READY:
1802 case FL_STATUS:
1803 case FL_CFI_QUERY:
1804 case FL_JEDEC_QUERY:
1805 chip->oldstate = chip->state;
1806 chip->state = FL_PM_SUSPENDED;
1807 /* No need to wake_up() on this state change -
1808 * as the whole point is that nobody can do anything
1809 * with the chip now anyway.
1810 */
1811 case FL_PM_SUSPENDED:
1812 break;
1813
1814 default:
1815 ret = -EAGAIN;
1816 break;
1817 }
1818 spin_unlock(chip->mutex);
1819 }
1820
1821 /* Unlock the chips again */
1822
1823 if (ret) {
1824 for (i--; i >=0; i--) {
1825 chip = &cfi->chips[i];
1826
1827 spin_lock(chip->mutex);
1828
1829 if (chip->state == FL_PM_SUSPENDED) {
1830 chip->state = chip->oldstate;
1831 wake_up(&chip->wq);
1832 }
1833 spin_unlock(chip->mutex);
1834 }
1835 }
1836
1837 return ret;
1838 }
1839
1840
1841 static void cfi_amdstd_resume(struct mtd_info *mtd)
1842 {
1843 struct map_info *map = mtd->priv;
1844 struct cfi_private *cfi = map->fldrv_priv;
1845 int i;
1846 struct flchip *chip;
1847
1848 for (i=0; i<cfi->numchips; i++) {
1849
1850 chip = &cfi->chips[i];
1851
1852 spin_lock(chip->mutex);
1853
1854 if (chip->state == FL_PM_SUSPENDED) {
1855 chip->state = FL_READY;
1856 map_write(map, CMD(0xF0), chip->start);
1857 wake_up(&chip->wq);
1858 }
1859 else
1860 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1861
1862 spin_unlock(chip->mutex);
1863 }
1864 }
1865
1866 static void cfi_amdstd_destroy(struct mtd_info *mtd)
1867 {
1868 struct map_info *map = mtd->priv;
1869 struct cfi_private *cfi = map->fldrv_priv;
1870
1871 kfree(cfi->cmdset_priv);
1872 kfree(cfi->cfiq);
1873 kfree(cfi);
1874 kfree(mtd->eraseregions);
1875 }
1876
1877 MODULE_LICENSE("GPL");
1878 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1879 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
Linux kernel - Deliverables
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