2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
9 * 2_by_8 routines added by Simon Munton
11 * 4_by_16 work by Carolyn J. Smith
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
16 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
20 * $Id: cfi_cmdset_0002.c,v 1.122 2005/11/07 11:14:22 gleixner Exp $
24 #include <linux/module.h>
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/sched.h>
28 #include <linux/init.h>
30 #include <asm/byteorder.h>
32 #include <linux/errno.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
35 #include <linux/interrupt.h>
36 #include <linux/mtd/compatmac.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
45 #define MAX_WORD_RETRIES 3
47 #define MANUFACTURER_AMD 0x0001
48 #define MANUFACTURER_ATMEL 0x001F
49 #define MANUFACTURER_SST 0x00BF
50 #define SST49LF004B 0x0060
51 #define SST49LF040B 0x0050
52 #define SST49LF008A 0x005a
53 #define AT49BV6416 0x00d6
55 static int cfi_amdstd_read (struct mtd_info
*, loff_t
, size_t, size_t *, u_char
*);
56 static int cfi_amdstd_write_words(struct mtd_info
*, loff_t
, size_t, size_t *, const u_char
*);
57 static int cfi_amdstd_write_buffers(struct mtd_info
*, loff_t
, size_t, size_t *, const u_char
*);
58 static int cfi_amdstd_erase_chip(struct mtd_info
*, struct erase_info
*);
59 static int cfi_amdstd_erase_varsize(struct mtd_info
*, struct erase_info
*);
60 static void cfi_amdstd_sync (struct mtd_info
*);
61 static int cfi_amdstd_suspend (struct mtd_info
*);
62 static void cfi_amdstd_resume (struct mtd_info
*);
63 static int cfi_amdstd_secsi_read (struct mtd_info
*, loff_t
, size_t, size_t *, u_char
*);
65 static void cfi_amdstd_destroy(struct mtd_info
*);
67 struct mtd_info
*cfi_cmdset_0002(struct map_info
*, int);
68 static struct mtd_info
*cfi_amdstd_setup (struct mtd_info
*);
70 static int get_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int mode
);
71 static void put_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
);
74 static int cfi_atmel_lock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
);
75 static int cfi_atmel_unlock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
);
77 static struct mtd_chip_driver cfi_amdstd_chipdrv
= {
78 .probe
= NULL
, /* Not usable directly */
79 .destroy
= cfi_amdstd_destroy
,
80 .name
= "cfi_cmdset_0002",
85 /* #define DEBUG_CFI_FEATURES */
88 #ifdef DEBUG_CFI_FEATURES
89 static void cfi_tell_features(struct cfi_pri_amdstd
*extp
)
91 const char* erase_suspend
[3] = {
92 "Not supported", "Read only", "Read/write"
94 const char* top_bottom
[6] = {
95 "No WP", "8x8KiB sectors at top & bottom, no WP",
96 "Bottom boot", "Top boot",
97 "Uniform, Bottom WP", "Uniform, Top WP"
100 printk(" Silicon revision: %d\n", extp
->SiliconRevision
>> 1);
101 printk(" Address sensitive unlock: %s\n",
102 (extp
->SiliconRevision
& 1) ? "Not required" : "Required");
104 if (extp
->EraseSuspend
< ARRAY_SIZE(erase_suspend
))
105 printk(" Erase Suspend: %s\n", erase_suspend
[extp
->EraseSuspend
]);
107 printk(" Erase Suspend: Unknown value %d\n", extp
->EraseSuspend
);
109 if (extp
->BlkProt
== 0)
110 printk(" Block protection: Not supported\n");
112 printk(" Block protection: %d sectors per group\n", extp
->BlkProt
);
115 printk(" Temporary block unprotect: %s\n",
116 extp
->TmpBlkUnprotect
? "Supported" : "Not supported");
117 printk(" Block protect/unprotect scheme: %d\n", extp
->BlkProtUnprot
);
118 printk(" Number of simultaneous operations: %d\n", extp
->SimultaneousOps
);
119 printk(" Burst mode: %s\n",
120 extp
->BurstMode
? "Supported" : "Not supported");
121 if (extp
->PageMode
== 0)
122 printk(" Page mode: Not supported\n");
124 printk(" Page mode: %d word page\n", extp
->PageMode
<< 2);
126 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
127 extp
->VppMin
>> 4, extp
->VppMin
& 0xf);
128 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
129 extp
->VppMax
>> 4, extp
->VppMax
& 0xf);
131 if (extp
->TopBottom
< ARRAY_SIZE(top_bottom
))
132 printk(" Top/Bottom Boot Block: %s\n", top_bottom
[extp
->TopBottom
]);
134 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp
->TopBottom
);
138 #ifdef AMD_BOOTLOC_BUG
139 /* Wheee. Bring me the head of someone at AMD. */
140 static void fixup_amd_bootblock(struct mtd_info
*mtd
, void* param
)
142 struct map_info
*map
= mtd
->priv
;
143 struct cfi_private
*cfi
= map
->fldrv_priv
;
144 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
145 __u8 major
= extp
->MajorVersion
;
146 __u8 minor
= extp
->MinorVersion
;
148 if (((major
<< 8) | minor
) < 0x3131) {
149 /* CFI version 1.0 => don't trust bootloc */
150 if (cfi
->id
& 0x80) {
151 printk(KERN_WARNING
"%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map
->name
, cfi
->id
);
152 extp
->TopBottom
= 3; /* top boot */
154 extp
->TopBottom
= 2; /* bottom boot */
160 static void fixup_use_write_buffers(struct mtd_info
*mtd
, void *param
)
162 struct map_info
*map
= mtd
->priv
;
163 struct cfi_private
*cfi
= map
->fldrv_priv
;
164 if (cfi
->cfiq
->BufWriteTimeoutTyp
) {
165 DEBUG(MTD_DEBUG_LEVEL1
, "Using buffer write method\n" );
166 mtd
->write
= cfi_amdstd_write_buffers
;
170 /* Atmel chips don't use the same PRI format as AMD chips */
171 static void fixup_convert_atmel_pri(struct mtd_info
*mtd
, void *param
)
173 struct map_info
*map
= mtd
->priv
;
174 struct cfi_private
*cfi
= map
->fldrv_priv
;
175 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
176 struct cfi_pri_atmel atmel_pri
;
178 memcpy(&atmel_pri
, extp
, sizeof(atmel_pri
));
179 memset((char *)extp
+ 5, 0, sizeof(*extp
) - 5);
181 if (atmel_pri
.Features
& 0x02)
182 extp
->EraseSuspend
= 2;
184 if (atmel_pri
.BottomBoot
)
190 static void fixup_use_secsi(struct mtd_info
*mtd
, void *param
)
192 /* Setup for chips with a secsi area */
193 mtd
->read_user_prot_reg
= cfi_amdstd_secsi_read
;
194 mtd
->read_fact_prot_reg
= cfi_amdstd_secsi_read
;
197 static void fixup_use_erase_chip(struct mtd_info
*mtd
, void *param
)
199 struct map_info
*map
= mtd
->priv
;
200 struct cfi_private
*cfi
= map
->fldrv_priv
;
201 if ((cfi
->cfiq
->NumEraseRegions
== 1) &&
202 ((cfi
->cfiq
->EraseRegionInfo
[0] & 0xffff) == 0)) {
203 mtd
->erase
= cfi_amdstd_erase_chip
;
209 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
212 static void fixup_use_atmel_lock(struct mtd_info
*mtd
, void *param
)
214 mtd
->lock
= cfi_atmel_lock
;
215 mtd
->unlock
= cfi_atmel_unlock
;
216 mtd
->flags
|= MTD_STUPID_LOCK
;
219 static struct cfi_fixup cfi_fixup_table
[] = {
220 #ifdef AMD_BOOTLOC_BUG
221 { CFI_MFR_AMD
, CFI_ID_ANY
, fixup_amd_bootblock
, NULL
},
223 { CFI_MFR_AMD
, 0x0050, fixup_use_secsi
, NULL
, },
224 { CFI_MFR_AMD
, 0x0053, fixup_use_secsi
, NULL
, },
225 { CFI_MFR_AMD
, 0x0055, fixup_use_secsi
, NULL
, },
226 { CFI_MFR_AMD
, 0x0056, fixup_use_secsi
, NULL
, },
227 { CFI_MFR_AMD
, 0x005C, fixup_use_secsi
, NULL
, },
228 { CFI_MFR_AMD
, 0x005F, fixup_use_secsi
, NULL
, },
229 #if !FORCE_WORD_WRITE
230 { CFI_MFR_ANY
, CFI_ID_ANY
, fixup_use_write_buffers
, NULL
, },
232 { CFI_MFR_ATMEL
, CFI_ID_ANY
, fixup_convert_atmel_pri
, NULL
},
235 static struct cfi_fixup jedec_fixup_table
[] = {
236 { MANUFACTURER_SST
, SST49LF004B
, fixup_use_fwh_lock
, NULL
, },
237 { MANUFACTURER_SST
, SST49LF040B
, fixup_use_fwh_lock
, NULL
, },
238 { MANUFACTURER_SST
, SST49LF008A
, fixup_use_fwh_lock
, NULL
, },
242 static struct cfi_fixup fixup_table
[] = {
243 /* The CFI vendor ids and the JEDEC vendor IDs appear
244 * to be common. It is like the devices id's are as
245 * well. This table is to pick all cases where
246 * we know that is the case.
248 { CFI_MFR_ANY
, CFI_ID_ANY
, fixup_use_erase_chip
, NULL
},
249 { CFI_MFR_ATMEL
, AT49BV6416
, fixup_use_atmel_lock
, NULL
},
254 struct mtd_info
*cfi_cmdset_0002(struct map_info
*map
, int primary
)
256 struct cfi_private
*cfi
= map
->fldrv_priv
;
257 struct mtd_info
*mtd
;
260 mtd
= kzalloc(sizeof(*mtd
), GFP_KERNEL
);
262 printk(KERN_WARNING
"Failed to allocate memory for MTD device\n");
266 mtd
->type
= MTD_NORFLASH
;
268 /* Fill in the default mtd operations */
269 mtd
->erase
= cfi_amdstd_erase_varsize
;
270 mtd
->write
= cfi_amdstd_write_words
;
271 mtd
->read
= cfi_amdstd_read
;
272 mtd
->sync
= cfi_amdstd_sync
;
273 mtd
->suspend
= cfi_amdstd_suspend
;
274 mtd
->resume
= cfi_amdstd_resume
;
275 mtd
->flags
= MTD_CAP_NORFLASH
;
276 mtd
->name
= map
->name
;
279 if (cfi
->cfi_mode
==CFI_MODE_CFI
){
280 unsigned char bootloc
;
282 * It's a real CFI chip, not one for which the probe
283 * routine faked a CFI structure. So we read the feature
286 __u16 adr
= primary
?cfi
->cfiq
->P_ADR
:cfi
->cfiq
->A_ADR
;
287 struct cfi_pri_amdstd
*extp
;
289 extp
= (struct cfi_pri_amdstd
*)cfi_read_pri(map
, adr
, sizeof(*extp
), "Amd/Fujitsu");
295 if (extp
->MajorVersion
!= '1' ||
296 (extp
->MinorVersion
< '0' || extp
->MinorVersion
> '4')) {
297 printk(KERN_ERR
" Unknown Amd/Fujitsu Extended Query "
298 "version %c.%c.\n", extp
->MajorVersion
,
305 /* Install our own private info structure */
306 cfi
->cmdset_priv
= extp
;
308 /* Apply cfi device specific fixups */
309 cfi_fixup(mtd
, cfi_fixup_table
);
311 #ifdef DEBUG_CFI_FEATURES
312 /* Tell the user about it in lots of lovely detail */
313 cfi_tell_features(extp
);
316 bootloc
= extp
->TopBottom
;
317 if ((bootloc
!= 2) && (bootloc
!= 3)) {
318 printk(KERN_WARNING
"%s: CFI does not contain boot "
319 "bank location. Assuming top.\n", map
->name
);
323 if (bootloc
== 3 && cfi
->cfiq
->NumEraseRegions
> 1) {
324 printk(KERN_WARNING
"%s: Swapping erase regions for broken CFI table.\n", map
->name
);
326 for (i
=0; i
<cfi
->cfiq
->NumEraseRegions
/ 2; i
++) {
327 int j
= (cfi
->cfiq
->NumEraseRegions
-1)-i
;
330 swap
= cfi
->cfiq
->EraseRegionInfo
[i
];
331 cfi
->cfiq
->EraseRegionInfo
[i
] = cfi
->cfiq
->EraseRegionInfo
[j
];
332 cfi
->cfiq
->EraseRegionInfo
[j
] = swap
;
335 /* Set the default CFI lock/unlock addresses */
336 cfi
->addr_unlock1
= 0x555;
337 cfi
->addr_unlock2
= 0x2aa;
338 /* Modify the unlock address if we are in compatibility mode */
339 if ( /* x16 in x8 mode */
340 ((cfi
->device_type
== CFI_DEVICETYPE_X8
) &&
341 (cfi
->cfiq
->InterfaceDesc
== 2)) ||
342 /* x32 in x16 mode */
343 ((cfi
->device_type
== CFI_DEVICETYPE_X16
) &&
344 (cfi
->cfiq
->InterfaceDesc
== 4)))
346 cfi
->addr_unlock1
= 0xaaa;
347 cfi
->addr_unlock2
= 0x555;
351 else if (cfi
->cfi_mode
== CFI_MODE_JEDEC
) {
352 /* Apply jedec specific fixups */
353 cfi_fixup(mtd
, jedec_fixup_table
);
355 /* Apply generic fixups */
356 cfi_fixup(mtd
, fixup_table
);
358 for (i
=0; i
< cfi
->numchips
; i
++) {
359 cfi
->chips
[i
].word_write_time
= 1<<cfi
->cfiq
->WordWriteTimeoutTyp
;
360 cfi
->chips
[i
].buffer_write_time
= 1<<cfi
->cfiq
->BufWriteTimeoutTyp
;
361 cfi
->chips
[i
].erase_time
= 1<<cfi
->cfiq
->BlockEraseTimeoutTyp
;
364 map
->fldrv
= &cfi_amdstd_chipdrv
;
366 return cfi_amdstd_setup(mtd
);
368 EXPORT_SYMBOL_GPL(cfi_cmdset_0002
);
370 static struct mtd_info
*cfi_amdstd_setup(struct mtd_info
*mtd
)
372 struct map_info
*map
= mtd
->priv
;
373 struct cfi_private
*cfi
= map
->fldrv_priv
;
374 unsigned long devsize
= (1<<cfi
->cfiq
->DevSize
) * cfi
->interleave
;
375 unsigned long offset
= 0;
378 printk(KERN_NOTICE
"number of %s chips: %d\n",
379 (cfi
->cfi_mode
== CFI_MODE_CFI
)?"CFI":"JEDEC",cfi
->numchips
);
380 /* Select the correct geometry setup */
381 mtd
->size
= devsize
* cfi
->numchips
;
383 mtd
->numeraseregions
= cfi
->cfiq
->NumEraseRegions
* cfi
->numchips
;
384 mtd
->eraseregions
= kmalloc(sizeof(struct mtd_erase_region_info
)
385 * mtd
->numeraseregions
, GFP_KERNEL
);
386 if (!mtd
->eraseregions
) {
387 printk(KERN_WARNING
"Failed to allocate memory for MTD erase region info\n");
391 for (i
=0; i
<cfi
->cfiq
->NumEraseRegions
; i
++) {
392 unsigned long ernum
, ersize
;
393 ersize
= ((cfi
->cfiq
->EraseRegionInfo
[i
] >> 8) & ~0xff) * cfi
->interleave
;
394 ernum
= (cfi
->cfiq
->EraseRegionInfo
[i
] & 0xffff) + 1;
396 if (mtd
->erasesize
< ersize
) {
397 mtd
->erasesize
= ersize
;
399 for (j
=0; j
<cfi
->numchips
; j
++) {
400 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].offset
= (j
*devsize
)+offset
;
401 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].erasesize
= ersize
;
402 mtd
->eraseregions
[(j
*cfi
->cfiq
->NumEraseRegions
)+i
].numblocks
= ernum
;
404 offset
+= (ersize
* ernum
);
406 if (offset
!= devsize
) {
408 printk(KERN_WARNING
"Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset
, devsize
);
413 for (i
=0; i
<mtd
->numeraseregions
;i
++){
414 printk("%d: offset=0x%x,size=0x%x,blocks=%d\n",
415 i
,mtd
->eraseregions
[i
].offset
,
416 mtd
->eraseregions
[i
].erasesize
,
417 mtd
->eraseregions
[i
].numblocks
);
421 /* FIXME: erase-suspend-program is broken. See
422 http://lists.infradead.org/pipermail/linux-mtd/2003-December/009001.html */
423 printk(KERN_NOTICE
"cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness.\n");
425 __module_get(THIS_MODULE
);
430 kfree(mtd
->eraseregions
);
433 kfree(cfi
->cmdset_priv
);
439 * Return true if the chip is ready.
441 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
442 * non-suspended sector) and is indicated by no toggle bits toggling.
444 * Note that anything more complicated than checking if no bits are toggling
445 * (including checking DQ5 for an error status) is tricky to get working
446 * correctly and is therefore not done (particulary with interleaved chips
447 * as each chip must be checked independantly of the others).
449 static int __xipram
chip_ready(struct map_info
*map
, unsigned long addr
)
453 d
= map_read(map
, addr
);
454 t
= map_read(map
, addr
);
456 return map_word_equal(map
, d
, t
);
460 * Return true if the chip is ready and has the correct value.
462 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
463 * non-suspended sector) and it is indicated by no bits toggling.
465 * Error are indicated by toggling bits or bits held with the wrong value,
466 * or with bits toggling.
468 * Note that anything more complicated than checking if no bits are toggling
469 * (including checking DQ5 for an error status) is tricky to get working
470 * correctly and is therefore not done (particulary with interleaved chips
471 * as each chip must be checked independantly of the others).
474 static int __xipram
chip_good(struct map_info
*map
, unsigned long addr
, map_word expected
)
478 oldd
= map_read(map
, addr
);
479 curd
= map_read(map
, addr
);
481 return map_word_equal(map
, oldd
, curd
) &&
482 map_word_equal(map
, curd
, expected
);
485 static int get_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int mode
)
487 DECLARE_WAITQUEUE(wait
, current
);
488 struct cfi_private
*cfi
= map
->fldrv_priv
;
490 struct cfi_pri_amdstd
*cfip
= (struct cfi_pri_amdstd
*)cfi
->cmdset_priv
;
493 timeo
= jiffies
+ HZ
;
495 switch (chip
->state
) {
499 if (chip_ready(map
, adr
))
502 if (time_after(jiffies
, timeo
)) {
503 printk(KERN_ERR
"Waiting for chip to be ready timed out.\n");
504 spin_unlock(chip
->mutex
);
507 spin_unlock(chip
->mutex
);
509 spin_lock(chip
->mutex
);
510 /* Someone else might have been playing with it. */
520 if (mode
== FL_WRITING
) /* FIXME: Erase-suspend-program appears broken. */
523 if (!( mode
== FL_READY
526 || (mode
== FL_WRITING
&& (cfip
->EraseSuspend
& 0x2))
527 || (mode
== FL_WRITING
&& (cfip
->EraseSuspend
& 0x1)
531 /* We could check to see if we're trying to access the sector
532 * that is currently being erased. However, no user will try
533 * anything like that so we just wait for the timeout. */
536 /* It's harmless to issue the Erase-Suspend and Erase-Resume
537 * commands when the erase algorithm isn't in progress. */
538 map_write(map
, CMD(0xB0), chip
->in_progress_block_addr
);
539 chip
->oldstate
= FL_ERASING
;
540 chip
->state
= FL_ERASE_SUSPENDING
;
541 chip
->erase_suspended
= 1;
543 if (chip_ready(map
, adr
))
546 if (time_after(jiffies
, timeo
)) {
547 /* Should have suspended the erase by now.
548 * Send an Erase-Resume command as either
549 * there was an error (so leave the erase
550 * routine to recover from it) or we trying to
551 * use the erase-in-progress sector. */
552 map_write(map
, CMD(0x30), chip
->in_progress_block_addr
);
553 chip
->state
= FL_ERASING
;
554 chip
->oldstate
= FL_READY
;
555 printk(KERN_ERR
"MTD %s(): chip not ready after erase suspend\n", __func__
);
559 spin_unlock(chip
->mutex
);
561 spin_lock(chip
->mutex
);
562 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
563 So we can just loop here. */
565 chip
->state
= FL_READY
;
568 case FL_XIP_WHILE_ERASING
:
569 if (mode
!= FL_READY
&& mode
!= FL_POINT
&&
570 (!cfip
|| !(cfip
->EraseSuspend
&2)))
572 chip
->oldstate
= chip
->state
;
573 chip
->state
= FL_READY
;
577 /* Only if there's no operation suspended... */
578 if (mode
== FL_READY
&& chip
->oldstate
== FL_READY
)
583 set_current_state(TASK_UNINTERRUPTIBLE
);
584 add_wait_queue(&chip
->wq
, &wait
);
585 spin_unlock(chip
->mutex
);
587 remove_wait_queue(&chip
->wq
, &wait
);
588 spin_lock(chip
->mutex
);
594 static void put_chip(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
)
596 struct cfi_private
*cfi
= map
->fldrv_priv
;
598 switch(chip
->oldstate
) {
600 chip
->state
= chip
->oldstate
;
601 map_write(map
, CMD(0x30), chip
->in_progress_block_addr
);
602 chip
->oldstate
= FL_READY
;
603 chip
->state
= FL_ERASING
;
606 case FL_XIP_WHILE_ERASING
:
607 chip
->state
= chip
->oldstate
;
608 chip
->oldstate
= FL_READY
;
613 /* We should really make set_vpp() count, rather than doing this */
617 printk(KERN_ERR
"MTD: put_chip() called with oldstate %d!!\n", chip
->oldstate
);
622 #ifdef CONFIG_MTD_XIP
625 * No interrupt what so ever can be serviced while the flash isn't in array
626 * mode. This is ensured by the xip_disable() and xip_enable() functions
627 * enclosing any code path where the flash is known not to be in array mode.
628 * And within a XIP disabled code path, only functions marked with __xipram
629 * may be called and nothing else (it's a good thing to inspect generated
630 * assembly to make sure inline functions were actually inlined and that gcc
631 * didn't emit calls to its own support functions). Also configuring MTD CFI
632 * support to a single buswidth and a single interleave is also recommended.
635 static void xip_disable(struct map_info
*map
, struct flchip
*chip
,
638 /* TODO: chips with no XIP use should ignore and return */
639 (void) map_read(map
, adr
); /* ensure mmu mapping is up to date */
643 static void __xipram
xip_enable(struct map_info
*map
, struct flchip
*chip
,
646 struct cfi_private
*cfi
= map
->fldrv_priv
;
648 if (chip
->state
!= FL_POINT
&& chip
->state
!= FL_READY
) {
649 map_write(map
, CMD(0xf0), adr
);
650 chip
->state
= FL_READY
;
652 (void) map_read(map
, adr
);
658 * When a delay is required for the flash operation to complete, the
659 * xip_udelay() function is polling for both the given timeout and pending
660 * (but still masked) hardware interrupts. Whenever there is an interrupt
661 * pending then the flash erase operation is suspended, array mode restored
662 * and interrupts unmasked. Task scheduling might also happen at that
663 * point. The CPU eventually returns from the interrupt or the call to
664 * schedule() and the suspended flash operation is resumed for the remaining
665 * of the delay period.
667 * Warning: this function _will_ fool interrupt latency tracing tools.
670 static void __xipram
xip_udelay(struct map_info
*map
, struct flchip
*chip
,
671 unsigned long adr
, int usec
)
673 struct cfi_private
*cfi
= map
->fldrv_priv
;
674 struct cfi_pri_amdstd
*extp
= cfi
->cmdset_priv
;
675 map_word status
, OK
= CMD(0x80);
676 unsigned long suspended
, start
= xip_currtime();
681 if (xip_irqpending() && extp
&&
682 ((chip
->state
== FL_ERASING
&& (extp
->EraseSuspend
& 2))) &&
683 (cfi_interleave_is_1(cfi
) || chip
->oldstate
== FL_READY
)) {
685 * Let's suspend the erase operation when supported.
686 * Note that we currently don't try to suspend
687 * interleaved chips if there is already another
688 * operation suspended (imagine what happens
689 * when one chip was already done with the current
690 * operation while another chip suspended it, then
691 * we resume the whole thing at once). Yes, it
694 map_write(map
, CMD(0xb0), adr
);
695 usec
-= xip_elapsed_since(start
);
696 suspended
= xip_currtime();
698 if (xip_elapsed_since(suspended
) > 100000) {
700 * The chip doesn't want to suspend
701 * after waiting for 100 msecs.
702 * This is a critical error but there
703 * is not much we can do here.
707 status
= map_read(map
, adr
);
708 } while (!map_word_andequal(map
, status
, OK
, OK
));
710 /* Suspend succeeded */
711 oldstate
= chip
->state
;
712 if (!map_word_bitsset(map
, status
, CMD(0x40)))
714 chip
->state
= FL_XIP_WHILE_ERASING
;
715 chip
->erase_suspended
= 1;
716 map_write(map
, CMD(0xf0), adr
);
717 (void) map_read(map
, adr
);
718 asm volatile (".rep 8; nop; .endr");
720 spin_unlock(chip
->mutex
);
721 asm volatile (".rep 8; nop; .endr");
725 * We're back. However someone else might have
726 * decided to go write to the chip if we are in
727 * a suspended erase state. If so let's wait
730 spin_lock(chip
->mutex
);
731 while (chip
->state
!= FL_XIP_WHILE_ERASING
) {
732 DECLARE_WAITQUEUE(wait
, current
);
733 set_current_state(TASK_UNINTERRUPTIBLE
);
734 add_wait_queue(&chip
->wq
, &wait
);
735 spin_unlock(chip
->mutex
);
737 remove_wait_queue(&chip
->wq
, &wait
);
738 spin_lock(chip
->mutex
);
740 /* Disallow XIP again */
743 /* Resume the write or erase operation */
744 map_write(map
, CMD(0x30), adr
);
745 chip
->state
= oldstate
;
746 start
= xip_currtime();
747 } else if (usec
>= 1000000/HZ
) {
749 * Try to save on CPU power when waiting delay
750 * is at least a system timer tick period.
751 * No need to be extremely accurate here.
755 status
= map_read(map
, adr
);
756 } while (!map_word_andequal(map
, status
, OK
, OK
)
757 && xip_elapsed_since(start
) < usec
);
760 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
763 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
764 * the flash is actively programming or erasing since we have to poll for
765 * the operation to complete anyway. We can't do that in a generic way with
766 * a XIP setup so do it before the actual flash operation in this case
767 * and stub it out from INVALIDATE_CACHE_UDELAY.
769 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
770 INVALIDATE_CACHED_RANGE(map, from, size)
772 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
773 UDELAY(map, chip, adr, usec)
778 * Activating this XIP support changes the way the code works a bit. For
779 * example the code to suspend the current process when concurrent access
780 * happens is never executed because xip_udelay() will always return with the
781 * same chip state as it was entered with. This is why there is no care for
782 * the presence of add_wait_queue() or schedule() calls from within a couple
783 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
784 * The queueing and scheduling are always happening within xip_udelay().
786 * Similarly, get_chip() and put_chip() just happen to always be executed
787 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
788 * is in array mode, therefore never executing many cases therein and not
789 * causing any problem with XIP.
794 #define xip_disable(map, chip, adr)
795 #define xip_enable(map, chip, adr)
796 #define XIP_INVAL_CACHED_RANGE(x...)
798 #define UDELAY(map, chip, adr, usec) \
800 spin_unlock(chip->mutex); \
802 spin_lock(chip->mutex); \
805 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
807 spin_unlock(chip->mutex); \
808 INVALIDATE_CACHED_RANGE(map, adr, len); \
810 spin_lock(chip->mutex); \
815 static inline int do_read_onechip(struct map_info
*map
, struct flchip
*chip
, loff_t adr
, size_t len
, u_char
*buf
)
817 unsigned long cmd_addr
;
818 struct cfi_private
*cfi
= map
->fldrv_priv
;
823 /* Ensure cmd read/writes are aligned. */
824 cmd_addr
= adr
& ~(map_bankwidth(map
)-1);
826 spin_lock(chip
->mutex
);
827 ret
= get_chip(map
, chip
, cmd_addr
, FL_READY
);
829 spin_unlock(chip
->mutex
);
833 if (chip
->state
!= FL_POINT
&& chip
->state
!= FL_READY
) {
834 map_write(map
, CMD(0xf0), cmd_addr
);
835 chip
->state
= FL_READY
;
838 map_copy_from(map
, buf
, adr
, len
);
840 put_chip(map
, chip
, cmd_addr
);
842 spin_unlock(chip
->mutex
);
847 static int cfi_amdstd_read (struct mtd_info
*mtd
, loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
849 struct map_info
*map
= mtd
->priv
;
850 struct cfi_private
*cfi
= map
->fldrv_priv
;
855 /* ofs: offset within the first chip that the first read should start */
857 chipnum
= (from
>> cfi
->chipshift
);
858 ofs
= from
- (chipnum
<< cfi
->chipshift
);
864 unsigned long thislen
;
866 if (chipnum
>= cfi
->numchips
)
869 if ((len
+ ofs
-1) >> cfi
->chipshift
)
870 thislen
= (1<<cfi
->chipshift
) - ofs
;
874 ret
= do_read_onechip(map
, &cfi
->chips
[chipnum
], ofs
, thislen
, buf
);
889 static inline int do_read_secsi_onechip(struct map_info
*map
, struct flchip
*chip
, loff_t adr
, size_t len
, u_char
*buf
)
891 DECLARE_WAITQUEUE(wait
, current
);
892 unsigned long timeo
= jiffies
+ HZ
;
893 struct cfi_private
*cfi
= map
->fldrv_priv
;
896 spin_lock(chip
->mutex
);
898 if (chip
->state
!= FL_READY
){
900 printk(KERN_DEBUG
"Waiting for chip to read, status = %d\n", chip
->state
);
902 set_current_state(TASK_UNINTERRUPTIBLE
);
903 add_wait_queue(&chip
->wq
, &wait
);
905 spin_unlock(chip
->mutex
);
908 remove_wait_queue(&chip
->wq
, &wait
);
910 if(signal_pending(current
))
913 timeo
= jiffies
+ HZ
;
920 chip
->state
= FL_READY
;
922 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
923 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
924 cfi_send_gen_cmd(0x88, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
926 map_copy_from(map
, buf
, adr
, len
);
928 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
929 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
930 cfi_send_gen_cmd(0x90, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
931 cfi_send_gen_cmd(0x00, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
934 spin_unlock(chip
->mutex
);
939 static int cfi_amdstd_secsi_read (struct mtd_info
*mtd
, loff_t from
, size_t len
, size_t *retlen
, u_char
*buf
)
941 struct map_info
*map
= mtd
->priv
;
942 struct cfi_private
*cfi
= map
->fldrv_priv
;
948 /* ofs: offset within the first chip that the first read should start */
950 /* 8 secsi bytes per chip */
958 unsigned long thislen
;
960 if (chipnum
>= cfi
->numchips
)
963 if ((len
+ ofs
-1) >> 3)
964 thislen
= (1<<3) - ofs
;
968 ret
= do_read_secsi_onechip(map
, &cfi
->chips
[chipnum
], ofs
, thislen
, buf
);
983 static int __xipram
do_write_oneword(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, map_word datum
)
985 struct cfi_private
*cfi
= map
->fldrv_priv
;
986 unsigned long timeo
= jiffies
+ HZ
;
988 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
989 * have a max write time of a few hundreds usec). However, we should
990 * use the maximum timeout value given by the chip at probe time
991 * instead. Unfortunately, struct flchip does have a field for
992 * maximum timeout, only for typical which can be far too short
993 * depending of the conditions. The ' + 1' is to avoid having a
994 * timeout of 0 jiffies if HZ is smaller than 1000.
996 unsigned long uWriteTimeout
= ( HZ
/ 1000 ) + 1;
1003 spin_lock(chip
->mutex
);
1004 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1006 spin_unlock(chip
->mutex
);
1010 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1011 __func__
, adr
, datum
.x
[0] );
1014 * Check for a NOP for the case when the datum to write is already
1015 * present - it saves time and works around buggy chips that corrupt
1016 * data at other locations when 0xff is written to a location that
1017 * already contains 0xff.
1019 oldd
= map_read(map
, adr
);
1020 if (map_word_equal(map
, oldd
, datum
)) {
1021 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): NOP\n",
1026 XIP_INVAL_CACHED_RANGE(map
, adr
, map_bankwidth(map
));
1028 xip_disable(map
, chip
, adr
);
1030 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1031 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1032 cfi_send_gen_cmd(0xA0, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1033 map_write(map
, datum
, adr
);
1034 chip
->state
= FL_WRITING
;
1036 INVALIDATE_CACHE_UDELAY(map
, chip
,
1037 adr
, map_bankwidth(map
),
1038 chip
->word_write_time
);
1040 /* See comment above for timeout value. */
1041 timeo
= jiffies
+ uWriteTimeout
;
1043 if (chip
->state
!= FL_WRITING
) {
1044 /* Someone's suspended the write. Sleep */
1045 DECLARE_WAITQUEUE(wait
, current
);
1047 set_current_state(TASK_UNINTERRUPTIBLE
);
1048 add_wait_queue(&chip
->wq
, &wait
);
1049 spin_unlock(chip
->mutex
);
1051 remove_wait_queue(&chip
->wq
, &wait
);
1052 timeo
= jiffies
+ (HZ
/ 2); /* FIXME */
1053 spin_lock(chip
->mutex
);
1057 if (time_after(jiffies
, timeo
) && !chip_ready(map
, adr
)){
1058 xip_enable(map
, chip
, adr
);
1059 printk(KERN_WARNING
"MTD %s(): software timeout\n", __func__
);
1060 xip_disable(map
, chip
, adr
);
1064 if (chip_ready(map
, adr
))
1067 /* Latency issues. Drop the lock, wait a while and retry */
1068 UDELAY(map
, chip
, adr
, 1);
1070 /* Did we succeed? */
1071 if (!chip_good(map
, adr
, datum
)) {
1072 /* reset on all failures. */
1073 map_write( map
, CMD(0xF0), chip
->start
);
1074 /* FIXME - should have reset delay before continuing */
1076 if (++retry_cnt
<= MAX_WORD_RETRIES
)
1081 xip_enable(map
, chip
, adr
);
1083 chip
->state
= FL_READY
;
1084 put_chip(map
, chip
, adr
);
1085 spin_unlock(chip
->mutex
);
1091 static int cfi_amdstd_write_words(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1092 size_t *retlen
, const u_char
*buf
)
1094 struct map_info
*map
= mtd
->priv
;
1095 struct cfi_private
*cfi
= map
->fldrv_priv
;
1098 unsigned long ofs
, chipstart
;
1099 DECLARE_WAITQUEUE(wait
, current
);
1105 chipnum
= to
>> cfi
->chipshift
;
1106 ofs
= to
- (chipnum
<< cfi
->chipshift
);
1107 chipstart
= cfi
->chips
[chipnum
].start
;
1109 /* If it's not bus-aligned, do the first byte write */
1110 if (ofs
& (map_bankwidth(map
)-1)) {
1111 unsigned long bus_ofs
= ofs
& ~(map_bankwidth(map
)-1);
1112 int i
= ofs
- bus_ofs
;
1117 spin_lock(cfi
->chips
[chipnum
].mutex
);
1119 if (cfi
->chips
[chipnum
].state
!= FL_READY
) {
1121 printk(KERN_DEBUG
"Waiting for chip to write, status = %d\n", cfi
->chips
[chipnum
].state
);
1123 set_current_state(TASK_UNINTERRUPTIBLE
);
1124 add_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1126 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1129 remove_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1131 if(signal_pending(current
))
1137 /* Load 'tmp_buf' with old contents of flash */
1138 tmp_buf
= map_read(map
, bus_ofs
+chipstart
);
1140 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1142 /* Number of bytes to copy from buffer */
1143 n
= min_t(int, len
, map_bankwidth(map
)-i
);
1145 tmp_buf
= map_word_load_partial(map
, tmp_buf
, buf
, i
, n
);
1147 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1157 if (ofs
>> cfi
->chipshift
) {
1160 if (chipnum
== cfi
->numchips
)
1165 /* We are now aligned, write as much as possible */
1166 while(len
>= map_bankwidth(map
)) {
1169 datum
= map_word_load(map
, buf
);
1171 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1176 ofs
+= map_bankwidth(map
);
1177 buf
+= map_bankwidth(map
);
1178 (*retlen
) += map_bankwidth(map
);
1179 len
-= map_bankwidth(map
);
1181 if (ofs
>> cfi
->chipshift
) {
1184 if (chipnum
== cfi
->numchips
)
1186 chipstart
= cfi
->chips
[chipnum
].start
;
1190 /* Write the trailing bytes if any */
1191 if (len
& (map_bankwidth(map
)-1)) {
1195 spin_lock(cfi
->chips
[chipnum
].mutex
);
1197 if (cfi
->chips
[chipnum
].state
!= FL_READY
) {
1199 printk(KERN_DEBUG
"Waiting for chip to write, status = %d\n", cfi
->chips
[chipnum
].state
);
1201 set_current_state(TASK_UNINTERRUPTIBLE
);
1202 add_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1204 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1207 remove_wait_queue(&cfi
->chips
[chipnum
].wq
, &wait
);
1209 if(signal_pending(current
))
1215 tmp_buf
= map_read(map
, ofs
+ chipstart
);
1217 spin_unlock(cfi
->chips
[chipnum
].mutex
);
1219 tmp_buf
= map_word_load_partial(map
, tmp_buf
, buf
, 0, len
);
1221 ret
= do_write_oneword(map
, &cfi
->chips
[chipnum
],
1234 * FIXME: interleaved mode not tested, and probably not supported!
1236 static int __xipram
do_write_buffer(struct map_info
*map
, struct flchip
*chip
,
1237 unsigned long adr
, const u_char
*buf
,
1240 struct cfi_private
*cfi
= map
->fldrv_priv
;
1241 unsigned long timeo
= jiffies
+ HZ
;
1242 /* see comments in do_write_oneword() regarding uWriteTimeo. */
1243 unsigned long uWriteTimeout
= ( HZ
/ 1000 ) + 1;
1245 unsigned long cmd_adr
;
1252 spin_lock(chip
->mutex
);
1253 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1255 spin_unlock(chip
->mutex
);
1259 datum
= map_word_load(map
, buf
);
1261 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1262 __func__
, adr
, datum
.x
[0] );
1264 XIP_INVAL_CACHED_RANGE(map
, adr
, len
);
1266 xip_disable(map
, chip
, cmd_adr
);
1268 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1269 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1270 //cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1272 /* Write Buffer Load */
1273 map_write(map
, CMD(0x25), cmd_adr
);
1275 chip
->state
= FL_WRITING_TO_BUFFER
;
1277 /* Write length of data to come */
1278 words
= len
/ map_bankwidth(map
);
1279 map_write(map
, CMD(words
- 1), cmd_adr
);
1282 while(z
< words
* map_bankwidth(map
)) {
1283 datum
= map_word_load(map
, buf
);
1284 map_write(map
, datum
, adr
+ z
);
1286 z
+= map_bankwidth(map
);
1287 buf
+= map_bankwidth(map
);
1289 z
-= map_bankwidth(map
);
1293 /* Write Buffer Program Confirm: GO GO GO */
1294 map_write(map
, CMD(0x29), cmd_adr
);
1295 chip
->state
= FL_WRITING
;
1297 INVALIDATE_CACHE_UDELAY(map
, chip
,
1298 adr
, map_bankwidth(map
),
1299 chip
->word_write_time
);
1301 timeo
= jiffies
+ uWriteTimeout
;
1304 if (chip
->state
!= FL_WRITING
) {
1305 /* Someone's suspended the write. Sleep */
1306 DECLARE_WAITQUEUE(wait
, current
);
1308 set_current_state(TASK_UNINTERRUPTIBLE
);
1309 add_wait_queue(&chip
->wq
, &wait
);
1310 spin_unlock(chip
->mutex
);
1312 remove_wait_queue(&chip
->wq
, &wait
);
1313 timeo
= jiffies
+ (HZ
/ 2); /* FIXME */
1314 spin_lock(chip
->mutex
);
1318 if (time_after(jiffies
, timeo
) && !chip_ready(map
, adr
))
1321 if (chip_ready(map
, adr
)) {
1322 xip_enable(map
, chip
, adr
);
1326 /* Latency issues. Drop the lock, wait a while and retry */
1327 UDELAY(map
, chip
, adr
, 1);
1330 /* reset on all failures. */
1331 map_write( map
, CMD(0xF0), chip
->start
);
1332 xip_enable(map
, chip
, adr
);
1333 /* FIXME - should have reset delay before continuing */
1335 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1340 chip
->state
= FL_READY
;
1341 put_chip(map
, chip
, adr
);
1342 spin_unlock(chip
->mutex
);
1348 static int cfi_amdstd_write_buffers(struct mtd_info
*mtd
, loff_t to
, size_t len
,
1349 size_t *retlen
, const u_char
*buf
)
1351 struct map_info
*map
= mtd
->priv
;
1352 struct cfi_private
*cfi
= map
->fldrv_priv
;
1353 int wbufsize
= cfi_interleave(cfi
) << cfi
->cfiq
->MaxBufWriteSize
;
1362 chipnum
= to
>> cfi
->chipshift
;
1363 ofs
= to
- (chipnum
<< cfi
->chipshift
);
1365 /* If it's not bus-aligned, do the first word write */
1366 if (ofs
& (map_bankwidth(map
)-1)) {
1367 size_t local_len
= (-ofs
)&(map_bankwidth(map
)-1);
1368 if (local_len
> len
)
1370 ret
= cfi_amdstd_write_words(mtd
, ofs
+ (chipnum
<<cfi
->chipshift
),
1371 local_len
, retlen
, buf
);
1378 if (ofs
>> cfi
->chipshift
) {
1381 if (chipnum
== cfi
->numchips
)
1386 /* Write buffer is worth it only if more than one word to write... */
1387 while (len
>= map_bankwidth(map
) * 2) {
1388 /* We must not cross write block boundaries */
1389 int size
= wbufsize
- (ofs
& (wbufsize
-1));
1393 if (size
% map_bankwidth(map
))
1394 size
-= size
% map_bankwidth(map
);
1396 ret
= do_write_buffer(map
, &cfi
->chips
[chipnum
],
1406 if (ofs
>> cfi
->chipshift
) {
1409 if (chipnum
== cfi
->numchips
)
1415 size_t retlen_dregs
= 0;
1417 ret
= cfi_amdstd_write_words(mtd
, ofs
+ (chipnum
<<cfi
->chipshift
),
1418 len
, &retlen_dregs
, buf
);
1420 *retlen
+= retlen_dregs
;
1429 * Handle devices with one erase region, that only implement
1430 * the chip erase command.
1432 static int __xipram
do_erase_chip(struct map_info
*map
, struct flchip
*chip
)
1434 struct cfi_private
*cfi
= map
->fldrv_priv
;
1435 unsigned long timeo
= jiffies
+ HZ
;
1436 unsigned long int adr
;
1437 DECLARE_WAITQUEUE(wait
, current
);
1440 adr
= cfi
->addr_unlock1
;
1442 spin_lock(chip
->mutex
);
1443 ret
= get_chip(map
, chip
, adr
, FL_WRITING
);
1445 spin_unlock(chip
->mutex
);
1449 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): ERASE 0x%.8lx\n",
1450 __func__
, chip
->start
);
1452 XIP_INVAL_CACHED_RANGE(map
, adr
, map
->size
);
1454 xip_disable(map
, chip
, adr
);
1456 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1457 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1458 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1459 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1460 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1461 cfi_send_gen_cmd(0x10, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1463 chip
->state
= FL_ERASING
;
1464 chip
->erase_suspended
= 0;
1465 chip
->in_progress_block_addr
= adr
;
1467 INVALIDATE_CACHE_UDELAY(map
, chip
,
1469 chip
->erase_time
*500);
1471 timeo
= jiffies
+ (HZ
*20);
1474 if (chip
->state
!= FL_ERASING
) {
1475 /* Someone's suspended the erase. Sleep */
1476 set_current_state(TASK_UNINTERRUPTIBLE
);
1477 add_wait_queue(&chip
->wq
, &wait
);
1478 spin_unlock(chip
->mutex
);
1480 remove_wait_queue(&chip
->wq
, &wait
);
1481 spin_lock(chip
->mutex
);
1484 if (chip
->erase_suspended
) {
1485 /* This erase was suspended and resumed.
1486 Adjust the timeout */
1487 timeo
= jiffies
+ (HZ
*20); /* FIXME */
1488 chip
->erase_suspended
= 0;
1491 if (chip_ready(map
, adr
))
1494 if (time_after(jiffies
, timeo
)) {
1495 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1500 /* Latency issues. Drop the lock, wait a while and retry */
1501 UDELAY(map
, chip
, adr
, 1000000/HZ
);
1503 /* Did we succeed? */
1504 if (!chip_good(map
, adr
, map_word_ff(map
))) {
1505 /* reset on all failures. */
1506 map_write( map
, CMD(0xF0), chip
->start
);
1507 /* FIXME - should have reset delay before continuing */
1512 chip
->state
= FL_READY
;
1513 xip_enable(map
, chip
, adr
);
1514 put_chip(map
, chip
, adr
);
1515 spin_unlock(chip
->mutex
);
1521 static int __xipram
do_erase_oneblock(struct map_info
*map
, struct flchip
*chip
, unsigned long adr
, int len
, void *thunk
)
1523 struct cfi_private
*cfi
= map
->fldrv_priv
;
1524 unsigned long timeo
= jiffies
+ HZ
;
1525 DECLARE_WAITQUEUE(wait
, current
);
1530 spin_lock(chip
->mutex
);
1531 ret
= get_chip(map
, chip
, adr
, FL_ERASING
);
1533 spin_unlock(chip
->mutex
);
1537 DEBUG( MTD_DEBUG_LEVEL3
, "MTD %s(): ERASE 0x%.8lx\n",
1540 XIP_INVAL_CACHED_RANGE(map
, adr
, len
);
1542 xip_disable(map
, chip
, adr
);
1544 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1545 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1546 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1547 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1548 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
, cfi
->device_type
, NULL
);
1549 map_write(map
, CMD(0x30), adr
);
1551 chip
->state
= FL_ERASING
;
1552 chip
->erase_suspended
= 0;
1553 chip
->in_progress_block_addr
= adr
;
1555 INVALIDATE_CACHE_UDELAY(map
, chip
,
1557 chip
->erase_time
*500);
1559 timeo
= jiffies
+ (HZ
*20);
1562 if (chip
->state
!= FL_ERASING
) {
1563 /* Someone's suspended the erase. Sleep */
1564 set_current_state(TASK_UNINTERRUPTIBLE
);
1565 add_wait_queue(&chip
->wq
, &wait
);
1566 spin_unlock(chip
->mutex
);
1568 remove_wait_queue(&chip
->wq
, &wait
);
1569 spin_lock(chip
->mutex
);
1572 if (chip
->erase_suspended
) {
1573 /* This erase was suspended and resumed.
1574 Adjust the timeout */
1575 timeo
= jiffies
+ (HZ
*20); /* FIXME */
1576 chip
->erase_suspended
= 0;
1579 if (chip_ready(map
, adr
)) {
1580 xip_enable(map
, chip
, adr
);
1584 if (time_after(jiffies
, timeo
)) {
1585 xip_enable(map
, chip
, adr
);
1586 printk(KERN_WARNING
"MTD %s(): software timeout\n",
1591 /* Latency issues. Drop the lock, wait a while and retry */
1592 UDELAY(map
, chip
, adr
, 1000000/HZ
);
1594 /* Did we succeed? */
1595 if (!chip_good(map
, adr
, map_word_ff(map
))) {
1596 /* reset on all failures. */
1597 map_write( map
, CMD(0xF0), chip
->start
);
1598 /* FIXME - should have reset delay before continuing */
1603 chip
->state
= FL_READY
;
1604 put_chip(map
, chip
, adr
);
1605 spin_unlock(chip
->mutex
);
1610 int cfi_amdstd_erase_varsize(struct mtd_info
*mtd
, struct erase_info
*instr
)
1612 unsigned long ofs
, len
;
1618 ret
= cfi_varsize_frob(mtd
, do_erase_oneblock
, ofs
, len
, NULL
);
1622 instr
->state
= MTD_ERASE_DONE
;
1623 mtd_erase_callback(instr
);
1629 static int cfi_amdstd_erase_chip(struct mtd_info
*mtd
, struct erase_info
*instr
)
1631 struct map_info
*map
= mtd
->priv
;
1632 struct cfi_private
*cfi
= map
->fldrv_priv
;
1635 if (instr
->addr
!= 0)
1638 if (instr
->len
!= mtd
->size
)
1641 ret
= do_erase_chip(map
, &cfi
->chips
[0]);
1645 instr
->state
= MTD_ERASE_DONE
;
1646 mtd_erase_callback(instr
);
1651 static int do_atmel_lock(struct map_info
*map
, struct flchip
*chip
,
1652 unsigned long adr
, int len
, void *thunk
)
1654 struct cfi_private
*cfi
= map
->fldrv_priv
;
1657 spin_lock(chip
->mutex
);
1658 ret
= get_chip(map
, chip
, adr
+ chip
->start
, FL_LOCKING
);
1661 chip
->state
= FL_LOCKING
;
1663 DEBUG(MTD_DEBUG_LEVEL3
, "MTD %s(): LOCK 0x%08lx len %d\n",
1664 __func__
, adr
, len
);
1666 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1667 cfi
->device_type
, NULL
);
1668 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
,
1669 cfi
->device_type
, NULL
);
1670 cfi_send_gen_cmd(0x80, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1671 cfi
->device_type
, NULL
);
1672 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1673 cfi
->device_type
, NULL
);
1674 cfi_send_gen_cmd(0x55, cfi
->addr_unlock2
, chip
->start
, map
, cfi
,
1675 cfi
->device_type
, NULL
);
1676 map_write(map
, CMD(0x40), chip
->start
+ adr
);
1678 chip
->state
= FL_READY
;
1679 put_chip(map
, chip
, adr
+ chip
->start
);
1683 spin_unlock(chip
->mutex
);
1687 static int do_atmel_unlock(struct map_info
*map
, struct flchip
*chip
,
1688 unsigned long adr
, int len
, void *thunk
)
1690 struct cfi_private
*cfi
= map
->fldrv_priv
;
1693 spin_lock(chip
->mutex
);
1694 ret
= get_chip(map
, chip
, adr
+ chip
->start
, FL_UNLOCKING
);
1697 chip
->state
= FL_UNLOCKING
;
1699 DEBUG(MTD_DEBUG_LEVEL3
, "MTD %s(): LOCK 0x%08lx len %d\n",
1700 __func__
, adr
, len
);
1702 cfi_send_gen_cmd(0xAA, cfi
->addr_unlock1
, chip
->start
, map
, cfi
,
1703 cfi
->device_type
, NULL
);
1704 map_write(map
, CMD(0x70), adr
);
1706 chip
->state
= FL_READY
;
1707 put_chip(map
, chip
, adr
+ chip
->start
);
1711 spin_unlock(chip
->mutex
);
1715 static int cfi_atmel_lock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
)
1717 return cfi_varsize_frob(mtd
, do_atmel_lock
, ofs
, len
, NULL
);
1720 static int cfi_atmel_unlock(struct mtd_info
*mtd
, loff_t ofs
, size_t len
)
1722 return cfi_varsize_frob(mtd
, do_atmel_unlock
, ofs
, len
, NULL
);
1726 static void cfi_amdstd_sync (struct mtd_info
*mtd
)
1728 struct map_info
*map
= mtd
->priv
;
1729 struct cfi_private
*cfi
= map
->fldrv_priv
;
1731 struct flchip
*chip
;
1733 DECLARE_WAITQUEUE(wait
, current
);
1735 for (i
=0; !ret
&& i
<cfi
->numchips
; i
++) {
1736 chip
= &cfi
->chips
[i
];
1739 spin_lock(chip
->mutex
);
1741 switch(chip
->state
) {
1745 case FL_JEDEC_QUERY
:
1746 chip
->oldstate
= chip
->state
;
1747 chip
->state
= FL_SYNCING
;
1748 /* No need to wake_up() on this state change -
1749 * as the whole point is that nobody can do anything
1750 * with the chip now anyway.
1753 spin_unlock(chip
->mutex
);
1757 /* Not an idle state */
1758 add_wait_queue(&chip
->wq
, &wait
);
1760 spin_unlock(chip
->mutex
);
1764 remove_wait_queue(&chip
->wq
, &wait
);
1770 /* Unlock the chips again */
1772 for (i
--; i
>=0; i
--) {
1773 chip
= &cfi
->chips
[i
];
1775 spin_lock(chip
->mutex
);
1777 if (chip
->state
== FL_SYNCING
) {
1778 chip
->state
= chip
->oldstate
;
1781 spin_unlock(chip
->mutex
);
1786 static int cfi_amdstd_suspend(struct mtd_info
*mtd
)
1788 struct map_info
*map
= mtd
->priv
;
1789 struct cfi_private
*cfi
= map
->fldrv_priv
;
1791 struct flchip
*chip
;
1794 for (i
=0; !ret
&& i
<cfi
->numchips
; i
++) {
1795 chip
= &cfi
->chips
[i
];
1797 spin_lock(chip
->mutex
);
1799 switch(chip
->state
) {
1803 case FL_JEDEC_QUERY
:
1804 chip
->oldstate
= chip
->state
;
1805 chip
->state
= FL_PM_SUSPENDED
;
1806 /* No need to wake_up() on this state change -
1807 * as the whole point is that nobody can do anything
1808 * with the chip now anyway.
1810 case FL_PM_SUSPENDED
:
1817 spin_unlock(chip
->mutex
);
1820 /* Unlock the chips again */
1823 for (i
--; i
>=0; i
--) {
1824 chip
= &cfi
->chips
[i
];
1826 spin_lock(chip
->mutex
);
1828 if (chip
->state
== FL_PM_SUSPENDED
) {
1829 chip
->state
= chip
->oldstate
;
1832 spin_unlock(chip
->mutex
);
1840 static void cfi_amdstd_resume(struct mtd_info
*mtd
)
1842 struct map_info
*map
= mtd
->priv
;
1843 struct cfi_private
*cfi
= map
->fldrv_priv
;
1845 struct flchip
*chip
;
1847 for (i
=0; i
<cfi
->numchips
; i
++) {
1849 chip
= &cfi
->chips
[i
];
1851 spin_lock(chip
->mutex
);
1853 if (chip
->state
== FL_PM_SUSPENDED
) {
1854 chip
->state
= FL_READY
;
1855 map_write(map
, CMD(0xF0), chip
->start
);
1859 printk(KERN_ERR
"Argh. Chip not in PM_SUSPENDED state upon resume()\n");
1861 spin_unlock(chip
->mutex
);
1865 static void cfi_amdstd_destroy(struct mtd_info
*mtd
)
1867 struct map_info
*map
= mtd
->priv
;
1868 struct cfi_private
*cfi
= map
->fldrv_priv
;
1870 kfree(cfi
->cmdset_priv
);
1873 kfree(mtd
->eraseregions
);
1876 MODULE_LICENSE("GPL");
1877 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
1878 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");