projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
mtd: m25p80: Use OPCODE_QUAD_READ_4B for 4-byte addressing
[deliverable/linux.git] / drivers / mtd / devices / m25p80.c
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h>
34
35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h>
37
38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_QUAD_READ 0x6b /* Read data bytes */
45 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
46 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
47 #define OPCODE_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
48 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
49 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
50 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
51 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
52 #define OPCODE_RDCR 0x35 /* Read configuration register */
53
54 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
55 #define OPCODE_NORM_READ_4B 0x13 /* Read data bytes (low frequency) */
56 #define OPCODE_FAST_READ_4B 0x0c /* Read data bytes (high frequency) */
57 #define OPCODE_QUAD_READ_4B 0x6c /* Read data bytes */
58 #define OPCODE_PP_4B 0x12 /* Page program (up to 256 bytes) */
59 #define OPCODE_SE_4B 0xdc /* Sector erase (usually 64KiB) */
60
61 /* Used for SST flashes only. */
62 #define OPCODE_BP 0x02 /* Byte program */
63 #define OPCODE_WRDI 0x04 /* Write disable */
64 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
65
66 /* Used for Macronix and Winbond flashes. */
67 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
68 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
69
70 /* Used for Spansion flashes only. */
71 #define OPCODE_BRWR 0x17 /* Bank register write */
72
73 /* Status Register bits. */
74 #define SR_WIP 1 /* Write in progress */
75 #define SR_WEL 2 /* Write enable latch */
76 /* meaning of other SR_* bits may differ between vendors */
77 #define SR_BP0 4 /* Block protect 0 */
78 #define SR_BP1 8 /* Block protect 1 */
79 #define SR_BP2 0x10 /* Block protect 2 */
80 #define SR_SRWD 0x80 /* SR write protect */
81
82 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
83
84 /* Configuration Register bits. */
85 #define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
86
87 /* Define max times to check status register before we give up. */
88 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
89 #define MAX_CMD_SIZE 6
90
91 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
92
93 /****************************************************************************/
94
95 enum read_type {
96 M25P80_NORMAL = 0,
97 M25P80_FAST,
98 M25P80_QUAD,
99 };
100
101 struct m25p {
102 struct spi_device *spi;
103 struct mutex lock;
104 struct mtd_info mtd;
105 u16 page_size;
106 u16 addr_width;
107 u8 erase_opcode;
108 u8 read_opcode;
109 u8 program_opcode;
110 u8 *command;
111 enum read_type flash_read;
112 };
113
114 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
115 {
116 return container_of(mtd, struct m25p, mtd);
117 }
118
119 /****************************************************************************/
120
121 /*
122 * Internal helper functions
123 */
124
125 /*
126 * Read the status register, returning its value in the location
127 * Return the status register value.
128 * Returns negative if error occurred.
129 */
130 static int read_sr(struct m25p *flash)
131 {
132 ssize_t retval;
133 u8 code = OPCODE_RDSR;
134 u8 val;
135
136 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
137
138 if (retval < 0) {
139 dev_err(&flash->spi->dev, "error %d reading SR\n",
140 (int) retval);
141 return retval;
142 }
143
144 return val;
145 }
146
147 /*
148 * Read configuration register, returning its value in the
149 * location. Return the configuration register value.
150 * Returns negative if error occured.
151 */
152 static int read_cr(struct m25p *flash)
153 {
154 u8 code = OPCODE_RDCR;
155 int ret;
156 u8 val;
157
158 ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
159 if (ret < 0) {
160 dev_err(&flash->spi->dev, "error %d reading CR\n", ret);
161 return ret;
162 }
163
164 return val;
165 }
166
167 /*
168 * Write status register 1 byte
169 * Returns negative if error occurred.
170 */
171 static int write_sr(struct m25p *flash, u8 val)
172 {
173 flash->command[0] = OPCODE_WRSR;
174 flash->command[1] = val;
175
176 return spi_write(flash->spi, flash->command, 2);
177 }
178
179 /*
180 * Set write enable latch with Write Enable command.
181 * Returns negative if error occurred.
182 */
183 static inline int write_enable(struct m25p *flash)
184 {
185 u8 code = OPCODE_WREN;
186
187 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
188 }
189
190 /*
191 * Send write disble instruction to the chip.
192 */
193 static inline int write_disable(struct m25p *flash)
194 {
195 u8 code = OPCODE_WRDI;
196
197 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
198 }
199
200 /*
201 * Enable/disable 4-byte addressing mode.
202 */
203 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
204 {
205 int status;
206 bool need_wren = false;
207
208 switch (JEDEC_MFR(jedec_id)) {
209 case CFI_MFR_ST: /* Micron, actually */
210 /* Some Micron need WREN command; all will accept it */
211 need_wren = true;
212 case CFI_MFR_MACRONIX:
213 case 0xEF /* winbond */:
214 if (need_wren)
215 write_enable(flash);
216
217 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
218 status = spi_write(flash->spi, flash->command, 1);
219
220 if (need_wren)
221 write_disable(flash);
222
223 return status;
224 default:
225 /* Spansion style */
226 flash->command[0] = OPCODE_BRWR;
227 flash->command[1] = enable << 7;
228 return spi_write(flash->spi, flash->command, 2);
229 }
230 }
231
232 /*
233 * Service routine to read status register until ready, or timeout occurs.
234 * Returns non-zero if error.
235 */
236 static int wait_till_ready(struct m25p *flash)
237 {
238 unsigned long deadline;
239 int sr;
240
241 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
242
243 do {
244 if ((sr = read_sr(flash)) < 0)
245 break;
246 else if (!(sr & SR_WIP))
247 return 0;
248
249 cond_resched();
250
251 } while (!time_after_eq(jiffies, deadline));
252
253 return 1;
254 }
255
256 /*
257 * Write status Register and configuration register with 2 bytes
258 * The first byte will be written to the status register, while the
259 * second byte will be written to the configuration register.
260 * Return negative if error occured.
261 */
262 static int write_sr_cr(struct m25p *flash, u16 val)
263 {
264 flash->command[0] = OPCODE_WRSR;
265 flash->command[1] = val & 0xff;
266 flash->command[2] = (val >> 8);
267
268 return spi_write(flash->spi, flash->command, 3);
269 }
270
271 static int macronix_quad_enable(struct m25p *flash)
272 {
273 int ret, val;
274 u8 cmd[2];
275 cmd[0] = OPCODE_WRSR;
276
277 val = read_sr(flash);
278 cmd[1] = val | SR_QUAD_EN_MX;
279 write_enable(flash);
280
281 spi_write(flash->spi, &cmd, 2);
282
283 if (wait_till_ready(flash))
284 return 1;
285
286 ret = read_sr(flash);
287 if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
288 dev_err(&flash->spi->dev, "Macronix Quad bit not set\n");
289 return -EINVAL;
290 }
291
292 return 0;
293 }
294
295 static int spansion_quad_enable(struct m25p *flash)
296 {
297 int ret;
298 int quad_en = CR_QUAD_EN_SPAN << 8;
299
300 write_enable(flash);
301
302 ret = write_sr_cr(flash, quad_en);
303 if (ret < 0) {
304 dev_err(&flash->spi->dev,
305 "error while writing configuration register\n");
306 return -EINVAL;
307 }
308
309 /* read back and check it */
310 ret = read_cr(flash);
311 if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
312 dev_err(&flash->spi->dev, "Spansion Quad bit not set\n");
313 return -EINVAL;
314 }
315
316 return 0;
317 }
318
319 static int set_quad_mode(struct m25p *flash, u32 jedec_id)
320 {
321 int status;
322
323 switch (JEDEC_MFR(jedec_id)) {
324 case CFI_MFR_MACRONIX:
325 status = macronix_quad_enable(flash);
326 if (status) {
327 dev_err(&flash->spi->dev,
328 "Macronix quad-read not enabled\n");
329 return -EINVAL;
330 }
331 return status;
332 default:
333 status = spansion_quad_enable(flash);
334 if (status) {
335 dev_err(&flash->spi->dev,
336 "Spansion quad-read not enabled\n");
337 return -EINVAL;
338 }
339 return status;
340 }
341 }
342
343 /*
344 * Erase the whole flash memory
345 *
346 * Returns 0 if successful, non-zero otherwise.
347 */
348 static int erase_chip(struct m25p *flash)
349 {
350 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
351 (long long)(flash->mtd.size >> 10));
352
353 /* Wait until finished previous write command. */
354 if (wait_till_ready(flash))
355 return 1;
356
357 /* Send write enable, then erase commands. */
358 write_enable(flash);
359
360 /* Set up command buffer. */
361 flash->command[0] = OPCODE_CHIP_ERASE;
362
363 spi_write(flash->spi, flash->command, 1);
364
365 return 0;
366 }
367
368 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
369 {
370 /* opcode is in cmd[0] */
371 cmd[1] = addr >> (flash->addr_width * 8 - 8);
372 cmd[2] = addr >> (flash->addr_width * 8 - 16);
373 cmd[3] = addr >> (flash->addr_width * 8 - 24);
374 cmd[4] = addr >> (flash->addr_width * 8 - 32);
375 }
376
377 static int m25p_cmdsz(struct m25p *flash)
378 {
379 return 1 + flash->addr_width;
380 }
381
382 /*
383 * Erase one sector of flash memory at offset ``offset'' which is any
384 * address within the sector which should be erased.
385 *
386 * Returns 0 if successful, non-zero otherwise.
387 */
388 static int erase_sector(struct m25p *flash, u32 offset)
389 {
390 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
391 __func__, flash->mtd.erasesize / 1024, offset);
392
393 /* Wait until finished previous write command. */
394 if (wait_till_ready(flash))
395 return 1;
396
397 /* Send write enable, then erase commands. */
398 write_enable(flash);
399
400 /* Set up command buffer. */
401 flash->command[0] = flash->erase_opcode;
402 m25p_addr2cmd(flash, offset, flash->command);
403
404 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
405
406 return 0;
407 }
408
409 /****************************************************************************/
410
411 /*
412 * MTD implementation
413 */
414
415 /*
416 * Erase an address range on the flash chip. The address range may extend
417 * one or more erase sectors. Return an error is there is a problem erasing.
418 */
419 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
420 {
421 struct m25p *flash = mtd_to_m25p(mtd);
422 u32 addr,len;
423 uint32_t rem;
424
425 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
426 __func__, (long long)instr->addr,
427 (long long)instr->len);
428
429 div_u64_rem(instr->len, mtd->erasesize, &rem);
430 if (rem)
431 return -EINVAL;
432
433 addr = instr->addr;
434 len = instr->len;
435
436 mutex_lock(&flash->lock);
437
438 /* whole-chip erase? */
439 if (len == flash->mtd.size) {
440 if (erase_chip(flash)) {
441 instr->state = MTD_ERASE_FAILED;
442 mutex_unlock(&flash->lock);
443 return -EIO;
444 }
445
446 /* REVISIT in some cases we could speed up erasing large regions
447 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
448 * to use "small sector erase", but that's not always optimal.
449 */
450
451 /* "sector"-at-a-time erase */
452 } else {
453 while (len) {
454 if (erase_sector(flash, addr)) {
455 instr->state = MTD_ERASE_FAILED;
456 mutex_unlock(&flash->lock);
457 return -EIO;
458 }
459
460 addr += mtd->erasesize;
461 len -= mtd->erasesize;
462 }
463 }
464
465 mutex_unlock(&flash->lock);
466
467 instr->state = MTD_ERASE_DONE;
468 mtd_erase_callback(instr);
469
470 return 0;
471 }
472
473 /*
474 * Dummy Cycle calculation for different type of read.
475 * It can be used to support more commands with
476 * different dummy cycle requirements.
477 */
478 static inline int m25p80_dummy_cycles_read(struct m25p *flash)
479 {
480 switch (flash->flash_read) {
481 case M25P80_FAST:
482 case M25P80_QUAD:
483 return 1;
484 case M25P80_NORMAL:
485 return 0;
486 default:
487 dev_err(&flash->spi->dev, "No valid read type supported\n");
488 return -1;
489 }
490 }
491
492 /*
493 * Read an address range from the flash chip. The address range
494 * may be any size provided it is within the physical boundaries.
495 */
496 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
497 size_t *retlen, u_char *buf)
498 {
499 struct m25p *flash = mtd_to_m25p(mtd);
500 struct spi_transfer t[2];
501 struct spi_message m;
502 uint8_t opcode;
503 int dummy;
504
505 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
506 __func__, (u32)from, len);
507
508 spi_message_init(&m);
509 memset(t, 0, (sizeof t));
510
511 dummy = m25p80_dummy_cycles_read(flash);
512 if (dummy < 0) {
513 dev_err(&flash->spi->dev, "No valid read command supported\n");
514 return -EINVAL;
515 }
516
517 t[0].tx_buf = flash->command;
518 t[0].len = m25p_cmdsz(flash) + dummy;
519 spi_message_add_tail(&t[0], &m);
520
521 t[1].rx_buf = buf;
522 t[1].len = len;
523 spi_message_add_tail(&t[1], &m);
524
525 mutex_lock(&flash->lock);
526
527 /* Wait till previous write/erase is done. */
528 if (wait_till_ready(flash)) {
529 /* REVISIT status return?? */
530 mutex_unlock(&flash->lock);
531 return 1;
532 }
533
534 /* Set up the write data buffer. */
535 opcode = flash->read_opcode;
536 flash->command[0] = opcode;
537 m25p_addr2cmd(flash, from, flash->command);
538
539 spi_sync(flash->spi, &m);
540
541 *retlen = m.actual_length - m25p_cmdsz(flash) - dummy;
542
543 mutex_unlock(&flash->lock);
544
545 return 0;
546 }
547
548 /*
549 * Write an address range to the flash chip. Data must be written in
550 * FLASH_PAGESIZE chunks. The address range may be any size provided
551 * it is within the physical boundaries.
552 */
553 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
554 size_t *retlen, const u_char *buf)
555 {
556 struct m25p *flash = mtd_to_m25p(mtd);
557 u32 page_offset, page_size;
558 struct spi_transfer t[2];
559 struct spi_message m;
560
561 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
562 __func__, (u32)to, len);
563
564 spi_message_init(&m);
565 memset(t, 0, (sizeof t));
566
567 t[0].tx_buf = flash->command;
568 t[0].len = m25p_cmdsz(flash);
569 spi_message_add_tail(&t[0], &m);
570
571 t[1].tx_buf = buf;
572 spi_message_add_tail(&t[1], &m);
573
574 mutex_lock(&flash->lock);
575
576 /* Wait until finished previous write command. */
577 if (wait_till_ready(flash)) {
578 mutex_unlock(&flash->lock);
579 return 1;
580 }
581
582 write_enable(flash);
583
584 /* Set up the opcode in the write buffer. */
585 flash->command[0] = flash->program_opcode;
586 m25p_addr2cmd(flash, to, flash->command);
587
588 page_offset = to & (flash->page_size - 1);
589
590 /* do all the bytes fit onto one page? */
591 if (page_offset + len <= flash->page_size) {
592 t[1].len = len;
593
594 spi_sync(flash->spi, &m);
595
596 *retlen = m.actual_length - m25p_cmdsz(flash);
597 } else {
598 u32 i;
599
600 /* the size of data remaining on the first page */
601 page_size = flash->page_size - page_offset;
602
603 t[1].len = page_size;
604 spi_sync(flash->spi, &m);
605
606 *retlen = m.actual_length - m25p_cmdsz(flash);
607
608 /* write everything in flash->page_size chunks */
609 for (i = page_size; i < len; i += page_size) {
610 page_size = len - i;
611 if (page_size > flash->page_size)
612 page_size = flash->page_size;
613
614 /* write the next page to flash */
615 m25p_addr2cmd(flash, to + i, flash->command);
616
617 t[1].tx_buf = buf + i;
618 t[1].len = page_size;
619
620 wait_till_ready(flash);
621
622 write_enable(flash);
623
624 spi_sync(flash->spi, &m);
625
626 *retlen += m.actual_length - m25p_cmdsz(flash);
627 }
628 }
629
630 mutex_unlock(&flash->lock);
631
632 return 0;
633 }
634
635 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
636 size_t *retlen, const u_char *buf)
637 {
638 struct m25p *flash = mtd_to_m25p(mtd);
639 struct spi_transfer t[2];
640 struct spi_message m;
641 size_t actual;
642 int cmd_sz, ret;
643
644 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
645 __func__, (u32)to, len);
646
647 spi_message_init(&m);
648 memset(t, 0, (sizeof t));
649
650 t[0].tx_buf = flash->command;
651 t[0].len = m25p_cmdsz(flash);
652 spi_message_add_tail(&t[0], &m);
653
654 t[1].tx_buf = buf;
655 spi_message_add_tail(&t[1], &m);
656
657 mutex_lock(&flash->lock);
658
659 /* Wait until finished previous write command. */
660 ret = wait_till_ready(flash);
661 if (ret)
662 goto time_out;
663
664 write_enable(flash);
665
666 actual = to % 2;
667 /* Start write from odd address. */
668 if (actual) {
669 flash->command[0] = OPCODE_BP;
670 m25p_addr2cmd(flash, to, flash->command);
671
672 /* write one byte. */
673 t[1].len = 1;
674 spi_sync(flash->spi, &m);
675 ret = wait_till_ready(flash);
676 if (ret)
677 goto time_out;
678 *retlen += m.actual_length - m25p_cmdsz(flash);
679 }
680 to += actual;
681
682 flash->command[0] = OPCODE_AAI_WP;
683 m25p_addr2cmd(flash, to, flash->command);
684
685 /* Write out most of the data here. */
686 cmd_sz = m25p_cmdsz(flash);
687 for (; actual < len - 1; actual += 2) {
688 t[0].len = cmd_sz;
689 /* write two bytes. */
690 t[1].len = 2;
691 t[1].tx_buf = buf + actual;
692
693 spi_sync(flash->spi, &m);
694 ret = wait_till_ready(flash);
695 if (ret)
696 goto time_out;
697 *retlen += m.actual_length - cmd_sz;
698 cmd_sz = 1;
699 to += 2;
700 }
701 write_disable(flash);
702 ret = wait_till_ready(flash);
703 if (ret)
704 goto time_out;
705
706 /* Write out trailing byte if it exists. */
707 if (actual != len) {
708 write_enable(flash);
709 flash->command[0] = OPCODE_BP;
710 m25p_addr2cmd(flash, to, flash->command);
711 t[0].len = m25p_cmdsz(flash);
712 t[1].len = 1;
713 t[1].tx_buf = buf + actual;
714
715 spi_sync(flash->spi, &m);
716 ret = wait_till_ready(flash);
717 if (ret)
718 goto time_out;
719 *retlen += m.actual_length - m25p_cmdsz(flash);
720 write_disable(flash);
721 }
722
723 time_out:
724 mutex_unlock(&flash->lock);
725 return ret;
726 }
727
728 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
729 {
730 struct m25p *flash = mtd_to_m25p(mtd);
731 uint32_t offset = ofs;
732 uint8_t status_old, status_new;
733 int res = 0;
734
735 mutex_lock(&flash->lock);
736 /* Wait until finished previous command */
737 if (wait_till_ready(flash)) {
738 res = 1;
739 goto err;
740 }
741
742 status_old = read_sr(flash);
743
744 if (offset < flash->mtd.size-(flash->mtd.size/2))
745 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
746 else if (offset < flash->mtd.size-(flash->mtd.size/4))
747 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
748 else if (offset < flash->mtd.size-(flash->mtd.size/8))
749 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
750 else if (offset < flash->mtd.size-(flash->mtd.size/16))
751 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
752 else if (offset < flash->mtd.size-(flash->mtd.size/32))
753 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
754 else if (offset < flash->mtd.size-(flash->mtd.size/64))
755 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
756 else
757 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
758
759 /* Only modify protection if it will not unlock other areas */
760 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
761 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
762 write_enable(flash);
763 if (write_sr(flash, status_new) < 0) {
764 res = 1;
765 goto err;
766 }
767 }
768
769 err: mutex_unlock(&flash->lock);
770 return res;
771 }
772
773 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
774 {
775 struct m25p *flash = mtd_to_m25p(mtd);
776 uint32_t offset = ofs;
777 uint8_t status_old, status_new;
778 int res = 0;
779
780 mutex_lock(&flash->lock);
781 /* Wait until finished previous command */
782 if (wait_till_ready(flash)) {
783 res = 1;
784 goto err;
785 }
786
787 status_old = read_sr(flash);
788
789 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
790 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
791 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
792 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
793 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
794 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
795 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
796 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
797 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
798 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
799 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
800 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
801 else
802 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
803
804 /* Only modify protection if it will not lock other areas */
805 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
806 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
807 write_enable(flash);
808 if (write_sr(flash, status_new) < 0) {
809 res = 1;
810 goto err;
811 }
812 }
813
814 err: mutex_unlock(&flash->lock);
815 return res;
816 }
817
818 /****************************************************************************/
819
820 /*
821 * SPI device driver setup and teardown
822 */
823
824 struct flash_info {
825 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
826 * a high byte of zero plus three data bytes: the manufacturer id,
827 * then a two byte device id.
828 */
829 u32 jedec_id;
830 u16 ext_id;
831
832 /* The size listed here is what works with OPCODE_SE, which isn't
833 * necessarily called a "sector" by the vendor.
834 */
835 unsigned sector_size;
836 u16 n_sectors;
837
838 u16 page_size;
839 u16 addr_width;
840
841 u16 flags;
842 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
843 #define M25P_NO_ERASE 0x02 /* No erase command needed */
844 #define SST_WRITE 0x04 /* use SST byte programming */
845 #define M25P_NO_FR 0x08 /* Can't do fastread */
846 #define SECT_4K_PMC 0x10 /* OPCODE_BE_4K_PMC works uniformly */
847 #define M25P80_QUAD_READ 0x20 /* Flash supports Quad Read */
848 };
849
850 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
851 ((kernel_ulong_t)&(struct flash_info) { \
852 .jedec_id = (_jedec_id), \
853 .ext_id = (_ext_id), \
854 .sector_size = (_sector_size), \
855 .n_sectors = (_n_sectors), \
856 .page_size = 256, \
857 .flags = (_flags), \
858 })
859
860 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
861 ((kernel_ulong_t)&(struct flash_info) { \
862 .sector_size = (_sector_size), \
863 .n_sectors = (_n_sectors), \
864 .page_size = (_page_size), \
865 .addr_width = (_addr_width), \
866 .flags = (_flags), \
867 })
868
869 /* NOTE: double check command sets and memory organization when you add
870 * more flash chips. This current list focusses on newer chips, which
871 * have been converging on command sets which including JEDEC ID.
872 */
873 static const struct spi_device_id m25p_ids[] = {
874 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
875 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
876 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
877
878 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
879 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
880 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
881
882 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
883 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
884 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
885 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
886
887 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
888
889 /* EON -- en25xxx */
890 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
891 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
892 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
893 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
894 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
895 { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
896
897 /* ESMT */
898 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
899
900 /* Everspin */
901 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, M25P_NO_ERASE | M25P_NO_FR) },
902 { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, M25P_NO_ERASE | M25P_NO_FR) },
903
904 /* GigaDevice */
905 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
906 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
907
908 /* Intel/Numonyx -- xxxs33b */
909 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
910 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
911 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
912
913 /* Macronix */
914 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
915 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
916 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
917 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
918 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
919 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
920 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
921 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
922 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
923 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
924 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
925 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, M25P80_QUAD_READ) },
926
927 /* Micron */
928 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
929 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
930 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
931 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
932 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
933
934 /* PMC */
935 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
936 { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
937 { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
938
939 /* Spansion -- single (large) sector size only, at least
940 * for the chips listed here (without boot sectors).
941 */
942 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
943 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
944 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
945 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, M25P80_QUAD_READ) },
946 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
947 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
948 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
949 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
950 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
951 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
952 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
953 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
954 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
955 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
956 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
957 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
958 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
959
960 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
961 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
962 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
963 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
964 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
965 { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
966 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
967 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
968 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
969 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
970
971 /* ST Microelectronics -- newer production may have feature updates */
972 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
973 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
974 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
975 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
976 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
977 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
978 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
979 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
980 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
981 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
982
983 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
984 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
985 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
986 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
987 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
988 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
989 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
990 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
991 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
992
993 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
994 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
995 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
996
997 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
998 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
999 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1000
1001 { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1002 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1003 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1004 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1005 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1006
1007 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1008 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1009 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1010 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1011 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1012 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1013 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1014 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1015 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
1016 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1017 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1018 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1019 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1020 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1021 { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1022 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1023
1024 /* Catalyst / On Semiconductor -- non-JEDEC */
1025 { "cat25c11", CAT25_INFO( 16, 8, 16, 1, M25P_NO_ERASE | M25P_NO_FR) },
1026 { "cat25c03", CAT25_INFO( 32, 8, 16, 2, M25P_NO_ERASE | M25P_NO_FR) },
1027 { "cat25c09", CAT25_INFO( 128, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
1028 { "cat25c17", CAT25_INFO( 256, 8, 32, 2, M25P_NO_ERASE | M25P_NO_FR) },
1029 { "cat25128", CAT25_INFO(2048, 8, 64, 2, M25P_NO_ERASE | M25P_NO_FR) },
1030 { },
1031 };
1032 MODULE_DEVICE_TABLE(spi, m25p_ids);
1033
1034 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
1035 {
1036 int tmp;
1037 u8 code = OPCODE_RDID;
1038 u8 id[5];
1039 u32 jedec;
1040 u16 ext_jedec;
1041 struct flash_info *info;
1042
1043 /* JEDEC also defines an optional "extended device information"
1044 * string for after vendor-specific data, after the three bytes
1045 * we use here. Supporting some chips might require using it.
1046 */
1047 tmp = spi_write_then_read(spi, &code, 1, id, 5);
1048 if (tmp < 0) {
1049 pr_debug("%s: error %d reading JEDEC ID\n",
1050 dev_name(&spi->dev), tmp);
1051 return ERR_PTR(tmp);
1052 }
1053 jedec = id[0];
1054 jedec = jedec << 8;
1055 jedec |= id[1];
1056 jedec = jedec << 8;
1057 jedec |= id[2];
1058
1059 ext_jedec = id[3] << 8 | id[4];
1060
1061 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
1062 info = (void *)m25p_ids[tmp].driver_data;
1063 if (info->jedec_id == jedec) {
1064 if (info->ext_id != 0 && info->ext_id != ext_jedec)
1065 continue;
1066 return &m25p_ids[tmp];
1067 }
1068 }
1069 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
1070 return ERR_PTR(-ENODEV);
1071 }
1072
1073
1074 /*
1075 * board specific setup should have ensured the SPI clock used here
1076 * matches what the READ command supports, at least until this driver
1077 * understands FAST_READ (for clocks over 25 MHz).
1078 */
1079 static int m25p_probe(struct spi_device *spi)
1080 {
1081 const struct spi_device_id *id = spi_get_device_id(spi);
1082 struct flash_platform_data *data;
1083 struct m25p *flash;
1084 struct flash_info *info;
1085 unsigned i;
1086 struct mtd_part_parser_data ppdata;
1087 struct device_node *np = spi->dev.of_node;
1088 int ret;
1089
1090 /* Platform data helps sort out which chip type we have, as
1091 * well as how this board partitions it. If we don't have
1092 * a chip ID, try the JEDEC id commands; they'll work for most
1093 * newer chips, even if we don't recognize the particular chip.
1094 */
1095 data = dev_get_platdata(&spi->dev);
1096 if (data && data->type) {
1097 const struct spi_device_id *plat_id;
1098
1099 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
1100 plat_id = &m25p_ids[i];
1101 if (strcmp(data->type, plat_id->name))
1102 continue;
1103 break;
1104 }
1105
1106 if (i < ARRAY_SIZE(m25p_ids) - 1)
1107 id = plat_id;
1108 else
1109 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
1110 }
1111
1112 info = (void *)id->driver_data;
1113
1114 if (info->jedec_id) {
1115 const struct spi_device_id *jid;
1116
1117 jid = jedec_probe(spi);
1118 if (IS_ERR(jid)) {
1119 return PTR_ERR(jid);
1120 } else if (jid != id) {
1121 /*
1122 * JEDEC knows better, so overwrite platform ID. We
1123 * can't trust partitions any longer, but we'll let
1124 * mtd apply them anyway, since some partitions may be
1125 * marked read-only, and we don't want to lose that
1126 * information, even if it's not 100% accurate.
1127 */
1128 dev_warn(&spi->dev, "found %s, expected %s\n",
1129 jid->name, id->name);
1130 id = jid;
1131 info = (void *)jid->driver_data;
1132 }
1133 }
1134
1135 flash = devm_kzalloc(&spi->dev, sizeof(*flash), GFP_KERNEL);
1136 if (!flash)
1137 return -ENOMEM;
1138
1139 flash->command = devm_kzalloc(&spi->dev, MAX_CMD_SIZE, GFP_KERNEL);
1140 if (!flash->command)
1141 return -ENOMEM;
1142
1143 flash->spi = spi;
1144 mutex_init(&flash->lock);
1145 spi_set_drvdata(spi, flash);
1146
1147 /*
1148 * Atmel, SST and Intel/Numonyx serial flash tend to power
1149 * up with the software protection bits set
1150 */
1151
1152 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
1153 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
1154 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
1155 write_enable(flash);
1156 write_sr(flash, 0);
1157 }
1158
1159 if (data && data->name)
1160 flash->mtd.name = data->name;
1161 else
1162 flash->mtd.name = dev_name(&spi->dev);
1163
1164 flash->mtd.type = MTD_NORFLASH;
1165 flash->mtd.writesize = 1;
1166 flash->mtd.flags = MTD_CAP_NORFLASH;
1167 flash->mtd.size = info->sector_size * info->n_sectors;
1168 flash->mtd._erase = m25p80_erase;
1169 flash->mtd._read = m25p80_read;
1170
1171 /* flash protection support for STmicro chips */
1172 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
1173 flash->mtd._lock = m25p80_lock;
1174 flash->mtd._unlock = m25p80_unlock;
1175 }
1176
1177 /* sst flash chips use AAI word program */
1178 if (info->flags & SST_WRITE)
1179 flash->mtd._write = sst_write;
1180 else
1181 flash->mtd._write = m25p80_write;
1182
1183 /* prefer "small sector" erase if possible */
1184 if (info->flags & SECT_4K) {
1185 flash->erase_opcode = OPCODE_BE_4K;
1186 flash->mtd.erasesize = 4096;
1187 } else if (info->flags & SECT_4K_PMC) {
1188 flash->erase_opcode = OPCODE_BE_4K_PMC;
1189 flash->mtd.erasesize = 4096;
1190 } else {
1191 flash->erase_opcode = OPCODE_SE;
1192 flash->mtd.erasesize = info->sector_size;
1193 }
1194
1195 if (info->flags & M25P_NO_ERASE)
1196 flash->mtd.flags |= MTD_NO_ERASE;
1197
1198 ppdata.of_node = spi->dev.of_node;
1199 flash->mtd.dev.parent = &spi->dev;
1200 flash->page_size = info->page_size;
1201 flash->mtd.writebufsize = flash->page_size;
1202
1203 if (np) {
1204 /* If we were instantiated by DT, use it */
1205 if (of_property_read_bool(np, "m25p,fast-read"))
1206 flash->flash_read = M25P80_FAST;
1207 } else {
1208 /* If we weren't instantiated by DT, default to fast-read */
1209 flash->flash_read = M25P80_FAST;
1210 }
1211
1212 /* Some devices cannot do fast-read, no matter what DT tells us */
1213 if (info->flags & M25P_NO_FR)
1214 flash->flash_read = M25P80_NORMAL;
1215
1216 /* Quad-read mode takes precedence over fast/normal */
1217 if (spi->mode & SPI_RX_QUAD && info->flags & M25P80_QUAD_READ) {
1218 ret = set_quad_mode(flash, info->jedec_id);
1219 if (ret) {
1220 dev_err(&flash->spi->dev, "quad mode not supported\n");
1221 return ret;
1222 }
1223 flash->flash_read = M25P80_QUAD;
1224 }
1225
1226 /* Default commands */
1227 switch (flash->flash_read) {
1228 case M25P80_QUAD:
1229 flash->read_opcode = OPCODE_QUAD_READ;
1230 break;
1231 case M25P80_FAST:
1232 flash->read_opcode = OPCODE_FAST_READ;
1233 break;
1234 case M25P80_NORMAL:
1235 flash->read_opcode = OPCODE_NORM_READ;
1236 break;
1237 default:
1238 dev_err(&flash->spi->dev, "No Read opcode defined\n");
1239 return -EINVAL;
1240 }
1241
1242 flash->program_opcode = OPCODE_PP;
1243
1244 if (info->addr_width)
1245 flash->addr_width = info->addr_width;
1246 else if (flash->mtd.size > 0x1000000) {
1247 /* enable 4-byte addressing if the device exceeds 16MiB */
1248 flash->addr_width = 4;
1249 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
1250 /* Dedicated 4-byte command set */
1251 switch (flash->flash_read) {
1252 case M25P80_QUAD:
1253 flash->read_opcode = OPCODE_QUAD_READ_4B;
1254 break;
1255 case M25P80_FAST:
1256 flash->read_opcode = OPCODE_FAST_READ_4B;
1257 break;
1258 case M25P80_NORMAL:
1259 flash->read_opcode = OPCODE_NORM_READ_4B;
1260 break;
1261 }
1262 flash->program_opcode = OPCODE_PP_4B;
1263 /* No small sector erase for 4-byte command set */
1264 flash->erase_opcode = OPCODE_SE_4B;
1265 flash->mtd.erasesize = info->sector_size;
1266 } else
1267 set_4byte(flash, info->jedec_id, 1);
1268 } else {
1269 flash->addr_width = 3;
1270 }
1271
1272 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1273 (long long)flash->mtd.size >> 10);
1274
1275 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1276 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1277 flash->mtd.name,
1278 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1279 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1280 flash->mtd.numeraseregions);
1281
1282 if (flash->mtd.numeraseregions)
1283 for (i = 0; i < flash->mtd.numeraseregions; i++)
1284 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1285 ".erasesize = 0x%.8x (%uKiB), "
1286 ".numblocks = %d }\n",
1287 i, (long long)flash->mtd.eraseregions[i].offset,
1288 flash->mtd.eraseregions[i].erasesize,
1289 flash->mtd.eraseregions[i].erasesize / 1024,
1290 flash->mtd.eraseregions[i].numblocks);
1291
1292
1293 /* partitions should match sector boundaries; and it may be good to
1294 * use readonly partitions for writeprotected sectors (BP2..BP0).
1295 */
1296 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1297 data ? data->parts : NULL,
1298 data ? data->nr_parts : 0);
1299 }
1300
1301
1302 static int m25p_remove(struct spi_device *spi)
1303 {
1304 struct m25p *flash = spi_get_drvdata(spi);
1305
1306 /* Clean up MTD stuff. */
1307 return mtd_device_unregister(&flash->mtd);
1308 }
1309
1310
1311 static struct spi_driver m25p80_driver = {
1312 .driver = {
1313 .name = "m25p80",
1314 .owner = THIS_MODULE,
1315 },
1316 .id_table = m25p_ids,
1317 .probe = m25p_probe,
1318 .remove = m25p_remove,
1319
1320 /* REVISIT: many of these chips have deep power-down modes, which
1321 * should clearly be entered on suspend() to minimize power use.
1322 * And also when they're otherwise idle...
1323 */
1324 };
1325
1326 module_spi_driver(m25p80_driver);
1327
1328 MODULE_LICENSE("GPL");
1329 MODULE_AUTHOR("Mike Lavender");
1330 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
Linux kernel - Deliverables
This page took 0.084351 seconds and 5 git commands to generate.