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mtd: replace DEBUG() with pr_debug()
[deliverable/linux.git] / drivers / mtd / devices / m25p80.c
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33
34 #include <linux/spi/spi.h>
35 #include <linux/spi/flash.h>
36
37 /* Flash opcodes. */
38 #define OPCODE_WREN 0x06 /* Write enable */
39 #define OPCODE_RDSR 0x05 /* Read status register */
40 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
41 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
42 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
43 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
44 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
45 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
46 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
47 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
48 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
49
50 /* Used for SST flashes only. */
51 #define OPCODE_BP 0x02 /* Byte program */
52 #define OPCODE_WRDI 0x04 /* Write disable */
53 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
54
55 /* Used for Macronix flashes only. */
56 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
57 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
58
59 /* Used for Spansion flashes only. */
60 #define OPCODE_BRWR 0x17 /* Bank register write */
61
62 /* Status Register bits. */
63 #define SR_WIP 1 /* Write in progress */
64 #define SR_WEL 2 /* Write enable latch */
65 /* meaning of other SR_* bits may differ between vendors */
66 #define SR_BP0 4 /* Block protect 0 */
67 #define SR_BP1 8 /* Block protect 1 */
68 #define SR_BP2 0x10 /* Block protect 2 */
69 #define SR_SRWD 0x80 /* SR write protect */
70
71 /* Define max times to check status register before we give up. */
72 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
73 #define MAX_CMD_SIZE 5
74
75 #ifdef CONFIG_M25PXX_USE_FAST_READ
76 #define OPCODE_READ OPCODE_FAST_READ
77 #define FAST_READ_DUMMY_BYTE 1
78 #else
79 #define OPCODE_READ OPCODE_NORM_READ
80 #define FAST_READ_DUMMY_BYTE 0
81 #endif
82
83 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
84
85 /****************************************************************************/
86
87 struct m25p {
88 struct spi_device *spi;
89 struct mutex lock;
90 struct mtd_info mtd;
91 u16 page_size;
92 u16 addr_width;
93 u8 erase_opcode;
94 u8 *command;
95 };
96
97 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
98 {
99 return container_of(mtd, struct m25p, mtd);
100 }
101
102 /****************************************************************************/
103
104 /*
105 * Internal helper functions
106 */
107
108 /*
109 * Read the status register, returning its value in the location
110 * Return the status register value.
111 * Returns negative if error occurred.
112 */
113 static int read_sr(struct m25p *flash)
114 {
115 ssize_t retval;
116 u8 code = OPCODE_RDSR;
117 u8 val;
118
119 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
120
121 if (retval < 0) {
122 dev_err(&flash->spi->dev, "error %d reading SR\n",
123 (int) retval);
124 return retval;
125 }
126
127 return val;
128 }
129
130 /*
131 * Write status register 1 byte
132 * Returns negative if error occurred.
133 */
134 static int write_sr(struct m25p *flash, u8 val)
135 {
136 flash->command[0] = OPCODE_WRSR;
137 flash->command[1] = val;
138
139 return spi_write(flash->spi, flash->command, 2);
140 }
141
142 /*
143 * Set write enable latch with Write Enable command.
144 * Returns negative if error occurred.
145 */
146 static inline int write_enable(struct m25p *flash)
147 {
148 u8 code = OPCODE_WREN;
149
150 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
151 }
152
153 /*
154 * Send write disble instruction to the chip.
155 */
156 static inline int write_disable(struct m25p *flash)
157 {
158 u8 code = OPCODE_WRDI;
159
160 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
161 }
162
163 /*
164 * Enable/disable 4-byte addressing mode.
165 */
166 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
167 {
168 switch (JEDEC_MFR(jedec_id)) {
169 case CFI_MFR_MACRONIX:
170 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
171 return spi_write(flash->spi, flash->command, 1);
172 default:
173 /* Spansion style */
174 flash->command[0] = OPCODE_BRWR;
175 flash->command[1] = enable << 7;
176 return spi_write(flash->spi, flash->command, 2);
177 }
178 }
179
180 /*
181 * Service routine to read status register until ready, or timeout occurs.
182 * Returns non-zero if error.
183 */
184 static int wait_till_ready(struct m25p *flash)
185 {
186 unsigned long deadline;
187 int sr;
188
189 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
190
191 do {
192 if ((sr = read_sr(flash)) < 0)
193 break;
194 else if (!(sr & SR_WIP))
195 return 0;
196
197 cond_resched();
198
199 } while (!time_after_eq(jiffies, deadline));
200
201 return 1;
202 }
203
204 /*
205 * Erase the whole flash memory
206 *
207 * Returns 0 if successful, non-zero otherwise.
208 */
209 static int erase_chip(struct m25p *flash)
210 {
211 pr_debug("%s: %s %lldKiB\n",
212 dev_name(&flash->spi->dev), __func__,
213 (long long)(flash->mtd.size >> 10));
214
215 /* Wait until finished previous write command. */
216 if (wait_till_ready(flash))
217 return 1;
218
219 /* Send write enable, then erase commands. */
220 write_enable(flash);
221
222 /* Set up command buffer. */
223 flash->command[0] = OPCODE_CHIP_ERASE;
224
225 spi_write(flash->spi, flash->command, 1);
226
227 return 0;
228 }
229
230 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
231 {
232 /* opcode is in cmd[0] */
233 cmd[1] = addr >> (flash->addr_width * 8 - 8);
234 cmd[2] = addr >> (flash->addr_width * 8 - 16);
235 cmd[3] = addr >> (flash->addr_width * 8 - 24);
236 cmd[4] = addr >> (flash->addr_width * 8 - 32);
237 }
238
239 static int m25p_cmdsz(struct m25p *flash)
240 {
241 return 1 + flash->addr_width;
242 }
243
244 /*
245 * Erase one sector of flash memory at offset ``offset'' which is any
246 * address within the sector which should be erased.
247 *
248 * Returns 0 if successful, non-zero otherwise.
249 */
250 static int erase_sector(struct m25p *flash, u32 offset)
251 {
252 pr_debug("%s: %s %dKiB at 0x%08x\n",
253 dev_name(&flash->spi->dev), __func__,
254 flash->mtd.erasesize / 1024, offset);
255
256 /* Wait until finished previous write command. */
257 if (wait_till_ready(flash))
258 return 1;
259
260 /* Send write enable, then erase commands. */
261 write_enable(flash);
262
263 /* Set up command buffer. */
264 flash->command[0] = flash->erase_opcode;
265 m25p_addr2cmd(flash, offset, flash->command);
266
267 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
268
269 return 0;
270 }
271
272 /****************************************************************************/
273
274 /*
275 * MTD implementation
276 */
277
278 /*
279 * Erase an address range on the flash chip. The address range may extend
280 * one or more erase sectors. Return an error is there is a problem erasing.
281 */
282 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
283 {
284 struct m25p *flash = mtd_to_m25p(mtd);
285 u32 addr,len;
286 uint32_t rem;
287
288 pr_debug("%s: %s %s 0x%llx, len %lld\n",
289 dev_name(&flash->spi->dev), __func__, "at",
290 (long long)instr->addr, (long long)instr->len);
291
292 /* sanity checks */
293 if (instr->addr + instr->len > flash->mtd.size)
294 return -EINVAL;
295 div_u64_rem(instr->len, mtd->erasesize, &rem);
296 if (rem)
297 return -EINVAL;
298
299 addr = instr->addr;
300 len = instr->len;
301
302 mutex_lock(&flash->lock);
303
304 /* whole-chip erase? */
305 if (len == flash->mtd.size) {
306 if (erase_chip(flash)) {
307 instr->state = MTD_ERASE_FAILED;
308 mutex_unlock(&flash->lock);
309 return -EIO;
310 }
311
312 /* REVISIT in some cases we could speed up erasing large regions
313 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
314 * to use "small sector erase", but that's not always optimal.
315 */
316
317 /* "sector"-at-a-time erase */
318 } else {
319 while (len) {
320 if (erase_sector(flash, addr)) {
321 instr->state = MTD_ERASE_FAILED;
322 mutex_unlock(&flash->lock);
323 return -EIO;
324 }
325
326 addr += mtd->erasesize;
327 len -= mtd->erasesize;
328 }
329 }
330
331 mutex_unlock(&flash->lock);
332
333 instr->state = MTD_ERASE_DONE;
334 mtd_erase_callback(instr);
335
336 return 0;
337 }
338
339 /*
340 * Read an address range from the flash chip. The address range
341 * may be any size provided it is within the physical boundaries.
342 */
343 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
344 size_t *retlen, u_char *buf)
345 {
346 struct m25p *flash = mtd_to_m25p(mtd);
347 struct spi_transfer t[2];
348 struct spi_message m;
349
350 pr_debug("%s: %s %s 0x%08x, len %zd\n",
351 dev_name(&flash->spi->dev), __func__, "from",
352 (u32)from, len);
353
354 /* sanity checks */
355 if (!len)
356 return 0;
357
358 if (from + len > flash->mtd.size)
359 return -EINVAL;
360
361 spi_message_init(&m);
362 memset(t, 0, (sizeof t));
363
364 /* NOTE:
365 * OPCODE_FAST_READ (if available) is faster.
366 * Should add 1 byte DUMMY_BYTE.
367 */
368 t[0].tx_buf = flash->command;
369 t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
370 spi_message_add_tail(&t[0], &m);
371
372 t[1].rx_buf = buf;
373 t[1].len = len;
374 spi_message_add_tail(&t[1], &m);
375
376 /* Byte count starts at zero. */
377 *retlen = 0;
378
379 mutex_lock(&flash->lock);
380
381 /* Wait till previous write/erase is done. */
382 if (wait_till_ready(flash)) {
383 /* REVISIT status return?? */
384 mutex_unlock(&flash->lock);
385 return 1;
386 }
387
388 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
389 * clocks; and at this writing, every chip this driver handles
390 * supports that opcode.
391 */
392
393 /* Set up the write data buffer. */
394 flash->command[0] = OPCODE_READ;
395 m25p_addr2cmd(flash, from, flash->command);
396
397 spi_sync(flash->spi, &m);
398
399 *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
400
401 mutex_unlock(&flash->lock);
402
403 return 0;
404 }
405
406 /*
407 * Write an address range to the flash chip. Data must be written in
408 * FLASH_PAGESIZE chunks. The address range may be any size provided
409 * it is within the physical boundaries.
410 */
411 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
412 size_t *retlen, const u_char *buf)
413 {
414 struct m25p *flash = mtd_to_m25p(mtd);
415 u32 page_offset, page_size;
416 struct spi_transfer t[2];
417 struct spi_message m;
418
419 pr_debug("%s: %s %s 0x%08x, len %zd\n",
420 dev_name(&flash->spi->dev), __func__, "to",
421 (u32)to, len);
422
423 *retlen = 0;
424
425 /* sanity checks */
426 if (!len)
427 return(0);
428
429 if (to + len > flash->mtd.size)
430 return -EINVAL;
431
432 spi_message_init(&m);
433 memset(t, 0, (sizeof t));
434
435 t[0].tx_buf = flash->command;
436 t[0].len = m25p_cmdsz(flash);
437 spi_message_add_tail(&t[0], &m);
438
439 t[1].tx_buf = buf;
440 spi_message_add_tail(&t[1], &m);
441
442 mutex_lock(&flash->lock);
443
444 /* Wait until finished previous write command. */
445 if (wait_till_ready(flash)) {
446 mutex_unlock(&flash->lock);
447 return 1;
448 }
449
450 write_enable(flash);
451
452 /* Set up the opcode in the write buffer. */
453 flash->command[0] = OPCODE_PP;
454 m25p_addr2cmd(flash, to, flash->command);
455
456 page_offset = to & (flash->page_size - 1);
457
458 /* do all the bytes fit onto one page? */
459 if (page_offset + len <= flash->page_size) {
460 t[1].len = len;
461
462 spi_sync(flash->spi, &m);
463
464 *retlen = m.actual_length - m25p_cmdsz(flash);
465 } else {
466 u32 i;
467
468 /* the size of data remaining on the first page */
469 page_size = flash->page_size - page_offset;
470
471 t[1].len = page_size;
472 spi_sync(flash->spi, &m);
473
474 *retlen = m.actual_length - m25p_cmdsz(flash);
475
476 /* write everything in flash->page_size chunks */
477 for (i = page_size; i < len; i += page_size) {
478 page_size = len - i;
479 if (page_size > flash->page_size)
480 page_size = flash->page_size;
481
482 /* write the next page to flash */
483 m25p_addr2cmd(flash, to + i, flash->command);
484
485 t[1].tx_buf = buf + i;
486 t[1].len = page_size;
487
488 wait_till_ready(flash);
489
490 write_enable(flash);
491
492 spi_sync(flash->spi, &m);
493
494 *retlen += m.actual_length - m25p_cmdsz(flash);
495 }
496 }
497
498 mutex_unlock(&flash->lock);
499
500 return 0;
501 }
502
503 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
504 size_t *retlen, const u_char *buf)
505 {
506 struct m25p *flash = mtd_to_m25p(mtd);
507 struct spi_transfer t[2];
508 struct spi_message m;
509 size_t actual;
510 int cmd_sz, ret;
511
512 pr_debug("%s: %s %s 0x%08x, len %zd\n",
513 dev_name(&flash->spi->dev), __func__, "to",
514 (u32)to, len);
515
516 *retlen = 0;
517
518 /* sanity checks */
519 if (!len)
520 return 0;
521
522 if (to + len > flash->mtd.size)
523 return -EINVAL;
524
525 spi_message_init(&m);
526 memset(t, 0, (sizeof t));
527
528 t[0].tx_buf = flash->command;
529 t[0].len = m25p_cmdsz(flash);
530 spi_message_add_tail(&t[0], &m);
531
532 t[1].tx_buf = buf;
533 spi_message_add_tail(&t[1], &m);
534
535 mutex_lock(&flash->lock);
536
537 /* Wait until finished previous write command. */
538 ret = wait_till_ready(flash);
539 if (ret)
540 goto time_out;
541
542 write_enable(flash);
543
544 actual = to % 2;
545 /* Start write from odd address. */
546 if (actual) {
547 flash->command[0] = OPCODE_BP;
548 m25p_addr2cmd(flash, to, flash->command);
549
550 /* write one byte. */
551 t[1].len = 1;
552 spi_sync(flash->spi, &m);
553 ret = wait_till_ready(flash);
554 if (ret)
555 goto time_out;
556 *retlen += m.actual_length - m25p_cmdsz(flash);
557 }
558 to += actual;
559
560 flash->command[0] = OPCODE_AAI_WP;
561 m25p_addr2cmd(flash, to, flash->command);
562
563 /* Write out most of the data here. */
564 cmd_sz = m25p_cmdsz(flash);
565 for (; actual < len - 1; actual += 2) {
566 t[0].len = cmd_sz;
567 /* write two bytes. */
568 t[1].len = 2;
569 t[1].tx_buf = buf + actual;
570
571 spi_sync(flash->spi, &m);
572 ret = wait_till_ready(flash);
573 if (ret)
574 goto time_out;
575 *retlen += m.actual_length - cmd_sz;
576 cmd_sz = 1;
577 to += 2;
578 }
579 write_disable(flash);
580 ret = wait_till_ready(flash);
581 if (ret)
582 goto time_out;
583
584 /* Write out trailing byte if it exists. */
585 if (actual != len) {
586 write_enable(flash);
587 flash->command[0] = OPCODE_BP;
588 m25p_addr2cmd(flash, to, flash->command);
589 t[0].len = m25p_cmdsz(flash);
590 t[1].len = 1;
591 t[1].tx_buf = buf + actual;
592
593 spi_sync(flash->spi, &m);
594 ret = wait_till_ready(flash);
595 if (ret)
596 goto time_out;
597 *retlen += m.actual_length - m25p_cmdsz(flash);
598 write_disable(flash);
599 }
600
601 time_out:
602 mutex_unlock(&flash->lock);
603 return ret;
604 }
605
606 /****************************************************************************/
607
608 /*
609 * SPI device driver setup and teardown
610 */
611
612 struct flash_info {
613 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
614 * a high byte of zero plus three data bytes: the manufacturer id,
615 * then a two byte device id.
616 */
617 u32 jedec_id;
618 u16 ext_id;
619
620 /* The size listed here is what works with OPCODE_SE, which isn't
621 * necessarily called a "sector" by the vendor.
622 */
623 unsigned sector_size;
624 u16 n_sectors;
625
626 u16 page_size;
627 u16 addr_width;
628
629 u16 flags;
630 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
631 #define M25P_NO_ERASE 0x02 /* No erase command needed */
632 };
633
634 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
635 ((kernel_ulong_t)&(struct flash_info) { \
636 .jedec_id = (_jedec_id), \
637 .ext_id = (_ext_id), \
638 .sector_size = (_sector_size), \
639 .n_sectors = (_n_sectors), \
640 .page_size = 256, \
641 .flags = (_flags), \
642 })
643
644 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
645 ((kernel_ulong_t)&(struct flash_info) { \
646 .sector_size = (_sector_size), \
647 .n_sectors = (_n_sectors), \
648 .page_size = (_page_size), \
649 .addr_width = (_addr_width), \
650 .flags = M25P_NO_ERASE, \
651 })
652
653 /* NOTE: double check command sets and memory organization when you add
654 * more flash chips. This current list focusses on newer chips, which
655 * have been converging on command sets which including JEDEC ID.
656 */
657 static const struct spi_device_id m25p_ids[] = {
658 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
659 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
660 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
661
662 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
663 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
664
665 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
666 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
667 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
668 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
669
670 /* EON -- en25xxx */
671 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
672 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
673 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
674
675 /* Intel/Numonyx -- xxxs33b */
676 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
677 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
678 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
679
680 /* Macronix */
681 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
682 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
683 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
684 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
685 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
686 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
687 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
688 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
689 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
690
691 /* Spansion -- single (large) sector size only, at least
692 * for the chips listed here (without boot sectors).
693 */
694 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
695 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
696 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
697 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
698 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
699 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
700 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
701 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
702 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
703 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
704 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
705 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
706 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
707 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
708 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
709 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
710
711 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
712 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
713 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
714 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
715 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
716 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
717 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
718 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
719 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
720
721 /* ST Microelectronics -- newer production may have feature updates */
722 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
723 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
724 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
725 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
726 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
727 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
728 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
729 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
730 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
731
732 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
733 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
734 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
735 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
736 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
737 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
738 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
739 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
740 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
741
742 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
743 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
744 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
745
746 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
747 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
748
749 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
750 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
751 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
752 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
753
754 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
755 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
756 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
757 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
758 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
759 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
760 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
761 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
762 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
763 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
764
765 /* Catalyst / On Semiconductor -- non-JEDEC */
766 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
767 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
768 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
769 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
770 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
771 { },
772 };
773 MODULE_DEVICE_TABLE(spi, m25p_ids);
774
775 static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
776 {
777 int tmp;
778 u8 code = OPCODE_RDID;
779 u8 id[5];
780 u32 jedec;
781 u16 ext_jedec;
782 struct flash_info *info;
783
784 /* JEDEC also defines an optional "extended device information"
785 * string for after vendor-specific data, after the three bytes
786 * we use here. Supporting some chips might require using it.
787 */
788 tmp = spi_write_then_read(spi, &code, 1, id, 5);
789 if (tmp < 0) {
790 pr_debug("%s: error %d reading JEDEC ID\n",
791 dev_name(&spi->dev), tmp);
792 return ERR_PTR(tmp);
793 }
794 jedec = id[0];
795 jedec = jedec << 8;
796 jedec |= id[1];
797 jedec = jedec << 8;
798 jedec |= id[2];
799
800 ext_jedec = id[3] << 8 | id[4];
801
802 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
803 info = (void *)m25p_ids[tmp].driver_data;
804 if (info->jedec_id == jedec) {
805 if (info->ext_id != 0 && info->ext_id != ext_jedec)
806 continue;
807 return &m25p_ids[tmp];
808 }
809 }
810 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
811 return ERR_PTR(-ENODEV);
812 }
813
814
815 /*
816 * board specific setup should have ensured the SPI clock used here
817 * matches what the READ command supports, at least until this driver
818 * understands FAST_READ (for clocks over 25 MHz).
819 */
820 static int __devinit m25p_probe(struct spi_device *spi)
821 {
822 const struct spi_device_id *id = spi_get_device_id(spi);
823 struct flash_platform_data *data;
824 struct m25p *flash;
825 struct flash_info *info;
826 unsigned i;
827 struct mtd_part_parser_data ppdata;
828
829 /* Platform data helps sort out which chip type we have, as
830 * well as how this board partitions it. If we don't have
831 * a chip ID, try the JEDEC id commands; they'll work for most
832 * newer chips, even if we don't recognize the particular chip.
833 */
834 data = spi->dev.platform_data;
835 if (data && data->type) {
836 const struct spi_device_id *plat_id;
837
838 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
839 plat_id = &m25p_ids[i];
840 if (strcmp(data->type, plat_id->name))
841 continue;
842 break;
843 }
844
845 if (i < ARRAY_SIZE(m25p_ids) - 1)
846 id = plat_id;
847 else
848 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
849 }
850
851 info = (void *)id->driver_data;
852
853 if (info->jedec_id) {
854 const struct spi_device_id *jid;
855
856 jid = jedec_probe(spi);
857 if (IS_ERR(jid)) {
858 return PTR_ERR(jid);
859 } else if (jid != id) {
860 /*
861 * JEDEC knows better, so overwrite platform ID. We
862 * can't trust partitions any longer, but we'll let
863 * mtd apply them anyway, since some partitions may be
864 * marked read-only, and we don't want to lose that
865 * information, even if it's not 100% accurate.
866 */
867 dev_warn(&spi->dev, "found %s, expected %s\n",
868 jid->name, id->name);
869 id = jid;
870 info = (void *)jid->driver_data;
871 }
872 }
873
874 flash = kzalloc(sizeof *flash, GFP_KERNEL);
875 if (!flash)
876 return -ENOMEM;
877 flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
878 if (!flash->command) {
879 kfree(flash);
880 return -ENOMEM;
881 }
882
883 flash->spi = spi;
884 mutex_init(&flash->lock);
885 dev_set_drvdata(&spi->dev, flash);
886
887 /*
888 * Atmel, SST and Intel/Numonyx serial flash tend to power
889 * up with the software protection bits set
890 */
891
892 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
893 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
894 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
895 write_enable(flash);
896 write_sr(flash, 0);
897 }
898
899 if (data && data->name)
900 flash->mtd.name = data->name;
901 else
902 flash->mtd.name = dev_name(&spi->dev);
903
904 flash->mtd.type = MTD_NORFLASH;
905 flash->mtd.writesize = 1;
906 flash->mtd.flags = MTD_CAP_NORFLASH;
907 flash->mtd.size = info->sector_size * info->n_sectors;
908 flash->mtd.erase = m25p80_erase;
909 flash->mtd.read = m25p80_read;
910
911 /* sst flash chips use AAI word program */
912 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
913 flash->mtd.write = sst_write;
914 else
915 flash->mtd.write = m25p80_write;
916
917 /* prefer "small sector" erase if possible */
918 if (info->flags & SECT_4K) {
919 flash->erase_opcode = OPCODE_BE_4K;
920 flash->mtd.erasesize = 4096;
921 } else {
922 flash->erase_opcode = OPCODE_SE;
923 flash->mtd.erasesize = info->sector_size;
924 }
925
926 if (info->flags & M25P_NO_ERASE)
927 flash->mtd.flags |= MTD_NO_ERASE;
928
929 ppdata.of_node = spi->dev.of_node;
930 flash->mtd.dev.parent = &spi->dev;
931 flash->page_size = info->page_size;
932
933 if (info->addr_width)
934 flash->addr_width = info->addr_width;
935 else {
936 /* enable 4-byte addressing if the device exceeds 16MiB */
937 if (flash->mtd.size > 0x1000000) {
938 flash->addr_width = 4;
939 set_4byte(flash, info->jedec_id, 1);
940 } else
941 flash->addr_width = 3;
942 }
943
944 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
945 (long long)flash->mtd.size >> 10);
946
947 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
948 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
949 flash->mtd.name,
950 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
951 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
952 flash->mtd.numeraseregions);
953
954 if (flash->mtd.numeraseregions)
955 for (i = 0; i < flash->mtd.numeraseregions; i++)
956 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
957 ".erasesize = 0x%.8x (%uKiB), "
958 ".numblocks = %d }\n",
959 i, (long long)flash->mtd.eraseregions[i].offset,
960 flash->mtd.eraseregions[i].erasesize,
961 flash->mtd.eraseregions[i].erasesize / 1024,
962 flash->mtd.eraseregions[i].numblocks);
963
964
965 /* partitions should match sector boundaries; and it may be good to
966 * use readonly partitions for writeprotected sectors (BP2..BP0).
967 */
968 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
969 data ? data->parts : NULL,
970 data ? data->nr_parts : 0);
971 }
972
973
974 static int __devexit m25p_remove(struct spi_device *spi)
975 {
976 struct m25p *flash = dev_get_drvdata(&spi->dev);
977 int status;
978
979 /* Clean up MTD stuff. */
980 status = mtd_device_unregister(&flash->mtd);
981 if (status == 0) {
982 kfree(flash->command);
983 kfree(flash);
984 }
985 return 0;
986 }
987
988
989 static struct spi_driver m25p80_driver = {
990 .driver = {
991 .name = "m25p80",
992 .bus = &spi_bus_type,
993 .owner = THIS_MODULE,
994 },
995 .id_table = m25p_ids,
996 .probe = m25p_probe,
997 .remove = __devexit_p(m25p_remove),
998
999 /* REVISIT: many of these chips have deep power-down modes, which
1000 * should clearly be entered on suspend() to minimize power use.
1001 * And also when they're otherwise idle...
1002 */
1003 };
1004
1005
1006 static int __init m25p80_init(void)
1007 {
1008 return spi_register_driver(&m25p80_driver);
1009 }
1010
1011
1012 static void __exit m25p80_exit(void)
1013 {
1014 spi_unregister_driver(&m25p80_driver);
1015 }
1016
1017
1018 module_init(m25p80_init);
1019 module_exit(m25p80_exit);
1020
1021 MODULE_LICENSE("GPL");
1022 MODULE_AUTHOR("Mike Lavender");
1023 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
Linux kernel - Deliverables
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