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mtd: cleanup style on pr_debug messages
[deliverable/linux.git] / drivers / mtd / devices / m25p80.c
1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 *
4 * Author: Mike Lavender, mike@steroidmicros.com
5 *
6 * Copyright (c) 2005, Intec Automation Inc.
7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 *
10 * Cleaned up and generalized based on mtd_dataflash.c
11 *
12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18 #include <linux/init.h>
19 #include <linux/err.h>
20 #include <linux/errno.h>
21 #include <linux/module.h>
22 #include <linux/device.h>
23 #include <linux/interrupt.h>
24 #include <linux/mutex.h>
25 #include <linux/math64.h>
26 #include <linux/slab.h>
27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h>
29
30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h>
33
34 #include <linux/spi/spi.h>
35 #include <linux/spi/flash.h>
36
37 /* Flash opcodes. */
38 #define OPCODE_WREN 0x06 /* Write enable */
39 #define OPCODE_RDSR 0x05 /* Read status register */
40 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
41 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
42 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
43 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
44 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
45 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
46 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
47 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
48 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
49
50 /* Used for SST flashes only. */
51 #define OPCODE_BP 0x02 /* Byte program */
52 #define OPCODE_WRDI 0x04 /* Write disable */
53 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
54
55 /* Used for Macronix flashes only. */
56 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
57 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
58
59 /* Used for Spansion flashes only. */
60 #define OPCODE_BRWR 0x17 /* Bank register write */
61
62 /* Status Register bits. */
63 #define SR_WIP 1 /* Write in progress */
64 #define SR_WEL 2 /* Write enable latch */
65 /* meaning of other SR_* bits may differ between vendors */
66 #define SR_BP0 4 /* Block protect 0 */
67 #define SR_BP1 8 /* Block protect 1 */
68 #define SR_BP2 0x10 /* Block protect 2 */
69 #define SR_SRWD 0x80 /* SR write protect */
70
71 /* Define max times to check status register before we give up. */
72 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
73 #define MAX_CMD_SIZE 5
74
75 #ifdef CONFIG_M25PXX_USE_FAST_READ
76 #define OPCODE_READ OPCODE_FAST_READ
77 #define FAST_READ_DUMMY_BYTE 1
78 #else
79 #define OPCODE_READ OPCODE_NORM_READ
80 #define FAST_READ_DUMMY_BYTE 0
81 #endif
82
83 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
84
85 /****************************************************************************/
86
87 struct m25p {
88 struct spi_device *spi;
89 struct mutex lock;
90 struct mtd_info mtd;
91 u16 page_size;
92 u16 addr_width;
93 u8 erase_opcode;
94 u8 *command;
95 };
96
97 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
98 {
99 return container_of(mtd, struct m25p, mtd);
100 }
101
102 /****************************************************************************/
103
104 /*
105 * Internal helper functions
106 */
107
108 /*
109 * Read the status register, returning its value in the location
110 * Return the status register value.
111 * Returns negative if error occurred.
112 */
113 static int read_sr(struct m25p *flash)
114 {
115 ssize_t retval;
116 u8 code = OPCODE_RDSR;
117 u8 val;
118
119 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
120
121 if (retval < 0) {
122 dev_err(&flash->spi->dev, "error %d reading SR\n",
123 (int) retval);
124 return retval;
125 }
126
127 return val;
128 }
129
130 /*
131 * Write status register 1 byte
132 * Returns negative if error occurred.
133 */
134 static int write_sr(struct m25p *flash, u8 val)
135 {
136 flash->command[0] = OPCODE_WRSR;
137 flash->command[1] = val;
138
139 return spi_write(flash->spi, flash->command, 2);
140 }
141
142 /*
143 * Set write enable latch with Write Enable command.
144 * Returns negative if error occurred.
145 */
146 static inline int write_enable(struct m25p *flash)
147 {
148 u8 code = OPCODE_WREN;
149
150 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
151 }
152
153 /*
154 * Send write disble instruction to the chip.
155 */
156 static inline int write_disable(struct m25p *flash)
157 {
158 u8 code = OPCODE_WRDI;
159
160 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
161 }
162
163 /*
164 * Enable/disable 4-byte addressing mode.
165 */
166 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
167 {
168 switch (JEDEC_MFR(jedec_id)) {
169 case CFI_MFR_MACRONIX:
170 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
171 return spi_write(flash->spi, flash->command, 1);
172 default:
173 /* Spansion style */
174 flash->command[0] = OPCODE_BRWR;
175 flash->command[1] = enable << 7;
176 return spi_write(flash->spi, flash->command, 2);
177 }
178 }
179
180 /*
181 * Service routine to read status register until ready, or timeout occurs.
182 * Returns non-zero if error.
183 */
184 static int wait_till_ready(struct m25p *flash)
185 {
186 unsigned long deadline;
187 int sr;
188
189 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
190
191 do {
192 if ((sr = read_sr(flash)) < 0)
193 break;
194 else if (!(sr & SR_WIP))
195 return 0;
196
197 cond_resched();
198
199 } while (!time_after_eq(jiffies, deadline));
200
201 return 1;
202 }
203
204 /*
205 * Erase the whole flash memory
206 *
207 * Returns 0 if successful, non-zero otherwise.
208 */
209 static int erase_chip(struct m25p *flash)
210 {
211 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
212 (long long)(flash->mtd.size >> 10));
213
214 /* Wait until finished previous write command. */
215 if (wait_till_ready(flash))
216 return 1;
217
218 /* Send write enable, then erase commands. */
219 write_enable(flash);
220
221 /* Set up command buffer. */
222 flash->command[0] = OPCODE_CHIP_ERASE;
223
224 spi_write(flash->spi, flash->command, 1);
225
226 return 0;
227 }
228
229 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
230 {
231 /* opcode is in cmd[0] */
232 cmd[1] = addr >> (flash->addr_width * 8 - 8);
233 cmd[2] = addr >> (flash->addr_width * 8 - 16);
234 cmd[3] = addr >> (flash->addr_width * 8 - 24);
235 cmd[4] = addr >> (flash->addr_width * 8 - 32);
236 }
237
238 static int m25p_cmdsz(struct m25p *flash)
239 {
240 return 1 + flash->addr_width;
241 }
242
243 /*
244 * Erase one sector of flash memory at offset ``offset'' which is any
245 * address within the sector which should be erased.
246 *
247 * Returns 0 if successful, non-zero otherwise.
248 */
249 static int erase_sector(struct m25p *flash, u32 offset)
250 {
251 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
252 __func__, flash->mtd.erasesize / 1024, offset);
253
254 /* Wait until finished previous write command. */
255 if (wait_till_ready(flash))
256 return 1;
257
258 /* Send write enable, then erase commands. */
259 write_enable(flash);
260
261 /* Set up command buffer. */
262 flash->command[0] = flash->erase_opcode;
263 m25p_addr2cmd(flash, offset, flash->command);
264
265 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
266
267 return 0;
268 }
269
270 /****************************************************************************/
271
272 /*
273 * MTD implementation
274 */
275
276 /*
277 * Erase an address range on the flash chip. The address range may extend
278 * one or more erase sectors. Return an error is there is a problem erasing.
279 */
280 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
281 {
282 struct m25p *flash = mtd_to_m25p(mtd);
283 u32 addr,len;
284 uint32_t rem;
285
286 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
287 __func__, (long long)instr->addr,
288 (long long)instr->len);
289
290 /* sanity checks */
291 if (instr->addr + instr->len > flash->mtd.size)
292 return -EINVAL;
293 div_u64_rem(instr->len, mtd->erasesize, &rem);
294 if (rem)
295 return -EINVAL;
296
297 addr = instr->addr;
298 len = instr->len;
299
300 mutex_lock(&flash->lock);
301
302 /* whole-chip erase? */
303 if (len == flash->mtd.size) {
304 if (erase_chip(flash)) {
305 instr->state = MTD_ERASE_FAILED;
306 mutex_unlock(&flash->lock);
307 return -EIO;
308 }
309
310 /* REVISIT in some cases we could speed up erasing large regions
311 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
312 * to use "small sector erase", but that's not always optimal.
313 */
314
315 /* "sector"-at-a-time erase */
316 } else {
317 while (len) {
318 if (erase_sector(flash, addr)) {
319 instr->state = MTD_ERASE_FAILED;
320 mutex_unlock(&flash->lock);
321 return -EIO;
322 }
323
324 addr += mtd->erasesize;
325 len -= mtd->erasesize;
326 }
327 }
328
329 mutex_unlock(&flash->lock);
330
331 instr->state = MTD_ERASE_DONE;
332 mtd_erase_callback(instr);
333
334 return 0;
335 }
336
337 /*
338 * Read an address range from the flash chip. The address range
339 * may be any size provided it is within the physical boundaries.
340 */
341 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
342 size_t *retlen, u_char *buf)
343 {
344 struct m25p *flash = mtd_to_m25p(mtd);
345 struct spi_transfer t[2];
346 struct spi_message m;
347
348 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
349 __func__, (u32)from, len);
350
351 /* sanity checks */
352 if (!len)
353 return 0;
354
355 if (from + len > flash->mtd.size)
356 return -EINVAL;
357
358 spi_message_init(&m);
359 memset(t, 0, (sizeof t));
360
361 /* NOTE:
362 * OPCODE_FAST_READ (if available) is faster.
363 * Should add 1 byte DUMMY_BYTE.
364 */
365 t[0].tx_buf = flash->command;
366 t[0].len = m25p_cmdsz(flash) + FAST_READ_DUMMY_BYTE;
367 spi_message_add_tail(&t[0], &m);
368
369 t[1].rx_buf = buf;
370 t[1].len = len;
371 spi_message_add_tail(&t[1], &m);
372
373 /* Byte count starts at zero. */
374 *retlen = 0;
375
376 mutex_lock(&flash->lock);
377
378 /* Wait till previous write/erase is done. */
379 if (wait_till_ready(flash)) {
380 /* REVISIT status return?? */
381 mutex_unlock(&flash->lock);
382 return 1;
383 }
384
385 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
386 * clocks; and at this writing, every chip this driver handles
387 * supports that opcode.
388 */
389
390 /* Set up the write data buffer. */
391 flash->command[0] = OPCODE_READ;
392 m25p_addr2cmd(flash, from, flash->command);
393
394 spi_sync(flash->spi, &m);
395
396 *retlen = m.actual_length - m25p_cmdsz(flash) - FAST_READ_DUMMY_BYTE;
397
398 mutex_unlock(&flash->lock);
399
400 return 0;
401 }
402
403 /*
404 * Write an address range to the flash chip. Data must be written in
405 * FLASH_PAGESIZE chunks. The address range may be any size provided
406 * it is within the physical boundaries.
407 */
408 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
409 size_t *retlen, const u_char *buf)
410 {
411 struct m25p *flash = mtd_to_m25p(mtd);
412 u32 page_offset, page_size;
413 struct spi_transfer t[2];
414 struct spi_message m;
415
416 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
417 __func__, (u32)to, len);
418
419 *retlen = 0;
420
421 /* sanity checks */
422 if (!len)
423 return(0);
424
425 if (to + len > flash->mtd.size)
426 return -EINVAL;
427
428 spi_message_init(&m);
429 memset(t, 0, (sizeof t));
430
431 t[0].tx_buf = flash->command;
432 t[0].len = m25p_cmdsz(flash);
433 spi_message_add_tail(&t[0], &m);
434
435 t[1].tx_buf = buf;
436 spi_message_add_tail(&t[1], &m);
437
438 mutex_lock(&flash->lock);
439
440 /* Wait until finished previous write command. */
441 if (wait_till_ready(flash)) {
442 mutex_unlock(&flash->lock);
443 return 1;
444 }
445
446 write_enable(flash);
447
448 /* Set up the opcode in the write buffer. */
449 flash->command[0] = OPCODE_PP;
450 m25p_addr2cmd(flash, to, flash->command);
451
452 page_offset = to & (flash->page_size - 1);
453
454 /* do all the bytes fit onto one page? */
455 if (page_offset + len <= flash->page_size) {
456 t[1].len = len;
457
458 spi_sync(flash->spi, &m);
459
460 *retlen = m.actual_length - m25p_cmdsz(flash);
461 } else {
462 u32 i;
463
464 /* the size of data remaining on the first page */
465 page_size = flash->page_size - page_offset;
466
467 t[1].len = page_size;
468 spi_sync(flash->spi, &m);
469
470 *retlen = m.actual_length - m25p_cmdsz(flash);
471
472 /* write everything in flash->page_size chunks */
473 for (i = page_size; i < len; i += page_size) {
474 page_size = len - i;
475 if (page_size > flash->page_size)
476 page_size = flash->page_size;
477
478 /* write the next page to flash */
479 m25p_addr2cmd(flash, to + i, flash->command);
480
481 t[1].tx_buf = buf + i;
482 t[1].len = page_size;
483
484 wait_till_ready(flash);
485
486 write_enable(flash);
487
488 spi_sync(flash->spi, &m);
489
490 *retlen += m.actual_length - m25p_cmdsz(flash);
491 }
492 }
493
494 mutex_unlock(&flash->lock);
495
496 return 0;
497 }
498
499 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
500 size_t *retlen, const u_char *buf)
501 {
502 struct m25p *flash = mtd_to_m25p(mtd);
503 struct spi_transfer t[2];
504 struct spi_message m;
505 size_t actual;
506 int cmd_sz, ret;
507
508 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
509 __func__, (u32)to, len);
510
511 *retlen = 0;
512
513 /* sanity checks */
514 if (!len)
515 return 0;
516
517 if (to + len > flash->mtd.size)
518 return -EINVAL;
519
520 spi_message_init(&m);
521 memset(t, 0, (sizeof t));
522
523 t[0].tx_buf = flash->command;
524 t[0].len = m25p_cmdsz(flash);
525 spi_message_add_tail(&t[0], &m);
526
527 t[1].tx_buf = buf;
528 spi_message_add_tail(&t[1], &m);
529
530 mutex_lock(&flash->lock);
531
532 /* Wait until finished previous write command. */
533 ret = wait_till_ready(flash);
534 if (ret)
535 goto time_out;
536
537 write_enable(flash);
538
539 actual = to % 2;
540 /* Start write from odd address. */
541 if (actual) {
542 flash->command[0] = OPCODE_BP;
543 m25p_addr2cmd(flash, to, flash->command);
544
545 /* write one byte. */
546 t[1].len = 1;
547 spi_sync(flash->spi, &m);
548 ret = wait_till_ready(flash);
549 if (ret)
550 goto time_out;
551 *retlen += m.actual_length - m25p_cmdsz(flash);
552 }
553 to += actual;
554
555 flash->command[0] = OPCODE_AAI_WP;
556 m25p_addr2cmd(flash, to, flash->command);
557
558 /* Write out most of the data here. */
559 cmd_sz = m25p_cmdsz(flash);
560 for (; actual < len - 1; actual += 2) {
561 t[0].len = cmd_sz;
562 /* write two bytes. */
563 t[1].len = 2;
564 t[1].tx_buf = buf + actual;
565
566 spi_sync(flash->spi, &m);
567 ret = wait_till_ready(flash);
568 if (ret)
569 goto time_out;
570 *retlen += m.actual_length - cmd_sz;
571 cmd_sz = 1;
572 to += 2;
573 }
574 write_disable(flash);
575 ret = wait_till_ready(flash);
576 if (ret)
577 goto time_out;
578
579 /* Write out trailing byte if it exists. */
580 if (actual != len) {
581 write_enable(flash);
582 flash->command[0] = OPCODE_BP;
583 m25p_addr2cmd(flash, to, flash->command);
584 t[0].len = m25p_cmdsz(flash);
585 t[1].len = 1;
586 t[1].tx_buf = buf + actual;
587
588 spi_sync(flash->spi, &m);
589 ret = wait_till_ready(flash);
590 if (ret)
591 goto time_out;
592 *retlen += m.actual_length - m25p_cmdsz(flash);
593 write_disable(flash);
594 }
595
596 time_out:
597 mutex_unlock(&flash->lock);
598 return ret;
599 }
600
601 /****************************************************************************/
602
603 /*
604 * SPI device driver setup and teardown
605 */
606
607 struct flash_info {
608 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
609 * a high byte of zero plus three data bytes: the manufacturer id,
610 * then a two byte device id.
611 */
612 u32 jedec_id;
613 u16 ext_id;
614
615 /* The size listed here is what works with OPCODE_SE, which isn't
616 * necessarily called a "sector" by the vendor.
617 */
618 unsigned sector_size;
619 u16 n_sectors;
620
621 u16 page_size;
622 u16 addr_width;
623
624 u16 flags;
625 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
626 #define M25P_NO_ERASE 0x02 /* No erase command needed */
627 };
628
629 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
630 ((kernel_ulong_t)&(struct flash_info) { \
631 .jedec_id = (_jedec_id), \
632 .ext_id = (_ext_id), \
633 .sector_size = (_sector_size), \
634 .n_sectors = (_n_sectors), \
635 .page_size = 256, \
636 .flags = (_flags), \
637 })
638
639 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
640 ((kernel_ulong_t)&(struct flash_info) { \
641 .sector_size = (_sector_size), \
642 .n_sectors = (_n_sectors), \
643 .page_size = (_page_size), \
644 .addr_width = (_addr_width), \
645 .flags = M25P_NO_ERASE, \
646 })
647
648 /* NOTE: double check command sets and memory organization when you add
649 * more flash chips. This current list focusses on newer chips, which
650 * have been converging on command sets which including JEDEC ID.
651 */
652 static const struct spi_device_id m25p_ids[] = {
653 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
654 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
655 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
656
657 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
658 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
659
660 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
661 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
662 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
663 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
664
665 /* EON -- en25xxx */
666 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
667 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
668 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
669
670 /* Intel/Numonyx -- xxxs33b */
671 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
672 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
673 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
674
675 /* Macronix */
676 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
677 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
678 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
679 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
680 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
681 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
682 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
683 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
684 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
685
686 /* Spansion -- single (large) sector size only, at least
687 * for the chips listed here (without boot sectors).
688 */
689 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
690 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
691 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
692 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
693 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SECT_4K) },
694 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
695 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
696 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
697 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
698 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
699 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
700 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
701 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
702 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
703 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
704 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
705
706 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
707 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
708 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
709 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
710 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
711 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
712 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
713 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
714 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
715
716 /* ST Microelectronics -- newer production may have feature updates */
717 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
718 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
719 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
720 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
721 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
722 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
723 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
724 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
725 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
726
727 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
728 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
729 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
730 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
731 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
732 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
733 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
734 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
735 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
736
737 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
738 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
739 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
740
741 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
742 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
743
744 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
745 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
746 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
747 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
748
749 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
750 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
751 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
752 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
753 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
754 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
755 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
756 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
757 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
758 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
759
760 /* Catalyst / On Semiconductor -- non-JEDEC */
761 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
762 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
763 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
764 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
765 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
766 { },
767 };
768 MODULE_DEVICE_TABLE(spi, m25p_ids);
769
770 static const struct spi_device_id *__devinit jedec_probe(struct spi_device *spi)
771 {
772 int tmp;
773 u8 code = OPCODE_RDID;
774 u8 id[5];
775 u32 jedec;
776 u16 ext_jedec;
777 struct flash_info *info;
778
779 /* JEDEC also defines an optional "extended device information"
780 * string for after vendor-specific data, after the three bytes
781 * we use here. Supporting some chips might require using it.
782 */
783 tmp = spi_write_then_read(spi, &code, 1, id, 5);
784 if (tmp < 0) {
785 pr_debug("%s: error %d reading JEDEC ID\n",
786 dev_name(&spi->dev), tmp);
787 return ERR_PTR(tmp);
788 }
789 jedec = id[0];
790 jedec = jedec << 8;
791 jedec |= id[1];
792 jedec = jedec << 8;
793 jedec |= id[2];
794
795 ext_jedec = id[3] << 8 | id[4];
796
797 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
798 info = (void *)m25p_ids[tmp].driver_data;
799 if (info->jedec_id == jedec) {
800 if (info->ext_id != 0 && info->ext_id != ext_jedec)
801 continue;
802 return &m25p_ids[tmp];
803 }
804 }
805 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
806 return ERR_PTR(-ENODEV);
807 }
808
809
810 /*
811 * board specific setup should have ensured the SPI clock used here
812 * matches what the READ command supports, at least until this driver
813 * understands FAST_READ (for clocks over 25 MHz).
814 */
815 static int __devinit m25p_probe(struct spi_device *spi)
816 {
817 const struct spi_device_id *id = spi_get_device_id(spi);
818 struct flash_platform_data *data;
819 struct m25p *flash;
820 struct flash_info *info;
821 unsigned i;
822 struct mtd_part_parser_data ppdata;
823
824 /* Platform data helps sort out which chip type we have, as
825 * well as how this board partitions it. If we don't have
826 * a chip ID, try the JEDEC id commands; they'll work for most
827 * newer chips, even if we don't recognize the particular chip.
828 */
829 data = spi->dev.platform_data;
830 if (data && data->type) {
831 const struct spi_device_id *plat_id;
832
833 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
834 plat_id = &m25p_ids[i];
835 if (strcmp(data->type, plat_id->name))
836 continue;
837 break;
838 }
839
840 if (i < ARRAY_SIZE(m25p_ids) - 1)
841 id = plat_id;
842 else
843 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
844 }
845
846 info = (void *)id->driver_data;
847
848 if (info->jedec_id) {
849 const struct spi_device_id *jid;
850
851 jid = jedec_probe(spi);
852 if (IS_ERR(jid)) {
853 return PTR_ERR(jid);
854 } else if (jid != id) {
855 /*
856 * JEDEC knows better, so overwrite platform ID. We
857 * can't trust partitions any longer, but we'll let
858 * mtd apply them anyway, since some partitions may be
859 * marked read-only, and we don't want to lose that
860 * information, even if it's not 100% accurate.
861 */
862 dev_warn(&spi->dev, "found %s, expected %s\n",
863 jid->name, id->name);
864 id = jid;
865 info = (void *)jid->driver_data;
866 }
867 }
868
869 flash = kzalloc(sizeof *flash, GFP_KERNEL);
870 if (!flash)
871 return -ENOMEM;
872 flash->command = kmalloc(MAX_CMD_SIZE + FAST_READ_DUMMY_BYTE, GFP_KERNEL);
873 if (!flash->command) {
874 kfree(flash);
875 return -ENOMEM;
876 }
877
878 flash->spi = spi;
879 mutex_init(&flash->lock);
880 dev_set_drvdata(&spi->dev, flash);
881
882 /*
883 * Atmel, SST and Intel/Numonyx serial flash tend to power
884 * up with the software protection bits set
885 */
886
887 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
888 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
889 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
890 write_enable(flash);
891 write_sr(flash, 0);
892 }
893
894 if (data && data->name)
895 flash->mtd.name = data->name;
896 else
897 flash->mtd.name = dev_name(&spi->dev);
898
899 flash->mtd.type = MTD_NORFLASH;
900 flash->mtd.writesize = 1;
901 flash->mtd.flags = MTD_CAP_NORFLASH;
902 flash->mtd.size = info->sector_size * info->n_sectors;
903 flash->mtd.erase = m25p80_erase;
904 flash->mtd.read = m25p80_read;
905
906 /* sst flash chips use AAI word program */
907 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
908 flash->mtd.write = sst_write;
909 else
910 flash->mtd.write = m25p80_write;
911
912 /* prefer "small sector" erase if possible */
913 if (info->flags & SECT_4K) {
914 flash->erase_opcode = OPCODE_BE_4K;
915 flash->mtd.erasesize = 4096;
916 } else {
917 flash->erase_opcode = OPCODE_SE;
918 flash->mtd.erasesize = info->sector_size;
919 }
920
921 if (info->flags & M25P_NO_ERASE)
922 flash->mtd.flags |= MTD_NO_ERASE;
923
924 ppdata.of_node = spi->dev.of_node;
925 flash->mtd.dev.parent = &spi->dev;
926 flash->page_size = info->page_size;
927
928 if (info->addr_width)
929 flash->addr_width = info->addr_width;
930 else {
931 /* enable 4-byte addressing if the device exceeds 16MiB */
932 if (flash->mtd.size > 0x1000000) {
933 flash->addr_width = 4;
934 set_4byte(flash, info->jedec_id, 1);
935 } else
936 flash->addr_width = 3;
937 }
938
939 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
940 (long long)flash->mtd.size >> 10);
941
942 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
943 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
944 flash->mtd.name,
945 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
946 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
947 flash->mtd.numeraseregions);
948
949 if (flash->mtd.numeraseregions)
950 for (i = 0; i < flash->mtd.numeraseregions; i++)
951 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
952 ".erasesize = 0x%.8x (%uKiB), "
953 ".numblocks = %d }\n",
954 i, (long long)flash->mtd.eraseregions[i].offset,
955 flash->mtd.eraseregions[i].erasesize,
956 flash->mtd.eraseregions[i].erasesize / 1024,
957 flash->mtd.eraseregions[i].numblocks);
958
959
960 /* partitions should match sector boundaries; and it may be good to
961 * use readonly partitions for writeprotected sectors (BP2..BP0).
962 */
963 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
964 data ? data->parts : NULL,
965 data ? data->nr_parts : 0);
966 }
967
968
969 static int __devexit m25p_remove(struct spi_device *spi)
970 {
971 struct m25p *flash = dev_get_drvdata(&spi->dev);
972 int status;
973
974 /* Clean up MTD stuff. */
975 status = mtd_device_unregister(&flash->mtd);
976 if (status == 0) {
977 kfree(flash->command);
978 kfree(flash);
979 }
980 return 0;
981 }
982
983
984 static struct spi_driver m25p80_driver = {
985 .driver = {
986 .name = "m25p80",
987 .bus = &spi_bus_type,
988 .owner = THIS_MODULE,
989 },
990 .id_table = m25p_ids,
991 .probe = m25p_probe,
992 .remove = __devexit_p(m25p_remove),
993
994 /* REVISIT: many of these chips have deep power-down modes, which
995 * should clearly be entered on suspend() to minimize power use.
996 * And also when they're otherwise idle...
997 */
998 };
999
1000
1001 static int __init m25p80_init(void)
1002 {
1003 return spi_register_driver(&m25p80_driver);
1004 }
1005
1006
1007 static void __exit m25p80_exit(void)
1008 {
1009 spi_unregister_driver(&m25p80_driver);
1010 }
1011
1012
1013 module_init(m25p80_init);
1014 module_exit(m25p80_exit);
1015
1016 MODULE_LICENSE("GPL");
1017 MODULE_AUTHOR("Mike Lavender");
1018 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
Linux kernel - Deliverables
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