2 * drivers/mtd/nand/ams-delta.c
4 * Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
6 * Derived from drivers/mtd/toto.c
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * This is a device driver for the NAND flash device found on the
17 #include <linux/slab.h>
18 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/delay.h>
21 #include <linux/mtd/mtd.h>
22 #include <linux/mtd/nand.h>
23 #include <linux/mtd/partitions.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/sizes.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/arch/board-ams-delta.h>
31 * MTD structure for E3 (Delta)
33 static struct mtd_info
*ams_delta_mtd
= NULL
;
35 #define NAND_MASK (AMS_DELTA_LATCH2_NAND_NRE | AMS_DELTA_LATCH2_NAND_NWE | AMS_DELTA_LATCH2_NAND_CLE | AMS_DELTA_LATCH2_NAND_ALE | AMS_DELTA_LATCH2_NAND_NCE | AMS_DELTA_LATCH2_NAND_NWP)
37 #define T_NAND_CTL_CLRALE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_ALE, 0)
38 #define T_NAND_CTL_SETALE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_ALE, AMS_DELTA_LATCH2_NAND_ALE)
39 #define T_NAND_CTL_CLRCLE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE, 0)
40 #define T_NAND_CTL_SETCLE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_CLE, AMS_DELTA_LATCH2_NAND_CLE)
41 #define T_NAND_CTL_SETNCE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NCE, 0)
42 #define T_NAND_CTL_CLRNCE(iob) ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NCE, AMS_DELTA_LATCH2_NAND_NCE)
45 * Define partitions for flash devices
48 static struct mtd_partition partition_info
[] = {
51 .size
= 3 * SZ_1M
+ SZ_512K
},
53 .offset
= 3 * SZ_1M
+ SZ_512K
,
55 { .name
= "u-boot params",
56 .offset
= 3 * SZ_1M
+ SZ_512K
+ SZ_256K
,
58 { .name
= "Amstrad LDR",
61 { .name
= "File system",
62 .offset
= 4 * SZ_1M
+ 1 * SZ_256K
,
64 { .name
= "PBL reserved",
65 .offset
= 32 * SZ_1M
- 3 * SZ_256K
,
66 .size
= 3 * SZ_256K
},
70 * hardware specific access to control-lines
73 static void ams_delta_hwcontrol(struct mtd_info
*mtd
, int cmd
)
77 case NAND_CTL_SETCLE
: T_NAND_CTL_SETCLE(cmd
); break;
78 case NAND_CTL_CLRCLE
: T_NAND_CTL_CLRCLE(cmd
); break;
80 case NAND_CTL_SETALE
: T_NAND_CTL_SETALE(cmd
); break;
81 case NAND_CTL_CLRALE
: T_NAND_CTL_CLRALE(cmd
); break;
83 case NAND_CTL_SETNCE
: T_NAND_CTL_SETNCE(cmd
); break;
84 case NAND_CTL_CLRNCE
: T_NAND_CTL_CLRNCE(cmd
); break;
88 static void ams_delta_write_byte(struct mtd_info
*mtd
, u_char byte
)
90 struct nand_chip
*this = mtd
->priv
;
92 omap_writew(0, (OMAP_MPUIO_BASE
+ OMAP_MPUIO_IO_CNTL
));
93 omap_writew(byte
, this->IO_ADDR_W
);
94 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE
, 0);
96 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NWE
,
97 AMS_DELTA_LATCH2_NAND_NWE
);
100 static u_char
ams_delta_read_byte(struct mtd_info
*mtd
)
103 struct nand_chip
*this = mtd
->priv
;
105 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE
, 0);
107 omap_writew(~0, (OMAP_MPUIO_BASE
+ OMAP_MPUIO_IO_CNTL
));
108 res
= omap_readw(this->IO_ADDR_R
);
109 ams_delta_latch2_write(AMS_DELTA_LATCH2_NAND_NRE
,
110 AMS_DELTA_LATCH2_NAND_NRE
);
115 static void ams_delta_write_buf(struct mtd_info
*mtd
, const u_char
*buf
,
120 for (i
=0; i
<len
; i
++)
121 ams_delta_write_byte(mtd
, buf
[i
]);
124 static void ams_delta_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
128 for (i
=0; i
<len
; i
++)
129 buf
[i
] = ams_delta_read_byte(mtd
);
132 static int ams_delta_verify_buf(struct mtd_info
*mtd
, const u_char
*buf
,
137 for (i
=0; i
<len
; i
++)
138 if (buf
[i
] != ams_delta_read_byte(mtd
))
144 static int ams_delta_nand_ready(struct mtd_info
*mtd
)
146 return omap_get_gpio_datain(AMS_DELTA_GPIO_PIN_NAND_RB
);
150 * Main initialization routine
152 static int __init
ams_delta_init(void)
154 struct nand_chip
*this;
157 /* Allocate memory for MTD device structure and private data */
158 ams_delta_mtd
= kmalloc(sizeof(struct mtd_info
) +
159 sizeof(struct nand_chip
), GFP_KERNEL
);
160 if (!ams_delta_mtd
) {
161 printk (KERN_WARNING
"Unable to allocate E3 NAND MTD device structure.\n");
166 ams_delta_mtd
->owner
= THIS_MODULE
;
168 /* Get pointer to private data */
169 this = (struct nand_chip
*) (&ams_delta_mtd
[1]);
171 /* Initialize structures */
172 memset(ams_delta_mtd
, 0, sizeof(struct mtd_info
));
173 memset(this, 0, sizeof(struct nand_chip
));
175 /* Link the private data with the MTD structure */
176 ams_delta_mtd
->priv
= this;
178 /* Set address of NAND IO lines */
179 this->IO_ADDR_R
= (OMAP_MPUIO_BASE
+ OMAP_MPUIO_INPUT_LATCH
);
180 this->IO_ADDR_W
= (OMAP_MPUIO_BASE
+ OMAP_MPUIO_OUTPUT
);
181 this->read_byte
= ams_delta_read_byte
;
182 this->write_byte
= ams_delta_write_byte
;
183 this->write_buf
= ams_delta_write_buf
;
184 this->read_buf
= ams_delta_read_buf
;
185 this->verify_buf
= ams_delta_verify_buf
;
186 this->hwcontrol
= ams_delta_hwcontrol
;
187 if (!omap_request_gpio(AMS_DELTA_GPIO_PIN_NAND_RB
)) {
188 this->dev_ready
= ams_delta_nand_ready
;
190 this->dev_ready
= NULL
;
191 printk(KERN_NOTICE
"Couldn't request gpio for Delta NAND ready.\n");
193 /* 25 us command delay time */
194 this->chip_delay
= 30;
195 this->eccmode
= NAND_ECC_SOFT
;
197 /* Set chip enabled, but */
198 ams_delta_latch2_write(NAND_MASK
, AMS_DELTA_LATCH2_NAND_NRE
|
199 AMS_DELTA_LATCH2_NAND_NWE
|
200 AMS_DELTA_LATCH2_NAND_NCE
|
201 AMS_DELTA_LATCH2_NAND_NWP
);
203 /* Scan to find existance of the device */
204 if (nand_scan(ams_delta_mtd
, 1)) {
209 /* Register the partitions */
210 add_mtd_partitions(ams_delta_mtd
, partition_info
,
211 ARRAY_SIZE(partition_info
));
216 kfree(ams_delta_mtd
);
221 module_init(ams_delta_init
);
226 static void __exit
ams_delta_cleanup(void)
228 /* Release resources, unregister device */
229 nand_release(ams_delta_mtd
);
231 /* Free the MTD device structure */
232 kfree(ams_delta_mtd
);
234 module_exit(ams_delta_cleanup
);
236 MODULE_LICENSE("GPL");
237 MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
238 MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");