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Merge tag 'drm-amdkfd-next-fixes-2015-06-10' of git://people.freedesktop.org/~gabbayo...
[deliverable/linux.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2 * Copyright © 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
20 *
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #include <linux/clk.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/platform_device.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/of_mtd.h>
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/nand.h>
42 #include <linux/mtd/partitions.h>
43
44 #include <linux/delay.h>
45 #include <linux/dmaengine.h>
46 #include <linux/gpio.h>
47 #include <linux/interrupt.h>
48 #include <linux/io.h>
49 #include <linux/platform_data/atmel.h>
50
51 static int use_dma = 1;
52 module_param(use_dma, int, 0);
53
54 static int on_flash_bbt = 0;
55 module_param(on_flash_bbt, int, 0);
56
57 /* Register access macros */
58 #define ecc_readl(add, reg) \
59 __raw_readl(add + ATMEL_ECC_##reg)
60 #define ecc_writel(add, reg, value) \
61 __raw_writel((value), add + ATMEL_ECC_##reg)
62
63 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
64 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
65
66 struct atmel_nand_caps {
67 bool pmecc_correct_erase_page;
68 };
69
70 /* oob layout for large page size
71 * bad block info is on bytes 0 and 1
72 * the bytes have to be consecutives to avoid
73 * several NAND_CMD_RNDOUT during read
74 */
75 static struct nand_ecclayout atmel_oobinfo_large = {
76 .eccbytes = 4,
77 .eccpos = {60, 61, 62, 63},
78 .oobfree = {
79 {2, 58}
80 },
81 };
82
83 /* oob layout for small page size
84 * bad block info is on bytes 4 and 5
85 * the bytes have to be consecutives to avoid
86 * several NAND_CMD_RNDOUT during read
87 */
88 static struct nand_ecclayout atmel_oobinfo_small = {
89 .eccbytes = 4,
90 .eccpos = {0, 1, 2, 3},
91 .oobfree = {
92 {6, 10}
93 },
94 };
95
96 struct atmel_nfc {
97 void __iomem *base_cmd_regs;
98 void __iomem *hsmc_regs;
99 void *sram_bank0;
100 dma_addr_t sram_bank0_phys;
101 bool use_nfc_sram;
102 bool write_by_sram;
103
104 struct clk *clk;
105
106 bool is_initialized;
107 struct completion comp_ready;
108 struct completion comp_cmd_done;
109 struct completion comp_xfer_done;
110
111 /* Point to the sram bank which include readed data via NFC */
112 void *data_in_sram;
113 bool will_write_sram;
114 };
115 static struct atmel_nfc nand_nfc;
116
117 struct atmel_nand_host {
118 struct nand_chip nand_chip;
119 struct mtd_info mtd;
120 void __iomem *io_base;
121 dma_addr_t io_phys;
122 struct atmel_nand_data board;
123 struct device *dev;
124 void __iomem *ecc;
125
126 struct completion comp;
127 struct dma_chan *dma_chan;
128
129 struct atmel_nfc *nfc;
130
131 struct atmel_nand_caps *caps;
132 bool has_pmecc;
133 u8 pmecc_corr_cap;
134 u16 pmecc_sector_size;
135 bool has_no_lookup_table;
136 u32 pmecc_lookup_table_offset;
137 u32 pmecc_lookup_table_offset_512;
138 u32 pmecc_lookup_table_offset_1024;
139
140 int pmecc_degree; /* Degree of remainders */
141 int pmecc_cw_len; /* Length of codeword */
142
143 void __iomem *pmerrloc_base;
144 void __iomem *pmecc_rom_base;
145
146 /* lookup table for alpha_to and index_of */
147 void __iomem *pmecc_alpha_to;
148 void __iomem *pmecc_index_of;
149
150 /* data for pmecc computation */
151 int16_t *pmecc_partial_syn;
152 int16_t *pmecc_si;
153 int16_t *pmecc_smu; /* Sigma table */
154 int16_t *pmecc_lmu; /* polynomal order */
155 int *pmecc_mu;
156 int *pmecc_dmu;
157 int *pmecc_delta;
158 };
159
160 static struct nand_ecclayout atmel_pmecc_oobinfo;
161
162 /*
163 * Enable NAND.
164 */
165 static void atmel_nand_enable(struct atmel_nand_host *host)
166 {
167 if (gpio_is_valid(host->board.enable_pin))
168 gpio_set_value(host->board.enable_pin, 0);
169 }
170
171 /*
172 * Disable NAND.
173 */
174 static void atmel_nand_disable(struct atmel_nand_host *host)
175 {
176 if (gpio_is_valid(host->board.enable_pin))
177 gpio_set_value(host->board.enable_pin, 1);
178 }
179
180 /*
181 * Hardware specific access to control-lines
182 */
183 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
184 {
185 struct nand_chip *nand_chip = mtd->priv;
186 struct atmel_nand_host *host = nand_chip->priv;
187
188 if (ctrl & NAND_CTRL_CHANGE) {
189 if (ctrl & NAND_NCE)
190 atmel_nand_enable(host);
191 else
192 atmel_nand_disable(host);
193 }
194 if (cmd == NAND_CMD_NONE)
195 return;
196
197 if (ctrl & NAND_CLE)
198 writeb(cmd, host->io_base + (1 << host->board.cle));
199 else
200 writeb(cmd, host->io_base + (1 << host->board.ale));
201 }
202
203 /*
204 * Read the Device Ready pin.
205 */
206 static int atmel_nand_device_ready(struct mtd_info *mtd)
207 {
208 struct nand_chip *nand_chip = mtd->priv;
209 struct atmel_nand_host *host = nand_chip->priv;
210
211 return gpio_get_value(host->board.rdy_pin) ^
212 !!host->board.rdy_pin_active_low;
213 }
214
215 /* Set up for hardware ready pin and enable pin. */
216 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
217 {
218 struct nand_chip *chip = mtd->priv;
219 struct atmel_nand_host *host = chip->priv;
220 int res = 0;
221
222 if (gpio_is_valid(host->board.rdy_pin)) {
223 res = devm_gpio_request(host->dev,
224 host->board.rdy_pin, "nand_rdy");
225 if (res < 0) {
226 dev_err(host->dev,
227 "can't request rdy gpio %d\n",
228 host->board.rdy_pin);
229 return res;
230 }
231
232 res = gpio_direction_input(host->board.rdy_pin);
233 if (res < 0) {
234 dev_err(host->dev,
235 "can't request input direction rdy gpio %d\n",
236 host->board.rdy_pin);
237 return res;
238 }
239
240 chip->dev_ready = atmel_nand_device_ready;
241 }
242
243 if (gpio_is_valid(host->board.enable_pin)) {
244 res = devm_gpio_request(host->dev,
245 host->board.enable_pin, "nand_enable");
246 if (res < 0) {
247 dev_err(host->dev,
248 "can't request enable gpio %d\n",
249 host->board.enable_pin);
250 return res;
251 }
252
253 res = gpio_direction_output(host->board.enable_pin, 1);
254 if (res < 0) {
255 dev_err(host->dev,
256 "can't request output direction enable gpio %d\n",
257 host->board.enable_pin);
258 return res;
259 }
260 }
261
262 return res;
263 }
264
265 /*
266 * Minimal-overhead PIO for data access.
267 */
268 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
269 {
270 struct nand_chip *nand_chip = mtd->priv;
271 struct atmel_nand_host *host = nand_chip->priv;
272
273 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
274 memcpy(buf, host->nfc->data_in_sram, len);
275 host->nfc->data_in_sram += len;
276 } else {
277 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
278 }
279 }
280
281 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
282 {
283 struct nand_chip *nand_chip = mtd->priv;
284 struct atmel_nand_host *host = nand_chip->priv;
285
286 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
287 memcpy(buf, host->nfc->data_in_sram, len);
288 host->nfc->data_in_sram += len;
289 } else {
290 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
291 }
292 }
293
294 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
295 {
296 struct nand_chip *nand_chip = mtd->priv;
297
298 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
299 }
300
301 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
302 {
303 struct nand_chip *nand_chip = mtd->priv;
304
305 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
306 }
307
308 static void dma_complete_func(void *completion)
309 {
310 complete(completion);
311 }
312
313 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
314 {
315 /* NFC only has two banks. Must be 0 or 1 */
316 if (bank > 1)
317 return -EINVAL;
318
319 if (bank) {
320 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
321 if (host->mtd.writesize > 2048)
322 return -EINVAL;
323 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
324 } else {
325 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
326 }
327
328 return 0;
329 }
330
331 static uint nfc_get_sram_off(struct atmel_nand_host *host)
332 {
333 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
334 return NFC_SRAM_BANK1_OFFSET;
335 else
336 return 0;
337 }
338
339 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
340 {
341 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
342 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
343 else
344 return host->nfc->sram_bank0_phys;
345 }
346
347 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
348 int is_read)
349 {
350 struct dma_device *dma_dev;
351 enum dma_ctrl_flags flags;
352 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
353 struct dma_async_tx_descriptor *tx = NULL;
354 dma_cookie_t cookie;
355 struct nand_chip *chip = mtd->priv;
356 struct atmel_nand_host *host = chip->priv;
357 void *p = buf;
358 int err = -EIO;
359 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
360 struct atmel_nfc *nfc = host->nfc;
361
362 if (buf >= high_memory)
363 goto err_buf;
364
365 dma_dev = host->dma_chan->device;
366
367 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
368
369 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
370 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
371 dev_err(host->dev, "Failed to dma_map_single\n");
372 goto err_buf;
373 }
374
375 if (is_read) {
376 if (nfc && nfc->data_in_sram)
377 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
378 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
379 else
380 dma_src_addr = host->io_phys;
381
382 dma_dst_addr = phys_addr;
383 } else {
384 dma_src_addr = phys_addr;
385
386 if (nfc && nfc->write_by_sram)
387 dma_dst_addr = nfc_sram_phys(host);
388 else
389 dma_dst_addr = host->io_phys;
390 }
391
392 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
393 dma_src_addr, len, flags);
394 if (!tx) {
395 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
396 goto err_dma;
397 }
398
399 init_completion(&host->comp);
400 tx->callback = dma_complete_func;
401 tx->callback_param = &host->comp;
402
403 cookie = tx->tx_submit(tx);
404 if (dma_submit_error(cookie)) {
405 dev_err(host->dev, "Failed to do DMA tx_submit\n");
406 goto err_dma;
407 }
408
409 dma_async_issue_pending(host->dma_chan);
410 wait_for_completion(&host->comp);
411
412 if (is_read && nfc && nfc->data_in_sram)
413 /* After read data from SRAM, need to increase the position */
414 nfc->data_in_sram += len;
415
416 err = 0;
417
418 err_dma:
419 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
420 err_buf:
421 if (err != 0)
422 dev_dbg(host->dev, "Fall back to CPU I/O\n");
423 return err;
424 }
425
426 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
427 {
428 struct nand_chip *chip = mtd->priv;
429 struct atmel_nand_host *host = chip->priv;
430
431 if (use_dma && len > mtd->oobsize)
432 /* only use DMA for bigger than oob size: better performances */
433 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
434 return;
435
436 if (host->board.bus_width_16)
437 atmel_read_buf16(mtd, buf, len);
438 else
439 atmel_read_buf8(mtd, buf, len);
440 }
441
442 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
443 {
444 struct nand_chip *chip = mtd->priv;
445 struct atmel_nand_host *host = chip->priv;
446
447 if (use_dma && len > mtd->oobsize)
448 /* only use DMA for bigger than oob size: better performances */
449 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
450 return;
451
452 if (host->board.bus_width_16)
453 atmel_write_buf16(mtd, buf, len);
454 else
455 atmel_write_buf8(mtd, buf, len);
456 }
457
458 /*
459 * Return number of ecc bytes per sector according to sector size and
460 * correction capability
461 *
462 * Following table shows what at91 PMECC supported:
463 * Correction Capability Sector_512_bytes Sector_1024_bytes
464 * ===================== ================ =================
465 * 2-bits 4-bytes 4-bytes
466 * 4-bits 7-bytes 7-bytes
467 * 8-bits 13-bytes 14-bytes
468 * 12-bits 20-bytes 21-bytes
469 * 24-bits 39-bytes 42-bytes
470 */
471 static int pmecc_get_ecc_bytes(int cap, int sector_size)
472 {
473 int m = 12 + sector_size / 512;
474 return (m * cap + 7) / 8;
475 }
476
477 static void pmecc_config_ecc_layout(struct nand_ecclayout *layout,
478 int oobsize, int ecc_len)
479 {
480 int i;
481
482 layout->eccbytes = ecc_len;
483
484 /* ECC will occupy the last ecc_len bytes continuously */
485 for (i = 0; i < ecc_len; i++)
486 layout->eccpos[i] = oobsize - ecc_len + i;
487
488 layout->oobfree[0].offset = PMECC_OOB_RESERVED_BYTES;
489 layout->oobfree[0].length =
490 oobsize - ecc_len - layout->oobfree[0].offset;
491 }
492
493 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
494 {
495 int table_size;
496
497 table_size = host->pmecc_sector_size == 512 ?
498 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
499
500 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
501 table_size * sizeof(int16_t);
502 }
503
504 static int pmecc_data_alloc(struct atmel_nand_host *host)
505 {
506 const int cap = host->pmecc_corr_cap;
507 int size;
508
509 size = (2 * cap + 1) * sizeof(int16_t);
510 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
511 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
512 host->pmecc_lmu = devm_kzalloc(host->dev,
513 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
514 host->pmecc_smu = devm_kzalloc(host->dev,
515 (cap + 2) * size, GFP_KERNEL);
516
517 size = (cap + 1) * sizeof(int);
518 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
519 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
520 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
521
522 if (!host->pmecc_partial_syn ||
523 !host->pmecc_si ||
524 !host->pmecc_lmu ||
525 !host->pmecc_smu ||
526 !host->pmecc_mu ||
527 !host->pmecc_dmu ||
528 !host->pmecc_delta)
529 return -ENOMEM;
530
531 return 0;
532 }
533
534 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
535 {
536 struct nand_chip *nand_chip = mtd->priv;
537 struct atmel_nand_host *host = nand_chip->priv;
538 int i;
539 uint32_t value;
540
541 /* Fill odd syndromes */
542 for (i = 0; i < host->pmecc_corr_cap; i++) {
543 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
544 if (i & 1)
545 value >>= 16;
546 value &= 0xffff;
547 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
548 }
549 }
550
551 static void pmecc_substitute(struct mtd_info *mtd)
552 {
553 struct nand_chip *nand_chip = mtd->priv;
554 struct atmel_nand_host *host = nand_chip->priv;
555 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
556 int16_t __iomem *index_of = host->pmecc_index_of;
557 int16_t *partial_syn = host->pmecc_partial_syn;
558 const int cap = host->pmecc_corr_cap;
559 int16_t *si;
560 int i, j;
561
562 /* si[] is a table that holds the current syndrome value,
563 * an element of that table belongs to the field
564 */
565 si = host->pmecc_si;
566
567 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
568
569 /* Computation 2t syndromes based on S(x) */
570 /* Odd syndromes */
571 for (i = 1; i < 2 * cap; i += 2) {
572 for (j = 0; j < host->pmecc_degree; j++) {
573 if (partial_syn[i] & ((unsigned short)0x1 << j))
574 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
575 }
576 }
577 /* Even syndrome = (Odd syndrome) ** 2 */
578 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
579 if (si[j] == 0) {
580 si[i] = 0;
581 } else {
582 int16_t tmp;
583
584 tmp = readw_relaxed(index_of + si[j]);
585 tmp = (tmp * 2) % host->pmecc_cw_len;
586 si[i] = readw_relaxed(alpha_to + tmp);
587 }
588 }
589
590 return;
591 }
592
593 static void pmecc_get_sigma(struct mtd_info *mtd)
594 {
595 struct nand_chip *nand_chip = mtd->priv;
596 struct atmel_nand_host *host = nand_chip->priv;
597
598 int16_t *lmu = host->pmecc_lmu;
599 int16_t *si = host->pmecc_si;
600 int *mu = host->pmecc_mu;
601 int *dmu = host->pmecc_dmu; /* Discrepancy */
602 int *delta = host->pmecc_delta; /* Delta order */
603 int cw_len = host->pmecc_cw_len;
604 const int16_t cap = host->pmecc_corr_cap;
605 const int num = 2 * cap + 1;
606 int16_t __iomem *index_of = host->pmecc_index_of;
607 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
608 int i, j, k;
609 uint32_t dmu_0_count, tmp;
610 int16_t *smu = host->pmecc_smu;
611
612 /* index of largest delta */
613 int ro;
614 int largest;
615 int diff;
616
617 dmu_0_count = 0;
618
619 /* First Row */
620
621 /* Mu */
622 mu[0] = -1;
623
624 memset(smu, 0, sizeof(int16_t) * num);
625 smu[0] = 1;
626
627 /* discrepancy set to 1 */
628 dmu[0] = 1;
629 /* polynom order set to 0 */
630 lmu[0] = 0;
631 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
632
633 /* Second Row */
634
635 /* Mu */
636 mu[1] = 0;
637 /* Sigma(x) set to 1 */
638 memset(&smu[num], 0, sizeof(int16_t) * num);
639 smu[num] = 1;
640
641 /* discrepancy set to S1 */
642 dmu[1] = si[1];
643
644 /* polynom order set to 0 */
645 lmu[1] = 0;
646
647 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
648
649 /* Init the Sigma(x) last row */
650 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
651
652 for (i = 1; i <= cap; i++) {
653 mu[i + 1] = i << 1;
654 /* Begin Computing Sigma (Mu+1) and L(mu) */
655 /* check if discrepancy is set to 0 */
656 if (dmu[i] == 0) {
657 dmu_0_count++;
658
659 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
660 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
661 tmp += 2;
662 else
663 tmp += 1;
664
665 if (dmu_0_count == tmp) {
666 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
667 smu[(cap + 1) * num + j] =
668 smu[i * num + j];
669
670 lmu[cap + 1] = lmu[i];
671 return;
672 }
673
674 /* copy polynom */
675 for (j = 0; j <= lmu[i] >> 1; j++)
676 smu[(i + 1) * num + j] = smu[i * num + j];
677
678 /* copy previous polynom order to the next */
679 lmu[i + 1] = lmu[i];
680 } else {
681 ro = 0;
682 largest = -1;
683 /* find largest delta with dmu != 0 */
684 for (j = 0; j < i; j++) {
685 if ((dmu[j]) && (delta[j] > largest)) {
686 largest = delta[j];
687 ro = j;
688 }
689 }
690
691 /* compute difference */
692 diff = (mu[i] - mu[ro]);
693
694 /* Compute degree of the new smu polynomial */
695 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
696 lmu[i + 1] = lmu[i];
697 else
698 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
699
700 /* Init smu[i+1] with 0 */
701 for (k = 0; k < num; k++)
702 smu[(i + 1) * num + k] = 0;
703
704 /* Compute smu[i+1] */
705 for (k = 0; k <= lmu[ro] >> 1; k++) {
706 int16_t a, b, c;
707
708 if (!(smu[ro * num + k] && dmu[i]))
709 continue;
710 a = readw_relaxed(index_of + dmu[i]);
711 b = readw_relaxed(index_of + dmu[ro]);
712 c = readw_relaxed(index_of + smu[ro * num + k]);
713 tmp = a + (cw_len - b) + c;
714 a = readw_relaxed(alpha_to + tmp % cw_len);
715 smu[(i + 1) * num + (k + diff)] = a;
716 }
717
718 for (k = 0; k <= lmu[i] >> 1; k++)
719 smu[(i + 1) * num + k] ^= smu[i * num + k];
720 }
721
722 /* End Computing Sigma (Mu+1) and L(mu) */
723 /* In either case compute delta */
724 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
725
726 /* Do not compute discrepancy for the last iteration */
727 if (i >= cap)
728 continue;
729
730 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
731 tmp = 2 * (i - 1);
732 if (k == 0) {
733 dmu[i + 1] = si[tmp + 3];
734 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
735 int16_t a, b, c;
736 a = readw_relaxed(index_of +
737 smu[(i + 1) * num + k]);
738 b = si[2 * (i - 1) + 3 - k];
739 c = readw_relaxed(index_of + b);
740 tmp = a + c;
741 tmp %= cw_len;
742 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
743 dmu[i + 1];
744 }
745 }
746 }
747
748 return;
749 }
750
751 static int pmecc_err_location(struct mtd_info *mtd)
752 {
753 struct nand_chip *nand_chip = mtd->priv;
754 struct atmel_nand_host *host = nand_chip->priv;
755 unsigned long end_time;
756 const int cap = host->pmecc_corr_cap;
757 const int num = 2 * cap + 1;
758 int sector_size = host->pmecc_sector_size;
759 int err_nbr = 0; /* number of error */
760 int roots_nbr; /* number of roots */
761 int i;
762 uint32_t val;
763 int16_t *smu = host->pmecc_smu;
764
765 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
766
767 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
768 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
769 smu[(cap + 1) * num + i]);
770 err_nbr++;
771 }
772
773 val = (err_nbr - 1) << 16;
774 if (sector_size == 1024)
775 val |= 1;
776
777 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
778 pmerrloc_writel(host->pmerrloc_base, ELEN,
779 sector_size * 8 + host->pmecc_degree * cap);
780
781 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
782 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
783 & PMERRLOC_CALC_DONE)) {
784 if (unlikely(time_after(jiffies, end_time))) {
785 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
786 return -1;
787 }
788 cpu_relax();
789 }
790
791 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
792 & PMERRLOC_ERR_NUM_MASK) >> 8;
793 /* Number of roots == degree of smu hence <= cap */
794 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
795 return err_nbr - 1;
796
797 /* Number of roots does not match the degree of smu
798 * unable to correct error */
799 return -1;
800 }
801
802 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
803 int sector_num, int extra_bytes, int err_nbr)
804 {
805 struct nand_chip *nand_chip = mtd->priv;
806 struct atmel_nand_host *host = nand_chip->priv;
807 int i = 0;
808 int byte_pos, bit_pos, sector_size, pos;
809 uint32_t tmp;
810 uint8_t err_byte;
811
812 sector_size = host->pmecc_sector_size;
813
814 while (err_nbr) {
815 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_base, i) - 1;
816 byte_pos = tmp / 8;
817 bit_pos = tmp % 8;
818
819 if (byte_pos >= (sector_size + extra_bytes))
820 BUG(); /* should never happen */
821
822 if (byte_pos < sector_size) {
823 err_byte = *(buf + byte_pos);
824 *(buf + byte_pos) ^= (1 << bit_pos);
825
826 pos = sector_num * host->pmecc_sector_size + byte_pos;
827 dev_info(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
828 pos, bit_pos, err_byte, *(buf + byte_pos));
829 } else {
830 /* Bit flip in OOB area */
831 tmp = sector_num * nand_chip->ecc.bytes
832 + (byte_pos - sector_size);
833 err_byte = ecc[tmp];
834 ecc[tmp] ^= (1 << bit_pos);
835
836 pos = tmp + nand_chip->ecc.layout->eccpos[0];
837 dev_info(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
838 pos, bit_pos, err_byte, ecc[tmp]);
839 }
840
841 i++;
842 err_nbr--;
843 }
844
845 return;
846 }
847
848 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
849 u8 *ecc)
850 {
851 struct nand_chip *nand_chip = mtd->priv;
852 struct atmel_nand_host *host = nand_chip->priv;
853 int i, err_nbr;
854 uint8_t *buf_pos;
855 int max_bitflips = 0;
856
857 /* If can correct bitfilps from erased page, do the normal check */
858 if (host->caps->pmecc_correct_erase_page)
859 goto normal_check;
860
861 for (i = 0; i < nand_chip->ecc.total; i++)
862 if (ecc[i] != 0xff)
863 goto normal_check;
864 /* Erased page, return OK */
865 return 0;
866
867 normal_check:
868 for (i = 0; i < nand_chip->ecc.steps; i++) {
869 err_nbr = 0;
870 if (pmecc_stat & 0x1) {
871 buf_pos = buf + i * host->pmecc_sector_size;
872
873 pmecc_gen_syndrome(mtd, i);
874 pmecc_substitute(mtd);
875 pmecc_get_sigma(mtd);
876
877 err_nbr = pmecc_err_location(mtd);
878 if (err_nbr == -1) {
879 dev_err(host->dev, "PMECC: Too many errors\n");
880 mtd->ecc_stats.failed++;
881 return -EIO;
882 } else {
883 pmecc_correct_data(mtd, buf_pos, ecc, i,
884 nand_chip->ecc.bytes, err_nbr);
885 mtd->ecc_stats.corrected += err_nbr;
886 max_bitflips = max_t(int, max_bitflips, err_nbr);
887 }
888 }
889 pmecc_stat >>= 1;
890 }
891
892 return max_bitflips;
893 }
894
895 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
896 {
897 u32 val;
898
899 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
900 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
901 return;
902 }
903
904 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
905 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
906 val = pmecc_readl_relaxed(host->ecc, CFG);
907
908 if (ecc_op == NAND_ECC_READ)
909 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
910 | PMECC_CFG_AUTO_ENABLE);
911 else
912 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
913 & ~PMECC_CFG_AUTO_ENABLE);
914
915 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
916 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
917 }
918
919 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
920 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
921 {
922 struct atmel_nand_host *host = chip->priv;
923 int eccsize = chip->ecc.size * chip->ecc.steps;
924 uint8_t *oob = chip->oob_poi;
925 uint32_t *eccpos = chip->ecc.layout->eccpos;
926 uint32_t stat;
927 unsigned long end_time;
928 int bitflips = 0;
929
930 if (!host->nfc || !host->nfc->use_nfc_sram)
931 pmecc_enable(host, NAND_ECC_READ);
932
933 chip->read_buf(mtd, buf, eccsize);
934 chip->read_buf(mtd, oob, mtd->oobsize);
935
936 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
937 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
938 if (unlikely(time_after(jiffies, end_time))) {
939 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
940 return -EIO;
941 }
942 cpu_relax();
943 }
944
945 stat = pmecc_readl_relaxed(host->ecc, ISR);
946 if (stat != 0) {
947 bitflips = pmecc_correction(mtd, stat, buf, &oob[eccpos[0]]);
948 if (bitflips < 0)
949 /* uncorrectable errors */
950 return 0;
951 }
952
953 return bitflips;
954 }
955
956 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
957 struct nand_chip *chip, const uint8_t *buf, int oob_required)
958 {
959 struct atmel_nand_host *host = chip->priv;
960 uint32_t *eccpos = chip->ecc.layout->eccpos;
961 int i, j;
962 unsigned long end_time;
963
964 if (!host->nfc || !host->nfc->write_by_sram) {
965 pmecc_enable(host, NAND_ECC_WRITE);
966 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
967 }
968
969 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
970 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
971 if (unlikely(time_after(jiffies, end_time))) {
972 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
973 return -EIO;
974 }
975 cpu_relax();
976 }
977
978 for (i = 0; i < chip->ecc.steps; i++) {
979 for (j = 0; j < chip->ecc.bytes; j++) {
980 int pos;
981
982 pos = i * chip->ecc.bytes + j;
983 chip->oob_poi[eccpos[pos]] =
984 pmecc_readb_ecc_relaxed(host->ecc, i, j);
985 }
986 }
987 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
988
989 return 0;
990 }
991
992 static void atmel_pmecc_core_init(struct mtd_info *mtd)
993 {
994 struct nand_chip *nand_chip = mtd->priv;
995 struct atmel_nand_host *host = nand_chip->priv;
996 uint32_t val = 0;
997 struct nand_ecclayout *ecc_layout;
998
999 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1000 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1001
1002 switch (host->pmecc_corr_cap) {
1003 case 2:
1004 val = PMECC_CFG_BCH_ERR2;
1005 break;
1006 case 4:
1007 val = PMECC_CFG_BCH_ERR4;
1008 break;
1009 case 8:
1010 val = PMECC_CFG_BCH_ERR8;
1011 break;
1012 case 12:
1013 val = PMECC_CFG_BCH_ERR12;
1014 break;
1015 case 24:
1016 val = PMECC_CFG_BCH_ERR24;
1017 break;
1018 }
1019
1020 if (host->pmecc_sector_size == 512)
1021 val |= PMECC_CFG_SECTOR512;
1022 else if (host->pmecc_sector_size == 1024)
1023 val |= PMECC_CFG_SECTOR1024;
1024
1025 switch (nand_chip->ecc.steps) {
1026 case 1:
1027 val |= PMECC_CFG_PAGE_1SECTOR;
1028 break;
1029 case 2:
1030 val |= PMECC_CFG_PAGE_2SECTORS;
1031 break;
1032 case 4:
1033 val |= PMECC_CFG_PAGE_4SECTORS;
1034 break;
1035 case 8:
1036 val |= PMECC_CFG_PAGE_8SECTORS;
1037 break;
1038 }
1039
1040 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1041 | PMECC_CFG_AUTO_DISABLE);
1042 pmecc_writel(host->ecc, CFG, val);
1043
1044 ecc_layout = nand_chip->ecc.layout;
1045 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1046 pmecc_writel(host->ecc, SADDR, ecc_layout->eccpos[0]);
1047 pmecc_writel(host->ecc, EADDR,
1048 ecc_layout->eccpos[ecc_layout->eccbytes - 1]);
1049 /* See datasheet about PMECC Clock Control Register */
1050 pmecc_writel(host->ecc, CLK, 2);
1051 pmecc_writel(host->ecc, IDR, 0xff);
1052 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1053 }
1054
1055 /*
1056 * Get minimum ecc requirements from NAND.
1057 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1058 * will set them according to minimum ecc requirement. Otherwise, use the
1059 * value in DTS file.
1060 * return 0 if success. otherwise return error code.
1061 */
1062 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1063 int *cap, int *sector_size)
1064 {
1065 /* Get minimum ECC requirements */
1066 if (host->nand_chip.ecc_strength_ds) {
1067 *cap = host->nand_chip.ecc_strength_ds;
1068 *sector_size = host->nand_chip.ecc_step_ds;
1069 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1070 *cap, *sector_size);
1071 } else {
1072 *cap = 2;
1073 *sector_size = 512;
1074 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1075 }
1076
1077 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1078 if (host->pmecc_corr_cap == 0) {
1079 /* use the most fitable ecc bits (the near bigger one ) */
1080 if (*cap <= 2)
1081 host->pmecc_corr_cap = 2;
1082 else if (*cap <= 4)
1083 host->pmecc_corr_cap = 4;
1084 else if (*cap <= 8)
1085 host->pmecc_corr_cap = 8;
1086 else if (*cap <= 12)
1087 host->pmecc_corr_cap = 12;
1088 else if (*cap <= 24)
1089 host->pmecc_corr_cap = 24;
1090 else
1091 return -EINVAL;
1092 }
1093 if (host->pmecc_sector_size == 0) {
1094 /* use the most fitable sector size (the near smaller one ) */
1095 if (*sector_size >= 1024)
1096 host->pmecc_sector_size = 1024;
1097 else if (*sector_size >= 512)
1098 host->pmecc_sector_size = 512;
1099 else
1100 return -EINVAL;
1101 }
1102 return 0;
1103 }
1104
1105 static inline int deg(unsigned int poly)
1106 {
1107 /* polynomial degree is the most-significant bit index */
1108 return fls(poly) - 1;
1109 }
1110
1111 static int build_gf_tables(int mm, unsigned int poly,
1112 int16_t *index_of, int16_t *alpha_to)
1113 {
1114 unsigned int i, x = 1;
1115 const unsigned int k = 1 << deg(poly);
1116 unsigned int nn = (1 << mm) - 1;
1117
1118 /* primitive polynomial must be of degree m */
1119 if (k != (1u << mm))
1120 return -EINVAL;
1121
1122 for (i = 0; i < nn; i++) {
1123 alpha_to[i] = x;
1124 index_of[x] = i;
1125 if (i && (x == 1))
1126 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1127 return -EINVAL;
1128 x <<= 1;
1129 if (x & k)
1130 x ^= poly;
1131 }
1132 alpha_to[nn] = 1;
1133 index_of[0] = 0;
1134
1135 return 0;
1136 }
1137
1138 static uint16_t *create_lookup_table(struct device *dev, int sector_size)
1139 {
1140 int degree = (sector_size == 512) ?
1141 PMECC_GF_DIMENSION_13 :
1142 PMECC_GF_DIMENSION_14;
1143 unsigned int poly = (sector_size == 512) ?
1144 PMECC_GF_13_PRIMITIVE_POLY :
1145 PMECC_GF_14_PRIMITIVE_POLY;
1146 int table_size = (sector_size == 512) ?
1147 PMECC_LOOKUP_TABLE_SIZE_512 :
1148 PMECC_LOOKUP_TABLE_SIZE_1024;
1149
1150 int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
1151 GFP_KERNEL);
1152 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
1153 return NULL;
1154
1155 return addr;
1156 }
1157
1158 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1159 struct atmel_nand_host *host)
1160 {
1161 struct mtd_info *mtd = &host->mtd;
1162 struct nand_chip *nand_chip = &host->nand_chip;
1163 struct resource *regs, *regs_pmerr, *regs_rom;
1164 uint16_t *galois_table;
1165 int cap, sector_size, err_no;
1166
1167 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1168 if (err_no) {
1169 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1170 return err_no;
1171 }
1172
1173 if (cap > host->pmecc_corr_cap ||
1174 sector_size != host->pmecc_sector_size)
1175 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1176
1177 cap = host->pmecc_corr_cap;
1178 sector_size = host->pmecc_sector_size;
1179 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1180 host->pmecc_lookup_table_offset_512 :
1181 host->pmecc_lookup_table_offset_1024;
1182
1183 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1184 cap, sector_size);
1185
1186 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1187 if (!regs) {
1188 dev_warn(host->dev,
1189 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1190 nand_chip->ecc.mode = NAND_ECC_SOFT;
1191 return 0;
1192 }
1193
1194 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1195 if (IS_ERR(host->ecc)) {
1196 err_no = PTR_ERR(host->ecc);
1197 goto err;
1198 }
1199
1200 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1201 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1202 if (IS_ERR(host->pmerrloc_base)) {
1203 err_no = PTR_ERR(host->pmerrloc_base);
1204 goto err;
1205 }
1206
1207 if (!host->has_no_lookup_table) {
1208 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1209 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
1210 regs_rom);
1211 if (IS_ERR(host->pmecc_rom_base)) {
1212 dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1213 host->has_no_lookup_table = true;
1214 }
1215 }
1216
1217 if (host->has_no_lookup_table) {
1218 /* Build the look-up table in runtime */
1219 galois_table = create_lookup_table(host->dev, sector_size);
1220 if (!galois_table) {
1221 dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
1222 err_no = -EINVAL;
1223 goto err;
1224 }
1225
1226 host->pmecc_rom_base = (void __iomem *)galois_table;
1227 host->pmecc_lookup_table_offset = 0;
1228 }
1229
1230 nand_chip->ecc.size = sector_size;
1231
1232 /* set ECC page size and oob layout */
1233 switch (mtd->writesize) {
1234 case 512:
1235 case 1024:
1236 case 2048:
1237 case 4096:
1238 case 8192:
1239 if (sector_size > mtd->writesize) {
1240 dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1241 err_no = -EINVAL;
1242 goto err;
1243 }
1244
1245 host->pmecc_degree = (sector_size == 512) ?
1246 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1247 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1248 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1249 host->pmecc_index_of = host->pmecc_rom_base +
1250 host->pmecc_lookup_table_offset;
1251
1252 nand_chip->ecc.strength = cap;
1253 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1254 nand_chip->ecc.steps = mtd->writesize / sector_size;
1255 nand_chip->ecc.total = nand_chip->ecc.bytes *
1256 nand_chip->ecc.steps;
1257 if (nand_chip->ecc.total >
1258 mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1259 dev_err(host->dev, "No room for ECC bytes\n");
1260 err_no = -EINVAL;
1261 goto err;
1262 }
1263 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo,
1264 mtd->oobsize,
1265 nand_chip->ecc.total);
1266
1267 nand_chip->ecc.layout = &atmel_pmecc_oobinfo;
1268 break;
1269 default:
1270 dev_warn(host->dev,
1271 "Unsupported page size for PMECC, use Software ECC\n");
1272 /* page size not handled by HW ECC */
1273 /* switching back to soft ECC */
1274 nand_chip->ecc.mode = NAND_ECC_SOFT;
1275 return 0;
1276 }
1277
1278 /* Allocate data for PMECC computation */
1279 err_no = pmecc_data_alloc(host);
1280 if (err_no) {
1281 dev_err(host->dev,
1282 "Cannot allocate memory for PMECC computation!\n");
1283 goto err;
1284 }
1285
1286 nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1287 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1288 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1289
1290 atmel_pmecc_core_init(mtd);
1291
1292 return 0;
1293
1294 err:
1295 return err_no;
1296 }
1297
1298 /*
1299 * Calculate HW ECC
1300 *
1301 * function called after a write
1302 *
1303 * mtd: MTD block structure
1304 * dat: raw data (unused)
1305 * ecc_code: buffer for ECC
1306 */
1307 static int atmel_nand_calculate(struct mtd_info *mtd,
1308 const u_char *dat, unsigned char *ecc_code)
1309 {
1310 struct nand_chip *nand_chip = mtd->priv;
1311 struct atmel_nand_host *host = nand_chip->priv;
1312 unsigned int ecc_value;
1313
1314 /* get the first 2 ECC bytes */
1315 ecc_value = ecc_readl(host->ecc, PR);
1316
1317 ecc_code[0] = ecc_value & 0xFF;
1318 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1319
1320 /* get the last 2 ECC bytes */
1321 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1322
1323 ecc_code[2] = ecc_value & 0xFF;
1324 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1325
1326 return 0;
1327 }
1328
1329 /*
1330 * HW ECC read page function
1331 *
1332 * mtd: mtd info structure
1333 * chip: nand chip info structure
1334 * buf: buffer to store read data
1335 * oob_required: caller expects OOB data read to chip->oob_poi
1336 */
1337 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1338 uint8_t *buf, int oob_required, int page)
1339 {
1340 int eccsize = chip->ecc.size;
1341 int eccbytes = chip->ecc.bytes;
1342 uint32_t *eccpos = chip->ecc.layout->eccpos;
1343 uint8_t *p = buf;
1344 uint8_t *oob = chip->oob_poi;
1345 uint8_t *ecc_pos;
1346 int stat;
1347 unsigned int max_bitflips = 0;
1348
1349 /*
1350 * Errata: ALE is incorrectly wired up to the ECC controller
1351 * on the AP7000, so it will include the address cycles in the
1352 * ECC calculation.
1353 *
1354 * Workaround: Reset the parity registers before reading the
1355 * actual data.
1356 */
1357 struct atmel_nand_host *host = chip->priv;
1358 if (host->board.need_reset_workaround)
1359 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1360
1361 /* read the page */
1362 chip->read_buf(mtd, p, eccsize);
1363
1364 /* move to ECC position if needed */
1365 if (eccpos[0] != 0) {
1366 /* This only works on large pages
1367 * because the ECC controller waits for
1368 * NAND_CMD_RNDOUTSTART after the
1369 * NAND_CMD_RNDOUT.
1370 * anyway, for small pages, the eccpos[0] == 0
1371 */
1372 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1373 mtd->writesize + eccpos[0], -1);
1374 }
1375
1376 /* the ECC controller needs to read the ECC just after the data */
1377 ecc_pos = oob + eccpos[0];
1378 chip->read_buf(mtd, ecc_pos, eccbytes);
1379
1380 /* check if there's an error */
1381 stat = chip->ecc.correct(mtd, p, oob, NULL);
1382
1383 if (stat < 0) {
1384 mtd->ecc_stats.failed++;
1385 } else {
1386 mtd->ecc_stats.corrected += stat;
1387 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1388 }
1389
1390 /* get back to oob start (end of page) */
1391 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1392
1393 /* read the oob */
1394 chip->read_buf(mtd, oob, mtd->oobsize);
1395
1396 return max_bitflips;
1397 }
1398
1399 /*
1400 * HW ECC Correction
1401 *
1402 * function called after a read
1403 *
1404 * mtd: MTD block structure
1405 * dat: raw data read from the chip
1406 * read_ecc: ECC from the chip (unused)
1407 * isnull: unused
1408 *
1409 * Detect and correct a 1 bit error for a page
1410 */
1411 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1412 u_char *read_ecc, u_char *isnull)
1413 {
1414 struct nand_chip *nand_chip = mtd->priv;
1415 struct atmel_nand_host *host = nand_chip->priv;
1416 unsigned int ecc_status;
1417 unsigned int ecc_word, ecc_bit;
1418
1419 /* get the status from the Status Register */
1420 ecc_status = ecc_readl(host->ecc, SR);
1421
1422 /* if there's no error */
1423 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1424 return 0;
1425
1426 /* get error bit offset (4 bits) */
1427 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1428 /* get word address (12 bits) */
1429 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1430 ecc_word >>= 4;
1431
1432 /* if there are multiple errors */
1433 if (ecc_status & ATMEL_ECC_MULERR) {
1434 /* check if it is a freshly erased block
1435 * (filled with 0xff) */
1436 if ((ecc_bit == ATMEL_ECC_BITADDR)
1437 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1438 /* the block has just been erased, return OK */
1439 return 0;
1440 }
1441 /* it doesn't seems to be a freshly
1442 * erased block.
1443 * We can't correct so many errors */
1444 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1445 " Unable to correct.\n");
1446 return -EIO;
1447 }
1448
1449 /* if there's a single bit error : we can correct it */
1450 if (ecc_status & ATMEL_ECC_ECCERR) {
1451 /* there's nothing much to do here.
1452 * the bit error is on the ECC itself.
1453 */
1454 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1455 " Nothing to correct\n");
1456 return 0;
1457 }
1458
1459 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1460 " (word offset in the page :"
1461 " 0x%x bit offset : 0x%x)\n",
1462 ecc_word, ecc_bit);
1463 /* correct the error */
1464 if (nand_chip->options & NAND_BUSWIDTH_16) {
1465 /* 16 bits words */
1466 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1467 } else {
1468 /* 8 bits words */
1469 dat[ecc_word] ^= (1 << ecc_bit);
1470 }
1471 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1472 return 1;
1473 }
1474
1475 /*
1476 * Enable HW ECC : unused on most chips
1477 */
1478 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1479 {
1480 struct nand_chip *nand_chip = mtd->priv;
1481 struct atmel_nand_host *host = nand_chip->priv;
1482
1483 if (host->board.need_reset_workaround)
1484 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1485 }
1486
1487 static const struct of_device_id atmel_nand_dt_ids[];
1488
1489 static int atmel_of_init_port(struct atmel_nand_host *host,
1490 struct device_node *np)
1491 {
1492 u32 val;
1493 u32 offset[2];
1494 int ecc_mode;
1495 struct atmel_nand_data *board = &host->board;
1496 enum of_gpio_flags flags = 0;
1497
1498 host->caps = (struct atmel_nand_caps *)
1499 of_match_device(atmel_nand_dt_ids, host->dev)->data;
1500
1501 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1502 if (val >= 32) {
1503 dev_err(host->dev, "invalid addr-offset %u\n", val);
1504 return -EINVAL;
1505 }
1506 board->ale = val;
1507 }
1508
1509 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1510 if (val >= 32) {
1511 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1512 return -EINVAL;
1513 }
1514 board->cle = val;
1515 }
1516
1517 ecc_mode = of_get_nand_ecc_mode(np);
1518
1519 board->ecc_mode = ecc_mode < 0 ? NAND_ECC_SOFT : ecc_mode;
1520
1521 board->on_flash_bbt = of_get_nand_on_flash_bbt(np);
1522
1523 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1524
1525 if (of_get_nand_bus_width(np) == 16)
1526 board->bus_width_16 = 1;
1527
1528 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1529 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1530
1531 board->enable_pin = of_get_gpio(np, 1);
1532 board->det_pin = of_get_gpio(np, 2);
1533
1534 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1535
1536 /* load the nfc driver if there is */
1537 of_platform_populate(np, NULL, NULL, host->dev);
1538
1539 if (!(board->ecc_mode == NAND_ECC_HW) || !host->has_pmecc)
1540 return 0; /* Not using PMECC */
1541
1542 /* use PMECC, get correction capability, sector size and lookup
1543 * table offset.
1544 * If correction bits and sector size are not specified, then find
1545 * them from NAND ONFI parameters.
1546 */
1547 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1548 if ((val != 2) && (val != 4) && (val != 8) && (val != 12) &&
1549 (val != 24)) {
1550 dev_err(host->dev,
1551 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1552 val);
1553 return -EINVAL;
1554 }
1555 host->pmecc_corr_cap = (u8)val;
1556 }
1557
1558 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1559 if ((val != 512) && (val != 1024)) {
1560 dev_err(host->dev,
1561 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1562 val);
1563 return -EINVAL;
1564 }
1565 host->pmecc_sector_size = (u16)val;
1566 }
1567
1568 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1569 offset, 2) != 0) {
1570 dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1571 host->has_no_lookup_table = true;
1572 /* Will build a lookup table and initialize the offset later */
1573 return 0;
1574 }
1575 if (!offset[0] && !offset[1]) {
1576 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1577 return -EINVAL;
1578 }
1579 host->pmecc_lookup_table_offset_512 = offset[0];
1580 host->pmecc_lookup_table_offset_1024 = offset[1];
1581
1582 return 0;
1583 }
1584
1585 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1586 struct atmel_nand_host *host)
1587 {
1588 struct mtd_info *mtd = &host->mtd;
1589 struct nand_chip *nand_chip = &host->nand_chip;
1590 struct resource *regs;
1591
1592 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1593 if (!regs) {
1594 dev_err(host->dev,
1595 "Can't get I/O resource regs, use software ECC\n");
1596 nand_chip->ecc.mode = NAND_ECC_SOFT;
1597 return 0;
1598 }
1599
1600 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1601 if (IS_ERR(host->ecc))
1602 return PTR_ERR(host->ecc);
1603
1604 /* ECC is calculated for the whole page (1 step) */
1605 nand_chip->ecc.size = mtd->writesize;
1606
1607 /* set ECC page size and oob layout */
1608 switch (mtd->writesize) {
1609 case 512:
1610 nand_chip->ecc.layout = &atmel_oobinfo_small;
1611 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1612 break;
1613 case 1024:
1614 nand_chip->ecc.layout = &atmel_oobinfo_large;
1615 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1616 break;
1617 case 2048:
1618 nand_chip->ecc.layout = &atmel_oobinfo_large;
1619 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1620 break;
1621 case 4096:
1622 nand_chip->ecc.layout = &atmel_oobinfo_large;
1623 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1624 break;
1625 default:
1626 /* page size not handled by HW ECC */
1627 /* switching back to soft ECC */
1628 nand_chip->ecc.mode = NAND_ECC_SOFT;
1629 return 0;
1630 }
1631
1632 /* set up for HW ECC */
1633 nand_chip->ecc.calculate = atmel_nand_calculate;
1634 nand_chip->ecc.correct = atmel_nand_correct;
1635 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1636 nand_chip->ecc.read_page = atmel_nand_read_page;
1637 nand_chip->ecc.bytes = 4;
1638 nand_chip->ecc.strength = 1;
1639
1640 return 0;
1641 }
1642
1643 static inline u32 nfc_read_status(struct atmel_nand_host *host)
1644 {
1645 u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1646 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1647
1648 if (unlikely(nfc_status & err_flags)) {
1649 if (nfc_status & NFC_SR_DTOE)
1650 dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1651 else if (nfc_status & NFC_SR_UNDEF)
1652 dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1653 else if (nfc_status & NFC_SR_AWB)
1654 dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1655 else if (nfc_status & NFC_SR_ASE)
1656 dev_err(host->dev, "NFC: Access memory Size Error\n");
1657 }
1658
1659 return nfc_status;
1660 }
1661
1662 /* SMC interrupt service routine */
1663 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1664 {
1665 struct atmel_nand_host *host = dev_id;
1666 u32 status, mask, pending;
1667 irqreturn_t ret = IRQ_NONE;
1668
1669 status = nfc_read_status(host);
1670 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1671 pending = status & mask;
1672
1673 if (pending & NFC_SR_XFR_DONE) {
1674 complete(&host->nfc->comp_xfer_done);
1675 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1676 ret = IRQ_HANDLED;
1677 }
1678 if (pending & NFC_SR_RB_EDGE) {
1679 complete(&host->nfc->comp_ready);
1680 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_RB_EDGE);
1681 ret = IRQ_HANDLED;
1682 }
1683 if (pending & NFC_SR_CMD_DONE) {
1684 complete(&host->nfc->comp_cmd_done);
1685 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1686 ret = IRQ_HANDLED;
1687 }
1688
1689 return ret;
1690 }
1691
1692 /* NFC(Nand Flash Controller) related functions */
1693 static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1694 {
1695 if (flag & NFC_SR_XFR_DONE)
1696 init_completion(&host->nfc->comp_xfer_done);
1697
1698 if (flag & NFC_SR_RB_EDGE)
1699 init_completion(&host->nfc->comp_ready);
1700
1701 if (flag & NFC_SR_CMD_DONE)
1702 init_completion(&host->nfc->comp_cmd_done);
1703
1704 /* Enable interrupt that need to wait for */
1705 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1706 }
1707
1708 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1709 {
1710 int i, index = 0;
1711 struct completion *comp[3]; /* Support 3 interrupt completion */
1712
1713 if (flag & NFC_SR_XFR_DONE)
1714 comp[index++] = &host->nfc->comp_xfer_done;
1715
1716 if (flag & NFC_SR_RB_EDGE)
1717 comp[index++] = &host->nfc->comp_ready;
1718
1719 if (flag & NFC_SR_CMD_DONE)
1720 comp[index++] = &host->nfc->comp_cmd_done;
1721
1722 if (index == 0) {
1723 dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
1724 return -EINVAL;
1725 }
1726
1727 for (i = 0; i < index; i++) {
1728 if (wait_for_completion_timeout(comp[i],
1729 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1730 continue; /* wait for next completion */
1731 else
1732 goto err_timeout;
1733 }
1734
1735 return 0;
1736
1737 err_timeout:
1738 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1739 /* Disable the interrupt as it is not handled by interrupt handler */
1740 nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1741 return -ETIMEDOUT;
1742 }
1743
1744 static int nfc_send_command(struct atmel_nand_host *host,
1745 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1746 {
1747 unsigned long timeout;
1748 u32 flag = NFC_SR_CMD_DONE;
1749 flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1750
1751 dev_dbg(host->dev,
1752 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1753 cmd, addr, cycle0);
1754
1755 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1756 while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
1757 if (time_after(jiffies, timeout)) {
1758 dev_err(host->dev,
1759 "Time out to wait for NFC ready!\n");
1760 return -ETIMEDOUT;
1761 }
1762 }
1763
1764 nfc_prepare_interrupt(host, flag);
1765 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1766 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1767 return nfc_wait_interrupt(host, flag);
1768 }
1769
1770 static int nfc_device_ready(struct mtd_info *mtd)
1771 {
1772 u32 status, mask;
1773 struct nand_chip *nand_chip = mtd->priv;
1774 struct atmel_nand_host *host = nand_chip->priv;
1775
1776 status = nfc_read_status(host);
1777 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1778
1779 /* The mask should be 0. If not we may lost interrupts */
1780 if (unlikely(mask & status))
1781 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1782 mask & status);
1783
1784 return status & NFC_SR_RB_EDGE;
1785 }
1786
1787 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1788 {
1789 struct nand_chip *nand_chip = mtd->priv;
1790 struct atmel_nand_host *host = nand_chip->priv;
1791
1792 if (chip == -1)
1793 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1794 else
1795 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1796 }
1797
1798 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1799 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1800 {
1801 struct nand_chip *chip = mtd->priv;
1802
1803 int acycle = 0;
1804 unsigned char addr_bytes[8];
1805 int index = 0, bit_shift;
1806
1807 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1808
1809 *cycle0 = 0;
1810 *addr1234 = 0;
1811
1812 if (column != -1) {
1813 if (chip->options & NAND_BUSWIDTH_16 &&
1814 !nand_opcode_8bits(command))
1815 column >>= 1;
1816 addr_bytes[acycle++] = column & 0xff;
1817 if (mtd->writesize > 512)
1818 addr_bytes[acycle++] = (column >> 8) & 0xff;
1819 }
1820
1821 if (page_addr != -1) {
1822 addr_bytes[acycle++] = page_addr & 0xff;
1823 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1824 if (chip->chipsize > (128 << 20))
1825 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1826 }
1827
1828 if (acycle > 4)
1829 *cycle0 = addr_bytes[index++];
1830
1831 for (bit_shift = 0; index < acycle; bit_shift += 8)
1832 *addr1234 += addr_bytes[index++] << bit_shift;
1833
1834 /* return acycle in cmd register */
1835 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1836 }
1837
1838 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1839 int column, int page_addr)
1840 {
1841 struct nand_chip *chip = mtd->priv;
1842 struct atmel_nand_host *host = chip->priv;
1843 unsigned long timeout;
1844 unsigned int nfc_addr_cmd = 0;
1845
1846 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1847
1848 /* Set default settings: no cmd2, no addr cycle. read from nand */
1849 unsigned int cmd2 = 0;
1850 unsigned int vcmd2 = 0;
1851 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1852 int csid = NFCADDR_CMD_CSID_3;
1853 int dataen = NFCADDR_CMD_DATADIS;
1854 int nfcwr = NFCADDR_CMD_NFCRD;
1855 unsigned int addr1234 = 0;
1856 unsigned int cycle0 = 0;
1857 bool do_addr = true;
1858 host->nfc->data_in_sram = NULL;
1859
1860 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1861 __func__, command, column, page_addr);
1862
1863 switch (command) {
1864 case NAND_CMD_RESET:
1865 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1866 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1867 udelay(chip->chip_delay);
1868
1869 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1870 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1871 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1872 if (time_after(jiffies, timeout)) {
1873 dev_err(host->dev,
1874 "Time out to wait status ready!\n");
1875 break;
1876 }
1877 }
1878 return;
1879 case NAND_CMD_STATUS:
1880 do_addr = false;
1881 break;
1882 case NAND_CMD_PARAM:
1883 case NAND_CMD_READID:
1884 do_addr = false;
1885 acycle = NFCADDR_CMD_ACYCLE_1;
1886 if (column != -1)
1887 addr1234 = column;
1888 break;
1889 case NAND_CMD_RNDOUT:
1890 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1891 vcmd2 = NFCADDR_CMD_VCMD2;
1892 break;
1893 case NAND_CMD_READ0:
1894 case NAND_CMD_READOOB:
1895 if (command == NAND_CMD_READOOB) {
1896 column += mtd->writesize;
1897 command = NAND_CMD_READ0; /* only READ0 is valid */
1898 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1899 }
1900 if (host->nfc->use_nfc_sram) {
1901 /* Enable Data transfer to sram */
1902 dataen = NFCADDR_CMD_DATAEN;
1903
1904 /* Need enable PMECC now, since NFC will transfer
1905 * data in bus after sending nfc read command.
1906 */
1907 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1908 pmecc_enable(host, NAND_ECC_READ);
1909 }
1910
1911 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1912 vcmd2 = NFCADDR_CMD_VCMD2;
1913 break;
1914 /* For prgramming command, the cmd need set to write enable */
1915 case NAND_CMD_PAGEPROG:
1916 case NAND_CMD_SEQIN:
1917 case NAND_CMD_RNDIN:
1918 nfcwr = NFCADDR_CMD_NFCWR;
1919 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1920 dataen = NFCADDR_CMD_DATAEN;
1921 break;
1922 default:
1923 break;
1924 }
1925
1926 if (do_addr)
1927 acycle = nfc_make_addr(mtd, command, column, page_addr,
1928 &addr1234, &cycle0);
1929
1930 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1931 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1932
1933 /*
1934 * Program and erase have their own busy handlers status, sequential
1935 * in, and deplete1 need no delay.
1936 */
1937 switch (command) {
1938 case NAND_CMD_CACHEDPROG:
1939 case NAND_CMD_PAGEPROG:
1940 case NAND_CMD_ERASE1:
1941 case NAND_CMD_ERASE2:
1942 case NAND_CMD_RNDIN:
1943 case NAND_CMD_STATUS:
1944 case NAND_CMD_RNDOUT:
1945 case NAND_CMD_SEQIN:
1946 case NAND_CMD_READID:
1947 return;
1948
1949 case NAND_CMD_READ0:
1950 if (dataen == NFCADDR_CMD_DATAEN) {
1951 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1952 nfc_get_sram_off(host);
1953 return;
1954 }
1955 /* fall through */
1956 default:
1957 nfc_prepare_interrupt(host, NFC_SR_RB_EDGE);
1958 nfc_wait_interrupt(host, NFC_SR_RB_EDGE);
1959 }
1960 }
1961
1962 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1963 uint32_t offset, int data_len, const uint8_t *buf,
1964 int oob_required, int page, int cached, int raw)
1965 {
1966 int cfg, len;
1967 int status = 0;
1968 struct atmel_nand_host *host = chip->priv;
1969 void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
1970
1971 /* Subpage write is not supported */
1972 if (offset || (data_len < mtd->writesize))
1973 return -EINVAL;
1974
1975 len = mtd->writesize;
1976 /* Copy page data to sram that will write to nand via NFC */
1977 if (use_dma) {
1978 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
1979 /* Fall back to use cpu copy */
1980 memcpy(sram, buf, len);
1981 } else {
1982 memcpy(sram, buf, len);
1983 }
1984
1985 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
1986 if (unlikely(raw) && oob_required) {
1987 memcpy(sram + len, chip->oob_poi, mtd->oobsize);
1988 len += mtd->oobsize;
1989 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
1990 } else {
1991 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
1992 }
1993
1994 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1995 /*
1996 * When use NFC sram, need set up PMECC before send
1997 * NAND_CMD_SEQIN command. Since when the nand command
1998 * is sent, nfc will do transfer from sram and nand.
1999 */
2000 pmecc_enable(host, NAND_ECC_WRITE);
2001
2002 host->nfc->will_write_sram = true;
2003 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2004 host->nfc->will_write_sram = false;
2005
2006 if (likely(!raw))
2007 /* Need to write ecc into oob */
2008 status = chip->ecc.write_page(mtd, chip, buf, oob_required);
2009
2010 if (status < 0)
2011 return status;
2012
2013 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2014 status = chip->waitfunc(mtd, chip);
2015
2016 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2017 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
2018
2019 if (status & NAND_STATUS_FAIL)
2020 return -EIO;
2021
2022 return 0;
2023 }
2024
2025 static int nfc_sram_init(struct mtd_info *mtd)
2026 {
2027 struct nand_chip *chip = mtd->priv;
2028 struct atmel_nand_host *host = chip->priv;
2029 int res = 0;
2030
2031 /* Initialize the NFC CFG register */
2032 unsigned int cfg_nfc = 0;
2033
2034 /* set page size and oob layout */
2035 switch (mtd->writesize) {
2036 case 512:
2037 cfg_nfc = NFC_CFG_PAGESIZE_512;
2038 break;
2039 case 1024:
2040 cfg_nfc = NFC_CFG_PAGESIZE_1024;
2041 break;
2042 case 2048:
2043 cfg_nfc = NFC_CFG_PAGESIZE_2048;
2044 break;
2045 case 4096:
2046 cfg_nfc = NFC_CFG_PAGESIZE_4096;
2047 break;
2048 case 8192:
2049 cfg_nfc = NFC_CFG_PAGESIZE_8192;
2050 break;
2051 default:
2052 dev_err(host->dev, "Unsupported page size for NFC.\n");
2053 res = -ENXIO;
2054 return res;
2055 }
2056
2057 /* oob bytes size = (NFCSPARESIZE + 1) * 4
2058 * Max support spare size is 512 bytes. */
2059 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2060 & NFC_CFG_NFC_SPARESIZE);
2061 /* default set a max timeout */
2062 cfg_nfc |= NFC_CFG_RSPARE |
2063 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
2064
2065 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2066
2067 host->nfc->will_write_sram = false;
2068 nfc_set_sram_bank(host, 0);
2069
2070 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2071 if (host->nfc->write_by_sram) {
2072 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2073 chip->ecc.mode == NAND_ECC_NONE)
2074 chip->write_page = nfc_sram_write_page;
2075 else
2076 host->nfc->write_by_sram = false;
2077 }
2078
2079 dev_info(host->dev, "Using NFC Sram read %s\n",
2080 host->nfc->write_by_sram ? "and write" : "");
2081 return 0;
2082 }
2083
2084 static struct platform_driver atmel_nand_nfc_driver;
2085 /*
2086 * Probe for the NAND device.
2087 */
2088 static int atmel_nand_probe(struct platform_device *pdev)
2089 {
2090 struct atmel_nand_host *host;
2091 struct mtd_info *mtd;
2092 struct nand_chip *nand_chip;
2093 struct resource *mem;
2094 struct mtd_part_parser_data ppdata = {};
2095 int res, irq;
2096
2097 /* Allocate memory for the device structure (and zero it) */
2098 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2099 if (!host)
2100 return -ENOMEM;
2101
2102 res = platform_driver_register(&atmel_nand_nfc_driver);
2103 if (res)
2104 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2105
2106 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2107 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2108 if (IS_ERR(host->io_base)) {
2109 res = PTR_ERR(host->io_base);
2110 goto err_nand_ioremap;
2111 }
2112 host->io_phys = (dma_addr_t)mem->start;
2113
2114 mtd = &host->mtd;
2115 nand_chip = &host->nand_chip;
2116 host->dev = &pdev->dev;
2117 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2118 /* Only when CONFIG_OF is enabled of_node can be parsed */
2119 res = atmel_of_init_port(host, pdev->dev.of_node);
2120 if (res)
2121 goto err_nand_ioremap;
2122 } else {
2123 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2124 sizeof(struct atmel_nand_data));
2125 }
2126
2127 nand_chip->priv = host; /* link the private data structures */
2128 mtd->priv = nand_chip;
2129 mtd->owner = THIS_MODULE;
2130
2131 /* Set address of NAND IO lines */
2132 nand_chip->IO_ADDR_R = host->io_base;
2133 nand_chip->IO_ADDR_W = host->io_base;
2134
2135 if (nand_nfc.is_initialized) {
2136 /* NFC driver is probed and initialized */
2137 host->nfc = &nand_nfc;
2138
2139 nand_chip->select_chip = nfc_select_chip;
2140 nand_chip->dev_ready = nfc_device_ready;
2141 nand_chip->cmdfunc = nfc_nand_command;
2142
2143 /* Initialize the interrupt for NFC */
2144 irq = platform_get_irq(pdev, 0);
2145 if (irq < 0) {
2146 dev_err(host->dev, "Cannot get HSMC irq!\n");
2147 res = irq;
2148 goto err_nand_ioremap;
2149 }
2150
2151 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2152 0, "hsmc", host);
2153 if (res) {
2154 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2155 irq);
2156 goto err_nand_ioremap;
2157 }
2158 } else {
2159 res = atmel_nand_set_enable_ready_pins(mtd);
2160 if (res)
2161 goto err_nand_ioremap;
2162
2163 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2164 }
2165
2166 nand_chip->ecc.mode = host->board.ecc_mode;
2167 nand_chip->chip_delay = 40; /* 40us command delay time */
2168
2169 if (host->board.bus_width_16) /* 16-bit bus width */
2170 nand_chip->options |= NAND_BUSWIDTH_16;
2171
2172 nand_chip->read_buf = atmel_read_buf;
2173 nand_chip->write_buf = atmel_write_buf;
2174
2175 platform_set_drvdata(pdev, host);
2176 atmel_nand_enable(host);
2177
2178 if (gpio_is_valid(host->board.det_pin)) {
2179 res = devm_gpio_request(&pdev->dev,
2180 host->board.det_pin, "nand_det");
2181 if (res < 0) {
2182 dev_err(&pdev->dev,
2183 "can't request det gpio %d\n",
2184 host->board.det_pin);
2185 goto err_no_card;
2186 }
2187
2188 res = gpio_direction_input(host->board.det_pin);
2189 if (res < 0) {
2190 dev_err(&pdev->dev,
2191 "can't request input direction det gpio %d\n",
2192 host->board.det_pin);
2193 goto err_no_card;
2194 }
2195
2196 if (gpio_get_value(host->board.det_pin)) {
2197 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2198 res = -ENXIO;
2199 goto err_no_card;
2200 }
2201 }
2202
2203 if (host->board.on_flash_bbt || on_flash_bbt) {
2204 dev_info(&pdev->dev, "Use On Flash BBT\n");
2205 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2206 }
2207
2208 if (!host->board.has_dma)
2209 use_dma = 0;
2210
2211 if (use_dma) {
2212 dma_cap_mask_t mask;
2213
2214 dma_cap_zero(mask);
2215 dma_cap_set(DMA_MEMCPY, mask);
2216 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2217 if (!host->dma_chan) {
2218 dev_err(host->dev, "Failed to request DMA channel\n");
2219 use_dma = 0;
2220 }
2221 }
2222 if (use_dma)
2223 dev_info(host->dev, "Using %s for DMA transfers.\n",
2224 dma_chan_name(host->dma_chan));
2225 else
2226 dev_info(host->dev, "No DMA support for NAND access.\n");
2227
2228 /* first scan to find the device and get the page size */
2229 if (nand_scan_ident(mtd, 1, NULL)) {
2230 res = -ENXIO;
2231 goto err_scan_ident;
2232 }
2233
2234 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2235 if (host->has_pmecc)
2236 res = atmel_pmecc_nand_init_params(pdev, host);
2237 else
2238 res = atmel_hw_nand_init_params(pdev, host);
2239
2240 if (res != 0)
2241 goto err_hw_ecc;
2242 }
2243
2244 /* initialize the nfc configuration register */
2245 if (host->nfc && host->nfc->use_nfc_sram) {
2246 res = nfc_sram_init(mtd);
2247 if (res) {
2248 host->nfc->use_nfc_sram = false;
2249 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2250 }
2251 }
2252
2253 /* second phase scan */
2254 if (nand_scan_tail(mtd)) {
2255 res = -ENXIO;
2256 goto err_scan_tail;
2257 }
2258
2259 mtd->name = "atmel_nand";
2260 ppdata.of_node = pdev->dev.of_node;
2261 res = mtd_device_parse_register(mtd, NULL, &ppdata,
2262 host->board.parts, host->board.num_parts);
2263 if (!res)
2264 return res;
2265
2266 err_scan_tail:
2267 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2268 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2269 err_hw_ecc:
2270 err_scan_ident:
2271 err_no_card:
2272 atmel_nand_disable(host);
2273 if (host->dma_chan)
2274 dma_release_channel(host->dma_chan);
2275 err_nand_ioremap:
2276 return res;
2277 }
2278
2279 /*
2280 * Remove a NAND device.
2281 */
2282 static int atmel_nand_remove(struct platform_device *pdev)
2283 {
2284 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2285 struct mtd_info *mtd = &host->mtd;
2286
2287 nand_release(mtd);
2288
2289 atmel_nand_disable(host);
2290
2291 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2292 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2293 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2294 PMERRLOC_DISABLE);
2295 }
2296
2297 if (host->dma_chan)
2298 dma_release_channel(host->dma_chan);
2299
2300 platform_driver_unregister(&atmel_nand_nfc_driver);
2301
2302 return 0;
2303 }
2304
2305 static struct atmel_nand_caps at91rm9200_caps = {
2306 .pmecc_correct_erase_page = false,
2307 };
2308
2309 static struct atmel_nand_caps sama5d4_caps = {
2310 .pmecc_correct_erase_page = true,
2311 };
2312
2313 static const struct of_device_id atmel_nand_dt_ids[] = {
2314 { .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
2315 { .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
2316 { /* sentinel */ }
2317 };
2318
2319 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2320
2321 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2322 {
2323 struct atmel_nfc *nfc = &nand_nfc;
2324 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2325 int ret;
2326
2327 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2328 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2329 if (IS_ERR(nfc->base_cmd_regs))
2330 return PTR_ERR(nfc->base_cmd_regs);
2331
2332 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2333 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2334 if (IS_ERR(nfc->hsmc_regs))
2335 return PTR_ERR(nfc->hsmc_regs);
2336
2337 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2338 if (nfc_sram) {
2339 nfc->sram_bank0 = (void * __force)
2340 devm_ioremap_resource(&pdev->dev, nfc_sram);
2341 if (IS_ERR(nfc->sram_bank0)) {
2342 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2343 PTR_ERR(nfc->sram_bank0));
2344 } else {
2345 nfc->use_nfc_sram = true;
2346 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2347
2348 if (pdev->dev.of_node)
2349 nfc->write_by_sram = of_property_read_bool(
2350 pdev->dev.of_node,
2351 "atmel,write-by-sram");
2352 }
2353 }
2354
2355 nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2356 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
2357
2358 nfc->clk = devm_clk_get(&pdev->dev, NULL);
2359 if (!IS_ERR(nfc->clk)) {
2360 ret = clk_prepare_enable(nfc->clk);
2361 if (ret)
2362 return ret;
2363 } else {
2364 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2365 }
2366
2367 nfc->is_initialized = true;
2368 dev_info(&pdev->dev, "NFC is probed.\n");
2369
2370 return 0;
2371 }
2372
2373 static int atmel_nand_nfc_remove(struct platform_device *pdev)
2374 {
2375 struct atmel_nfc *nfc = &nand_nfc;
2376
2377 if (!IS_ERR(nfc->clk))
2378 clk_disable_unprepare(nfc->clk);
2379
2380 return 0;
2381 }
2382
2383 static const struct of_device_id atmel_nand_nfc_match[] = {
2384 { .compatible = "atmel,sama5d3-nfc" },
2385 { /* sentinel */ }
2386 };
2387 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2388
2389 static struct platform_driver atmel_nand_nfc_driver = {
2390 .driver = {
2391 .name = "atmel_nand_nfc",
2392 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2393 },
2394 .probe = atmel_nand_nfc_probe,
2395 .remove = atmel_nand_nfc_remove,
2396 };
2397
2398 static struct platform_driver atmel_nand_driver = {
2399 .probe = atmel_nand_probe,
2400 .remove = atmel_nand_remove,
2401 .driver = {
2402 .name = "atmel_nand",
2403 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2404 },
2405 };
2406
2407 module_platform_driver(atmel_nand_driver);
2408
2409 MODULE_LICENSE("GPL");
2410 MODULE_AUTHOR("Rick Bronson");
2411 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2412 MODULE_ALIAS("platform:atmel_nand");
Linux kernel - Deliverables
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