2 * Copyright © 2003 Rick Bronson
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License version 2 as
23 * published by the Free Software Foundation.
27 #include <linux/dma-mapping.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/platform_device.h>
33 #include <linux/of_device.h>
34 #include <linux/of_gpio.h>
35 #include <linux/of_mtd.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/nand.h>
38 #include <linux/mtd/partitions.h>
40 #include <linux/dmaengine.h>
41 #include <linux/gpio.h>
43 #include <linux/platform_data/atmel.h>
44 #include <linux/pinctrl/consumer.h>
48 static int use_dma
= 1;
49 module_param(use_dma
, int, 0);
51 static int on_flash_bbt
= 0;
52 module_param(on_flash_bbt
, int, 0);
54 /* Register access macros */
55 #define ecc_readl(add, reg) \
56 __raw_readl(add + ATMEL_ECC_##reg)
57 #define ecc_writel(add, reg, value) \
58 __raw_writel((value), add + ATMEL_ECC_##reg)
60 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
62 /* oob layout for large page size
63 * bad block info is on bytes 0 and 1
64 * the bytes have to be consecutives to avoid
65 * several NAND_CMD_RNDOUT during read
67 static struct nand_ecclayout atmel_oobinfo_large
= {
69 .eccpos
= {60, 61, 62, 63},
75 /* oob layout for small page size
76 * bad block info is on bytes 4 and 5
77 * the bytes have to be consecutives to avoid
78 * several NAND_CMD_RNDOUT during read
80 static struct nand_ecclayout atmel_oobinfo_small
= {
82 .eccpos
= {0, 1, 2, 3},
88 struct atmel_nand_host
{
89 struct nand_chip nand_chip
;
91 void __iomem
*io_base
;
93 struct atmel_nand_data board
;
97 struct completion comp
;
98 struct dma_chan
*dma_chan
;
102 u16 pmecc_sector_size
;
103 u32 pmecc_lookup_table_offset
;
105 int pmecc_bytes_per_sector
;
106 int pmecc_sector_number
;
107 int pmecc_degree
; /* Degree of remainders */
108 int pmecc_cw_len
; /* Length of codeword */
110 void __iomem
*pmerrloc_base
;
111 void __iomem
*pmecc_rom_base
;
113 /* lookup table for alpha_to and index_of */
114 void __iomem
*pmecc_alpha_to
;
115 void __iomem
*pmecc_index_of
;
117 /* data for pmecc computation */
118 int16_t *pmecc_partial_syn
;
120 int16_t *pmecc_smu
; /* Sigma table */
121 int16_t *pmecc_lmu
; /* polynomal order */
127 static struct nand_ecclayout atmel_pmecc_oobinfo
;
129 static int cpu_has_dma(void)
131 return cpu_is_at91sam9rl() || cpu_is_at91sam9g45();
137 static void atmel_nand_enable(struct atmel_nand_host
*host
)
139 if (gpio_is_valid(host
->board
.enable_pin
))
140 gpio_set_value(host
->board
.enable_pin
, 0);
146 static void atmel_nand_disable(struct atmel_nand_host
*host
)
148 if (gpio_is_valid(host
->board
.enable_pin
))
149 gpio_set_value(host
->board
.enable_pin
, 1);
153 * Hardware specific access to control-lines
155 static void atmel_nand_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
157 struct nand_chip
*nand_chip
= mtd
->priv
;
158 struct atmel_nand_host
*host
= nand_chip
->priv
;
160 if (ctrl
& NAND_CTRL_CHANGE
) {
162 atmel_nand_enable(host
);
164 atmel_nand_disable(host
);
166 if (cmd
== NAND_CMD_NONE
)
170 writeb(cmd
, host
->io_base
+ (1 << host
->board
.cle
));
172 writeb(cmd
, host
->io_base
+ (1 << host
->board
.ale
));
176 * Read the Device Ready pin.
178 static int atmel_nand_device_ready(struct mtd_info
*mtd
)
180 struct nand_chip
*nand_chip
= mtd
->priv
;
181 struct atmel_nand_host
*host
= nand_chip
->priv
;
183 return gpio_get_value(host
->board
.rdy_pin
) ^
184 !!host
->board
.rdy_pin_active_low
;
188 * Minimal-overhead PIO for data access.
190 static void atmel_read_buf8(struct mtd_info
*mtd
, u8
*buf
, int len
)
192 struct nand_chip
*nand_chip
= mtd
->priv
;
194 __raw_readsb(nand_chip
->IO_ADDR_R
, buf
, len
);
197 static void atmel_read_buf16(struct mtd_info
*mtd
, u8
*buf
, int len
)
199 struct nand_chip
*nand_chip
= mtd
->priv
;
201 __raw_readsw(nand_chip
->IO_ADDR_R
, buf
, len
/ 2);
204 static void atmel_write_buf8(struct mtd_info
*mtd
, const u8
*buf
, int len
)
206 struct nand_chip
*nand_chip
= mtd
->priv
;
208 __raw_writesb(nand_chip
->IO_ADDR_W
, buf
, len
);
211 static void atmel_write_buf16(struct mtd_info
*mtd
, const u8
*buf
, int len
)
213 struct nand_chip
*nand_chip
= mtd
->priv
;
215 __raw_writesw(nand_chip
->IO_ADDR_W
, buf
, len
/ 2);
218 static void dma_complete_func(void *completion
)
220 complete(completion
);
223 static int atmel_nand_dma_op(struct mtd_info
*mtd
, void *buf
, int len
,
226 struct dma_device
*dma_dev
;
227 enum dma_ctrl_flags flags
;
228 dma_addr_t dma_src_addr
, dma_dst_addr
, phys_addr
;
229 struct dma_async_tx_descriptor
*tx
= NULL
;
231 struct nand_chip
*chip
= mtd
->priv
;
232 struct atmel_nand_host
*host
= chip
->priv
;
235 enum dma_data_direction dir
= is_read
? DMA_FROM_DEVICE
: DMA_TO_DEVICE
;
237 if (buf
>= high_memory
)
240 dma_dev
= host
->dma_chan
->device
;
242 flags
= DMA_CTRL_ACK
| DMA_PREP_INTERRUPT
| DMA_COMPL_SKIP_SRC_UNMAP
|
243 DMA_COMPL_SKIP_DEST_UNMAP
;
245 phys_addr
= dma_map_single(dma_dev
->dev
, p
, len
, dir
);
246 if (dma_mapping_error(dma_dev
->dev
, phys_addr
)) {
247 dev_err(host
->dev
, "Failed to dma_map_single\n");
252 dma_src_addr
= host
->io_phys
;
253 dma_dst_addr
= phys_addr
;
255 dma_src_addr
= phys_addr
;
256 dma_dst_addr
= host
->io_phys
;
259 tx
= dma_dev
->device_prep_dma_memcpy(host
->dma_chan
, dma_dst_addr
,
260 dma_src_addr
, len
, flags
);
262 dev_err(host
->dev
, "Failed to prepare DMA memcpy\n");
266 init_completion(&host
->comp
);
267 tx
->callback
= dma_complete_func
;
268 tx
->callback_param
= &host
->comp
;
270 cookie
= tx
->tx_submit(tx
);
271 if (dma_submit_error(cookie
)) {
272 dev_err(host
->dev
, "Failed to do DMA tx_submit\n");
276 dma_async_issue_pending(host
->dma_chan
);
277 wait_for_completion(&host
->comp
);
282 dma_unmap_single(dma_dev
->dev
, phys_addr
, len
, dir
);
285 dev_warn(host
->dev
, "Fall back to CPU I/O\n");
289 static void atmel_read_buf(struct mtd_info
*mtd
, u8
*buf
, int len
)
291 struct nand_chip
*chip
= mtd
->priv
;
292 struct atmel_nand_host
*host
= chip
->priv
;
294 if (use_dma
&& len
> mtd
->oobsize
)
295 /* only use DMA for bigger than oob size: better performances */
296 if (atmel_nand_dma_op(mtd
, buf
, len
, 1) == 0)
299 if (host
->board
.bus_width_16
)
300 atmel_read_buf16(mtd
, buf
, len
);
302 atmel_read_buf8(mtd
, buf
, len
);
305 static void atmel_write_buf(struct mtd_info
*mtd
, const u8
*buf
, int len
)
307 struct nand_chip
*chip
= mtd
->priv
;
308 struct atmel_nand_host
*host
= chip
->priv
;
310 if (use_dma
&& len
> mtd
->oobsize
)
311 /* only use DMA for bigger than oob size: better performances */
312 if (atmel_nand_dma_op(mtd
, (void *)buf
, len
, 0) == 0)
315 if (host
->board
.bus_width_16
)
316 atmel_write_buf16(mtd
, buf
, len
);
318 atmel_write_buf8(mtd
, buf
, len
);
322 * Return number of ecc bytes per sector according to sector size and
323 * correction capability
325 * Following table shows what at91 PMECC supported:
326 * Correction Capability Sector_512_bytes Sector_1024_bytes
327 * ===================== ================ =================
328 * 2-bits 4-bytes 4-bytes
329 * 4-bits 7-bytes 7-bytes
330 * 8-bits 13-bytes 14-bytes
331 * 12-bits 20-bytes 21-bytes
332 * 24-bits 39-bytes 42-bytes
334 static int pmecc_get_ecc_bytes(int cap
, int sector_size
)
336 int m
= 12 + sector_size
/ 512;
337 return (m
* cap
+ 7) / 8;
340 static void pmecc_config_ecc_layout(struct nand_ecclayout
*layout
,
341 int oobsize
, int ecc_len
)
345 layout
->eccbytes
= ecc_len
;
347 /* ECC will occupy the last ecc_len bytes continuously */
348 for (i
= 0; i
< ecc_len
; i
++)
349 layout
->eccpos
[i
] = oobsize
- ecc_len
+ i
;
351 layout
->oobfree
[0].offset
= 2;
352 layout
->oobfree
[0].length
=
353 oobsize
- ecc_len
- layout
->oobfree
[0].offset
;
356 static void __iomem
*pmecc_get_alpha_to(struct atmel_nand_host
*host
)
360 table_size
= host
->pmecc_sector_size
== 512 ?
361 PMECC_LOOKUP_TABLE_SIZE_512
: PMECC_LOOKUP_TABLE_SIZE_1024
;
363 return host
->pmecc_rom_base
+ host
->pmecc_lookup_table_offset
+
364 table_size
* sizeof(int16_t);
367 static void pmecc_data_free(struct atmel_nand_host
*host
)
369 kfree(host
->pmecc_partial_syn
);
370 kfree(host
->pmecc_si
);
371 kfree(host
->pmecc_lmu
);
372 kfree(host
->pmecc_smu
);
373 kfree(host
->pmecc_mu
);
374 kfree(host
->pmecc_dmu
);
375 kfree(host
->pmecc_delta
);
378 static int pmecc_data_alloc(struct atmel_nand_host
*host
)
380 const int cap
= host
->pmecc_corr_cap
;
382 host
->pmecc_partial_syn
= kzalloc((2 * cap
+ 1) * sizeof(int16_t),
384 host
->pmecc_si
= kzalloc((2 * cap
+ 1) * sizeof(int16_t), GFP_KERNEL
);
385 host
->pmecc_lmu
= kzalloc((cap
+ 1) * sizeof(int16_t), GFP_KERNEL
);
386 host
->pmecc_smu
= kzalloc((cap
+ 2) * (2 * cap
+ 1) * sizeof(int16_t),
388 host
->pmecc_mu
= kzalloc((cap
+ 1) * sizeof(int), GFP_KERNEL
);
389 host
->pmecc_dmu
= kzalloc((cap
+ 1) * sizeof(int), GFP_KERNEL
);
390 host
->pmecc_delta
= kzalloc((cap
+ 1) * sizeof(int), GFP_KERNEL
);
392 if (host
->pmecc_partial_syn
&&
402 pmecc_data_free(host
);
406 static void pmecc_gen_syndrome(struct mtd_info
*mtd
, int sector
)
408 struct nand_chip
*nand_chip
= mtd
->priv
;
409 struct atmel_nand_host
*host
= nand_chip
->priv
;
413 /* Fill odd syndromes */
414 for (i
= 0; i
< host
->pmecc_corr_cap
; i
++) {
415 value
= pmecc_readl_rem_relaxed(host
->ecc
, sector
, i
/ 2);
419 host
->pmecc_partial_syn
[(2 * i
) + 1] = (int16_t)value
;
423 static void pmecc_substitute(struct mtd_info
*mtd
)
425 struct nand_chip
*nand_chip
= mtd
->priv
;
426 struct atmel_nand_host
*host
= nand_chip
->priv
;
427 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
428 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
429 int16_t *partial_syn
= host
->pmecc_partial_syn
;
430 const int cap
= host
->pmecc_corr_cap
;
434 /* si[] is a table that holds the current syndrome value,
435 * an element of that table belongs to the field
439 memset(&si
[1], 0, sizeof(int16_t) * (2 * cap
- 1));
441 /* Computation 2t syndromes based on S(x) */
443 for (i
= 1; i
< 2 * cap
; i
+= 2) {
444 for (j
= 0; j
< host
->pmecc_degree
; j
++) {
445 if (partial_syn
[i
] & ((unsigned short)0x1 << j
))
446 si
[i
] = readw_relaxed(alpha_to
+ i
* j
) ^ si
[i
];
449 /* Even syndrome = (Odd syndrome) ** 2 */
450 for (i
= 2, j
= 1; j
<= cap
; i
= ++j
<< 1) {
456 tmp
= readw_relaxed(index_of
+ si
[j
]);
457 tmp
= (tmp
* 2) % host
->pmecc_cw_len
;
458 si
[i
] = readw_relaxed(alpha_to
+ tmp
);
465 static void pmecc_get_sigma(struct mtd_info
*mtd
)
467 struct nand_chip
*nand_chip
= mtd
->priv
;
468 struct atmel_nand_host
*host
= nand_chip
->priv
;
470 int16_t *lmu
= host
->pmecc_lmu
;
471 int16_t *si
= host
->pmecc_si
;
472 int *mu
= host
->pmecc_mu
;
473 int *dmu
= host
->pmecc_dmu
; /* Discrepancy */
474 int *delta
= host
->pmecc_delta
; /* Delta order */
475 int cw_len
= host
->pmecc_cw_len
;
476 const int16_t cap
= host
->pmecc_corr_cap
;
477 const int num
= 2 * cap
+ 1;
478 int16_t __iomem
*index_of
= host
->pmecc_index_of
;
479 int16_t __iomem
*alpha_to
= host
->pmecc_alpha_to
;
481 uint32_t dmu_0_count
, tmp
;
482 int16_t *smu
= host
->pmecc_smu
;
484 /* index of largest delta */
496 memset(smu
, 0, sizeof(int16_t) * num
);
499 /* discrepancy set to 1 */
501 /* polynom order set to 0 */
503 delta
[0] = (mu
[0] * 2 - lmu
[0]) >> 1;
509 /* Sigma(x) set to 1 */
510 memset(&smu
[num
], 0, sizeof(int16_t) * num
);
513 /* discrepancy set to S1 */
516 /* polynom order set to 0 */
519 delta
[1] = (mu
[1] * 2 - lmu
[1]) >> 1;
521 /* Init the Sigma(x) last row */
522 memset(&smu
[(cap
+ 1) * num
], 0, sizeof(int16_t) * num
);
524 for (i
= 1; i
<= cap
; i
++) {
526 /* Begin Computing Sigma (Mu+1) and L(mu) */
527 /* check if discrepancy is set to 0 */
531 tmp
= ((cap
- (lmu
[i
] >> 1) - 1) / 2);
532 if ((cap
- (lmu
[i
] >> 1) - 1) & 0x1)
537 if (dmu_0_count
== tmp
) {
538 for (j
= 0; j
<= (lmu
[i
] >> 1) + 1; j
++)
539 smu
[(cap
+ 1) * num
+ j
] =
542 lmu
[cap
+ 1] = lmu
[i
];
547 for (j
= 0; j
<= lmu
[i
] >> 1; j
++)
548 smu
[(i
+ 1) * num
+ j
] = smu
[i
* num
+ j
];
550 /* copy previous polynom order to the next */
555 /* find largest delta with dmu != 0 */
556 for (j
= 0; j
< i
; j
++) {
557 if ((dmu
[j
]) && (delta
[j
] > largest
)) {
563 /* compute difference */
564 diff
= (mu
[i
] - mu
[ro
]);
566 /* Compute degree of the new smu polynomial */
567 if ((lmu
[i
] >> 1) > ((lmu
[ro
] >> 1) + diff
))
570 lmu
[i
+ 1] = ((lmu
[ro
] >> 1) + diff
) * 2;
572 /* Init smu[i+1] with 0 */
573 for (k
= 0; k
< num
; k
++)
574 smu
[(i
+ 1) * num
+ k
] = 0;
576 /* Compute smu[i+1] */
577 for (k
= 0; k
<= lmu
[ro
] >> 1; k
++) {
580 if (!(smu
[ro
* num
+ k
] && dmu
[i
]))
582 a
= readw_relaxed(index_of
+ dmu
[i
]);
583 b
= readw_relaxed(index_of
+ dmu
[ro
]);
584 c
= readw_relaxed(index_of
+ smu
[ro
* num
+ k
]);
585 tmp
= a
+ (cw_len
- b
) + c
;
586 a
= readw_relaxed(alpha_to
+ tmp
% cw_len
);
587 smu
[(i
+ 1) * num
+ (k
+ diff
)] = a
;
590 for (k
= 0; k
<= lmu
[i
] >> 1; k
++)
591 smu
[(i
+ 1) * num
+ k
] ^= smu
[i
* num
+ k
];
594 /* End Computing Sigma (Mu+1) and L(mu) */
595 /* In either case compute delta */
596 delta
[i
+ 1] = (mu
[i
+ 1] * 2 - lmu
[i
+ 1]) >> 1;
598 /* Do not compute discrepancy for the last iteration */
602 for (k
= 0; k
<= (lmu
[i
+ 1] >> 1); k
++) {
605 dmu
[i
+ 1] = si
[tmp
+ 3];
606 } else if (smu
[(i
+ 1) * num
+ k
] && si
[tmp
+ 3 - k
]) {
608 a
= readw_relaxed(index_of
+
609 smu
[(i
+ 1) * num
+ k
]);
610 b
= si
[2 * (i
- 1) + 3 - k
];
611 c
= readw_relaxed(index_of
+ b
);
614 dmu
[i
+ 1] = readw_relaxed(alpha_to
+ tmp
) ^
623 static int pmecc_err_location(struct mtd_info
*mtd
)
625 struct nand_chip
*nand_chip
= mtd
->priv
;
626 struct atmel_nand_host
*host
= nand_chip
->priv
;
627 unsigned long end_time
;
628 const int cap
= host
->pmecc_corr_cap
;
629 const int num
= 2 * cap
+ 1;
630 int sector_size
= host
->pmecc_sector_size
;
631 int err_nbr
= 0; /* number of error */
632 int roots_nbr
; /* number of roots */
635 int16_t *smu
= host
->pmecc_smu
;
637 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
, PMERRLOC_DISABLE
);
639 for (i
= 0; i
<= host
->pmecc_lmu
[cap
+ 1] >> 1; i
++) {
640 pmerrloc_writel_sigma_relaxed(host
->pmerrloc_base
, i
,
641 smu
[(cap
+ 1) * num
+ i
]);
645 val
= (err_nbr
- 1) << 16;
646 if (sector_size
== 1024)
649 pmerrloc_writel(host
->pmerrloc_base
, ELCFG
, val
);
650 pmerrloc_writel(host
->pmerrloc_base
, ELEN
,
651 sector_size
* 8 + host
->pmecc_degree
* cap
);
653 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
654 while (!(pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
655 & PMERRLOC_CALC_DONE
)) {
656 if (unlikely(time_after(jiffies
, end_time
))) {
657 dev_err(host
->dev
, "PMECC: Timeout to calculate error location.\n");
663 roots_nbr
= (pmerrloc_readl_relaxed(host
->pmerrloc_base
, ELISR
)
664 & PMERRLOC_ERR_NUM_MASK
) >> 8;
665 /* Number of roots == degree of smu hence <= cap */
666 if (roots_nbr
== host
->pmecc_lmu
[cap
+ 1] >> 1)
669 /* Number of roots does not match the degree of smu
670 * unable to correct error */
674 static void pmecc_correct_data(struct mtd_info
*mtd
, uint8_t *buf
, uint8_t *ecc
,
675 int sector_num
, int extra_bytes
, int err_nbr
)
677 struct nand_chip
*nand_chip
= mtd
->priv
;
678 struct atmel_nand_host
*host
= nand_chip
->priv
;
680 int byte_pos
, bit_pos
, sector_size
, pos
;
684 sector_size
= host
->pmecc_sector_size
;
687 tmp
= pmerrloc_readl_el_relaxed(host
->pmerrloc_base
, i
) - 1;
691 if (byte_pos
>= (sector_size
+ extra_bytes
))
692 BUG(); /* should never happen */
694 if (byte_pos
< sector_size
) {
695 err_byte
= *(buf
+ byte_pos
);
696 *(buf
+ byte_pos
) ^= (1 << bit_pos
);
698 pos
= sector_num
* host
->pmecc_sector_size
+ byte_pos
;
699 dev_info(host
->dev
, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
700 pos
, bit_pos
, err_byte
, *(buf
+ byte_pos
));
702 /* Bit flip in OOB area */
703 tmp
= sector_num
* host
->pmecc_bytes_per_sector
704 + (byte_pos
- sector_size
);
706 ecc
[tmp
] ^= (1 << bit_pos
);
708 pos
= tmp
+ nand_chip
->ecc
.layout
->eccpos
[0];
709 dev_info(host
->dev
, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
710 pos
, bit_pos
, err_byte
, ecc
[tmp
]);
720 static int pmecc_correction(struct mtd_info
*mtd
, u32 pmecc_stat
, uint8_t *buf
,
723 struct nand_chip
*nand_chip
= mtd
->priv
;
724 struct atmel_nand_host
*host
= nand_chip
->priv
;
725 int i
, err_nbr
, eccbytes
;
729 eccbytes
= nand_chip
->ecc
.bytes
;
730 for (i
= 0; i
< eccbytes
; i
++)
733 /* Erased page, return OK */
737 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
739 if (pmecc_stat
& 0x1) {
740 buf_pos
= buf
+ i
* host
->pmecc_sector_size
;
742 pmecc_gen_syndrome(mtd
, i
);
743 pmecc_substitute(mtd
);
744 pmecc_get_sigma(mtd
);
746 err_nbr
= pmecc_err_location(mtd
);
748 dev_err(host
->dev
, "PMECC: Too many errors\n");
749 mtd
->ecc_stats
.failed
++;
752 pmecc_correct_data(mtd
, buf_pos
, ecc
, i
,
753 host
->pmecc_bytes_per_sector
, err_nbr
);
754 mtd
->ecc_stats
.corrected
+= err_nbr
;
755 total_err
+= err_nbr
;
764 static int atmel_nand_pmecc_read_page(struct mtd_info
*mtd
,
765 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
767 struct atmel_nand_host
*host
= chip
->priv
;
768 int eccsize
= chip
->ecc
.size
;
769 uint8_t *oob
= chip
->oob_poi
;
770 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
772 unsigned long end_time
;
775 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
776 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
777 pmecc_writel(host
->ecc
, CFG
, (pmecc_readl_relaxed(host
->ecc
, CFG
)
778 & ~PMECC_CFG_WRITE_OP
) | PMECC_CFG_AUTO_ENABLE
);
780 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
781 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DATA
);
783 chip
->read_buf(mtd
, buf
, eccsize
);
784 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
786 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
787 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
788 if (unlikely(time_after(jiffies
, end_time
))) {
789 dev_err(host
->dev
, "PMECC: Timeout to get error status.\n");
795 stat
= pmecc_readl_relaxed(host
->ecc
, ISR
);
797 bitflips
= pmecc_correction(mtd
, stat
, buf
, &oob
[eccpos
[0]]);
799 /* uncorrectable errors */
806 static int atmel_nand_pmecc_write_page(struct mtd_info
*mtd
,
807 struct nand_chip
*chip
, const uint8_t *buf
, int oob_required
)
809 struct atmel_nand_host
*host
= chip
->priv
;
810 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
812 unsigned long end_time
;
814 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
815 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
817 pmecc_writel(host
->ecc
, CFG
, (pmecc_readl_relaxed(host
->ecc
, CFG
) |
818 PMECC_CFG_WRITE_OP
) & ~PMECC_CFG_AUTO_ENABLE
);
820 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
821 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DATA
);
823 chip
->write_buf(mtd
, (u8
*)buf
, mtd
->writesize
);
825 end_time
= jiffies
+ msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS
);
826 while ((pmecc_readl_relaxed(host
->ecc
, SR
) & PMECC_SR_BUSY
)) {
827 if (unlikely(time_after(jiffies
, end_time
))) {
828 dev_err(host
->dev
, "PMECC: Timeout to get ECC value.\n");
834 for (i
= 0; i
< host
->pmecc_sector_number
; i
++) {
835 for (j
= 0; j
< host
->pmecc_bytes_per_sector
; j
++) {
838 pos
= i
* host
->pmecc_bytes_per_sector
+ j
;
839 chip
->oob_poi
[eccpos
[pos
]] =
840 pmecc_readb_ecc_relaxed(host
->ecc
, i
, j
);
843 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
848 static void atmel_pmecc_core_init(struct mtd_info
*mtd
)
850 struct nand_chip
*nand_chip
= mtd
->priv
;
851 struct atmel_nand_host
*host
= nand_chip
->priv
;
853 struct nand_ecclayout
*ecc_layout
;
855 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_RST
);
856 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
858 switch (host
->pmecc_corr_cap
) {
860 val
= PMECC_CFG_BCH_ERR2
;
863 val
= PMECC_CFG_BCH_ERR4
;
866 val
= PMECC_CFG_BCH_ERR8
;
869 val
= PMECC_CFG_BCH_ERR12
;
872 val
= PMECC_CFG_BCH_ERR24
;
876 if (host
->pmecc_sector_size
== 512)
877 val
|= PMECC_CFG_SECTOR512
;
878 else if (host
->pmecc_sector_size
== 1024)
879 val
|= PMECC_CFG_SECTOR1024
;
881 switch (host
->pmecc_sector_number
) {
883 val
|= PMECC_CFG_PAGE_1SECTOR
;
886 val
|= PMECC_CFG_PAGE_2SECTORS
;
889 val
|= PMECC_CFG_PAGE_4SECTORS
;
892 val
|= PMECC_CFG_PAGE_8SECTORS
;
896 val
|= (PMECC_CFG_READ_OP
| PMECC_CFG_SPARE_DISABLE
897 | PMECC_CFG_AUTO_DISABLE
);
898 pmecc_writel(host
->ecc
, CFG
, val
);
900 ecc_layout
= nand_chip
->ecc
.layout
;
901 pmecc_writel(host
->ecc
, SAREA
, mtd
->oobsize
- 1);
902 pmecc_writel(host
->ecc
, SADDR
, ecc_layout
->eccpos
[0]);
903 pmecc_writel(host
->ecc
, EADDR
,
904 ecc_layout
->eccpos
[ecc_layout
->eccbytes
- 1]);
905 /* See datasheet about PMECC Clock Control Register */
906 pmecc_writel(host
->ecc
, CLK
, 2);
907 pmecc_writel(host
->ecc
, IDR
, 0xff);
908 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_ENABLE
);
911 static int __init
atmel_pmecc_nand_init_params(struct platform_device
*pdev
,
912 struct atmel_nand_host
*host
)
914 struct mtd_info
*mtd
= &host
->mtd
;
915 struct nand_chip
*nand_chip
= &host
->nand_chip
;
916 struct resource
*regs
, *regs_pmerr
, *regs_rom
;
917 int cap
, sector_size
, err_no
;
919 cap
= host
->pmecc_corr_cap
;
920 sector_size
= host
->pmecc_sector_size
;
921 dev_info(host
->dev
, "Initialize PMECC params, cap: %d, sector: %d\n",
924 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
927 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
928 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
932 host
->ecc
= ioremap(regs
->start
, resource_size(regs
));
933 if (host
->ecc
== NULL
) {
934 dev_err(host
->dev
, "ioremap failed\n");
936 goto err_pmecc_ioremap
;
939 regs_pmerr
= platform_get_resource(pdev
, IORESOURCE_MEM
, 2);
940 regs_rom
= platform_get_resource(pdev
, IORESOURCE_MEM
, 3);
941 if (regs_pmerr
&& regs_rom
) {
942 host
->pmerrloc_base
= ioremap(regs_pmerr
->start
,
943 resource_size(regs_pmerr
));
944 host
->pmecc_rom_base
= ioremap(regs_rom
->start
,
945 resource_size(regs_rom
));
948 if (!host
->pmerrloc_base
|| !host
->pmecc_rom_base
) {
950 "Can not get I/O resource for PMECC ERRLOC controller or ROM!\n");
952 goto err_pmloc_ioremap
;
955 /* ECC is calculated for the whole page (1 step) */
956 nand_chip
->ecc
.size
= mtd
->writesize
;
958 /* set ECC page size and oob layout */
959 switch (mtd
->writesize
) {
961 host
->pmecc_degree
= PMECC_GF_DIMENSION_13
;
962 host
->pmecc_cw_len
= (1 << host
->pmecc_degree
) - 1;
963 host
->pmecc_sector_number
= mtd
->writesize
/ sector_size
;
964 host
->pmecc_bytes_per_sector
= pmecc_get_ecc_bytes(
966 host
->pmecc_alpha_to
= pmecc_get_alpha_to(host
);
967 host
->pmecc_index_of
= host
->pmecc_rom_base
+
968 host
->pmecc_lookup_table_offset
;
970 nand_chip
->ecc
.steps
= 1;
971 nand_chip
->ecc
.strength
= cap
;
972 nand_chip
->ecc
.bytes
= host
->pmecc_bytes_per_sector
*
973 host
->pmecc_sector_number
;
974 if (nand_chip
->ecc
.bytes
> mtd
->oobsize
- 2) {
975 dev_err(host
->dev
, "No room for ECC bytes\n");
977 goto err_no_ecc_room
;
979 pmecc_config_ecc_layout(&atmel_pmecc_oobinfo
,
981 nand_chip
->ecc
.bytes
);
982 nand_chip
->ecc
.layout
= &atmel_pmecc_oobinfo
;
989 "Unsupported page size for PMECC, use Software ECC\n");
991 /* page size not handled by HW ECC */
992 /* switching back to soft ECC */
993 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
997 /* Allocate data for PMECC computation */
998 err_no
= pmecc_data_alloc(host
);
1001 "Cannot allocate memory for PMECC computation!\n");
1002 goto err_pmecc_data_alloc
;
1005 nand_chip
->ecc
.read_page
= atmel_nand_pmecc_read_page
;
1006 nand_chip
->ecc
.write_page
= atmel_nand_pmecc_write_page
;
1008 atmel_pmecc_core_init(mtd
);
1012 err_pmecc_data_alloc
:
1016 if (host
->pmerrloc_base
)
1017 iounmap(host
->pmerrloc_base
);
1018 if (host
->pmecc_rom_base
)
1019 iounmap(host
->pmecc_rom_base
);
1027 * function called after a write
1029 * mtd: MTD block structure
1030 * dat: raw data (unused)
1031 * ecc_code: buffer for ECC
1033 static int atmel_nand_calculate(struct mtd_info
*mtd
,
1034 const u_char
*dat
, unsigned char *ecc_code
)
1036 struct nand_chip
*nand_chip
= mtd
->priv
;
1037 struct atmel_nand_host
*host
= nand_chip
->priv
;
1038 unsigned int ecc_value
;
1040 /* get the first 2 ECC bytes */
1041 ecc_value
= ecc_readl(host
->ecc
, PR
);
1043 ecc_code
[0] = ecc_value
& 0xFF;
1044 ecc_code
[1] = (ecc_value
>> 8) & 0xFF;
1046 /* get the last 2 ECC bytes */
1047 ecc_value
= ecc_readl(host
->ecc
, NPR
) & ATMEL_ECC_NPARITY
;
1049 ecc_code
[2] = ecc_value
& 0xFF;
1050 ecc_code
[3] = (ecc_value
>> 8) & 0xFF;
1056 * HW ECC read page function
1058 * mtd: mtd info structure
1059 * chip: nand chip info structure
1060 * buf: buffer to store read data
1061 * oob_required: caller expects OOB data read to chip->oob_poi
1063 static int atmel_nand_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1064 uint8_t *buf
, int oob_required
, int page
)
1066 int eccsize
= chip
->ecc
.size
;
1067 int eccbytes
= chip
->ecc
.bytes
;
1068 uint32_t *eccpos
= chip
->ecc
.layout
->eccpos
;
1070 uint8_t *oob
= chip
->oob_poi
;
1073 unsigned int max_bitflips
= 0;
1076 * Errata: ALE is incorrectly wired up to the ECC controller
1077 * on the AP7000, so it will include the address cycles in the
1080 * Workaround: Reset the parity registers before reading the
1083 if (cpu_is_at32ap7000()) {
1084 struct atmel_nand_host
*host
= chip
->priv
;
1085 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1089 chip
->read_buf(mtd
, p
, eccsize
);
1091 /* move to ECC position if needed */
1092 if (eccpos
[0] != 0) {
1093 /* This only works on large pages
1094 * because the ECC controller waits for
1095 * NAND_CMD_RNDOUTSTART after the
1097 * anyway, for small pages, the eccpos[0] == 0
1099 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
,
1100 mtd
->writesize
+ eccpos
[0], -1);
1103 /* the ECC controller needs to read the ECC just after the data */
1104 ecc_pos
= oob
+ eccpos
[0];
1105 chip
->read_buf(mtd
, ecc_pos
, eccbytes
);
1107 /* check if there's an error */
1108 stat
= chip
->ecc
.correct(mtd
, p
, oob
, NULL
);
1111 mtd
->ecc_stats
.failed
++;
1113 mtd
->ecc_stats
.corrected
+= stat
;
1114 max_bitflips
= max_t(unsigned int, max_bitflips
, stat
);
1117 /* get back to oob start (end of page) */
1118 chip
->cmdfunc(mtd
, NAND_CMD_RNDOUT
, mtd
->writesize
, -1);
1121 chip
->read_buf(mtd
, oob
, mtd
->oobsize
);
1123 return max_bitflips
;
1129 * function called after a read
1131 * mtd: MTD block structure
1132 * dat: raw data read from the chip
1133 * read_ecc: ECC from the chip (unused)
1136 * Detect and correct a 1 bit error for a page
1138 static int atmel_nand_correct(struct mtd_info
*mtd
, u_char
*dat
,
1139 u_char
*read_ecc
, u_char
*isnull
)
1141 struct nand_chip
*nand_chip
= mtd
->priv
;
1142 struct atmel_nand_host
*host
= nand_chip
->priv
;
1143 unsigned int ecc_status
;
1144 unsigned int ecc_word
, ecc_bit
;
1146 /* get the status from the Status Register */
1147 ecc_status
= ecc_readl(host
->ecc
, SR
);
1149 /* if there's no error */
1150 if (likely(!(ecc_status
& ATMEL_ECC_RECERR
)))
1153 /* get error bit offset (4 bits) */
1154 ecc_bit
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_BITADDR
;
1155 /* get word address (12 bits) */
1156 ecc_word
= ecc_readl(host
->ecc
, PR
) & ATMEL_ECC_WORDADDR
;
1159 /* if there are multiple errors */
1160 if (ecc_status
& ATMEL_ECC_MULERR
) {
1161 /* check if it is a freshly erased block
1162 * (filled with 0xff) */
1163 if ((ecc_bit
== ATMEL_ECC_BITADDR
)
1164 && (ecc_word
== (ATMEL_ECC_WORDADDR
>> 4))) {
1165 /* the block has just been erased, return OK */
1168 /* it doesn't seems to be a freshly
1170 * We can't correct so many errors */
1171 dev_dbg(host
->dev
, "atmel_nand : multiple errors detected."
1172 " Unable to correct.\n");
1176 /* if there's a single bit error : we can correct it */
1177 if (ecc_status
& ATMEL_ECC_ECCERR
) {
1178 /* there's nothing much to do here.
1179 * the bit error is on the ECC itself.
1181 dev_dbg(host
->dev
, "atmel_nand : one bit error on ECC code."
1182 " Nothing to correct\n");
1186 dev_dbg(host
->dev
, "atmel_nand : one bit error on data."
1187 " (word offset in the page :"
1188 " 0x%x bit offset : 0x%x)\n",
1190 /* correct the error */
1191 if (nand_chip
->options
& NAND_BUSWIDTH_16
) {
1193 ((unsigned short *) dat
)[ecc_word
] ^= (1 << ecc_bit
);
1196 dat
[ecc_word
] ^= (1 << ecc_bit
);
1198 dev_dbg(host
->dev
, "atmel_nand : error corrected\n");
1203 * Enable HW ECC : unused on most chips
1205 static void atmel_nand_hwctl(struct mtd_info
*mtd
, int mode
)
1207 if (cpu_is_at32ap7000()) {
1208 struct nand_chip
*nand_chip
= mtd
->priv
;
1209 struct atmel_nand_host
*host
= nand_chip
->priv
;
1210 ecc_writel(host
->ecc
, CR
, ATMEL_ECC_RST
);
1214 #if defined(CONFIG_OF)
1215 static int atmel_of_init_port(struct atmel_nand_host
*host
,
1216 struct device_node
*np
)
1218 u32 val
, table_offset
;
1221 struct atmel_nand_data
*board
= &host
->board
;
1222 enum of_gpio_flags flags
;
1224 if (of_property_read_u32(np
, "atmel,nand-addr-offset", &val
) == 0) {
1226 dev_err(host
->dev
, "invalid addr-offset %u\n", val
);
1232 if (of_property_read_u32(np
, "atmel,nand-cmd-offset", &val
) == 0) {
1234 dev_err(host
->dev
, "invalid cmd-offset %u\n", val
);
1240 ecc_mode
= of_get_nand_ecc_mode(np
);
1242 board
->ecc_mode
= ecc_mode
< 0 ? NAND_ECC_SOFT
: ecc_mode
;
1244 board
->on_flash_bbt
= of_get_nand_on_flash_bbt(np
);
1246 if (of_get_nand_bus_width(np
) == 16)
1247 board
->bus_width_16
= 1;
1249 board
->rdy_pin
= of_get_gpio_flags(np
, 0, &flags
);
1250 board
->rdy_pin_active_low
= (flags
== OF_GPIO_ACTIVE_LOW
);
1252 board
->enable_pin
= of_get_gpio(np
, 1);
1253 board
->det_pin
= of_get_gpio(np
, 2);
1255 host
->has_pmecc
= of_property_read_bool(np
, "atmel,has-pmecc");
1257 if (!(board
->ecc_mode
== NAND_ECC_HW
) || !host
->has_pmecc
)
1258 return 0; /* Not using PMECC */
1260 /* use PMECC, get correction capability, sector size and lookup
1263 if (of_property_read_u32(np
, "atmel,pmecc-cap", &val
) != 0) {
1264 dev_err(host
->dev
, "Cannot decide PMECC Capability\n");
1266 } else if ((val
!= 2) && (val
!= 4) && (val
!= 8) && (val
!= 12) &&
1269 "Unsupported PMECC correction capability: %d; should be 2, 4, 8, 12 or 24\n",
1273 host
->pmecc_corr_cap
= (u8
)val
;
1275 if (of_property_read_u32(np
, "atmel,pmecc-sector-size", &val
) != 0) {
1276 dev_err(host
->dev
, "Cannot decide PMECC Sector Size\n");
1278 } else if ((val
!= 512) && (val
!= 1024)) {
1280 "Unsupported PMECC sector size: %d; should be 512 or 1024 bytes\n",
1284 host
->pmecc_sector_size
= (u16
)val
;
1286 if (of_property_read_u32_array(np
, "atmel,pmecc-lookup-table-offset",
1288 dev_err(host
->dev
, "Cannot get PMECC lookup table offset\n");
1291 table_offset
= host
->pmecc_sector_size
== 512 ? offset
[0] : offset
[1];
1293 if (!table_offset
) {
1294 dev_err(host
->dev
, "Invalid PMECC lookup table offset\n");
1297 host
->pmecc_lookup_table_offset
= table_offset
;
1302 static int atmel_of_init_port(struct atmel_nand_host
*host
,
1303 struct device_node
*np
)
1309 static int __init
atmel_hw_nand_init_params(struct platform_device
*pdev
,
1310 struct atmel_nand_host
*host
)
1312 struct mtd_info
*mtd
= &host
->mtd
;
1313 struct nand_chip
*nand_chip
= &host
->nand_chip
;
1314 struct resource
*regs
;
1316 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1319 "Can't get I/O resource regs, use software ECC\n");
1320 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1324 host
->ecc
= ioremap(regs
->start
, resource_size(regs
));
1325 if (host
->ecc
== NULL
) {
1326 dev_err(host
->dev
, "ioremap failed\n");
1330 /* ECC is calculated for the whole page (1 step) */
1331 nand_chip
->ecc
.size
= mtd
->writesize
;
1333 /* set ECC page size and oob layout */
1334 switch (mtd
->writesize
) {
1336 nand_chip
->ecc
.layout
= &atmel_oobinfo_small
;
1337 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_528
);
1340 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1341 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_1056
);
1344 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1345 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_2112
);
1348 nand_chip
->ecc
.layout
= &atmel_oobinfo_large
;
1349 ecc_writel(host
->ecc
, MR
, ATMEL_ECC_PAGESIZE_4224
);
1352 /* page size not handled by HW ECC */
1353 /* switching back to soft ECC */
1354 nand_chip
->ecc
.mode
= NAND_ECC_SOFT
;
1358 /* set up for HW ECC */
1359 nand_chip
->ecc
.calculate
= atmel_nand_calculate
;
1360 nand_chip
->ecc
.correct
= atmel_nand_correct
;
1361 nand_chip
->ecc
.hwctl
= atmel_nand_hwctl
;
1362 nand_chip
->ecc
.read_page
= atmel_nand_read_page
;
1363 nand_chip
->ecc
.bytes
= 4;
1364 nand_chip
->ecc
.strength
= 1;
1370 * Probe for the NAND device.
1372 static int __init
atmel_nand_probe(struct platform_device
*pdev
)
1374 struct atmel_nand_host
*host
;
1375 struct mtd_info
*mtd
;
1376 struct nand_chip
*nand_chip
;
1377 struct resource
*mem
;
1378 struct mtd_part_parser_data ppdata
= {};
1380 struct pinctrl
*pinctrl
;
1382 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1384 printk(KERN_ERR
"atmel_nand: can't get I/O resource mem\n");
1388 /* Allocate memory for the device structure (and zero it) */
1389 host
= kzalloc(sizeof(struct atmel_nand_host
), GFP_KERNEL
);
1391 printk(KERN_ERR
"atmel_nand: failed to allocate device structure.\n");
1395 host
->io_phys
= (dma_addr_t
)mem
->start
;
1397 host
->io_base
= ioremap(mem
->start
, resource_size(mem
));
1398 if (host
->io_base
== NULL
) {
1399 printk(KERN_ERR
"atmel_nand: ioremap failed\n");
1401 goto err_nand_ioremap
;
1405 nand_chip
= &host
->nand_chip
;
1406 host
->dev
= &pdev
->dev
;
1407 if (pdev
->dev
.of_node
) {
1408 res
= atmel_of_init_port(host
, pdev
->dev
.of_node
);
1410 goto err_ecc_ioremap
;
1412 memcpy(&host
->board
, pdev
->dev
.platform_data
,
1413 sizeof(struct atmel_nand_data
));
1416 nand_chip
->priv
= host
; /* link the private data structures */
1417 mtd
->priv
= nand_chip
;
1418 mtd
->owner
= THIS_MODULE
;
1420 /* Set address of NAND IO lines */
1421 nand_chip
->IO_ADDR_R
= host
->io_base
;
1422 nand_chip
->IO_ADDR_W
= host
->io_base
;
1423 nand_chip
->cmd_ctrl
= atmel_nand_cmd_ctrl
;
1425 pinctrl
= devm_pinctrl_get_select_default(&pdev
->dev
);
1426 if (IS_ERR(pinctrl
)) {
1427 dev_err(host
->dev
, "Failed to request pinctrl\n");
1428 res
= PTR_ERR(pinctrl
);
1429 goto err_ecc_ioremap
;
1432 if (gpio_is_valid(host
->board
.rdy_pin
)) {
1433 res
= gpio_request(host
->board
.rdy_pin
, "nand_rdy");
1436 "can't request rdy gpio %d\n",
1437 host
->board
.rdy_pin
);
1438 goto err_ecc_ioremap
;
1441 res
= gpio_direction_input(host
->board
.rdy_pin
);
1444 "can't request input direction rdy gpio %d\n",
1445 host
->board
.rdy_pin
);
1446 goto err_ecc_ioremap
;
1449 nand_chip
->dev_ready
= atmel_nand_device_ready
;
1452 if (gpio_is_valid(host
->board
.enable_pin
)) {
1453 res
= gpio_request(host
->board
.enable_pin
, "nand_enable");
1456 "can't request enable gpio %d\n",
1457 host
->board
.enable_pin
);
1458 goto err_ecc_ioremap
;
1461 res
= gpio_direction_output(host
->board
.enable_pin
, 1);
1464 "can't request output direction enable gpio %d\n",
1465 host
->board
.enable_pin
);
1466 goto err_ecc_ioremap
;
1470 nand_chip
->ecc
.mode
= host
->board
.ecc_mode
;
1471 nand_chip
->chip_delay
= 20; /* 20us command delay time */
1473 if (host
->board
.bus_width_16
) /* 16-bit bus width */
1474 nand_chip
->options
|= NAND_BUSWIDTH_16
;
1476 nand_chip
->read_buf
= atmel_read_buf
;
1477 nand_chip
->write_buf
= atmel_write_buf
;
1479 platform_set_drvdata(pdev
, host
);
1480 atmel_nand_enable(host
);
1482 if (gpio_is_valid(host
->board
.det_pin
)) {
1483 res
= gpio_request(host
->board
.det_pin
, "nand_det");
1486 "can't request det gpio %d\n",
1487 host
->board
.det_pin
);
1491 res
= gpio_direction_input(host
->board
.det_pin
);
1494 "can't request input direction det gpio %d\n",
1495 host
->board
.det_pin
);
1499 if (gpio_get_value(host
->board
.det_pin
)) {
1500 printk(KERN_INFO
"No SmartMedia card inserted.\n");
1506 if (host
->board
.on_flash_bbt
|| on_flash_bbt
) {
1507 printk(KERN_INFO
"atmel_nand: Use On Flash BBT\n");
1508 nand_chip
->bbt_options
|= NAND_BBT_USE_FLASH
;
1515 dma_cap_mask_t mask
;
1518 dma_cap_set(DMA_MEMCPY
, mask
);
1519 host
->dma_chan
= dma_request_channel(mask
, NULL
, NULL
);
1520 if (!host
->dma_chan
) {
1521 dev_err(host
->dev
, "Failed to request DMA channel\n");
1526 dev_info(host
->dev
, "Using %s for DMA transfers.\n",
1527 dma_chan_name(host
->dma_chan
));
1529 dev_info(host
->dev
, "No DMA support for NAND access.\n");
1531 /* first scan to find the device and get the page size */
1532 if (nand_scan_ident(mtd
, 1, NULL
)) {
1534 goto err_scan_ident
;
1537 if (nand_chip
->ecc
.mode
== NAND_ECC_HW
) {
1538 if (host
->has_pmecc
)
1539 res
= atmel_pmecc_nand_init_params(pdev
, host
);
1541 res
= atmel_hw_nand_init_params(pdev
, host
);
1547 /* second phase scan */
1548 if (nand_scan_tail(mtd
)) {
1553 mtd
->name
= "atmel_nand";
1554 ppdata
.of_node
= pdev
->dev
.of_node
;
1555 res
= mtd_device_parse_register(mtd
, NULL
, &ppdata
,
1556 host
->board
.parts
, host
->board
.num_parts
);
1561 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
) {
1562 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
1563 pmecc_data_free(host
);
1567 if (host
->pmerrloc_base
)
1568 iounmap(host
->pmerrloc_base
);
1569 if (host
->pmecc_rom_base
)
1570 iounmap(host
->pmecc_rom_base
);
1574 atmel_nand_disable(host
);
1575 platform_set_drvdata(pdev
, NULL
);
1577 dma_release_channel(host
->dma_chan
);
1579 iounmap(host
->io_base
);
1586 * Remove a NAND device.
1588 static int __exit
atmel_nand_remove(struct platform_device
*pdev
)
1590 struct atmel_nand_host
*host
= platform_get_drvdata(pdev
);
1591 struct mtd_info
*mtd
= &host
->mtd
;
1595 atmel_nand_disable(host
);
1597 if (host
->has_pmecc
&& host
->nand_chip
.ecc
.mode
== NAND_ECC_HW
) {
1598 pmecc_writel(host
->ecc
, CTRL
, PMECC_CTRL_DISABLE
);
1599 pmerrloc_writel(host
->pmerrloc_base
, ELDIS
,
1601 pmecc_data_free(host
);
1604 if (gpio_is_valid(host
->board
.det_pin
))
1605 gpio_free(host
->board
.det_pin
);
1607 if (gpio_is_valid(host
->board
.enable_pin
))
1608 gpio_free(host
->board
.enable_pin
);
1610 if (gpio_is_valid(host
->board
.rdy_pin
))
1611 gpio_free(host
->board
.rdy_pin
);
1615 if (host
->pmecc_rom_base
)
1616 iounmap(host
->pmecc_rom_base
);
1617 if (host
->pmerrloc_base
)
1618 iounmap(host
->pmerrloc_base
);
1621 dma_release_channel(host
->dma_chan
);
1623 iounmap(host
->io_base
);
1629 #if defined(CONFIG_OF)
1630 static const struct of_device_id atmel_nand_dt_ids
[] = {
1631 { .compatible
= "atmel,at91rm9200-nand" },
1635 MODULE_DEVICE_TABLE(of
, atmel_nand_dt_ids
);
1638 static struct platform_driver atmel_nand_driver
= {
1639 .remove
= __exit_p(atmel_nand_remove
),
1641 .name
= "atmel_nand",
1642 .owner
= THIS_MODULE
,
1643 .of_match_table
= of_match_ptr(atmel_nand_dt_ids
),
1647 static int __init
atmel_nand_init(void)
1649 return platform_driver_probe(&atmel_nand_driver
, atmel_nand_probe
);
1653 static void __exit
atmel_nand_exit(void)
1655 platform_driver_unregister(&atmel_nand_driver
);
1659 module_init(atmel_nand_init
);
1660 module_exit(atmel_nand_exit
);
1662 MODULE_LICENSE("GPL");
1663 MODULE_AUTHOR("Rick Bronson");
1664 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
1665 MODULE_ALIAS("platform:atmel_nand");