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Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
[deliverable/linux.git] / drivers / mtd / nand / atmel_nand.c
1 /*
2 * Copyright © 2003 Rick Bronson
3 *
4 * Derived from drivers/mtd/nand/autcpu12.c
5 * Copyright © 2001 Thomas Gleixner (gleixner@autronix.de)
6 *
7 * Derived from drivers/mtd/spia.c
8 * Copyright © 2000 Steven J. Hill (sjhill@cotw.com)
9 *
10 *
11 * Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
12 * Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright © 2007
13 *
14 * Derived from Das U-Boot source code
15 * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
16 * © Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
17 *
18 * Add Programmable Multibit ECC support for various AT91 SoC
19 * © Copyright 2012 ATMEL, Hong Xu
20 *
21 * Add Nand Flash Controller support for SAMA5 SoC
22 * © Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
23 *
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License version 2 as
26 * published by the Free Software Foundation.
27 *
28 */
29
30 #include <linux/clk.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/slab.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/platform_device.h>
36 #include <linux/of.h>
37 #include <linux/of_device.h>
38 #include <linux/of_gpio.h>
39 #include <linux/mtd/mtd.h>
40 #include <linux/mtd/nand.h>
41 #include <linux/mtd/partitions.h>
42
43 #include <linux/delay.h>
44 #include <linux/dmaengine.h>
45 #include <linux/gpio.h>
46 #include <linux/interrupt.h>
47 #include <linux/io.h>
48 #include <linux/platform_data/atmel.h>
49
50 static int use_dma = 1;
51 module_param(use_dma, int, 0);
52
53 static int on_flash_bbt = 0;
54 module_param(on_flash_bbt, int, 0);
55
56 /* Register access macros */
57 #define ecc_readl(add, reg) \
58 __raw_readl(add + ATMEL_ECC_##reg)
59 #define ecc_writel(add, reg, value) \
60 __raw_writel((value), add + ATMEL_ECC_##reg)
61
62 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
63 #include "atmel_nand_nfc.h" /* Nand Flash Controller definition */
64
65 struct atmel_nand_caps {
66 bool pmecc_correct_erase_page;
67 uint8_t pmecc_max_correction;
68 };
69
70 struct atmel_nand_nfc_caps {
71 uint32_t rb_mask;
72 };
73
74 /*
75 * oob layout for large page size
76 * bad block info is on bytes 0 and 1
77 * the bytes have to be consecutives to avoid
78 * several NAND_CMD_RNDOUT during read
79 *
80 * oob layout for small page size
81 * bad block info is on bytes 4 and 5
82 * the bytes have to be consecutives to avoid
83 * several NAND_CMD_RNDOUT during read
84 */
85 static int atmel_ooblayout_ecc_sp(struct mtd_info *mtd, int section,
86 struct mtd_oob_region *oobregion)
87 {
88 if (section)
89 return -ERANGE;
90
91 oobregion->length = 4;
92 oobregion->offset = 0;
93
94 return 0;
95 }
96
97 static int atmel_ooblayout_free_sp(struct mtd_info *mtd, int section,
98 struct mtd_oob_region *oobregion)
99 {
100 if (section)
101 return -ERANGE;
102
103 oobregion->offset = 6;
104 oobregion->length = mtd->oobsize - oobregion->offset;
105
106 return 0;
107 }
108
109 static const struct mtd_ooblayout_ops atmel_ooblayout_sp_ops = {
110 .ecc = atmel_ooblayout_ecc_sp,
111 .free = atmel_ooblayout_free_sp,
112 };
113
114 struct atmel_nfc {
115 void __iomem *base_cmd_regs;
116 void __iomem *hsmc_regs;
117 void *sram_bank0;
118 dma_addr_t sram_bank0_phys;
119 bool use_nfc_sram;
120 bool write_by_sram;
121
122 struct clk *clk;
123
124 bool is_initialized;
125 struct completion comp_ready;
126 struct completion comp_cmd_done;
127 struct completion comp_xfer_done;
128
129 /* Point to the sram bank which include readed data via NFC */
130 void *data_in_sram;
131 bool will_write_sram;
132 const struct atmel_nand_nfc_caps *caps;
133 };
134 static struct atmel_nfc nand_nfc;
135
136 struct atmel_nand_host {
137 struct nand_chip nand_chip;
138 void __iomem *io_base;
139 dma_addr_t io_phys;
140 struct atmel_nand_data board;
141 struct device *dev;
142 void __iomem *ecc;
143
144 struct completion comp;
145 struct dma_chan *dma_chan;
146
147 struct atmel_nfc *nfc;
148
149 const struct atmel_nand_caps *caps;
150 bool has_pmecc;
151 u8 pmecc_corr_cap;
152 u16 pmecc_sector_size;
153 bool has_no_lookup_table;
154 u32 pmecc_lookup_table_offset;
155 u32 pmecc_lookup_table_offset_512;
156 u32 pmecc_lookup_table_offset_1024;
157
158 int pmecc_degree; /* Degree of remainders */
159 int pmecc_cw_len; /* Length of codeword */
160
161 void __iomem *pmerrloc_base;
162 void __iomem *pmerrloc_el_base;
163 void __iomem *pmecc_rom_base;
164
165 /* lookup table for alpha_to and index_of */
166 void __iomem *pmecc_alpha_to;
167 void __iomem *pmecc_index_of;
168
169 /* data for pmecc computation */
170 int16_t *pmecc_partial_syn;
171 int16_t *pmecc_si;
172 int16_t *pmecc_smu; /* Sigma table */
173 int16_t *pmecc_lmu; /* polynomal order */
174 int *pmecc_mu;
175 int *pmecc_dmu;
176 int *pmecc_delta;
177 };
178
179 /*
180 * Enable NAND.
181 */
182 static void atmel_nand_enable(struct atmel_nand_host *host)
183 {
184 if (gpio_is_valid(host->board.enable_pin))
185 gpio_set_value(host->board.enable_pin, 0);
186 }
187
188 /*
189 * Disable NAND.
190 */
191 static void atmel_nand_disable(struct atmel_nand_host *host)
192 {
193 if (gpio_is_valid(host->board.enable_pin))
194 gpio_set_value(host->board.enable_pin, 1);
195 }
196
197 /*
198 * Hardware specific access to control-lines
199 */
200 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
201 {
202 struct nand_chip *nand_chip = mtd_to_nand(mtd);
203 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
204
205 if (ctrl & NAND_CTRL_CHANGE) {
206 if (ctrl & NAND_NCE)
207 atmel_nand_enable(host);
208 else
209 atmel_nand_disable(host);
210 }
211 if (cmd == NAND_CMD_NONE)
212 return;
213
214 if (ctrl & NAND_CLE)
215 writeb(cmd, host->io_base + (1 << host->board.cle));
216 else
217 writeb(cmd, host->io_base + (1 << host->board.ale));
218 }
219
220 /*
221 * Read the Device Ready pin.
222 */
223 static int atmel_nand_device_ready(struct mtd_info *mtd)
224 {
225 struct nand_chip *nand_chip = mtd_to_nand(mtd);
226 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
227
228 return gpio_get_value(host->board.rdy_pin) ^
229 !!host->board.rdy_pin_active_low;
230 }
231
232 /* Set up for hardware ready pin and enable pin. */
233 static int atmel_nand_set_enable_ready_pins(struct mtd_info *mtd)
234 {
235 struct nand_chip *chip = mtd_to_nand(mtd);
236 struct atmel_nand_host *host = nand_get_controller_data(chip);
237 int res = 0;
238
239 if (gpio_is_valid(host->board.rdy_pin)) {
240 res = devm_gpio_request(host->dev,
241 host->board.rdy_pin, "nand_rdy");
242 if (res < 0) {
243 dev_err(host->dev,
244 "can't request rdy gpio %d\n",
245 host->board.rdy_pin);
246 return res;
247 }
248
249 res = gpio_direction_input(host->board.rdy_pin);
250 if (res < 0) {
251 dev_err(host->dev,
252 "can't request input direction rdy gpio %d\n",
253 host->board.rdy_pin);
254 return res;
255 }
256
257 chip->dev_ready = atmel_nand_device_ready;
258 }
259
260 if (gpio_is_valid(host->board.enable_pin)) {
261 res = devm_gpio_request(host->dev,
262 host->board.enable_pin, "nand_enable");
263 if (res < 0) {
264 dev_err(host->dev,
265 "can't request enable gpio %d\n",
266 host->board.enable_pin);
267 return res;
268 }
269
270 res = gpio_direction_output(host->board.enable_pin, 1);
271 if (res < 0) {
272 dev_err(host->dev,
273 "can't request output direction enable gpio %d\n",
274 host->board.enable_pin);
275 return res;
276 }
277 }
278
279 return res;
280 }
281
282 /*
283 * Minimal-overhead PIO for data access.
284 */
285 static void atmel_read_buf8(struct mtd_info *mtd, u8 *buf, int len)
286 {
287 struct nand_chip *nand_chip = mtd_to_nand(mtd);
288 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
289
290 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
291 memcpy(buf, host->nfc->data_in_sram, len);
292 host->nfc->data_in_sram += len;
293 } else {
294 __raw_readsb(nand_chip->IO_ADDR_R, buf, len);
295 }
296 }
297
298 static void atmel_read_buf16(struct mtd_info *mtd, u8 *buf, int len)
299 {
300 struct nand_chip *nand_chip = mtd_to_nand(mtd);
301 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
302
303 if (host->nfc && host->nfc->use_nfc_sram && host->nfc->data_in_sram) {
304 memcpy(buf, host->nfc->data_in_sram, len);
305 host->nfc->data_in_sram += len;
306 } else {
307 __raw_readsw(nand_chip->IO_ADDR_R, buf, len / 2);
308 }
309 }
310
311 static void atmel_write_buf8(struct mtd_info *mtd, const u8 *buf, int len)
312 {
313 struct nand_chip *nand_chip = mtd_to_nand(mtd);
314
315 __raw_writesb(nand_chip->IO_ADDR_W, buf, len);
316 }
317
318 static void atmel_write_buf16(struct mtd_info *mtd, const u8 *buf, int len)
319 {
320 struct nand_chip *nand_chip = mtd_to_nand(mtd);
321
322 __raw_writesw(nand_chip->IO_ADDR_W, buf, len / 2);
323 }
324
325 static void dma_complete_func(void *completion)
326 {
327 complete(completion);
328 }
329
330 static int nfc_set_sram_bank(struct atmel_nand_host *host, unsigned int bank)
331 {
332 /* NFC only has two banks. Must be 0 or 1 */
333 if (bank > 1)
334 return -EINVAL;
335
336 if (bank) {
337 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
338
339 /* Only for a 2k-page or lower flash, NFC can handle 2 banks */
340 if (mtd->writesize > 2048)
341 return -EINVAL;
342 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK1);
343 } else {
344 nfc_writel(host->nfc->hsmc_regs, BANK, ATMEL_HSMC_NFC_BANK0);
345 }
346
347 return 0;
348 }
349
350 static uint nfc_get_sram_off(struct atmel_nand_host *host)
351 {
352 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
353 return NFC_SRAM_BANK1_OFFSET;
354 else
355 return 0;
356 }
357
358 static dma_addr_t nfc_sram_phys(struct atmel_nand_host *host)
359 {
360 if (nfc_readl(host->nfc->hsmc_regs, BANK) & ATMEL_HSMC_NFC_BANK1)
361 return host->nfc->sram_bank0_phys + NFC_SRAM_BANK1_OFFSET;
362 else
363 return host->nfc->sram_bank0_phys;
364 }
365
366 static int atmel_nand_dma_op(struct mtd_info *mtd, void *buf, int len,
367 int is_read)
368 {
369 struct dma_device *dma_dev;
370 enum dma_ctrl_flags flags;
371 dma_addr_t dma_src_addr, dma_dst_addr, phys_addr;
372 struct dma_async_tx_descriptor *tx = NULL;
373 dma_cookie_t cookie;
374 struct nand_chip *chip = mtd_to_nand(mtd);
375 struct atmel_nand_host *host = nand_get_controller_data(chip);
376 void *p = buf;
377 int err = -EIO;
378 enum dma_data_direction dir = is_read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
379 struct atmel_nfc *nfc = host->nfc;
380
381 if (buf >= high_memory)
382 goto err_buf;
383
384 dma_dev = host->dma_chan->device;
385
386 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
387
388 phys_addr = dma_map_single(dma_dev->dev, p, len, dir);
389 if (dma_mapping_error(dma_dev->dev, phys_addr)) {
390 dev_err(host->dev, "Failed to dma_map_single\n");
391 goto err_buf;
392 }
393
394 if (is_read) {
395 if (nfc && nfc->data_in_sram)
396 dma_src_addr = nfc_sram_phys(host) + (nfc->data_in_sram
397 - (nfc->sram_bank0 + nfc_get_sram_off(host)));
398 else
399 dma_src_addr = host->io_phys;
400
401 dma_dst_addr = phys_addr;
402 } else {
403 dma_src_addr = phys_addr;
404
405 if (nfc && nfc->write_by_sram)
406 dma_dst_addr = nfc_sram_phys(host);
407 else
408 dma_dst_addr = host->io_phys;
409 }
410
411 tx = dma_dev->device_prep_dma_memcpy(host->dma_chan, dma_dst_addr,
412 dma_src_addr, len, flags);
413 if (!tx) {
414 dev_err(host->dev, "Failed to prepare DMA memcpy\n");
415 goto err_dma;
416 }
417
418 init_completion(&host->comp);
419 tx->callback = dma_complete_func;
420 tx->callback_param = &host->comp;
421
422 cookie = tx->tx_submit(tx);
423 if (dma_submit_error(cookie)) {
424 dev_err(host->dev, "Failed to do DMA tx_submit\n");
425 goto err_dma;
426 }
427
428 dma_async_issue_pending(host->dma_chan);
429 wait_for_completion(&host->comp);
430
431 if (is_read && nfc && nfc->data_in_sram)
432 /* After read data from SRAM, need to increase the position */
433 nfc->data_in_sram += len;
434
435 err = 0;
436
437 err_dma:
438 dma_unmap_single(dma_dev->dev, phys_addr, len, dir);
439 err_buf:
440 if (err != 0)
441 dev_dbg(host->dev, "Fall back to CPU I/O\n");
442 return err;
443 }
444
445 static void atmel_read_buf(struct mtd_info *mtd, u8 *buf, int len)
446 {
447 struct nand_chip *chip = mtd_to_nand(mtd);
448
449 if (use_dma && len > mtd->oobsize)
450 /* only use DMA for bigger than oob size: better performances */
451 if (atmel_nand_dma_op(mtd, buf, len, 1) == 0)
452 return;
453
454 if (chip->options & NAND_BUSWIDTH_16)
455 atmel_read_buf16(mtd, buf, len);
456 else
457 atmel_read_buf8(mtd, buf, len);
458 }
459
460 static void atmel_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
461 {
462 struct nand_chip *chip = mtd_to_nand(mtd);
463
464 if (use_dma && len > mtd->oobsize)
465 /* only use DMA for bigger than oob size: better performances */
466 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) == 0)
467 return;
468
469 if (chip->options & NAND_BUSWIDTH_16)
470 atmel_write_buf16(mtd, buf, len);
471 else
472 atmel_write_buf8(mtd, buf, len);
473 }
474
475 /*
476 * Return number of ecc bytes per sector according to sector size and
477 * correction capability
478 *
479 * Following table shows what at91 PMECC supported:
480 * Correction Capability Sector_512_bytes Sector_1024_bytes
481 * ===================== ================ =================
482 * 2-bits 4-bytes 4-bytes
483 * 4-bits 7-bytes 7-bytes
484 * 8-bits 13-bytes 14-bytes
485 * 12-bits 20-bytes 21-bytes
486 * 24-bits 39-bytes 42-bytes
487 * 32-bits 52-bytes 56-bytes
488 */
489 static int pmecc_get_ecc_bytes(int cap, int sector_size)
490 {
491 int m = 12 + sector_size / 512;
492 return (m * cap + 7) / 8;
493 }
494
495 static void __iomem *pmecc_get_alpha_to(struct atmel_nand_host *host)
496 {
497 int table_size;
498
499 table_size = host->pmecc_sector_size == 512 ?
500 PMECC_LOOKUP_TABLE_SIZE_512 : PMECC_LOOKUP_TABLE_SIZE_1024;
501
502 return host->pmecc_rom_base + host->pmecc_lookup_table_offset +
503 table_size * sizeof(int16_t);
504 }
505
506 static int pmecc_data_alloc(struct atmel_nand_host *host)
507 {
508 const int cap = host->pmecc_corr_cap;
509 int size;
510
511 size = (2 * cap + 1) * sizeof(int16_t);
512 host->pmecc_partial_syn = devm_kzalloc(host->dev, size, GFP_KERNEL);
513 host->pmecc_si = devm_kzalloc(host->dev, size, GFP_KERNEL);
514 host->pmecc_lmu = devm_kzalloc(host->dev,
515 (cap + 1) * sizeof(int16_t), GFP_KERNEL);
516 host->pmecc_smu = devm_kzalloc(host->dev,
517 (cap + 2) * size, GFP_KERNEL);
518
519 size = (cap + 1) * sizeof(int);
520 host->pmecc_mu = devm_kzalloc(host->dev, size, GFP_KERNEL);
521 host->pmecc_dmu = devm_kzalloc(host->dev, size, GFP_KERNEL);
522 host->pmecc_delta = devm_kzalloc(host->dev, size, GFP_KERNEL);
523
524 if (!host->pmecc_partial_syn ||
525 !host->pmecc_si ||
526 !host->pmecc_lmu ||
527 !host->pmecc_smu ||
528 !host->pmecc_mu ||
529 !host->pmecc_dmu ||
530 !host->pmecc_delta)
531 return -ENOMEM;
532
533 return 0;
534 }
535
536 static void pmecc_gen_syndrome(struct mtd_info *mtd, int sector)
537 {
538 struct nand_chip *nand_chip = mtd_to_nand(mtd);
539 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
540 int i;
541 uint32_t value;
542
543 /* Fill odd syndromes */
544 for (i = 0; i < host->pmecc_corr_cap; i++) {
545 value = pmecc_readl_rem_relaxed(host->ecc, sector, i / 2);
546 if (i & 1)
547 value >>= 16;
548 value &= 0xffff;
549 host->pmecc_partial_syn[(2 * i) + 1] = (int16_t)value;
550 }
551 }
552
553 static void pmecc_substitute(struct mtd_info *mtd)
554 {
555 struct nand_chip *nand_chip = mtd_to_nand(mtd);
556 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
557 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
558 int16_t __iomem *index_of = host->pmecc_index_of;
559 int16_t *partial_syn = host->pmecc_partial_syn;
560 const int cap = host->pmecc_corr_cap;
561 int16_t *si;
562 int i, j;
563
564 /* si[] is a table that holds the current syndrome value,
565 * an element of that table belongs to the field
566 */
567 si = host->pmecc_si;
568
569 memset(&si[1], 0, sizeof(int16_t) * (2 * cap - 1));
570
571 /* Computation 2t syndromes based on S(x) */
572 /* Odd syndromes */
573 for (i = 1; i < 2 * cap; i += 2) {
574 for (j = 0; j < host->pmecc_degree; j++) {
575 if (partial_syn[i] & ((unsigned short)0x1 << j))
576 si[i] = readw_relaxed(alpha_to + i * j) ^ si[i];
577 }
578 }
579 /* Even syndrome = (Odd syndrome) ** 2 */
580 for (i = 2, j = 1; j <= cap; i = ++j << 1) {
581 if (si[j] == 0) {
582 si[i] = 0;
583 } else {
584 int16_t tmp;
585
586 tmp = readw_relaxed(index_of + si[j]);
587 tmp = (tmp * 2) % host->pmecc_cw_len;
588 si[i] = readw_relaxed(alpha_to + tmp);
589 }
590 }
591
592 return;
593 }
594
595 static void pmecc_get_sigma(struct mtd_info *mtd)
596 {
597 struct nand_chip *nand_chip = mtd_to_nand(mtd);
598 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
599
600 int16_t *lmu = host->pmecc_lmu;
601 int16_t *si = host->pmecc_si;
602 int *mu = host->pmecc_mu;
603 int *dmu = host->pmecc_dmu; /* Discrepancy */
604 int *delta = host->pmecc_delta; /* Delta order */
605 int cw_len = host->pmecc_cw_len;
606 const int16_t cap = host->pmecc_corr_cap;
607 const int num = 2 * cap + 1;
608 int16_t __iomem *index_of = host->pmecc_index_of;
609 int16_t __iomem *alpha_to = host->pmecc_alpha_to;
610 int i, j, k;
611 uint32_t dmu_0_count, tmp;
612 int16_t *smu = host->pmecc_smu;
613
614 /* index of largest delta */
615 int ro;
616 int largest;
617 int diff;
618
619 dmu_0_count = 0;
620
621 /* First Row */
622
623 /* Mu */
624 mu[0] = -1;
625
626 memset(smu, 0, sizeof(int16_t) * num);
627 smu[0] = 1;
628
629 /* discrepancy set to 1 */
630 dmu[0] = 1;
631 /* polynom order set to 0 */
632 lmu[0] = 0;
633 delta[0] = (mu[0] * 2 - lmu[0]) >> 1;
634
635 /* Second Row */
636
637 /* Mu */
638 mu[1] = 0;
639 /* Sigma(x) set to 1 */
640 memset(&smu[num], 0, sizeof(int16_t) * num);
641 smu[num] = 1;
642
643 /* discrepancy set to S1 */
644 dmu[1] = si[1];
645
646 /* polynom order set to 0 */
647 lmu[1] = 0;
648
649 delta[1] = (mu[1] * 2 - lmu[1]) >> 1;
650
651 /* Init the Sigma(x) last row */
652 memset(&smu[(cap + 1) * num], 0, sizeof(int16_t) * num);
653
654 for (i = 1; i <= cap; i++) {
655 mu[i + 1] = i << 1;
656 /* Begin Computing Sigma (Mu+1) and L(mu) */
657 /* check if discrepancy is set to 0 */
658 if (dmu[i] == 0) {
659 dmu_0_count++;
660
661 tmp = ((cap - (lmu[i] >> 1) - 1) / 2);
662 if ((cap - (lmu[i] >> 1) - 1) & 0x1)
663 tmp += 2;
664 else
665 tmp += 1;
666
667 if (dmu_0_count == tmp) {
668 for (j = 0; j <= (lmu[i] >> 1) + 1; j++)
669 smu[(cap + 1) * num + j] =
670 smu[i * num + j];
671
672 lmu[cap + 1] = lmu[i];
673 return;
674 }
675
676 /* copy polynom */
677 for (j = 0; j <= lmu[i] >> 1; j++)
678 smu[(i + 1) * num + j] = smu[i * num + j];
679
680 /* copy previous polynom order to the next */
681 lmu[i + 1] = lmu[i];
682 } else {
683 ro = 0;
684 largest = -1;
685 /* find largest delta with dmu != 0 */
686 for (j = 0; j < i; j++) {
687 if ((dmu[j]) && (delta[j] > largest)) {
688 largest = delta[j];
689 ro = j;
690 }
691 }
692
693 /* compute difference */
694 diff = (mu[i] - mu[ro]);
695
696 /* Compute degree of the new smu polynomial */
697 if ((lmu[i] >> 1) > ((lmu[ro] >> 1) + diff))
698 lmu[i + 1] = lmu[i];
699 else
700 lmu[i + 1] = ((lmu[ro] >> 1) + diff) * 2;
701
702 /* Init smu[i+1] with 0 */
703 for (k = 0; k < num; k++)
704 smu[(i + 1) * num + k] = 0;
705
706 /* Compute smu[i+1] */
707 for (k = 0; k <= lmu[ro] >> 1; k++) {
708 int16_t a, b, c;
709
710 if (!(smu[ro * num + k] && dmu[i]))
711 continue;
712 a = readw_relaxed(index_of + dmu[i]);
713 b = readw_relaxed(index_of + dmu[ro]);
714 c = readw_relaxed(index_of + smu[ro * num + k]);
715 tmp = a + (cw_len - b) + c;
716 a = readw_relaxed(alpha_to + tmp % cw_len);
717 smu[(i + 1) * num + (k + diff)] = a;
718 }
719
720 for (k = 0; k <= lmu[i] >> 1; k++)
721 smu[(i + 1) * num + k] ^= smu[i * num + k];
722 }
723
724 /* End Computing Sigma (Mu+1) and L(mu) */
725 /* In either case compute delta */
726 delta[i + 1] = (mu[i + 1] * 2 - lmu[i + 1]) >> 1;
727
728 /* Do not compute discrepancy for the last iteration */
729 if (i >= cap)
730 continue;
731
732 for (k = 0; k <= (lmu[i + 1] >> 1); k++) {
733 tmp = 2 * (i - 1);
734 if (k == 0) {
735 dmu[i + 1] = si[tmp + 3];
736 } else if (smu[(i + 1) * num + k] && si[tmp + 3 - k]) {
737 int16_t a, b, c;
738 a = readw_relaxed(index_of +
739 smu[(i + 1) * num + k]);
740 b = si[2 * (i - 1) + 3 - k];
741 c = readw_relaxed(index_of + b);
742 tmp = a + c;
743 tmp %= cw_len;
744 dmu[i + 1] = readw_relaxed(alpha_to + tmp) ^
745 dmu[i + 1];
746 }
747 }
748 }
749
750 return;
751 }
752
753 static int pmecc_err_location(struct mtd_info *mtd)
754 {
755 struct nand_chip *nand_chip = mtd_to_nand(mtd);
756 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
757 unsigned long end_time;
758 const int cap = host->pmecc_corr_cap;
759 const int num = 2 * cap + 1;
760 int sector_size = host->pmecc_sector_size;
761 int err_nbr = 0; /* number of error */
762 int roots_nbr; /* number of roots */
763 int i;
764 uint32_t val;
765 int16_t *smu = host->pmecc_smu;
766
767 pmerrloc_writel(host->pmerrloc_base, ELDIS, PMERRLOC_DISABLE);
768
769 for (i = 0; i <= host->pmecc_lmu[cap + 1] >> 1; i++) {
770 pmerrloc_writel_sigma_relaxed(host->pmerrloc_base, i,
771 smu[(cap + 1) * num + i]);
772 err_nbr++;
773 }
774
775 val = (err_nbr - 1) << 16;
776 if (sector_size == 1024)
777 val |= 1;
778
779 pmerrloc_writel(host->pmerrloc_base, ELCFG, val);
780 pmerrloc_writel(host->pmerrloc_base, ELEN,
781 sector_size * 8 + host->pmecc_degree * cap);
782
783 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
784 while (!(pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
785 & PMERRLOC_CALC_DONE)) {
786 if (unlikely(time_after(jiffies, end_time))) {
787 dev_err(host->dev, "PMECC: Timeout to calculate error location.\n");
788 return -1;
789 }
790 cpu_relax();
791 }
792
793 roots_nbr = (pmerrloc_readl_relaxed(host->pmerrloc_base, ELISR)
794 & PMERRLOC_ERR_NUM_MASK) >> 8;
795 /* Number of roots == degree of smu hence <= cap */
796 if (roots_nbr == host->pmecc_lmu[cap + 1] >> 1)
797 return err_nbr - 1;
798
799 /* Number of roots does not match the degree of smu
800 * unable to correct error */
801 return -1;
802 }
803
804 static void pmecc_correct_data(struct mtd_info *mtd, uint8_t *buf, uint8_t *ecc,
805 int sector_num, int extra_bytes, int err_nbr)
806 {
807 struct nand_chip *nand_chip = mtd_to_nand(mtd);
808 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
809 int i = 0;
810 int byte_pos, bit_pos, sector_size, pos;
811 uint32_t tmp;
812 uint8_t err_byte;
813
814 sector_size = host->pmecc_sector_size;
815
816 while (err_nbr) {
817 tmp = pmerrloc_readl_el_relaxed(host->pmerrloc_el_base, i) - 1;
818 byte_pos = tmp / 8;
819 bit_pos = tmp % 8;
820
821 if (byte_pos >= (sector_size + extra_bytes))
822 BUG(); /* should never happen */
823
824 if (byte_pos < sector_size) {
825 err_byte = *(buf + byte_pos);
826 *(buf + byte_pos) ^= (1 << bit_pos);
827
828 pos = sector_num * host->pmecc_sector_size + byte_pos;
829 dev_dbg(host->dev, "Bit flip in data area, byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
830 pos, bit_pos, err_byte, *(buf + byte_pos));
831 } else {
832 struct mtd_oob_region oobregion;
833
834 /* Bit flip in OOB area */
835 tmp = sector_num * nand_chip->ecc.bytes
836 + (byte_pos - sector_size);
837 err_byte = ecc[tmp];
838 ecc[tmp] ^= (1 << bit_pos);
839
840 mtd_ooblayout_ecc(mtd, 0, &oobregion);
841 pos = tmp + oobregion.offset;
842 dev_dbg(host->dev, "Bit flip in OOB, oob_byte_pos: %d, bit_pos: %d, 0x%02x -> 0x%02x\n",
843 pos, bit_pos, err_byte, ecc[tmp]);
844 }
845
846 i++;
847 err_nbr--;
848 }
849
850 return;
851 }
852
853 static int pmecc_correction(struct mtd_info *mtd, u32 pmecc_stat, uint8_t *buf,
854 u8 *ecc)
855 {
856 struct nand_chip *nand_chip = mtd_to_nand(mtd);
857 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
858 int i, err_nbr;
859 uint8_t *buf_pos;
860 int max_bitflips = 0;
861
862 for (i = 0; i < nand_chip->ecc.steps; i++) {
863 err_nbr = 0;
864 if (pmecc_stat & 0x1) {
865 buf_pos = buf + i * host->pmecc_sector_size;
866
867 pmecc_gen_syndrome(mtd, i);
868 pmecc_substitute(mtd);
869 pmecc_get_sigma(mtd);
870
871 err_nbr = pmecc_err_location(mtd);
872 if (err_nbr >= 0) {
873 pmecc_correct_data(mtd, buf_pos, ecc, i,
874 nand_chip->ecc.bytes,
875 err_nbr);
876 } else if (!host->caps->pmecc_correct_erase_page) {
877 u8 *ecc_pos = ecc + (i * nand_chip->ecc.bytes);
878
879 /* Try to detect erased pages */
880 err_nbr = nand_check_erased_ecc_chunk(buf_pos,
881 host->pmecc_sector_size,
882 ecc_pos,
883 nand_chip->ecc.bytes,
884 NULL, 0,
885 nand_chip->ecc.strength);
886 }
887
888 if (err_nbr < 0) {
889 dev_err(host->dev, "PMECC: Too many errors\n");
890 mtd->ecc_stats.failed++;
891 return -EIO;
892 }
893
894 mtd->ecc_stats.corrected += err_nbr;
895 max_bitflips = max_t(int, max_bitflips, err_nbr);
896 }
897 pmecc_stat >>= 1;
898 }
899
900 return max_bitflips;
901 }
902
903 static void pmecc_enable(struct atmel_nand_host *host, int ecc_op)
904 {
905 u32 val;
906
907 if (ecc_op != NAND_ECC_READ && ecc_op != NAND_ECC_WRITE) {
908 dev_err(host->dev, "atmel_nand: wrong pmecc operation type!");
909 return;
910 }
911
912 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
913 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
914 val = pmecc_readl_relaxed(host->ecc, CFG);
915
916 if (ecc_op == NAND_ECC_READ)
917 pmecc_writel(host->ecc, CFG, (val & ~PMECC_CFG_WRITE_OP)
918 | PMECC_CFG_AUTO_ENABLE);
919 else
920 pmecc_writel(host->ecc, CFG, (val | PMECC_CFG_WRITE_OP)
921 & ~PMECC_CFG_AUTO_ENABLE);
922
923 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
924 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DATA);
925 }
926
927 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
928 struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
929 {
930 struct atmel_nand_host *host = nand_get_controller_data(chip);
931 int eccsize = chip->ecc.size * chip->ecc.steps;
932 uint8_t *oob = chip->oob_poi;
933 uint32_t stat;
934 unsigned long end_time;
935 int bitflips = 0;
936
937 if (!host->nfc || !host->nfc->use_nfc_sram)
938 pmecc_enable(host, NAND_ECC_READ);
939
940 chip->read_buf(mtd, buf, eccsize);
941 chip->read_buf(mtd, oob, mtd->oobsize);
942
943 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
944 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
945 if (unlikely(time_after(jiffies, end_time))) {
946 dev_err(host->dev, "PMECC: Timeout to get error status.\n");
947 return -EIO;
948 }
949 cpu_relax();
950 }
951
952 stat = pmecc_readl_relaxed(host->ecc, ISR);
953 if (stat != 0) {
954 struct mtd_oob_region oobregion;
955
956 mtd_ooblayout_ecc(mtd, 0, &oobregion);
957 bitflips = pmecc_correction(mtd, stat, buf,
958 &oob[oobregion.offset]);
959 if (bitflips < 0)
960 /* uncorrectable errors */
961 return 0;
962 }
963
964 return bitflips;
965 }
966
967 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
968 struct nand_chip *chip, const uint8_t *buf, int oob_required,
969 int page)
970 {
971 struct atmel_nand_host *host = nand_get_controller_data(chip);
972 struct mtd_oob_region oobregion = { };
973 int i, j, section = 0;
974 unsigned long end_time;
975
976 if (!host->nfc || !host->nfc->write_by_sram) {
977 pmecc_enable(host, NAND_ECC_WRITE);
978 chip->write_buf(mtd, (u8 *)buf, mtd->writesize);
979 }
980
981 end_time = jiffies + msecs_to_jiffies(PMECC_MAX_TIMEOUT_MS);
982 while ((pmecc_readl_relaxed(host->ecc, SR) & PMECC_SR_BUSY)) {
983 if (unlikely(time_after(jiffies, end_time))) {
984 dev_err(host->dev, "PMECC: Timeout to get ECC value.\n");
985 return -EIO;
986 }
987 cpu_relax();
988 }
989
990 for (i = 0; i < chip->ecc.steps; i++) {
991 for (j = 0; j < chip->ecc.bytes; j++) {
992 if (!oobregion.length)
993 mtd_ooblayout_ecc(mtd, section, &oobregion);
994
995 chip->oob_poi[oobregion.offset] =
996 pmecc_readb_ecc_relaxed(host->ecc, i, j);
997 oobregion.length--;
998 oobregion.offset++;
999 section++;
1000 }
1001 }
1002 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
1003
1004 return 0;
1005 }
1006
1007 static void atmel_pmecc_core_init(struct mtd_info *mtd)
1008 {
1009 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1010 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1011 int eccbytes = mtd_ooblayout_count_eccbytes(mtd);
1012 uint32_t val = 0;
1013 struct mtd_oob_region oobregion;
1014
1015 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_RST);
1016 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
1017
1018 switch (host->pmecc_corr_cap) {
1019 case 2:
1020 val = PMECC_CFG_BCH_ERR2;
1021 break;
1022 case 4:
1023 val = PMECC_CFG_BCH_ERR4;
1024 break;
1025 case 8:
1026 val = PMECC_CFG_BCH_ERR8;
1027 break;
1028 case 12:
1029 val = PMECC_CFG_BCH_ERR12;
1030 break;
1031 case 24:
1032 val = PMECC_CFG_BCH_ERR24;
1033 break;
1034 case 32:
1035 val = PMECC_CFG_BCH_ERR32;
1036 break;
1037 }
1038
1039 if (host->pmecc_sector_size == 512)
1040 val |= PMECC_CFG_SECTOR512;
1041 else if (host->pmecc_sector_size == 1024)
1042 val |= PMECC_CFG_SECTOR1024;
1043
1044 switch (nand_chip->ecc.steps) {
1045 case 1:
1046 val |= PMECC_CFG_PAGE_1SECTOR;
1047 break;
1048 case 2:
1049 val |= PMECC_CFG_PAGE_2SECTORS;
1050 break;
1051 case 4:
1052 val |= PMECC_CFG_PAGE_4SECTORS;
1053 break;
1054 case 8:
1055 val |= PMECC_CFG_PAGE_8SECTORS;
1056 break;
1057 }
1058
1059 val |= (PMECC_CFG_READ_OP | PMECC_CFG_SPARE_DISABLE
1060 | PMECC_CFG_AUTO_DISABLE);
1061 pmecc_writel(host->ecc, CFG, val);
1062
1063 pmecc_writel(host->ecc, SAREA, mtd->oobsize - 1);
1064 mtd_ooblayout_ecc(mtd, 0, &oobregion);
1065 pmecc_writel(host->ecc, SADDR, oobregion.offset);
1066 pmecc_writel(host->ecc, EADDR,
1067 oobregion.offset + eccbytes - 1);
1068 /* See datasheet about PMECC Clock Control Register */
1069 pmecc_writel(host->ecc, CLK, 2);
1070 pmecc_writel(host->ecc, IDR, 0xff);
1071 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_ENABLE);
1072 }
1073
1074 /*
1075 * Get minimum ecc requirements from NAND.
1076 * If pmecc-cap, pmecc-sector-size in DTS are not specified, this function
1077 * will set them according to minimum ecc requirement. Otherwise, use the
1078 * value in DTS file.
1079 * return 0 if success. otherwise return error code.
1080 */
1081 static int pmecc_choose_ecc(struct atmel_nand_host *host,
1082 int *cap, int *sector_size)
1083 {
1084 /* Get minimum ECC requirements */
1085 if (host->nand_chip.ecc_strength_ds) {
1086 *cap = host->nand_chip.ecc_strength_ds;
1087 *sector_size = host->nand_chip.ecc_step_ds;
1088 dev_info(host->dev, "minimum ECC: %d bits in %d bytes\n",
1089 *cap, *sector_size);
1090 } else {
1091 *cap = 2;
1092 *sector_size = 512;
1093 dev_info(host->dev, "can't detect min. ECC, assume 2 bits in 512 bytes\n");
1094 }
1095
1096 /* If device tree doesn't specify, use NAND's minimum ECC parameters */
1097 if (host->pmecc_corr_cap == 0) {
1098 if (*cap > host->caps->pmecc_max_correction)
1099 return -EINVAL;
1100
1101 /* use the most fitable ecc bits (the near bigger one ) */
1102 if (*cap <= 2)
1103 host->pmecc_corr_cap = 2;
1104 else if (*cap <= 4)
1105 host->pmecc_corr_cap = 4;
1106 else if (*cap <= 8)
1107 host->pmecc_corr_cap = 8;
1108 else if (*cap <= 12)
1109 host->pmecc_corr_cap = 12;
1110 else if (*cap <= 24)
1111 host->pmecc_corr_cap = 24;
1112 else if (*cap <= 32)
1113 host->pmecc_corr_cap = 32;
1114 else
1115 return -EINVAL;
1116 }
1117 if (host->pmecc_sector_size == 0) {
1118 /* use the most fitable sector size (the near smaller one ) */
1119 if (*sector_size >= 1024)
1120 host->pmecc_sector_size = 1024;
1121 else if (*sector_size >= 512)
1122 host->pmecc_sector_size = 512;
1123 else
1124 return -EINVAL;
1125 }
1126 return 0;
1127 }
1128
1129 static inline int deg(unsigned int poly)
1130 {
1131 /* polynomial degree is the most-significant bit index */
1132 return fls(poly) - 1;
1133 }
1134
1135 static int build_gf_tables(int mm, unsigned int poly,
1136 int16_t *index_of, int16_t *alpha_to)
1137 {
1138 unsigned int i, x = 1;
1139 const unsigned int k = 1 << deg(poly);
1140 unsigned int nn = (1 << mm) - 1;
1141
1142 /* primitive polynomial must be of degree m */
1143 if (k != (1u << mm))
1144 return -EINVAL;
1145
1146 for (i = 0; i < nn; i++) {
1147 alpha_to[i] = x;
1148 index_of[x] = i;
1149 if (i && (x == 1))
1150 /* polynomial is not primitive (a^i=1 with 0<i<2^m-1) */
1151 return -EINVAL;
1152 x <<= 1;
1153 if (x & k)
1154 x ^= poly;
1155 }
1156 alpha_to[nn] = 1;
1157 index_of[0] = 0;
1158
1159 return 0;
1160 }
1161
1162 static uint16_t *create_lookup_table(struct device *dev, int sector_size)
1163 {
1164 int degree = (sector_size == 512) ?
1165 PMECC_GF_DIMENSION_13 :
1166 PMECC_GF_DIMENSION_14;
1167 unsigned int poly = (sector_size == 512) ?
1168 PMECC_GF_13_PRIMITIVE_POLY :
1169 PMECC_GF_14_PRIMITIVE_POLY;
1170 int table_size = (sector_size == 512) ?
1171 PMECC_LOOKUP_TABLE_SIZE_512 :
1172 PMECC_LOOKUP_TABLE_SIZE_1024;
1173
1174 int16_t *addr = devm_kzalloc(dev, 2 * table_size * sizeof(uint16_t),
1175 GFP_KERNEL);
1176 if (addr && build_gf_tables(degree, poly, addr, addr + table_size))
1177 return NULL;
1178
1179 return addr;
1180 }
1181
1182 static int atmel_pmecc_nand_init_params(struct platform_device *pdev,
1183 struct atmel_nand_host *host)
1184 {
1185 struct nand_chip *nand_chip = &host->nand_chip;
1186 struct mtd_info *mtd = nand_to_mtd(nand_chip);
1187 struct resource *regs, *regs_pmerr, *regs_rom;
1188 uint16_t *galois_table;
1189 int cap, sector_size, err_no;
1190
1191 err_no = pmecc_choose_ecc(host, &cap, &sector_size);
1192 if (err_no) {
1193 dev_err(host->dev, "The NAND flash's ECC requirement are not support!");
1194 return err_no;
1195 }
1196
1197 if (cap > host->pmecc_corr_cap ||
1198 sector_size != host->pmecc_sector_size)
1199 dev_info(host->dev, "WARNING: Be Caution! Using different PMECC parameters from Nand ONFI ECC reqirement.\n");
1200
1201 cap = host->pmecc_corr_cap;
1202 sector_size = host->pmecc_sector_size;
1203 host->pmecc_lookup_table_offset = (sector_size == 512) ?
1204 host->pmecc_lookup_table_offset_512 :
1205 host->pmecc_lookup_table_offset_1024;
1206
1207 dev_info(host->dev, "Initialize PMECC params, cap: %d, sector: %d\n",
1208 cap, sector_size);
1209
1210 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1211 if (!regs) {
1212 dev_warn(host->dev,
1213 "Can't get I/O resource regs for PMECC controller, rolling back on software ECC\n");
1214 nand_chip->ecc.mode = NAND_ECC_SOFT;
1215 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1216 return 0;
1217 }
1218
1219 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1220 if (IS_ERR(host->ecc)) {
1221 err_no = PTR_ERR(host->ecc);
1222 goto err;
1223 }
1224
1225 regs_pmerr = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1226 host->pmerrloc_base = devm_ioremap_resource(&pdev->dev, regs_pmerr);
1227 if (IS_ERR(host->pmerrloc_base)) {
1228 err_no = PTR_ERR(host->pmerrloc_base);
1229 goto err;
1230 }
1231 host->pmerrloc_el_base = host->pmerrloc_base + ATMEL_PMERRLOC_SIGMAx +
1232 (host->caps->pmecc_max_correction + 1) * 4;
1233
1234 if (!host->has_no_lookup_table) {
1235 regs_rom = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1236 host->pmecc_rom_base = devm_ioremap_resource(&pdev->dev,
1237 regs_rom);
1238 if (IS_ERR(host->pmecc_rom_base)) {
1239 dev_err(host->dev, "Can not get I/O resource for ROM, will build a lookup table in runtime!\n");
1240 host->has_no_lookup_table = true;
1241 }
1242 }
1243
1244 if (host->has_no_lookup_table) {
1245 /* Build the look-up table in runtime */
1246 galois_table = create_lookup_table(host->dev, sector_size);
1247 if (!galois_table) {
1248 dev_err(host->dev, "Failed to build a lookup table in runtime!\n");
1249 err_no = -EINVAL;
1250 goto err;
1251 }
1252
1253 host->pmecc_rom_base = (void __iomem *)galois_table;
1254 host->pmecc_lookup_table_offset = 0;
1255 }
1256
1257 nand_chip->ecc.size = sector_size;
1258
1259 /* set ECC page size and oob layout */
1260 switch (mtd->writesize) {
1261 case 512:
1262 case 1024:
1263 case 2048:
1264 case 4096:
1265 case 8192:
1266 if (sector_size > mtd->writesize) {
1267 dev_err(host->dev, "pmecc sector size is bigger than the page size!\n");
1268 err_no = -EINVAL;
1269 goto err;
1270 }
1271
1272 host->pmecc_degree = (sector_size == 512) ?
1273 PMECC_GF_DIMENSION_13 : PMECC_GF_DIMENSION_14;
1274 host->pmecc_cw_len = (1 << host->pmecc_degree) - 1;
1275 host->pmecc_alpha_to = pmecc_get_alpha_to(host);
1276 host->pmecc_index_of = host->pmecc_rom_base +
1277 host->pmecc_lookup_table_offset;
1278
1279 nand_chip->ecc.strength = cap;
1280 nand_chip->ecc.bytes = pmecc_get_ecc_bytes(cap, sector_size);
1281 nand_chip->ecc.steps = mtd->writesize / sector_size;
1282 nand_chip->ecc.total = nand_chip->ecc.bytes *
1283 nand_chip->ecc.steps;
1284 if (nand_chip->ecc.total >
1285 mtd->oobsize - PMECC_OOB_RESERVED_BYTES) {
1286 dev_err(host->dev, "No room for ECC bytes\n");
1287 err_no = -EINVAL;
1288 goto err;
1289 }
1290
1291 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1292 break;
1293 default:
1294 dev_warn(host->dev,
1295 "Unsupported page size for PMECC, use Software ECC\n");
1296 /* page size not handled by HW ECC */
1297 /* switching back to soft ECC */
1298 nand_chip->ecc.mode = NAND_ECC_SOFT;
1299 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1300 return 0;
1301 }
1302
1303 /* Allocate data for PMECC computation */
1304 err_no = pmecc_data_alloc(host);
1305 if (err_no) {
1306 dev_err(host->dev,
1307 "Cannot allocate memory for PMECC computation!\n");
1308 goto err;
1309 }
1310
1311 nand_chip->options |= NAND_NO_SUBPAGE_WRITE;
1312 nand_chip->ecc.read_page = atmel_nand_pmecc_read_page;
1313 nand_chip->ecc.write_page = atmel_nand_pmecc_write_page;
1314
1315 atmel_pmecc_core_init(mtd);
1316
1317 return 0;
1318
1319 err:
1320 return err_no;
1321 }
1322
1323 /*
1324 * Calculate HW ECC
1325 *
1326 * function called after a write
1327 *
1328 * mtd: MTD block structure
1329 * dat: raw data (unused)
1330 * ecc_code: buffer for ECC
1331 */
1332 static int atmel_nand_calculate(struct mtd_info *mtd,
1333 const u_char *dat, unsigned char *ecc_code)
1334 {
1335 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1336 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1337 unsigned int ecc_value;
1338
1339 /* get the first 2 ECC bytes */
1340 ecc_value = ecc_readl(host->ecc, PR);
1341
1342 ecc_code[0] = ecc_value & 0xFF;
1343 ecc_code[1] = (ecc_value >> 8) & 0xFF;
1344
1345 /* get the last 2 ECC bytes */
1346 ecc_value = ecc_readl(host->ecc, NPR) & ATMEL_ECC_NPARITY;
1347
1348 ecc_code[2] = ecc_value & 0xFF;
1349 ecc_code[3] = (ecc_value >> 8) & 0xFF;
1350
1351 return 0;
1352 }
1353
1354 /*
1355 * HW ECC read page function
1356 *
1357 * mtd: mtd info structure
1358 * chip: nand chip info structure
1359 * buf: buffer to store read data
1360 * oob_required: caller expects OOB data read to chip->oob_poi
1361 */
1362 static int atmel_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1363 uint8_t *buf, int oob_required, int page)
1364 {
1365 int eccsize = chip->ecc.size;
1366 int eccbytes = chip->ecc.bytes;
1367 uint8_t *p = buf;
1368 uint8_t *oob = chip->oob_poi;
1369 uint8_t *ecc_pos;
1370 int stat;
1371 unsigned int max_bitflips = 0;
1372 struct mtd_oob_region oobregion = {};
1373
1374 /*
1375 * Errata: ALE is incorrectly wired up to the ECC controller
1376 * on the AP7000, so it will include the address cycles in the
1377 * ECC calculation.
1378 *
1379 * Workaround: Reset the parity registers before reading the
1380 * actual data.
1381 */
1382 struct atmel_nand_host *host = nand_get_controller_data(chip);
1383 if (host->board.need_reset_workaround)
1384 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1385
1386 /* read the page */
1387 chip->read_buf(mtd, p, eccsize);
1388
1389 /* move to ECC position if needed */
1390 mtd_ooblayout_ecc(mtd, 0, &oobregion);
1391 if (oobregion.offset != 0) {
1392 /*
1393 * This only works on large pages because the ECC controller
1394 * waits for NAND_CMD_RNDOUTSTART after the NAND_CMD_RNDOUT.
1395 * Anyway, for small pages, the first ECC byte is at offset
1396 * 0 in the OOB area.
1397 */
1398 chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
1399 mtd->writesize + oobregion.offset, -1);
1400 }
1401
1402 /* the ECC controller needs to read the ECC just after the data */
1403 ecc_pos = oob + oobregion.offset;
1404 chip->read_buf(mtd, ecc_pos, eccbytes);
1405
1406 /* check if there's an error */
1407 stat = chip->ecc.correct(mtd, p, oob, NULL);
1408
1409 if (stat < 0) {
1410 mtd->ecc_stats.failed++;
1411 } else {
1412 mtd->ecc_stats.corrected += stat;
1413 max_bitflips = max_t(unsigned int, max_bitflips, stat);
1414 }
1415
1416 /* get back to oob start (end of page) */
1417 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
1418
1419 /* read the oob */
1420 chip->read_buf(mtd, oob, mtd->oobsize);
1421
1422 return max_bitflips;
1423 }
1424
1425 /*
1426 * HW ECC Correction
1427 *
1428 * function called after a read
1429 *
1430 * mtd: MTD block structure
1431 * dat: raw data read from the chip
1432 * read_ecc: ECC from the chip (unused)
1433 * isnull: unused
1434 *
1435 * Detect and correct a 1 bit error for a page
1436 */
1437 static int atmel_nand_correct(struct mtd_info *mtd, u_char *dat,
1438 u_char *read_ecc, u_char *isnull)
1439 {
1440 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1441 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1442 unsigned int ecc_status;
1443 unsigned int ecc_word, ecc_bit;
1444
1445 /* get the status from the Status Register */
1446 ecc_status = ecc_readl(host->ecc, SR);
1447
1448 /* if there's no error */
1449 if (likely(!(ecc_status & ATMEL_ECC_RECERR)))
1450 return 0;
1451
1452 /* get error bit offset (4 bits) */
1453 ecc_bit = ecc_readl(host->ecc, PR) & ATMEL_ECC_BITADDR;
1454 /* get word address (12 bits) */
1455 ecc_word = ecc_readl(host->ecc, PR) & ATMEL_ECC_WORDADDR;
1456 ecc_word >>= 4;
1457
1458 /* if there are multiple errors */
1459 if (ecc_status & ATMEL_ECC_MULERR) {
1460 /* check if it is a freshly erased block
1461 * (filled with 0xff) */
1462 if ((ecc_bit == ATMEL_ECC_BITADDR)
1463 && (ecc_word == (ATMEL_ECC_WORDADDR >> 4))) {
1464 /* the block has just been erased, return OK */
1465 return 0;
1466 }
1467 /* it doesn't seems to be a freshly
1468 * erased block.
1469 * We can't correct so many errors */
1470 dev_dbg(host->dev, "atmel_nand : multiple errors detected."
1471 " Unable to correct.\n");
1472 return -EBADMSG;
1473 }
1474
1475 /* if there's a single bit error : we can correct it */
1476 if (ecc_status & ATMEL_ECC_ECCERR) {
1477 /* there's nothing much to do here.
1478 * the bit error is on the ECC itself.
1479 */
1480 dev_dbg(host->dev, "atmel_nand : one bit error on ECC code."
1481 " Nothing to correct\n");
1482 return 0;
1483 }
1484
1485 dev_dbg(host->dev, "atmel_nand : one bit error on data."
1486 " (word offset in the page :"
1487 " 0x%x bit offset : 0x%x)\n",
1488 ecc_word, ecc_bit);
1489 /* correct the error */
1490 if (nand_chip->options & NAND_BUSWIDTH_16) {
1491 /* 16 bits words */
1492 ((unsigned short *) dat)[ecc_word] ^= (1 << ecc_bit);
1493 } else {
1494 /* 8 bits words */
1495 dat[ecc_word] ^= (1 << ecc_bit);
1496 }
1497 dev_dbg(host->dev, "atmel_nand : error corrected\n");
1498 return 1;
1499 }
1500
1501 /*
1502 * Enable HW ECC : unused on most chips
1503 */
1504 static void atmel_nand_hwctl(struct mtd_info *mtd, int mode)
1505 {
1506 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1507 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1508
1509 if (host->board.need_reset_workaround)
1510 ecc_writel(host->ecc, CR, ATMEL_ECC_RST);
1511 }
1512
1513 static int atmel_of_init_ecc(struct atmel_nand_host *host,
1514 struct device_node *np)
1515 {
1516 u32 offset[2];
1517 u32 val;
1518
1519 host->has_pmecc = of_property_read_bool(np, "atmel,has-pmecc");
1520
1521 /* Not using PMECC */
1522 if (!(host->nand_chip.ecc.mode == NAND_ECC_HW) || !host->has_pmecc)
1523 return 0;
1524
1525 /* use PMECC, get correction capability, sector size and lookup
1526 * table offset.
1527 * If correction bits and sector size are not specified, then find
1528 * them from NAND ONFI parameters.
1529 */
1530 if (of_property_read_u32(np, "atmel,pmecc-cap", &val) == 0) {
1531 if (val > host->caps->pmecc_max_correction) {
1532 dev_err(host->dev,
1533 "Required ECC strength too high: %u max %u\n",
1534 val, host->caps->pmecc_max_correction);
1535 return -EINVAL;
1536 }
1537 if ((val != 2) && (val != 4) && (val != 8) &&
1538 (val != 12) && (val != 24) && (val != 32)) {
1539 dev_err(host->dev,
1540 "Required ECC strength not supported: %u\n",
1541 val);
1542 return -EINVAL;
1543 }
1544 host->pmecc_corr_cap = (u8)val;
1545 }
1546
1547 if (of_property_read_u32(np, "atmel,pmecc-sector-size", &val) == 0) {
1548 if ((val != 512) && (val != 1024)) {
1549 dev_err(host->dev,
1550 "Required ECC sector size not supported: %u\n",
1551 val);
1552 return -EINVAL;
1553 }
1554 host->pmecc_sector_size = (u16)val;
1555 }
1556
1557 if (of_property_read_u32_array(np, "atmel,pmecc-lookup-table-offset",
1558 offset, 2) != 0) {
1559 dev_err(host->dev, "Cannot get PMECC lookup table offset, will build a lookup table in runtime.\n");
1560 host->has_no_lookup_table = true;
1561 /* Will build a lookup table and initialize the offset later */
1562 return 0;
1563 }
1564
1565 if (!offset[0] && !offset[1]) {
1566 dev_err(host->dev, "Invalid PMECC lookup table offset\n");
1567 return -EINVAL;
1568 }
1569
1570 host->pmecc_lookup_table_offset_512 = offset[0];
1571 host->pmecc_lookup_table_offset_1024 = offset[1];
1572
1573 return 0;
1574 }
1575
1576 static int atmel_of_init_port(struct atmel_nand_host *host,
1577 struct device_node *np)
1578 {
1579 u32 val;
1580 struct atmel_nand_data *board = &host->board;
1581 enum of_gpio_flags flags = 0;
1582
1583 host->caps = (struct atmel_nand_caps *)
1584 of_device_get_match_data(host->dev);
1585
1586 if (of_property_read_u32(np, "atmel,nand-addr-offset", &val) == 0) {
1587 if (val >= 32) {
1588 dev_err(host->dev, "invalid addr-offset %u\n", val);
1589 return -EINVAL;
1590 }
1591 board->ale = val;
1592 }
1593
1594 if (of_property_read_u32(np, "atmel,nand-cmd-offset", &val) == 0) {
1595 if (val >= 32) {
1596 dev_err(host->dev, "invalid cmd-offset %u\n", val);
1597 return -EINVAL;
1598 }
1599 board->cle = val;
1600 }
1601
1602 board->has_dma = of_property_read_bool(np, "atmel,nand-has-dma");
1603
1604 board->rdy_pin = of_get_gpio_flags(np, 0, &flags);
1605 board->rdy_pin_active_low = (flags == OF_GPIO_ACTIVE_LOW);
1606
1607 board->enable_pin = of_get_gpio(np, 1);
1608 board->det_pin = of_get_gpio(np, 2);
1609
1610 /* load the nfc driver if there is */
1611 of_platform_populate(np, NULL, NULL, host->dev);
1612
1613 /*
1614 * Initialize ECC mode to NAND_ECC_SOFT so that we have a correct value
1615 * even if the nand-ecc-mode property is not defined.
1616 */
1617 host->nand_chip.ecc.mode = NAND_ECC_SOFT;
1618 host->nand_chip.ecc.algo = NAND_ECC_HAMMING;
1619
1620 return 0;
1621 }
1622
1623 static int atmel_hw_nand_init_params(struct platform_device *pdev,
1624 struct atmel_nand_host *host)
1625 {
1626 struct nand_chip *nand_chip = &host->nand_chip;
1627 struct mtd_info *mtd = nand_to_mtd(nand_chip);
1628 struct resource *regs;
1629
1630 regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1631 if (!regs) {
1632 dev_err(host->dev,
1633 "Can't get I/O resource regs, use software ECC\n");
1634 nand_chip->ecc.mode = NAND_ECC_SOFT;
1635 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1636 return 0;
1637 }
1638
1639 host->ecc = devm_ioremap_resource(&pdev->dev, regs);
1640 if (IS_ERR(host->ecc))
1641 return PTR_ERR(host->ecc);
1642
1643 /* ECC is calculated for the whole page (1 step) */
1644 nand_chip->ecc.size = mtd->writesize;
1645
1646 /* set ECC page size and oob layout */
1647 switch (mtd->writesize) {
1648 case 512:
1649 mtd_set_ooblayout(mtd, &atmel_ooblayout_sp_ops);
1650 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_528);
1651 break;
1652 case 1024:
1653 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1654 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_1056);
1655 break;
1656 case 2048:
1657 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1658 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_2112);
1659 break;
1660 case 4096:
1661 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1662 ecc_writel(host->ecc, MR, ATMEL_ECC_PAGESIZE_4224);
1663 break;
1664 default:
1665 /* page size not handled by HW ECC */
1666 /* switching back to soft ECC */
1667 nand_chip->ecc.mode = NAND_ECC_SOFT;
1668 nand_chip->ecc.algo = NAND_ECC_HAMMING;
1669 return 0;
1670 }
1671
1672 /* set up for HW ECC */
1673 nand_chip->ecc.calculate = atmel_nand_calculate;
1674 nand_chip->ecc.correct = atmel_nand_correct;
1675 nand_chip->ecc.hwctl = atmel_nand_hwctl;
1676 nand_chip->ecc.read_page = atmel_nand_read_page;
1677 nand_chip->ecc.bytes = 4;
1678 nand_chip->ecc.strength = 1;
1679
1680 return 0;
1681 }
1682
1683 static inline u32 nfc_read_status(struct atmel_nand_host *host)
1684 {
1685 u32 err_flags = NFC_SR_DTOE | NFC_SR_UNDEF | NFC_SR_AWB | NFC_SR_ASE;
1686 u32 nfc_status = nfc_readl(host->nfc->hsmc_regs, SR);
1687
1688 if (unlikely(nfc_status & err_flags)) {
1689 if (nfc_status & NFC_SR_DTOE)
1690 dev_err(host->dev, "NFC: Waiting Nand R/B Timeout Error\n");
1691 else if (nfc_status & NFC_SR_UNDEF)
1692 dev_err(host->dev, "NFC: Access Undefined Area Error\n");
1693 else if (nfc_status & NFC_SR_AWB)
1694 dev_err(host->dev, "NFC: Access memory While NFC is busy\n");
1695 else if (nfc_status & NFC_SR_ASE)
1696 dev_err(host->dev, "NFC: Access memory Size Error\n");
1697 }
1698
1699 return nfc_status;
1700 }
1701
1702 /* SMC interrupt service routine */
1703 static irqreturn_t hsmc_interrupt(int irq, void *dev_id)
1704 {
1705 struct atmel_nand_host *host = dev_id;
1706 u32 status, mask, pending;
1707 irqreturn_t ret = IRQ_NONE;
1708
1709 status = nfc_read_status(host);
1710 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1711 pending = status & mask;
1712
1713 if (pending & NFC_SR_XFR_DONE) {
1714 complete(&host->nfc->comp_xfer_done);
1715 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_XFR_DONE);
1716 ret = IRQ_HANDLED;
1717 }
1718 if (pending & host->nfc->caps->rb_mask) {
1719 complete(&host->nfc->comp_ready);
1720 nfc_writel(host->nfc->hsmc_regs, IDR, host->nfc->caps->rb_mask);
1721 ret = IRQ_HANDLED;
1722 }
1723 if (pending & NFC_SR_CMD_DONE) {
1724 complete(&host->nfc->comp_cmd_done);
1725 nfc_writel(host->nfc->hsmc_regs, IDR, NFC_SR_CMD_DONE);
1726 ret = IRQ_HANDLED;
1727 }
1728
1729 return ret;
1730 }
1731
1732 /* NFC(Nand Flash Controller) related functions */
1733 static void nfc_prepare_interrupt(struct atmel_nand_host *host, u32 flag)
1734 {
1735 if (flag & NFC_SR_XFR_DONE)
1736 init_completion(&host->nfc->comp_xfer_done);
1737
1738 if (flag & host->nfc->caps->rb_mask)
1739 init_completion(&host->nfc->comp_ready);
1740
1741 if (flag & NFC_SR_CMD_DONE)
1742 init_completion(&host->nfc->comp_cmd_done);
1743
1744 /* Enable interrupt that need to wait for */
1745 nfc_writel(host->nfc->hsmc_regs, IER, flag);
1746 }
1747
1748 static int nfc_wait_interrupt(struct atmel_nand_host *host, u32 flag)
1749 {
1750 int i, index = 0;
1751 struct completion *comp[3]; /* Support 3 interrupt completion */
1752
1753 if (flag & NFC_SR_XFR_DONE)
1754 comp[index++] = &host->nfc->comp_xfer_done;
1755
1756 if (flag & host->nfc->caps->rb_mask)
1757 comp[index++] = &host->nfc->comp_ready;
1758
1759 if (flag & NFC_SR_CMD_DONE)
1760 comp[index++] = &host->nfc->comp_cmd_done;
1761
1762 if (index == 0) {
1763 dev_err(host->dev, "Unknown interrupt flag: 0x%08x\n", flag);
1764 return -EINVAL;
1765 }
1766
1767 for (i = 0; i < index; i++) {
1768 if (wait_for_completion_timeout(comp[i],
1769 msecs_to_jiffies(NFC_TIME_OUT_MS)))
1770 continue; /* wait for next completion */
1771 else
1772 goto err_timeout;
1773 }
1774
1775 return 0;
1776
1777 err_timeout:
1778 dev_err(host->dev, "Time out to wait for interrupt: 0x%08x\n", flag);
1779 /* Disable the interrupt as it is not handled by interrupt handler */
1780 nfc_writel(host->nfc->hsmc_regs, IDR, flag);
1781 return -ETIMEDOUT;
1782 }
1783
1784 static int nfc_send_command(struct atmel_nand_host *host,
1785 unsigned int cmd, unsigned int addr, unsigned char cycle0)
1786 {
1787 unsigned long timeout;
1788 u32 flag = NFC_SR_CMD_DONE;
1789 flag |= cmd & NFCADDR_CMD_DATAEN ? NFC_SR_XFR_DONE : 0;
1790
1791 dev_dbg(host->dev,
1792 "nfc_cmd: 0x%08x, addr1234: 0x%08x, cycle0: 0x%02x\n",
1793 cmd, addr, cycle0);
1794
1795 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1796 while (nfc_readl(host->nfc->hsmc_regs, SR) & NFC_SR_BUSY) {
1797 if (time_after(jiffies, timeout)) {
1798 dev_err(host->dev,
1799 "Time out to wait for NFC ready!\n");
1800 return -ETIMEDOUT;
1801 }
1802 }
1803
1804 nfc_prepare_interrupt(host, flag);
1805 nfc_writel(host->nfc->hsmc_regs, CYCLE0, cycle0);
1806 nfc_cmd_addr1234_writel(cmd, addr, host->nfc->base_cmd_regs);
1807 return nfc_wait_interrupt(host, flag);
1808 }
1809
1810 static int nfc_device_ready(struct mtd_info *mtd)
1811 {
1812 u32 status, mask;
1813 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1814 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1815
1816 status = nfc_read_status(host);
1817 mask = nfc_readl(host->nfc->hsmc_regs, IMR);
1818
1819 /* The mask should be 0. If not we may lost interrupts */
1820 if (unlikely(mask & status))
1821 dev_err(host->dev, "Lost the interrupt flags: 0x%08x\n",
1822 mask & status);
1823
1824 return status & host->nfc->caps->rb_mask;
1825 }
1826
1827 static void nfc_select_chip(struct mtd_info *mtd, int chip)
1828 {
1829 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1830 struct atmel_nand_host *host = nand_get_controller_data(nand_chip);
1831
1832 if (chip == -1)
1833 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_DISABLE);
1834 else
1835 nfc_writel(host->nfc->hsmc_regs, CTRL, NFC_CTRL_ENABLE);
1836 }
1837
1838 static int nfc_make_addr(struct mtd_info *mtd, int command, int column,
1839 int page_addr, unsigned int *addr1234, unsigned int *cycle0)
1840 {
1841 struct nand_chip *chip = mtd_to_nand(mtd);
1842
1843 int acycle = 0;
1844 unsigned char addr_bytes[8];
1845 int index = 0, bit_shift;
1846
1847 BUG_ON(addr1234 == NULL || cycle0 == NULL);
1848
1849 *cycle0 = 0;
1850 *addr1234 = 0;
1851
1852 if (column != -1) {
1853 if (chip->options & NAND_BUSWIDTH_16 &&
1854 !nand_opcode_8bits(command))
1855 column >>= 1;
1856 addr_bytes[acycle++] = column & 0xff;
1857 if (mtd->writesize > 512)
1858 addr_bytes[acycle++] = (column >> 8) & 0xff;
1859 }
1860
1861 if (page_addr != -1) {
1862 addr_bytes[acycle++] = page_addr & 0xff;
1863 addr_bytes[acycle++] = (page_addr >> 8) & 0xff;
1864 if (chip->chipsize > (128 << 20))
1865 addr_bytes[acycle++] = (page_addr >> 16) & 0xff;
1866 }
1867
1868 if (acycle > 4)
1869 *cycle0 = addr_bytes[index++];
1870
1871 for (bit_shift = 0; index < acycle; bit_shift += 8)
1872 *addr1234 += addr_bytes[index++] << bit_shift;
1873
1874 /* return acycle in cmd register */
1875 return acycle << NFCADDR_CMD_ACYCLE_BIT_POS;
1876 }
1877
1878 static void nfc_nand_command(struct mtd_info *mtd, unsigned int command,
1879 int column, int page_addr)
1880 {
1881 struct nand_chip *chip = mtd_to_nand(mtd);
1882 struct atmel_nand_host *host = nand_get_controller_data(chip);
1883 unsigned long timeout;
1884 unsigned int nfc_addr_cmd = 0;
1885
1886 unsigned int cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1887
1888 /* Set default settings: no cmd2, no addr cycle. read from nand */
1889 unsigned int cmd2 = 0;
1890 unsigned int vcmd2 = 0;
1891 int acycle = NFCADDR_CMD_ACYCLE_NONE;
1892 int csid = NFCADDR_CMD_CSID_3;
1893 int dataen = NFCADDR_CMD_DATADIS;
1894 int nfcwr = NFCADDR_CMD_NFCRD;
1895 unsigned int addr1234 = 0;
1896 unsigned int cycle0 = 0;
1897 bool do_addr = true;
1898 host->nfc->data_in_sram = NULL;
1899
1900 dev_dbg(host->dev, "%s: cmd = 0x%02x, col = 0x%08x, page = 0x%08x\n",
1901 __func__, command, column, page_addr);
1902
1903 switch (command) {
1904 case NAND_CMD_RESET:
1905 nfc_addr_cmd = cmd1 | acycle | csid | dataen | nfcwr;
1906 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1907 udelay(chip->chip_delay);
1908
1909 nfc_nand_command(mtd, NAND_CMD_STATUS, -1, -1);
1910 timeout = jiffies + msecs_to_jiffies(NFC_TIME_OUT_MS);
1911 while (!(chip->read_byte(mtd) & NAND_STATUS_READY)) {
1912 if (time_after(jiffies, timeout)) {
1913 dev_err(host->dev,
1914 "Time out to wait status ready!\n");
1915 break;
1916 }
1917 }
1918 return;
1919 case NAND_CMD_STATUS:
1920 do_addr = false;
1921 break;
1922 case NAND_CMD_PARAM:
1923 case NAND_CMD_READID:
1924 do_addr = false;
1925 acycle = NFCADDR_CMD_ACYCLE_1;
1926 if (column != -1)
1927 addr1234 = column;
1928 break;
1929 case NAND_CMD_RNDOUT:
1930 cmd2 = NAND_CMD_RNDOUTSTART << NFCADDR_CMD_CMD2_BIT_POS;
1931 vcmd2 = NFCADDR_CMD_VCMD2;
1932 break;
1933 case NAND_CMD_READ0:
1934 case NAND_CMD_READOOB:
1935 if (command == NAND_CMD_READOOB) {
1936 column += mtd->writesize;
1937 command = NAND_CMD_READ0; /* only READ0 is valid */
1938 cmd1 = command << NFCADDR_CMD_CMD1_BIT_POS;
1939 }
1940 if (host->nfc->use_nfc_sram) {
1941 /* Enable Data transfer to sram */
1942 dataen = NFCADDR_CMD_DATAEN;
1943
1944 /* Need enable PMECC now, since NFC will transfer
1945 * data in bus after sending nfc read command.
1946 */
1947 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
1948 pmecc_enable(host, NAND_ECC_READ);
1949 }
1950
1951 cmd2 = NAND_CMD_READSTART << NFCADDR_CMD_CMD2_BIT_POS;
1952 vcmd2 = NFCADDR_CMD_VCMD2;
1953 break;
1954 /* For prgramming command, the cmd need set to write enable */
1955 case NAND_CMD_PAGEPROG:
1956 case NAND_CMD_SEQIN:
1957 case NAND_CMD_RNDIN:
1958 nfcwr = NFCADDR_CMD_NFCWR;
1959 if (host->nfc->will_write_sram && command == NAND_CMD_SEQIN)
1960 dataen = NFCADDR_CMD_DATAEN;
1961 break;
1962 default:
1963 break;
1964 }
1965
1966 if (do_addr)
1967 acycle = nfc_make_addr(mtd, command, column, page_addr,
1968 &addr1234, &cycle0);
1969
1970 nfc_addr_cmd = cmd1 | cmd2 | vcmd2 | acycle | csid | dataen | nfcwr;
1971 nfc_send_command(host, nfc_addr_cmd, addr1234, cycle0);
1972
1973 /*
1974 * Program and erase have their own busy handlers status, sequential
1975 * in, and deplete1 need no delay.
1976 */
1977 switch (command) {
1978 case NAND_CMD_CACHEDPROG:
1979 case NAND_CMD_PAGEPROG:
1980 case NAND_CMD_ERASE1:
1981 case NAND_CMD_ERASE2:
1982 case NAND_CMD_RNDIN:
1983 case NAND_CMD_STATUS:
1984 case NAND_CMD_RNDOUT:
1985 case NAND_CMD_SEQIN:
1986 case NAND_CMD_READID:
1987 return;
1988
1989 case NAND_CMD_READ0:
1990 if (dataen == NFCADDR_CMD_DATAEN) {
1991 host->nfc->data_in_sram = host->nfc->sram_bank0 +
1992 nfc_get_sram_off(host);
1993 return;
1994 }
1995 /* fall through */
1996 default:
1997 nfc_prepare_interrupt(host, host->nfc->caps->rb_mask);
1998 nfc_wait_interrupt(host, host->nfc->caps->rb_mask);
1999 }
2000 }
2001
2002 static int nfc_sram_write_page(struct mtd_info *mtd, struct nand_chip *chip,
2003 uint32_t offset, int data_len, const uint8_t *buf,
2004 int oob_required, int page, int cached, int raw)
2005 {
2006 int cfg, len;
2007 int status = 0;
2008 struct atmel_nand_host *host = nand_get_controller_data(chip);
2009 void *sram = host->nfc->sram_bank0 + nfc_get_sram_off(host);
2010
2011 /* Subpage write is not supported */
2012 if (offset || (data_len < mtd->writesize))
2013 return -EINVAL;
2014
2015 len = mtd->writesize;
2016 /* Copy page data to sram that will write to nand via NFC */
2017 if (use_dma) {
2018 if (atmel_nand_dma_op(mtd, (void *)buf, len, 0) != 0)
2019 /* Fall back to use cpu copy */
2020 memcpy(sram, buf, len);
2021 } else {
2022 memcpy(sram, buf, len);
2023 }
2024
2025 cfg = nfc_readl(host->nfc->hsmc_regs, CFG);
2026 if (unlikely(raw) && oob_required) {
2027 memcpy(sram + len, chip->oob_poi, mtd->oobsize);
2028 len += mtd->oobsize;
2029 nfc_writel(host->nfc->hsmc_regs, CFG, cfg | NFC_CFG_WSPARE);
2030 } else {
2031 nfc_writel(host->nfc->hsmc_regs, CFG, cfg & ~NFC_CFG_WSPARE);
2032 }
2033
2034 if (chip->ecc.mode == NAND_ECC_HW && host->has_pmecc)
2035 /*
2036 * When use NFC sram, need set up PMECC before send
2037 * NAND_CMD_SEQIN command. Since when the nand command
2038 * is sent, nfc will do transfer from sram and nand.
2039 */
2040 pmecc_enable(host, NAND_ECC_WRITE);
2041
2042 host->nfc->will_write_sram = true;
2043 chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
2044 host->nfc->will_write_sram = false;
2045
2046 if (likely(!raw))
2047 /* Need to write ecc into oob */
2048 status = chip->ecc.write_page(mtd, chip, buf, oob_required,
2049 page);
2050
2051 if (status < 0)
2052 return status;
2053
2054 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
2055 status = chip->waitfunc(mtd, chip);
2056
2057 if ((status & NAND_STATUS_FAIL) && (chip->errstat))
2058 status = chip->errstat(mtd, chip, FL_WRITING, status, page);
2059
2060 if (status & NAND_STATUS_FAIL)
2061 return -EIO;
2062
2063 return 0;
2064 }
2065
2066 static int nfc_sram_init(struct mtd_info *mtd)
2067 {
2068 struct nand_chip *chip = mtd_to_nand(mtd);
2069 struct atmel_nand_host *host = nand_get_controller_data(chip);
2070 int res = 0;
2071
2072 /* Initialize the NFC CFG register */
2073 unsigned int cfg_nfc = 0;
2074
2075 /* set page size and oob layout */
2076 switch (mtd->writesize) {
2077 case 512:
2078 cfg_nfc = NFC_CFG_PAGESIZE_512;
2079 break;
2080 case 1024:
2081 cfg_nfc = NFC_CFG_PAGESIZE_1024;
2082 break;
2083 case 2048:
2084 cfg_nfc = NFC_CFG_PAGESIZE_2048;
2085 break;
2086 case 4096:
2087 cfg_nfc = NFC_CFG_PAGESIZE_4096;
2088 break;
2089 case 8192:
2090 cfg_nfc = NFC_CFG_PAGESIZE_8192;
2091 break;
2092 default:
2093 dev_err(host->dev, "Unsupported page size for NFC.\n");
2094 res = -ENXIO;
2095 return res;
2096 }
2097
2098 /* oob bytes size = (NFCSPARESIZE + 1) * 4
2099 * Max support spare size is 512 bytes. */
2100 cfg_nfc |= (((mtd->oobsize / 4) - 1) << NFC_CFG_NFC_SPARESIZE_BIT_POS
2101 & NFC_CFG_NFC_SPARESIZE);
2102 /* default set a max timeout */
2103 cfg_nfc |= NFC_CFG_RSPARE |
2104 NFC_CFG_NFC_DTOCYC | NFC_CFG_NFC_DTOMUL;
2105
2106 nfc_writel(host->nfc->hsmc_regs, CFG, cfg_nfc);
2107
2108 host->nfc->will_write_sram = false;
2109 nfc_set_sram_bank(host, 0);
2110
2111 /* Use Write page with NFC SRAM only for PMECC or ECC NONE. */
2112 if (host->nfc->write_by_sram) {
2113 if ((chip->ecc.mode == NAND_ECC_HW && host->has_pmecc) ||
2114 chip->ecc.mode == NAND_ECC_NONE)
2115 chip->write_page = nfc_sram_write_page;
2116 else
2117 host->nfc->write_by_sram = false;
2118 }
2119
2120 dev_info(host->dev, "Using NFC Sram read %s\n",
2121 host->nfc->write_by_sram ? "and write" : "");
2122 return 0;
2123 }
2124
2125 static struct platform_driver atmel_nand_nfc_driver;
2126 /*
2127 * Probe for the NAND device.
2128 */
2129 static int atmel_nand_probe(struct platform_device *pdev)
2130 {
2131 struct atmel_nand_host *host;
2132 struct mtd_info *mtd;
2133 struct nand_chip *nand_chip;
2134 struct resource *mem;
2135 int res, irq;
2136
2137 /* Allocate memory for the device structure (and zero it) */
2138 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2139 if (!host)
2140 return -ENOMEM;
2141
2142 res = platform_driver_register(&atmel_nand_nfc_driver);
2143 if (res)
2144 dev_err(&pdev->dev, "atmel_nand: can't register NFC driver\n");
2145
2146 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2147 host->io_base = devm_ioremap_resource(&pdev->dev, mem);
2148 if (IS_ERR(host->io_base)) {
2149 res = PTR_ERR(host->io_base);
2150 goto err_nand_ioremap;
2151 }
2152 host->io_phys = (dma_addr_t)mem->start;
2153
2154 nand_chip = &host->nand_chip;
2155 mtd = nand_to_mtd(nand_chip);
2156 host->dev = &pdev->dev;
2157 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2158 nand_set_flash_node(nand_chip, pdev->dev.of_node);
2159 /* Only when CONFIG_OF is enabled of_node can be parsed */
2160 res = atmel_of_init_port(host, pdev->dev.of_node);
2161 if (res)
2162 goto err_nand_ioremap;
2163 } else {
2164 memcpy(&host->board, dev_get_platdata(&pdev->dev),
2165 sizeof(struct atmel_nand_data));
2166 nand_chip->ecc.mode = host->board.ecc_mode;
2167
2168 /*
2169 * When using software ECC every supported avr32 board means
2170 * Hamming algorithm. If that ever changes we'll need to add
2171 * ecc_algo field to the struct atmel_nand_data.
2172 */
2173 if (nand_chip->ecc.mode == NAND_ECC_SOFT)
2174 nand_chip->ecc.algo = NAND_ECC_HAMMING;
2175
2176 /* 16-bit bus width */
2177 if (host->board.bus_width_16)
2178 nand_chip->options |= NAND_BUSWIDTH_16;
2179 }
2180
2181 /* link the private data structures */
2182 nand_set_controller_data(nand_chip, host);
2183 mtd->dev.parent = &pdev->dev;
2184
2185 /* Set address of NAND IO lines */
2186 nand_chip->IO_ADDR_R = host->io_base;
2187 nand_chip->IO_ADDR_W = host->io_base;
2188
2189 if (nand_nfc.is_initialized) {
2190 /* NFC driver is probed and initialized */
2191 host->nfc = &nand_nfc;
2192
2193 nand_chip->select_chip = nfc_select_chip;
2194 nand_chip->dev_ready = nfc_device_ready;
2195 nand_chip->cmdfunc = nfc_nand_command;
2196
2197 /* Initialize the interrupt for NFC */
2198 irq = platform_get_irq(pdev, 0);
2199 if (irq < 0) {
2200 dev_err(host->dev, "Cannot get HSMC irq!\n");
2201 res = irq;
2202 goto err_nand_ioremap;
2203 }
2204
2205 res = devm_request_irq(&pdev->dev, irq, hsmc_interrupt,
2206 0, "hsmc", host);
2207 if (res) {
2208 dev_err(&pdev->dev, "Unable to request HSMC irq %d\n",
2209 irq);
2210 goto err_nand_ioremap;
2211 }
2212 } else {
2213 res = atmel_nand_set_enable_ready_pins(mtd);
2214 if (res)
2215 goto err_nand_ioremap;
2216
2217 nand_chip->cmd_ctrl = atmel_nand_cmd_ctrl;
2218 }
2219
2220 nand_chip->chip_delay = 40; /* 40us command delay time */
2221
2222
2223 nand_chip->read_buf = atmel_read_buf;
2224 nand_chip->write_buf = atmel_write_buf;
2225
2226 platform_set_drvdata(pdev, host);
2227 atmel_nand_enable(host);
2228
2229 if (gpio_is_valid(host->board.det_pin)) {
2230 res = devm_gpio_request(&pdev->dev,
2231 host->board.det_pin, "nand_det");
2232 if (res < 0) {
2233 dev_err(&pdev->dev,
2234 "can't request det gpio %d\n",
2235 host->board.det_pin);
2236 goto err_no_card;
2237 }
2238
2239 res = gpio_direction_input(host->board.det_pin);
2240 if (res < 0) {
2241 dev_err(&pdev->dev,
2242 "can't request input direction det gpio %d\n",
2243 host->board.det_pin);
2244 goto err_no_card;
2245 }
2246
2247 if (gpio_get_value(host->board.det_pin)) {
2248 dev_info(&pdev->dev, "No SmartMedia card inserted.\n");
2249 res = -ENXIO;
2250 goto err_no_card;
2251 }
2252 }
2253
2254 if (!host->board.has_dma)
2255 use_dma = 0;
2256
2257 if (use_dma) {
2258 dma_cap_mask_t mask;
2259
2260 dma_cap_zero(mask);
2261 dma_cap_set(DMA_MEMCPY, mask);
2262 host->dma_chan = dma_request_channel(mask, NULL, NULL);
2263 if (!host->dma_chan) {
2264 dev_err(host->dev, "Failed to request DMA channel\n");
2265 use_dma = 0;
2266 }
2267 }
2268 if (use_dma)
2269 dev_info(host->dev, "Using %s for DMA transfers.\n",
2270 dma_chan_name(host->dma_chan));
2271 else
2272 dev_info(host->dev, "No DMA support for NAND access.\n");
2273
2274 /* first scan to find the device and get the page size */
2275 if (nand_scan_ident(mtd, 1, NULL)) {
2276 res = -ENXIO;
2277 goto err_scan_ident;
2278 }
2279
2280 if (host->board.on_flash_bbt || on_flash_bbt)
2281 nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
2282
2283 if (nand_chip->bbt_options & NAND_BBT_USE_FLASH)
2284 dev_info(&pdev->dev, "Use On Flash BBT\n");
2285
2286 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) {
2287 res = atmel_of_init_ecc(host, pdev->dev.of_node);
2288 if (res)
2289 goto err_hw_ecc;
2290 }
2291
2292 if (nand_chip->ecc.mode == NAND_ECC_HW) {
2293 if (host->has_pmecc)
2294 res = atmel_pmecc_nand_init_params(pdev, host);
2295 else
2296 res = atmel_hw_nand_init_params(pdev, host);
2297
2298 if (res != 0)
2299 goto err_hw_ecc;
2300 }
2301
2302 /* initialize the nfc configuration register */
2303 if (host->nfc && host->nfc->use_nfc_sram) {
2304 res = nfc_sram_init(mtd);
2305 if (res) {
2306 host->nfc->use_nfc_sram = false;
2307 dev_err(host->dev, "Disable use nfc sram for data transfer.\n");
2308 }
2309 }
2310
2311 /* second phase scan */
2312 if (nand_scan_tail(mtd)) {
2313 res = -ENXIO;
2314 goto err_scan_tail;
2315 }
2316
2317 mtd->name = "atmel_nand";
2318 res = mtd_device_register(mtd, host->board.parts,
2319 host->board.num_parts);
2320 if (!res)
2321 return res;
2322
2323 err_scan_tail:
2324 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW)
2325 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2326 err_hw_ecc:
2327 err_scan_ident:
2328 err_no_card:
2329 atmel_nand_disable(host);
2330 if (host->dma_chan)
2331 dma_release_channel(host->dma_chan);
2332 err_nand_ioremap:
2333 return res;
2334 }
2335
2336 /*
2337 * Remove a NAND device.
2338 */
2339 static int atmel_nand_remove(struct platform_device *pdev)
2340 {
2341 struct atmel_nand_host *host = platform_get_drvdata(pdev);
2342 struct mtd_info *mtd = nand_to_mtd(&host->nand_chip);
2343
2344 nand_release(mtd);
2345
2346 atmel_nand_disable(host);
2347
2348 if (host->has_pmecc && host->nand_chip.ecc.mode == NAND_ECC_HW) {
2349 pmecc_writel(host->ecc, CTRL, PMECC_CTRL_DISABLE);
2350 pmerrloc_writel(host->pmerrloc_base, ELDIS,
2351 PMERRLOC_DISABLE);
2352 }
2353
2354 if (host->dma_chan)
2355 dma_release_channel(host->dma_chan);
2356
2357 platform_driver_unregister(&atmel_nand_nfc_driver);
2358
2359 return 0;
2360 }
2361
2362 /*
2363 * AT91RM9200 does not have PMECC or PMECC Errloc peripherals for
2364 * BCH ECC. Combined with the "atmel,has-pmecc", it is used to describe
2365 * devices from the SAM9 family that have those.
2366 */
2367 static const struct atmel_nand_caps at91rm9200_caps = {
2368 .pmecc_correct_erase_page = false,
2369 .pmecc_max_correction = 24,
2370 };
2371
2372 static const struct atmel_nand_caps sama5d4_caps = {
2373 .pmecc_correct_erase_page = true,
2374 .pmecc_max_correction = 24,
2375 };
2376
2377 /*
2378 * The PMECC Errloc controller starting in SAMA5D2 is not compatible,
2379 * as the increased correction strength requires more registers.
2380 */
2381 static const struct atmel_nand_caps sama5d2_caps = {
2382 .pmecc_correct_erase_page = true,
2383 .pmecc_max_correction = 32,
2384 };
2385
2386 static const struct of_device_id atmel_nand_dt_ids[] = {
2387 { .compatible = "atmel,at91rm9200-nand", .data = &at91rm9200_caps },
2388 { .compatible = "atmel,sama5d4-nand", .data = &sama5d4_caps },
2389 { .compatible = "atmel,sama5d2-nand", .data = &sama5d2_caps },
2390 { /* sentinel */ }
2391 };
2392
2393 MODULE_DEVICE_TABLE(of, atmel_nand_dt_ids);
2394
2395 static int atmel_nand_nfc_probe(struct platform_device *pdev)
2396 {
2397 struct atmel_nfc *nfc = &nand_nfc;
2398 struct resource *nfc_cmd_regs, *nfc_hsmc_regs, *nfc_sram;
2399 int ret;
2400
2401 nfc_cmd_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2402 nfc->base_cmd_regs = devm_ioremap_resource(&pdev->dev, nfc_cmd_regs);
2403 if (IS_ERR(nfc->base_cmd_regs))
2404 return PTR_ERR(nfc->base_cmd_regs);
2405
2406 nfc_hsmc_regs = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2407 nfc->hsmc_regs = devm_ioremap_resource(&pdev->dev, nfc_hsmc_regs);
2408 if (IS_ERR(nfc->hsmc_regs))
2409 return PTR_ERR(nfc->hsmc_regs);
2410
2411 nfc_sram = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2412 if (nfc_sram) {
2413 nfc->sram_bank0 = (void * __force)
2414 devm_ioremap_resource(&pdev->dev, nfc_sram);
2415 if (IS_ERR(nfc->sram_bank0)) {
2416 dev_warn(&pdev->dev, "Fail to ioremap the NFC sram with error: %ld. So disable NFC sram.\n",
2417 PTR_ERR(nfc->sram_bank0));
2418 } else {
2419 nfc->use_nfc_sram = true;
2420 nfc->sram_bank0_phys = (dma_addr_t)nfc_sram->start;
2421
2422 if (pdev->dev.of_node)
2423 nfc->write_by_sram = of_property_read_bool(
2424 pdev->dev.of_node,
2425 "atmel,write-by-sram");
2426 }
2427 }
2428
2429 nfc->caps = (const struct atmel_nand_nfc_caps *)
2430 of_device_get_match_data(&pdev->dev);
2431 if (!nfc->caps)
2432 return -ENODEV;
2433
2434 nfc_writel(nfc->hsmc_regs, IDR, 0xffffffff);
2435 nfc_readl(nfc->hsmc_regs, SR); /* clear the NFC_SR */
2436
2437 nfc->clk = devm_clk_get(&pdev->dev, NULL);
2438 if (!IS_ERR(nfc->clk)) {
2439 ret = clk_prepare_enable(nfc->clk);
2440 if (ret)
2441 return ret;
2442 } else {
2443 dev_warn(&pdev->dev, "NFC clock missing, update your Device Tree");
2444 }
2445
2446 nfc->is_initialized = true;
2447 dev_info(&pdev->dev, "NFC is probed.\n");
2448
2449 return 0;
2450 }
2451
2452 static int atmel_nand_nfc_remove(struct platform_device *pdev)
2453 {
2454 struct atmel_nfc *nfc = &nand_nfc;
2455
2456 if (!IS_ERR(nfc->clk))
2457 clk_disable_unprepare(nfc->clk);
2458
2459 return 0;
2460 }
2461
2462 static const struct atmel_nand_nfc_caps sama5d3_nfc_caps = {
2463 .rb_mask = NFC_SR_RB_EDGE0,
2464 };
2465
2466 static const struct atmel_nand_nfc_caps sama5d4_nfc_caps = {
2467 .rb_mask = NFC_SR_RB_EDGE3,
2468 };
2469
2470 static const struct of_device_id atmel_nand_nfc_match[] = {
2471 { .compatible = "atmel,sama5d3-nfc", .data = &sama5d3_nfc_caps },
2472 { .compatible = "atmel,sama5d4-nfc", .data = &sama5d4_nfc_caps },
2473 { /* sentinel */ }
2474 };
2475 MODULE_DEVICE_TABLE(of, atmel_nand_nfc_match);
2476
2477 static struct platform_driver atmel_nand_nfc_driver = {
2478 .driver = {
2479 .name = "atmel_nand_nfc",
2480 .of_match_table = of_match_ptr(atmel_nand_nfc_match),
2481 },
2482 .probe = atmel_nand_nfc_probe,
2483 .remove = atmel_nand_nfc_remove,
2484 };
2485
2486 static struct platform_driver atmel_nand_driver = {
2487 .probe = atmel_nand_probe,
2488 .remove = atmel_nand_remove,
2489 .driver = {
2490 .name = "atmel_nand",
2491 .of_match_table = of_match_ptr(atmel_nand_dt_ids),
2492 },
2493 };
2494
2495 module_platform_driver(atmel_nand_driver);
2496
2497 MODULE_LICENSE("GPL");
2498 MODULE_AUTHOR("Rick Bronson");
2499 MODULE_DESCRIPTION("NAND/SmartMedia driver for AT91 / AVR32");
2500 MODULE_ALIAS("platform:atmel_nand");
Linux kernel - Deliverables
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