drivers/mtd/nand/au1550nd.c

   1 /*
   2  *  drivers/mtd/nand/au1550nd.c
   3  *
   4  *  Copyright (C) 2004 Embedded Edge, LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include <linux/slab.h>
  13 #include <linux/gpio.h>
  14 #include <linux/init.h>
  15 #include <linux/module.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/mtd/mtd.h>
  18 #include <linux/mtd/nand.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <asm/io.h>
  21
  22 #include <asm/mach-au1x00/au1xxx.h>
  23 #include <asm/mach-db1x00/bcsr.h>
  24
  25 /*
  26  * MTD structure for NAND controller
  27  */
  28 static struct mtd_info *au1550_mtd = NULL;
  29 static void __iomem *p_nand;
  30 static int nand_width = 1;      /* default x8 */
  31 static void (*au1550_write_byte)(struct mtd_info *, u_char);
  32
  33 /*
  34  * Define partitions for flash device
  35  */
  36 static const struct mtd_partition partition_info[] = {
  37         {
  38          .name = "NAND FS 0",
  39          .offset = 0,
  40          .size = 8 * 1024 * 1024},
  41         {
  42          .name = "NAND FS 1",
  43          .offset = MTDPART_OFS_APPEND,
  44          .size = MTDPART_SIZ_FULL}
  45 };
  46
  47 /**
  48  * au_read_byte -  read one byte from the chip
  49  * @mtd:        MTD device structure
  50  *
  51  *  read function for 8bit buswith
  52  */
  53 static u_char au_read_byte(struct mtd_info *mtd)
  54 {
  55         struct nand_chip *this = mtd->priv;
  56         u_char ret = readb(this->IO_ADDR_R);
  57         au_sync();
  58         return ret;
  59 }
  60
  61 /**
  62  * au_write_byte -  write one byte to the chip
  63  * @mtd:        MTD device structure
  64  * @byte:       pointer to data byte to write
  65  *
  66  *  write function for 8it buswith
  67  */
  68 static void au_write_byte(struct mtd_info *mtd, u_char byte)
  69 {
  70         struct nand_chip *this = mtd->priv;
  71         writeb(byte, this->IO_ADDR_W);
  72         au_sync();
  73 }
  74
  75 /**
  76  * au_read_byte16 -  read one byte endianess aware from the chip
  77  * @mtd:        MTD device structure
  78  *
  79  *  read function for 16bit buswith with
  80  * endianess conversion
  81  */
  82 static u_char au_read_byte16(struct mtd_info *mtd)
  83 {
  84         struct nand_chip *this = mtd->priv;
  85         u_char ret = (u_char) cpu_to_le16(readw(this->IO_ADDR_R));
  86         au_sync();
  87         return ret;
  88 }
  89
  90 /**
  91  * au_write_byte16 -  write one byte endianess aware to the chip
  92  * @mtd:        MTD device structure
  93  * @byte:       pointer to data byte to write
  94  *
  95  *  write function for 16bit buswith with
  96  * endianess conversion
  97  */
  98 static void au_write_byte16(struct mtd_info *mtd, u_char byte)
  99 {
 100         struct nand_chip *this = mtd->priv;
 101         writew(le16_to_cpu((u16) byte), this->IO_ADDR_W);
 102         au_sync();
 103 }
 104
 105 /**
 106  * au_read_word -  read one word from the chip
 107  * @mtd:        MTD device structure
 108  *
 109  *  read function for 16bit buswith without
 110  * endianess conversion
 111  */
 112 static u16 au_read_word(struct mtd_info *mtd)
 113 {
 114         struct nand_chip *this = mtd->priv;
 115         u16 ret = readw(this->IO_ADDR_R);
 116         au_sync();
 117         return ret;
 118 }
 119
 120 /**
 121  * au_write_buf -  write buffer to chip
 122  * @mtd:        MTD device structure
 123  * @buf:        data buffer
 124  * @len:        number of bytes to write
 125  *
 126  *  write function for 8bit buswith
 127  */
 128 static void au_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 129 {
 130         int i;
 131         struct nand_chip *this = mtd->priv;
 132
 133         for (i = 0; i < len; i++) {
 134                 writeb(buf[i], this->IO_ADDR_W);
 135                 au_sync();
 136         }
 137 }
 138
 139 /**
 140  * au_read_buf -  read chip data into buffer
 141  * @mtd:        MTD device structure
 142  * @buf:        buffer to store date
 143  * @len:        number of bytes to read
 144  *
 145  *  read function for 8bit buswith
 146  */
 147 static void au_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 148 {
 149         int i;
 150         struct nand_chip *this = mtd->priv;
 151
 152         for (i = 0; i < len; i++) {
 153                 buf[i] = readb(this->IO_ADDR_R);
 154                 au_sync();
 155         }
 156 }
 157
 158 /**
 159  * au_verify_buf -  Verify chip data against buffer
 160  * @mtd:        MTD device structure
 161  * @buf:        buffer containing the data to compare
 162  * @len:        number of bytes to compare
 163  *
 164  *  verify function for 8bit buswith
 165  */
 166 static int au_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
 167 {
 168         int i;
 169         struct nand_chip *this = mtd->priv;
 170
 171         for (i = 0; i < len; i++) {
 172                 if (buf[i] != readb(this->IO_ADDR_R))
 173                         return -EFAULT;
 174                 au_sync();
 175         }
 176
 177         return 0;
 178 }
 179
 180 /**
 181  * au_write_buf16 -  write buffer to chip
 182  * @mtd:        MTD device structure
 183  * @buf:        data buffer
 184  * @len:        number of bytes to write
 185  *
 186  *  write function for 16bit buswith
 187  */
 188 static void au_write_buf16(struct mtd_info *mtd, const u_char *buf, int len)
 189 {
 190         int i;
 191         struct nand_chip *this = mtd->priv;
 192         u16 *p = (u16 *) buf;
 193         len >>= 1;
 194
 195         for (i = 0; i < len; i++) {
 196                 writew(p[i], this->IO_ADDR_W);
 197                 au_sync();
 198         }
 199
 200 }
 201
 202 /**
 203  * au_read_buf16 -  read chip data into buffer
 204  * @mtd:        MTD device structure
 205  * @buf:        buffer to store date
 206  * @len:        number of bytes to read
 207  *
 208  *  read function for 16bit buswith
 209  */
 210 static void au_read_buf16(struct mtd_info *mtd, u_char *buf, int len)
 211 {
 212         int i;
 213         struct nand_chip *this = mtd->priv;
 214         u16 *p = (u16 *) buf;
 215         len >>= 1;
 216
 217         for (i = 0; i < len; i++) {
 218                 p[i] = readw(this->IO_ADDR_R);
 219                 au_sync();
 220         }
 221 }
 222
 223 /**
 224  * au_verify_buf16 -  Verify chip data against buffer
 225  * @mtd:        MTD device structure
 226  * @buf:        buffer containing the data to compare
 227  * @len:        number of bytes to compare
 228  *
 229  *  verify function for 16bit buswith
 230  */
 231 static int au_verify_buf16(struct mtd_info *mtd, const u_char *buf, int len)
 232 {
 233         int i;
 234         struct nand_chip *this = mtd->priv;
 235         u16 *p = (u16 *) buf;
 236         len >>= 1;
 237
 238         for (i = 0; i < len; i++) {
 239                 if (p[i] != readw(this->IO_ADDR_R))
 240                         return -EFAULT;
 241                 au_sync();
 242         }
 243         return 0;
 244 }
 245
 246 /* Select the chip by setting nCE to low */
 247 #define NAND_CTL_SETNCE         1
 248 /* Deselect the chip by setting nCE to high */
 249 #define NAND_CTL_CLRNCE         2
 250 /* Select the command latch by setting CLE to high */
 251 #define NAND_CTL_SETCLE         3
 252 /* Deselect the command latch by setting CLE to low */
 253 #define NAND_CTL_CLRCLE         4
 254 /* Select the address latch by setting ALE to high */
 255 #define NAND_CTL_SETALE         5
 256 /* Deselect the address latch by setting ALE to low */
 257 #define NAND_CTL_CLRALE         6
 258
 259 static void au1550_hwcontrol(struct mtd_info *mtd, int cmd)
 260 {
 261         register struct nand_chip *this = mtd->priv;
 262
 263         switch (cmd) {
 264
 265         case NAND_CTL_SETCLE:
 266                 this->IO_ADDR_W = p_nand + MEM_STNAND_CMD;
 267                 break;
 268
 269         case NAND_CTL_CLRCLE:
 270                 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
 271                 break;
 272
 273         case NAND_CTL_SETALE:
 274                 this->IO_ADDR_W = p_nand + MEM_STNAND_ADDR;
 275                 break;
 276
 277         case NAND_CTL_CLRALE:
 278                 this->IO_ADDR_W = p_nand + MEM_STNAND_DATA;
 279                 /* FIXME: Nobody knows why this is necessary,
 280                  * but it works only that way */
 281                 udelay(1);
 282                 break;
 283
 284         case NAND_CTL_SETNCE:
 285                 /* assert (force assert) chip enable */
 286                 au_writel((1 << (4 + NAND_CS)), MEM_STNDCTL);
 287                 break;
 288
 289         case NAND_CTL_CLRNCE:
 290                 /* deassert chip enable */
 291                 au_writel(0, MEM_STNDCTL);
 292                 break;
 293         }
 294
 295         this->IO_ADDR_R = this->IO_ADDR_W;
 296
 297         /* Drain the writebuffer */
 298         au_sync();
 299 }
 300
 301 int au1550_device_ready(struct mtd_info *mtd)
 302 {
 303         int ret = (au_readl(MEM_STSTAT) & 0x1) ? 1 : 0;
 304         au_sync();
 305         return ret;
 306 }
 307
 308 /**
 309  * au1550_select_chip - control -CE line
 310  *      Forbid driving -CE manually permitting the NAND controller to do this.
 311  *      Keeping -CE asserted during the whole sector reads interferes with the
 312  *      NOR flash and PCMCIA drivers as it causes contention on the static bus.
 313  *      We only have to hold -CE low for the NAND read commands since the flash
 314  *      chip needs it to be asserted during chip not ready time but the NAND
 315  *      controller keeps it released.
 316  *
 317  * @mtd:        MTD device structure
 318  * @chip:       chipnumber to select, -1 for deselect
 319  */
 320 static void au1550_select_chip(struct mtd_info *mtd, int chip)
 321 {
 322 }
 323
 324 /**
 325  * au1550_command - Send command to NAND device
 326  * @mtd:        MTD device structure
 327  * @command:    the command to be sent
 328  * @column:     the column address for this command, -1 if none
 329  * @page_addr:  the page address for this command, -1 if none
 330  */
 331 static void au1550_command(struct mtd_info *mtd, unsigned command, int column, int page_addr)
 332 {
 333         register struct nand_chip *this = mtd->priv;
 334         int ce_override = 0, i;
 335         ulong flags;
 336
 337         /* Begin command latch cycle */
 338         au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
 339         /*
 340          * Write out the command to the device.
 341          */
 342         if (command == NAND_CMD_SEQIN) {
 343                 int readcmd;
 344
 345                 if (column >= mtd->writesize) {
 346                         /* OOB area */
 347                         column -= mtd->writesize;
 348                         readcmd = NAND_CMD_READOOB;
 349                 } else if (column < 256) {
 350                         /* First 256 bytes --> READ0 */
 351                         readcmd = NAND_CMD_READ0;
 352                 } else {
 353                         column -= 256;
 354                         readcmd = NAND_CMD_READ1;
 355                 }
 356                 au1550_write_byte(mtd, readcmd);
 357         }
 358         au1550_write_byte(mtd, command);
 359
 360         /* Set ALE and clear CLE to start address cycle */
 361         au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
 362
 363         if (column != -1 || page_addr != -1) {
 364                 au1550_hwcontrol(mtd, NAND_CTL_SETALE);
 365
 366                 /* Serially input address */
 367                 if (column != -1) {
 368                         /* Adjust columns for 16 bit buswidth */
 369                         if (this->options & NAND_BUSWIDTH_16)
 370                                 column >>= 1;
 371                         au1550_write_byte(mtd, column);
 372                 }
 373                 if (page_addr != -1) {
 374                         au1550_write_byte(mtd, (u8)(page_addr & 0xff));
 375
 376                         if (command == NAND_CMD_READ0 ||
 377                             command == NAND_CMD_READ1 ||
 378                             command == NAND_CMD_READOOB) {
 379                                 /*
 380                                  * NAND controller will release -CE after
 381                                  * the last address byte is written, so we'll
 382                                  * have to forcibly assert it. No interrupts
 383                                  * are allowed while we do this as we don't
 384                                  * want the NOR flash or PCMCIA drivers to
 385                                  * steal our precious bytes of data...
 386                                  */
 387                                 ce_override = 1;
 388                                 local_irq_save(flags);
 389                                 au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
 390                         }
 391
 392                         au1550_write_byte(mtd, (u8)(page_addr >> 8));
 393
 394                         /* One more address cycle for devices > 32MiB */
 395                         if (this->chipsize > (32 << 20))
 396                                 au1550_write_byte(mtd, (u8)((page_addr >> 16) & 0x0f));
 397                 }
 398                 /* Latch in address */
 399                 au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
 400         }
 401
 402         /*
 403          * Program and erase have their own busy handlers.
 404          * Status and sequential in need no delay.
 405          */
 406         switch (command) {
 407
 408         case NAND_CMD_PAGEPROG:
 409         case NAND_CMD_ERASE1:
 410         case NAND_CMD_ERASE2:
 411         case NAND_CMD_SEQIN:
 412         case NAND_CMD_STATUS:
 413                 return;
 414
 415         case NAND_CMD_RESET:
 416                 break;
 417
 418         case NAND_CMD_READ0:
 419         case NAND_CMD_READ1:
 420         case NAND_CMD_READOOB:
 421                 /* Check if we're really driving -CE low (just in case) */
 422                 if (unlikely(!ce_override))
 423                         break;
 424
 425                 /* Apply a short delay always to ensure that we do wait tWB. */
 426                 ndelay(100);
 427                 /* Wait for a chip to become ready... */
 428                 for (i = this->chip_delay; !this->dev_ready(mtd) && i > 0; --i)
 429                         udelay(1);
 430
 431                 /* Release -CE and re-enable interrupts. */
 432                 au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
 433                 local_irq_restore(flags);
 434                 return;
 435         }
 436         /* Apply this short delay always to ensure that we do wait tWB. */
 437         ndelay(100);
 438
 439         while(!this->dev_ready(mtd));
 440 }
 441
 442
 443 /*
 444  * Main initialization routine
 445  */
 446 static int __init au1xxx_nand_init(void)
 447 {
 448         struct nand_chip *this;
 449         u16 boot_swapboot = 0;  /* default value */
 450         int retval;
 451         u32 mem_staddr;
 452         u32 nand_phys;
 453
 454         /* Allocate memory for MTD device structure and private data */
 455         au1550_mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct nand_chip), GFP_KERNEL);
 456         if (!au1550_mtd) {
 457                 printk("Unable to allocate NAND MTD dev structure.\n");
 458                 return -ENOMEM;
 459         }
 460
 461         /* Get pointer to private data */
 462         this = (struct nand_chip *)(&au1550_mtd[1]);
 463
 464         /* Link the private data with the MTD structure */
 465         au1550_mtd->priv = this;
 466         au1550_mtd->owner = THIS_MODULE;
 467
 468
 469         /* MEM_STNDCTL: disable ints, disable nand boot */
 470         au_writel(0, MEM_STNDCTL);
 471
 472 #ifdef CONFIG_MIPS_PB1550
 473         /* set gpio206 high */
 474         gpio_direction_input(206);
 475
 476         boot_swapboot = (au_readl(MEM_STSTAT) & (0x7 << 1)) | ((bcsr_read(BCSR_STATUS) >> 6) & 0x1);
 477
 478         switch (boot_swapboot) {
 479         case 0:
 480         case 2:
 481         case 8:
 482         case 0xC:
 483         case 0xD:
 484                 /* x16 NAND Flash */
 485                 nand_width = 0;
 486                 break;
 487         case 1:
 488         case 9:
 489         case 3:
 490         case 0xE:
 491         case 0xF:
 492                 /* x8 NAND Flash */
 493                 nand_width = 1;
 494                 break;
 495         default:
 496                 printk("Pb1550 NAND: bad boot:swap\n");
 497                 retval = -EINVAL;
 498                 goto outmem;
 499         }
 500 #endif
 501
 502         /* Configure chip-select; normally done by boot code, e.g. YAMON */
 503 #ifdef NAND_STCFG
 504         if (NAND_CS == 0) {
 505                 au_writel(NAND_STCFG,  MEM_STCFG0);
 506                 au_writel(NAND_STTIME, MEM_STTIME0);
 507                 au_writel(NAND_STADDR, MEM_STADDR0);
 508         }
 509         if (NAND_CS == 1) {
 510                 au_writel(NAND_STCFG,  MEM_STCFG1);
 511                 au_writel(NAND_STTIME, MEM_STTIME1);
 512                 au_writel(NAND_STADDR, MEM_STADDR1);
 513         }
 514         if (NAND_CS == 2) {
 515                 au_writel(NAND_STCFG,  MEM_STCFG2);
 516                 au_writel(NAND_STTIME, MEM_STTIME2);
 517                 au_writel(NAND_STADDR, MEM_STADDR2);
 518         }
 519         if (NAND_CS == 3) {
 520                 au_writel(NAND_STCFG,  MEM_STCFG3);
 521                 au_writel(NAND_STTIME, MEM_STTIME3);
 522                 au_writel(NAND_STADDR, MEM_STADDR3);
 523         }
 524 #endif
 525
 526         /* Locate NAND chip-select in order to determine NAND phys address */
 527         mem_staddr = 0x00000000;
 528         if (((au_readl(MEM_STCFG0) & 0x7) == 0x5) && (NAND_CS == 0))
 529                 mem_staddr = au_readl(MEM_STADDR0);
 530         else if (((au_readl(MEM_STCFG1) & 0x7) == 0x5) && (NAND_CS == 1))
 531                 mem_staddr = au_readl(MEM_STADDR1);
 532         else if (((au_readl(MEM_STCFG2) & 0x7) == 0x5) && (NAND_CS == 2))
 533                 mem_staddr = au_readl(MEM_STADDR2);
 534         else if (((au_readl(MEM_STCFG3) & 0x7) == 0x5) && (NAND_CS == 3))
 535                 mem_staddr = au_readl(MEM_STADDR3);
 536
 537         if (mem_staddr == 0x00000000) {
 538                 printk("Au1xxx NAND: ERROR WITH NAND CHIP-SELECT\n");
 539                 kfree(au1550_mtd);
 540                 return 1;
 541         }
 542         nand_phys = (mem_staddr << 4) & 0xFFFC0000;
 543
 544         p_nand = ioremap(nand_phys, 0x1000);
 545
 546         /* make controller and MTD agree */
 547         if (NAND_CS == 0)
 548                 nand_width = au_readl(MEM_STCFG0) & (1 << 22);
 549         if (NAND_CS == 1)
 550                 nand_width = au_readl(MEM_STCFG1) & (1 << 22);
 551         if (NAND_CS == 2)
 552                 nand_width = au_readl(MEM_STCFG2) & (1 << 22);
 553         if (NAND_CS == 3)
 554                 nand_width = au_readl(MEM_STCFG3) & (1 << 22);
 555
 556         /* Set address of hardware control function */
 557         this->dev_ready = au1550_device_ready;
 558         this->select_chip = au1550_select_chip;
 559         this->cmdfunc = au1550_command;
 560
 561         /* 30 us command delay time */
 562         this->chip_delay = 30;
 563         this->ecc.mode = NAND_ECC_SOFT;
 564
 565         this->options = NAND_NO_AUTOINCR;
 566
 567         if (!nand_width)
 568                 this->options |= NAND_BUSWIDTH_16;
 569
 570         this->read_byte = (!nand_width) ? au_read_byte16 : au_read_byte;
 571         au1550_write_byte = (!nand_width) ? au_write_byte16 : au_write_byte;
 572         this->read_word = au_read_word;
 573         this->write_buf = (!nand_width) ? au_write_buf16 : au_write_buf;
 574         this->read_buf = (!nand_width) ? au_read_buf16 : au_read_buf;
 575         this->verify_buf = (!nand_width) ? au_verify_buf16 : au_verify_buf;
 576
 577         /* Scan to find existence of the device */
 578         if (nand_scan(au1550_mtd, 1)) {
 579                 retval = -ENXIO;
 580                 goto outio;
 581         }
 582
 583         /* Register the partitions */
 584         mtd_device_register(au1550_mtd, partition_info,
 585                             ARRAY_SIZE(partition_info));
 586
 587         return 0;
 588
 589  outio:
 590         iounmap(p_nand);
 591
 592  outmem:
 593         kfree(au1550_mtd);
 594         return retval;
 595 }
 596
 597 module_init(au1xxx_nand_init);
 598
 599 /*
 600  * Clean up routine
 601  */
 602 static void __exit au1550_cleanup(void)
 603 {
 604         /* Release resources, unregister device */
 605         nand_release(au1550_mtd);
 606
 607         /* Free the MTD device structure */
 608         kfree(au1550_mtd);
 609
 610         /* Unmap */
 611         iounmap(p_nand);
 612 }
 613
 614 module_exit(au1550_cleanup);
 615
 616 MODULE_LICENSE("GPL");
 617 MODULE_AUTHOR("Embedded Edge, LLC");
 618 MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on Pb1550 board");