drivers/mtd/nand/bcm47xxnflash/ops_bcm4706.c

   1 /*
   2  * BCM47XX NAND flash driver
   3  *
   4  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include "bcm47xxnflash.h"
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/slab.h>
  17 #include <linux/delay.h>
  18 #include <linux/bcma/bcma.h>
  19
  20 /* Broadcom uses 1'000'000 but it seems to be too many. Tests on WNDR4500 has
  21  * shown ~1000 retries as maxiumum. */
  22 #define NFLASH_READY_RETRIES            10000
  23
  24 #define NFLASH_SECTOR_SIZE              512
  25
  26 #define NCTL_CMD0                       0x00010000
  27 #define NCTL_CMD1W                      0x00080000
  28 #define NCTL_READ                       0x00100000
  29 #define NCTL_WRITE                      0x00200000
  30 #define NCTL_SPECADDR                   0x01000000
  31 #define NCTL_READY                      0x04000000
  32 #define NCTL_ERR                        0x08000000
  33 #define NCTL_CSA                        0x40000000
  34 #define NCTL_START                      0x80000000
  35
  36 /**************************************************
  37  * Various helpers
  38  **************************************************/
  39
  40 static inline u8 bcm47xxnflash_ops_bcm4706_ns_to_cycle(u16 ns, u16 clock)
  41 {
  42         return ((ns * 1000 * clock) / 1000000) + 1;
  43 }
  44
  45 static int bcm47xxnflash_ops_bcm4706_ctl_cmd(struct bcma_drv_cc *cc, u32 code)
  46 {
  47         int i = 0;
  48
  49         bcma_cc_write32(cc, BCMA_CC_NFLASH_CTL, NCTL_START | code);
  50         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  51                 if (!(bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_START)) {
  52                         i = 0;
  53                         break;
  54                 }
  55         }
  56         if (i) {
  57                 pr_err("NFLASH control command not ready!\n");
  58                 return -EBUSY;
  59         }
  60         return 0;
  61 }
  62
  63 static int bcm47xxnflash_ops_bcm4706_poll(struct bcma_drv_cc *cc)
  64 {
  65         int i;
  66
  67         for (i = 0; i < NFLASH_READY_RETRIES; i++) {
  68                 if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) & NCTL_READY) {
  69                         if (bcma_cc_read32(cc, BCMA_CC_NFLASH_CTL) &
  70                             BCMA_CC_NFLASH_CTL_ERR) {
  71                                 pr_err("Error on polling\n");
  72                                 return -EBUSY;
  73                         } else {
  74                                 return 0;
  75                         }
  76                 }
  77         }
  78
  79         pr_err("Polling timeout!\n");
  80         return -EBUSY;
  81 }
  82
  83 /**************************************************
  84  * R/W
  85  **************************************************/
  86
  87 static void bcm47xxnflash_ops_bcm4706_read(struct mtd_info *mtd, uint8_t *buf,
  88                                            int len)
  89 {
  90         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
  91         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
  92
  93         u32 ctlcode;
  94         u32 *dest = (u32 *)buf;
  95         int i;
  96         int toread;
  97
  98         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
  99         /* Don't validate column using nand_chip->page_shift, it may be bigger
 100          * when accessing OOB */
 101
 102         while (len) {
 103                 /* We can read maximum of 0x200 bytes at once */
 104                 toread = min(len, 0x200);
 105
 106                 /* Set page and column */
 107                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_COL_ADDR,
 108                                 b47n->curr_column);
 109                 bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_ROW_ADDR,
 110                                 b47n->curr_page_addr);
 111
 112                 /* Prepare to read */
 113                 ctlcode = NCTL_CSA | NCTL_CMD1W | 0x00040000 | 0x00020000 |
 114                           NCTL_CMD0;
 115                 ctlcode |= NAND_CMD_READSTART << 8;
 116                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode))
 117                         return;
 118                 if (bcm47xxnflash_ops_bcm4706_poll(b47n->cc))
 119                         return;
 120
 121                 /* Eventually read some data :) */
 122                 for (i = 0; i < toread; i += 4, dest++) {
 123                         ctlcode = NCTL_CSA | 0x30000000 | NCTL_READ;
 124                         if (i == toread - 4) /* Last read goes without that */
 125                                 ctlcode &= ~NCTL_CSA;
 126                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 127                                                               ctlcode))
 128                                 return;
 129                         *dest = bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA);
 130                 }
 131
 132                 b47n->curr_column += toread;
 133                 len -= toread;
 134         }
 135 }
 136
 137 static void bcm47xxnflash_ops_bcm4706_write(struct mtd_info *mtd,
 138                                             const uint8_t *buf, int len)
 139 {
 140         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 141         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 142         struct bcma_drv_cc *cc = b47n->cc;
 143
 144         u32 ctlcode;
 145         const u32 *data = (u32 *)buf;
 146         int i;
 147
 148         BUG_ON(b47n->curr_page_addr & ~nand_chip->pagemask);
 149         /* Don't validate column using nand_chip->page_shift, it may be bigger
 150          * when accessing OOB */
 151
 152         for (i = 0; i < len; i += 4, data++) {
 153                 bcma_cc_write32(cc, BCMA_CC_NFLASH_DATA, *data);
 154
 155                 ctlcode = NCTL_CSA | 0x30000000 | NCTL_WRITE;
 156                 if (i == len - 4) /* Last read goes without that */
 157                         ctlcode &= ~NCTL_CSA;
 158                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode)) {
 159                         pr_err("%s ctl_cmd didn't work!\n", __func__);
 160                         return;
 161                 }
 162         }
 163
 164         b47n->curr_column += len;
 165 }
 166
 167 /**************************************************
 168  * NAND chip ops
 169  **************************************************/
 170
 171 static void bcm47xxnflash_ops_bcm4706_cmd_ctrl(struct mtd_info *mtd, int cmd,
 172                                                unsigned int ctrl)
 173 {
 174         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 175         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 176         u32 code = 0;
 177
 178         if (cmd == NAND_CMD_NONE)
 179                 return;
 180
 181         if (cmd & NAND_CTRL_CLE)
 182                 code = cmd | NCTL_CMD0;
 183
 184         /* nCS is not needed for reset command */
 185         if (cmd != NAND_CMD_RESET)
 186                 code |= NCTL_CSA;
 187
 188         bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, code);
 189 }
 190
 191 /* Default nand_select_chip calls cmd_ctrl, which is not used in BCM4706 */
 192 static void bcm47xxnflash_ops_bcm4706_select_chip(struct mtd_info *mtd,
 193                                                   int chip)
 194 {
 195         return;
 196 }
 197
 198 static int bcm47xxnflash_ops_bcm4706_dev_ready(struct mtd_info *mtd)
 199 {
 200         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 201         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 202
 203         return !!(bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_CTL) & NCTL_READY);
 204 }
 205
 206 /*
 207  * Default nand_command and nand_command_lp don't match BCM4706 hardware layout.
 208  * For example, reading chip id is performed in a non-standard way.
 209  * Setting column and page is also handled differently, we use a special
 210  * registers of ChipCommon core. Hacking cmd_ctrl to understand and convert
 211  * standard commands would be much more complicated.
 212  */
 213 static void bcm47xxnflash_ops_bcm4706_cmdfunc(struct mtd_info *mtd,
 214                                               unsigned command, int column,
 215                                               int page_addr)
 216 {
 217         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 218         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 219         struct bcma_drv_cc *cc = b47n->cc;
 220         u32 ctlcode;
 221         int i;
 222
 223         if (column != -1)
 224                 b47n->curr_column = column;
 225         if (page_addr != -1)
 226                 b47n->curr_page_addr = page_addr;
 227
 228         switch (command) {
 229         case NAND_CMD_RESET:
 230                 nand_chip->cmd_ctrl(mtd, command, NAND_CTRL_CLE);
 231
 232                 ndelay(100);
 233                 nand_wait_ready(mtd);
 234                 break;
 235         case NAND_CMD_READID:
 236                 ctlcode = NCTL_CSA | 0x01000000 | NCTL_CMD1W | NCTL_CMD0;
 237                 ctlcode |= NAND_CMD_READID;
 238                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc, ctlcode)) {
 239                         pr_err("READID error\n");
 240                         break;
 241                 }
 242
 243                 /*
 244                  * Reading is specific, last one has to go without NCTL_CSA
 245                  * bit. We don't know how many reads NAND subsystem is going
 246                  * to perform, so cache everything.
 247                  */
 248                 for (i = 0; i < ARRAY_SIZE(b47n->id_data); i++) {
 249                         ctlcode = NCTL_CSA | NCTL_READ;
 250                         if (i == ARRAY_SIZE(b47n->id_data) - 1)
 251                                 ctlcode &= ~NCTL_CSA;
 252                         if (bcm47xxnflash_ops_bcm4706_ctl_cmd(b47n->cc,
 253                                                               ctlcode)) {
 254                                 pr_err("READID error\n");
 255                                 break;
 256                         }
 257                         b47n->id_data[i] =
 258                                 bcma_cc_read32(b47n->cc, BCMA_CC_NFLASH_DATA)
 259                                 & 0xFF;
 260                 }
 261
 262                 break;
 263         case NAND_CMD_STATUS:
 264                 ctlcode = NCTL_CSA | NCTL_CMD0 | NAND_CMD_STATUS;
 265                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 266                         pr_err("STATUS command error\n");
 267                 break;
 268         case NAND_CMD_READ0:
 269                 break;
 270         case NAND_CMD_READOOB:
 271                 if (page_addr != -1)
 272                         b47n->curr_column += mtd->writesize;
 273                 break;
 274         case NAND_CMD_ERASE1:
 275                 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
 276                                 b47n->curr_page_addr);
 277                 ctlcode = 0x00040000 | NCTL_CMD1W | NCTL_CMD0 |
 278                           NAND_CMD_ERASE1 | (NAND_CMD_ERASE2 << 8);
 279                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 280                         pr_err("ERASE1 failed\n");
 281                 break;
 282         case NAND_CMD_ERASE2:
 283                 break;
 284         case NAND_CMD_SEQIN:
 285                 /* Set page and column */
 286                 bcma_cc_write32(cc, BCMA_CC_NFLASH_COL_ADDR,
 287                                 b47n->curr_column);
 288                 bcma_cc_write32(cc, BCMA_CC_NFLASH_ROW_ADDR,
 289                                 b47n->curr_page_addr);
 290
 291                 /* Prepare to write */
 292                 ctlcode = 0x40000000 | 0x00040000 | 0x00020000 | 0x00010000;
 293                 ctlcode |= NAND_CMD_SEQIN;
 294                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, ctlcode))
 295                         pr_err("SEQIN failed\n");
 296                 break;
 297         case NAND_CMD_PAGEPROG:
 298                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, 0x00010000 |
 299                                                           NAND_CMD_PAGEPROG))
 300                         pr_err("PAGEPROG failed\n");
 301                 if (bcm47xxnflash_ops_bcm4706_poll(cc))
 302                         pr_err("PAGEPROG not ready\n");
 303                 break;
 304         default:
 305                 pr_err("Command 0x%X unsupported\n", command);
 306                 break;
 307         }
 308         b47n->curr_command = command;
 309 }
 310
 311 static u8 bcm47xxnflash_ops_bcm4706_read_byte(struct mtd_info *mtd)
 312 {
 313         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 314         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 315         struct bcma_drv_cc *cc = b47n->cc;
 316         u32 tmp = 0;
 317
 318         switch (b47n->curr_command) {
 319         case NAND_CMD_READID:
 320                 if (b47n->curr_column >= ARRAY_SIZE(b47n->id_data)) {
 321                         pr_err("Requested invalid id_data: %d\n",
 322                                b47n->curr_column);
 323                         return 0;
 324                 }
 325                 return b47n->id_data[b47n->curr_column++];
 326         case NAND_CMD_STATUS:
 327                 if (bcm47xxnflash_ops_bcm4706_ctl_cmd(cc, NCTL_READ))
 328                         return 0;
 329                 return bcma_cc_read32(cc, BCMA_CC_NFLASH_DATA) & 0xff;
 330         case NAND_CMD_READOOB:
 331                 bcm47xxnflash_ops_bcm4706_read(mtd, (u8 *)&tmp, 4);
 332                 return tmp & 0xFF;
 333         }
 334
 335         pr_err("Invalid command for byte read: 0x%X\n", b47n->curr_command);
 336         return 0;
 337 }
 338
 339 static void bcm47xxnflash_ops_bcm4706_read_buf(struct mtd_info *mtd,
 340                                                uint8_t *buf, int len)
 341 {
 342         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 343         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 344
 345         switch (b47n->curr_command) {
 346         case NAND_CMD_READ0:
 347         case NAND_CMD_READOOB:
 348                 bcm47xxnflash_ops_bcm4706_read(mtd, buf, len);
 349                 return;
 350         }
 351
 352         pr_err("Invalid command for buf read: 0x%X\n", b47n->curr_command);
 353 }
 354
 355 static void bcm47xxnflash_ops_bcm4706_write_buf(struct mtd_info *mtd,
 356                                                 const uint8_t *buf, int len)
 357 {
 358         struct nand_chip *nand_chip = (struct nand_chip *)mtd->priv;
 359         struct bcm47xxnflash *b47n = (struct bcm47xxnflash *)nand_chip->priv;
 360
 361         switch (b47n->curr_command) {
 362         case NAND_CMD_SEQIN:
 363                 bcm47xxnflash_ops_bcm4706_write(mtd, buf, len);
 364                 return;
 365         }
 366
 367         pr_err("Invalid command for buf write: 0x%X\n", b47n->curr_command);
 368 }
 369
 370 /**************************************************
 371  * Init
 372  **************************************************/
 373
 374 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n)
 375 {
 376         struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip;
 377         int err;
 378         u32 freq;
 379         u16 clock;
 380         u8 w0, w1, w2, w3, w4;
 381
 382         unsigned long chipsize; /* MiB */
 383         u8 tbits, col_bits, col_size, row_bits, row_bsize;
 384         u32 val;
 385
 386         b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
 387         nand_chip->cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
 388         nand_chip->dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
 389         b47n->nand_chip.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
 390         b47n->nand_chip.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
 391         b47n->nand_chip.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
 392         b47n->nand_chip.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
 393
 394         nand_chip->chip_delay = 50;
 395         b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
 396         b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
 397
 398         /* Enable NAND flash access */
 399         bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 400                       BCMA_CC_4706_FLASHSCFG_NF1);
 401
 402         /* Configure wait counters */
 403         if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
 404                 /* 400 MHz */
 405                 freq = 400000000 / 4;
 406         } else {
 407                 freq = bcma_chipco_pll_read(b47n->cc, 4);
 408                 freq = (freq & 0xFFF) >> 3;
 409                 /* Fixed reference clock 25 MHz and m = 2 */
 410                 freq = (freq * 25000000 / 2) / 4;
 411         }
 412         clock = freq / 1000000;
 413         w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
 414         w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
 415         w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 416         w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
 417         w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
 418         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0,
 419                         (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
 420
 421         /* Scan NAND */
 422         err = nand_scan(&b47n->mtd, 1);
 423         if (err) {
 424                 pr_err("Could not scan NAND flash: %d\n", err);
 425                 goto exit;
 426         }
 427
 428         /* Configure FLASH */
 429         chipsize = b47n->nand_chip.chipsize >> 20;
 430         tbits = ffs(chipsize); /* find first bit set */
 431         if (!tbits || tbits != fls(chipsize)) {
 432                 pr_err("Invalid flash size: 0x%lX\n", chipsize);
 433                 err = -ENOTSUPP;
 434                 goto exit;
 435         }
 436         tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
 437
 438         col_bits = b47n->nand_chip.page_shift + 1;
 439         col_size = (col_bits + 7) / 8;
 440
 441         row_bits = tbits - col_bits + 1;
 442         row_bsize = (row_bits + 7) / 8;
 443
 444         val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
 445         bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
 446
 447 exit:
 448         if (err)
 449                 bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG,
 450                                ~BCMA_CC_4706_FLASHSCFG_NF1);
 451         return err;
 452 }