projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'cec-defines' into for-linus
[deliverable/linux.git] / drivers / mtd / nand / brcmnand / brcmnand.c
1 /*
2 * Copyright © 2010-2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/version.h>
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/err.h>
22 #include <linux/completion.h>
23 #include <linux/interrupt.h>
24 #include <linux/spinlock.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/ioport.h>
27 #include <linux/bug.h>
28 #include <linux/kernel.h>
29 #include <linux/bitops.h>
30 #include <linux/mm.h>
31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/of.h>
35 #include <linux/of_mtd.h>
36 #include <linux/of_platform.h>
37 #include <linux/slab.h>
38 #include <linux/list.h>
39 #include <linux/log2.h>
40
41 #include "brcmnand.h"
42
43 /*
44 * This flag controls if WP stays on between erase/write commands to mitigate
45 * flash corruption due to power glitches. Values:
46 * 0: NAND_WP is not used or not available
47 * 1: NAND_WP is set by default, cleared for erase/write operations
48 * 2: NAND_WP is always cleared
49 */
50 static int wp_on = 1;
51 module_param(wp_on, int, 0444);
52
53 /***********************************************************************
54 * Definitions
55 ***********************************************************************/
56
57 #define DRV_NAME "brcmnand"
58
59 #define CMD_NULL 0x00
60 #define CMD_PAGE_READ 0x01
61 #define CMD_SPARE_AREA_READ 0x02
62 #define CMD_STATUS_READ 0x03
63 #define CMD_PROGRAM_PAGE 0x04
64 #define CMD_PROGRAM_SPARE_AREA 0x05
65 #define CMD_COPY_BACK 0x06
66 #define CMD_DEVICE_ID_READ 0x07
67 #define CMD_BLOCK_ERASE 0x08
68 #define CMD_FLASH_RESET 0x09
69 #define CMD_BLOCKS_LOCK 0x0a
70 #define CMD_BLOCKS_LOCK_DOWN 0x0b
71 #define CMD_BLOCKS_UNLOCK 0x0c
72 #define CMD_READ_BLOCKS_LOCK_STATUS 0x0d
73 #define CMD_PARAMETER_READ 0x0e
74 #define CMD_PARAMETER_CHANGE_COL 0x0f
75 #define CMD_LOW_LEVEL_OP 0x10
76
77 struct brcm_nand_dma_desc {
78 u32 next_desc;
79 u32 next_desc_ext;
80 u32 cmd_irq;
81 u32 dram_addr;
82 u32 dram_addr_ext;
83 u32 tfr_len;
84 u32 total_len;
85 u32 flash_addr;
86 u32 flash_addr_ext;
87 u32 cs;
88 u32 pad2[5];
89 u32 status_valid;
90 } __packed;
91
92 /* Bitfields for brcm_nand_dma_desc::status_valid */
93 #define FLASH_DMA_ECC_ERROR (1 << 8)
94 #define FLASH_DMA_CORR_ERROR (1 << 9)
95
96 /* 512B flash cache in the NAND controller HW */
97 #define FC_SHIFT 9U
98 #define FC_BYTES 512U
99 #define FC_WORDS (FC_BYTES >> 2)
100
101 #define BRCMNAND_MIN_PAGESIZE 512
102 #define BRCMNAND_MIN_BLOCKSIZE (8 * 1024)
103 #define BRCMNAND_MIN_DEVSIZE (4ULL * 1024 * 1024)
104
105 /* Controller feature flags */
106 enum {
107 BRCMNAND_HAS_1K_SECTORS = BIT(0),
108 BRCMNAND_HAS_PREFETCH = BIT(1),
109 BRCMNAND_HAS_CACHE_MODE = BIT(2),
110 BRCMNAND_HAS_WP = BIT(3),
111 };
112
113 struct brcmnand_controller {
114 struct device *dev;
115 struct nand_hw_control controller;
116 void __iomem *nand_base;
117 void __iomem *nand_fc; /* flash cache */
118 void __iomem *flash_dma_base;
119 unsigned int irq;
120 unsigned int dma_irq;
121 int nand_version;
122
123 /* Some SoCs provide custom interrupt status register(s) */
124 struct brcmnand_soc *soc;
125
126 /* Some SoCs have a gateable clock for the controller */
127 struct clk *clk;
128
129 int cmd_pending;
130 bool dma_pending;
131 struct completion done;
132 struct completion dma_done;
133
134 /* List of NAND hosts (one for each chip-select) */
135 struct list_head host_list;
136
137 struct brcm_nand_dma_desc *dma_desc;
138 dma_addr_t dma_pa;
139
140 /* in-memory cache of the FLASH_CACHE, used only for some commands */
141 u8 flash_cache[FC_BYTES];
142
143 /* Controller revision details */
144 const u16 *reg_offsets;
145 unsigned int reg_spacing; /* between CS1, CS2, ... regs */
146 const u8 *cs_offsets; /* within each chip-select */
147 const u8 *cs0_offsets; /* within CS0, if different */
148 unsigned int max_block_size;
149 const unsigned int *block_sizes;
150 unsigned int max_page_size;
151 const unsigned int *page_sizes;
152 unsigned int max_oob;
153 u32 features;
154
155 /* for low-power standby/resume only */
156 u32 nand_cs_nand_select;
157 u32 nand_cs_nand_xor;
158 u32 corr_stat_threshold;
159 u32 flash_dma_mode;
160 };
161
162 struct brcmnand_cfg {
163 u64 device_size;
164 unsigned int block_size;
165 unsigned int page_size;
166 unsigned int spare_area_size;
167 unsigned int device_width;
168 unsigned int col_adr_bytes;
169 unsigned int blk_adr_bytes;
170 unsigned int ful_adr_bytes;
171 unsigned int sector_size_1k;
172 unsigned int ecc_level;
173 /* use for low-power standby/resume only */
174 u32 acc_control;
175 u32 config;
176 u32 config_ext;
177 u32 timing_1;
178 u32 timing_2;
179 };
180
181 struct brcmnand_host {
182 struct list_head node;
183
184 struct nand_chip chip;
185 struct platform_device *pdev;
186 int cs;
187
188 unsigned int last_cmd;
189 unsigned int last_byte;
190 u64 last_addr;
191 struct brcmnand_cfg hwcfg;
192 struct brcmnand_controller *ctrl;
193 };
194
195 enum brcmnand_reg {
196 BRCMNAND_CMD_START = 0,
197 BRCMNAND_CMD_EXT_ADDRESS,
198 BRCMNAND_CMD_ADDRESS,
199 BRCMNAND_INTFC_STATUS,
200 BRCMNAND_CS_SELECT,
201 BRCMNAND_CS_XOR,
202 BRCMNAND_LL_OP,
203 BRCMNAND_CS0_BASE,
204 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
205 BRCMNAND_CORR_THRESHOLD,
206 BRCMNAND_CORR_THRESHOLD_EXT,
207 BRCMNAND_UNCORR_COUNT,
208 BRCMNAND_CORR_COUNT,
209 BRCMNAND_CORR_EXT_ADDR,
210 BRCMNAND_CORR_ADDR,
211 BRCMNAND_UNCORR_EXT_ADDR,
212 BRCMNAND_UNCORR_ADDR,
213 BRCMNAND_SEMAPHORE,
214 BRCMNAND_ID,
215 BRCMNAND_ID_EXT,
216 BRCMNAND_LL_RDATA,
217 BRCMNAND_OOB_READ_BASE,
218 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
219 BRCMNAND_OOB_WRITE_BASE,
220 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
221 BRCMNAND_FC_BASE,
222 };
223
224 /* BRCMNAND v4.0 */
225 static const u16 brcmnand_regs_v40[] = {
226 [BRCMNAND_CMD_START] = 0x04,
227 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
228 [BRCMNAND_CMD_ADDRESS] = 0x0c,
229 [BRCMNAND_INTFC_STATUS] = 0x6c,
230 [BRCMNAND_CS_SELECT] = 0x14,
231 [BRCMNAND_CS_XOR] = 0x18,
232 [BRCMNAND_LL_OP] = 0x178,
233 [BRCMNAND_CS0_BASE] = 0x40,
234 [BRCMNAND_CS1_BASE] = 0xd0,
235 [BRCMNAND_CORR_THRESHOLD] = 0x84,
236 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
237 [BRCMNAND_UNCORR_COUNT] = 0,
238 [BRCMNAND_CORR_COUNT] = 0,
239 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
240 [BRCMNAND_CORR_ADDR] = 0x74,
241 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
242 [BRCMNAND_UNCORR_ADDR] = 0x7c,
243 [BRCMNAND_SEMAPHORE] = 0x58,
244 [BRCMNAND_ID] = 0x60,
245 [BRCMNAND_ID_EXT] = 0x64,
246 [BRCMNAND_LL_RDATA] = 0x17c,
247 [BRCMNAND_OOB_READ_BASE] = 0x20,
248 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
249 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
250 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
251 [BRCMNAND_FC_BASE] = 0x200,
252 };
253
254 /* BRCMNAND v5.0 */
255 static const u16 brcmnand_regs_v50[] = {
256 [BRCMNAND_CMD_START] = 0x04,
257 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
258 [BRCMNAND_CMD_ADDRESS] = 0x0c,
259 [BRCMNAND_INTFC_STATUS] = 0x6c,
260 [BRCMNAND_CS_SELECT] = 0x14,
261 [BRCMNAND_CS_XOR] = 0x18,
262 [BRCMNAND_LL_OP] = 0x178,
263 [BRCMNAND_CS0_BASE] = 0x40,
264 [BRCMNAND_CS1_BASE] = 0xd0,
265 [BRCMNAND_CORR_THRESHOLD] = 0x84,
266 [BRCMNAND_CORR_THRESHOLD_EXT] = 0,
267 [BRCMNAND_UNCORR_COUNT] = 0,
268 [BRCMNAND_CORR_COUNT] = 0,
269 [BRCMNAND_CORR_EXT_ADDR] = 0x70,
270 [BRCMNAND_CORR_ADDR] = 0x74,
271 [BRCMNAND_UNCORR_EXT_ADDR] = 0x78,
272 [BRCMNAND_UNCORR_ADDR] = 0x7c,
273 [BRCMNAND_SEMAPHORE] = 0x58,
274 [BRCMNAND_ID] = 0x60,
275 [BRCMNAND_ID_EXT] = 0x64,
276 [BRCMNAND_LL_RDATA] = 0x17c,
277 [BRCMNAND_OOB_READ_BASE] = 0x20,
278 [BRCMNAND_OOB_READ_10_BASE] = 0x130,
279 [BRCMNAND_OOB_WRITE_BASE] = 0x30,
280 [BRCMNAND_OOB_WRITE_10_BASE] = 0x140,
281 [BRCMNAND_FC_BASE] = 0x200,
282 };
283
284 /* BRCMNAND v6.0 - v7.1 */
285 static const u16 brcmnand_regs_v60[] = {
286 [BRCMNAND_CMD_START] = 0x04,
287 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
288 [BRCMNAND_CMD_ADDRESS] = 0x0c,
289 [BRCMNAND_INTFC_STATUS] = 0x14,
290 [BRCMNAND_CS_SELECT] = 0x18,
291 [BRCMNAND_CS_XOR] = 0x1c,
292 [BRCMNAND_LL_OP] = 0x20,
293 [BRCMNAND_CS0_BASE] = 0x50,
294 [BRCMNAND_CS1_BASE] = 0,
295 [BRCMNAND_CORR_THRESHOLD] = 0xc0,
296 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xc4,
297 [BRCMNAND_UNCORR_COUNT] = 0xfc,
298 [BRCMNAND_CORR_COUNT] = 0x100,
299 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
300 [BRCMNAND_CORR_ADDR] = 0x110,
301 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
302 [BRCMNAND_UNCORR_ADDR] = 0x118,
303 [BRCMNAND_SEMAPHORE] = 0x150,
304 [BRCMNAND_ID] = 0x194,
305 [BRCMNAND_ID_EXT] = 0x198,
306 [BRCMNAND_LL_RDATA] = 0x19c,
307 [BRCMNAND_OOB_READ_BASE] = 0x200,
308 [BRCMNAND_OOB_READ_10_BASE] = 0,
309 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
310 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
311 [BRCMNAND_FC_BASE] = 0x400,
312 };
313
314 /* BRCMNAND v7.1 */
315 static const u16 brcmnand_regs_v71[] = {
316 [BRCMNAND_CMD_START] = 0x04,
317 [BRCMNAND_CMD_EXT_ADDRESS] = 0x08,
318 [BRCMNAND_CMD_ADDRESS] = 0x0c,
319 [BRCMNAND_INTFC_STATUS] = 0x14,
320 [BRCMNAND_CS_SELECT] = 0x18,
321 [BRCMNAND_CS_XOR] = 0x1c,
322 [BRCMNAND_LL_OP] = 0x20,
323 [BRCMNAND_CS0_BASE] = 0x50,
324 [BRCMNAND_CS1_BASE] = 0,
325 [BRCMNAND_CORR_THRESHOLD] = 0xdc,
326 [BRCMNAND_CORR_THRESHOLD_EXT] = 0xe0,
327 [BRCMNAND_UNCORR_COUNT] = 0xfc,
328 [BRCMNAND_CORR_COUNT] = 0x100,
329 [BRCMNAND_CORR_EXT_ADDR] = 0x10c,
330 [BRCMNAND_CORR_ADDR] = 0x110,
331 [BRCMNAND_UNCORR_EXT_ADDR] = 0x114,
332 [BRCMNAND_UNCORR_ADDR] = 0x118,
333 [BRCMNAND_SEMAPHORE] = 0x150,
334 [BRCMNAND_ID] = 0x194,
335 [BRCMNAND_ID_EXT] = 0x198,
336 [BRCMNAND_LL_RDATA] = 0x19c,
337 [BRCMNAND_OOB_READ_BASE] = 0x200,
338 [BRCMNAND_OOB_READ_10_BASE] = 0,
339 [BRCMNAND_OOB_WRITE_BASE] = 0x280,
340 [BRCMNAND_OOB_WRITE_10_BASE] = 0,
341 [BRCMNAND_FC_BASE] = 0x400,
342 };
343
344 enum brcmnand_cs_reg {
345 BRCMNAND_CS_CFG_EXT = 0,
346 BRCMNAND_CS_CFG,
347 BRCMNAND_CS_ACC_CONTROL,
348 BRCMNAND_CS_TIMING1,
349 BRCMNAND_CS_TIMING2,
350 };
351
352 /* Per chip-select offsets for v7.1 */
353 static const u8 brcmnand_cs_offsets_v71[] = {
354 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
355 [BRCMNAND_CS_CFG_EXT] = 0x04,
356 [BRCMNAND_CS_CFG] = 0x08,
357 [BRCMNAND_CS_TIMING1] = 0x0c,
358 [BRCMNAND_CS_TIMING2] = 0x10,
359 };
360
361 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
362 static const u8 brcmnand_cs_offsets[] = {
363 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
364 [BRCMNAND_CS_CFG_EXT] = 0x04,
365 [BRCMNAND_CS_CFG] = 0x04,
366 [BRCMNAND_CS_TIMING1] = 0x08,
367 [BRCMNAND_CS_TIMING2] = 0x0c,
368 };
369
370 /* Per chip-select offset for <= v5.0 on CS0 only */
371 static const u8 brcmnand_cs_offsets_cs0[] = {
372 [BRCMNAND_CS_ACC_CONTROL] = 0x00,
373 [BRCMNAND_CS_CFG_EXT] = 0x08,
374 [BRCMNAND_CS_CFG] = 0x08,
375 [BRCMNAND_CS_TIMING1] = 0x10,
376 [BRCMNAND_CS_TIMING2] = 0x14,
377 };
378
379 /*
380 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
381 * one config register, but once the bitfields overflowed, newer controllers
382 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
383 */
384 enum {
385 CFG_BLK_ADR_BYTES_SHIFT = 8,
386 CFG_COL_ADR_BYTES_SHIFT = 12,
387 CFG_FUL_ADR_BYTES_SHIFT = 16,
388 CFG_BUS_WIDTH_SHIFT = 23,
389 CFG_BUS_WIDTH = BIT(CFG_BUS_WIDTH_SHIFT),
390 CFG_DEVICE_SIZE_SHIFT = 24,
391
392 /* Only for pre-v7.1 (with no CFG_EXT register) */
393 CFG_PAGE_SIZE_SHIFT = 20,
394 CFG_BLK_SIZE_SHIFT = 28,
395
396 /* Only for v7.1+ (with CFG_EXT register) */
397 CFG_EXT_PAGE_SIZE_SHIFT = 0,
398 CFG_EXT_BLK_SIZE_SHIFT = 4,
399 };
400
401 /* BRCMNAND_INTFC_STATUS */
402 enum {
403 INTFC_FLASH_STATUS = GENMASK(7, 0),
404
405 INTFC_ERASED = BIT(27),
406 INTFC_OOB_VALID = BIT(28),
407 INTFC_CACHE_VALID = BIT(29),
408 INTFC_FLASH_READY = BIT(30),
409 INTFC_CTLR_READY = BIT(31),
410 };
411
412 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs)
413 {
414 return brcmnand_readl(ctrl->nand_base + offs);
415 }
416
417 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs,
418 u32 val)
419 {
420 brcmnand_writel(val, ctrl->nand_base + offs);
421 }
422
423 static int brcmnand_revision_init(struct brcmnand_controller *ctrl)
424 {
425 static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
426 static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
427 static const unsigned int page_sizes[] = { 512, 2048, 4096, 8192, 0 };
428
429 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
430
431 /* Only support v4.0+? */
432 if (ctrl->nand_version < 0x0400) {
433 dev_err(ctrl->dev, "version %#x not supported\n",
434 ctrl->nand_version);
435 return -ENODEV;
436 }
437
438 /* Register offsets */
439 if (ctrl->nand_version >= 0x0701)
440 ctrl->reg_offsets = brcmnand_regs_v71;
441 else if (ctrl->nand_version >= 0x0600)
442 ctrl->reg_offsets = brcmnand_regs_v60;
443 else if (ctrl->nand_version >= 0x0500)
444 ctrl->reg_offsets = brcmnand_regs_v50;
445 else if (ctrl->nand_version >= 0x0400)
446 ctrl->reg_offsets = brcmnand_regs_v40;
447
448 /* Chip-select stride */
449 if (ctrl->nand_version >= 0x0701)
450 ctrl->reg_spacing = 0x14;
451 else
452 ctrl->reg_spacing = 0x10;
453
454 /* Per chip-select registers */
455 if (ctrl->nand_version >= 0x0701) {
456 ctrl->cs_offsets = brcmnand_cs_offsets_v71;
457 } else {
458 ctrl->cs_offsets = brcmnand_cs_offsets;
459
460 /* v5.0 and earlier has a different CS0 offset layout */
461 if (ctrl->nand_version <= 0x0500)
462 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0;
463 }
464
465 /* Page / block sizes */
466 if (ctrl->nand_version >= 0x0701) {
467 /* >= v7.1 use nice power-of-2 values! */
468 ctrl->max_page_size = 16 * 1024;
469 ctrl->max_block_size = 2 * 1024 * 1024;
470 } else {
471 ctrl->page_sizes = page_sizes;
472 if (ctrl->nand_version >= 0x0600)
473 ctrl->block_sizes = block_sizes_v6;
474 else
475 ctrl->block_sizes = block_sizes_v4;
476
477 if (ctrl->nand_version < 0x0400) {
478 ctrl->max_page_size = 4096;
479 ctrl->max_block_size = 512 * 1024;
480 }
481 }
482
483 /* Maximum spare area sector size (per 512B) */
484 if (ctrl->nand_version >= 0x0600)
485 ctrl->max_oob = 64;
486 else if (ctrl->nand_version >= 0x0500)
487 ctrl->max_oob = 32;
488 else
489 ctrl->max_oob = 16;
490
491 /* v6.0 and newer (except v6.1) have prefetch support */
492 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601)
493 ctrl->features |= BRCMNAND_HAS_PREFETCH;
494
495 /*
496 * v6.x has cache mode, but it's implemented differently. Ignore it for
497 * now.
498 */
499 if (ctrl->nand_version >= 0x0700)
500 ctrl->features |= BRCMNAND_HAS_CACHE_MODE;
501
502 if (ctrl->nand_version >= 0x0500)
503 ctrl->features |= BRCMNAND_HAS_1K_SECTORS;
504
505 if (ctrl->nand_version >= 0x0700)
506 ctrl->features |= BRCMNAND_HAS_WP;
507 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp"))
508 ctrl->features |= BRCMNAND_HAS_WP;
509
510 return 0;
511 }
512
513 static inline u32 brcmnand_read_reg(struct brcmnand_controller *ctrl,
514 enum brcmnand_reg reg)
515 {
516 u16 offs = ctrl->reg_offsets[reg];
517
518 if (offs)
519 return nand_readreg(ctrl, offs);
520 else
521 return 0;
522 }
523
524 static inline void brcmnand_write_reg(struct brcmnand_controller *ctrl,
525 enum brcmnand_reg reg, u32 val)
526 {
527 u16 offs = ctrl->reg_offsets[reg];
528
529 if (offs)
530 nand_writereg(ctrl, offs, val);
531 }
532
533 static inline void brcmnand_rmw_reg(struct brcmnand_controller *ctrl,
534 enum brcmnand_reg reg, u32 mask, unsigned
535 int shift, u32 val)
536 {
537 u32 tmp = brcmnand_read_reg(ctrl, reg);
538
539 tmp &= ~mask;
540 tmp |= val << shift;
541 brcmnand_write_reg(ctrl, reg, tmp);
542 }
543
544 static inline u32 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word)
545 {
546 return __raw_readl(ctrl->nand_fc + word * 4);
547 }
548
549 static inline void brcmnand_write_fc(struct brcmnand_controller *ctrl,
550 int word, u32 val)
551 {
552 __raw_writel(val, ctrl->nand_fc + word * 4);
553 }
554
555 static inline u16 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs,
556 enum brcmnand_cs_reg reg)
557 {
558 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE];
559 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE];
560 u8 cs_offs;
561
562 if (cs == 0 && ctrl->cs0_offsets)
563 cs_offs = ctrl->cs0_offsets[reg];
564 else
565 cs_offs = ctrl->cs_offsets[reg];
566
567 if (cs && offs_cs1)
568 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs;
569
570 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs;
571 }
572
573 static inline u32 brcmnand_count_corrected(struct brcmnand_controller *ctrl)
574 {
575 if (ctrl->nand_version < 0x0600)
576 return 1;
577 return brcmnand_read_reg(ctrl, BRCMNAND_CORR_COUNT);
578 }
579
580 static void brcmnand_wr_corr_thresh(struct brcmnand_host *host, u8 val)
581 {
582 struct brcmnand_controller *ctrl = host->ctrl;
583 unsigned int shift = 0, bits;
584 enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
585 int cs = host->cs;
586
587 if (ctrl->nand_version >= 0x0600)
588 bits = 6;
589 else if (ctrl->nand_version >= 0x0500)
590 bits = 5;
591 else
592 bits = 4;
593
594 if (ctrl->nand_version >= 0x0600) {
595 if (cs >= 5)
596 reg = BRCMNAND_CORR_THRESHOLD_EXT;
597 shift = (cs % 5) * bits;
598 }
599 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val);
600 }
601
602 static inline int brcmnand_cmd_shift(struct brcmnand_controller *ctrl)
603 {
604 if (ctrl->nand_version < 0x0700)
605 return 24;
606 return 0;
607 }
608
609 /***********************************************************************
610 * NAND ACC CONTROL bitfield
611 *
612 * Some bits have remained constant throughout hardware revision, while
613 * others have shifted around.
614 ***********************************************************************/
615
616 /* Constant for all versions (where supported) */
617 enum {
618 /* See BRCMNAND_HAS_CACHE_MODE */
619 ACC_CONTROL_CACHE_MODE = BIT(22),
620
621 /* See BRCMNAND_HAS_PREFETCH */
622 ACC_CONTROL_PREFETCH = BIT(23),
623
624 ACC_CONTROL_PAGE_HIT = BIT(24),
625 ACC_CONTROL_WR_PREEMPT = BIT(25),
626 ACC_CONTROL_PARTIAL_PAGE = BIT(26),
627 ACC_CONTROL_RD_ERASED = BIT(27),
628 ACC_CONTROL_FAST_PGM_RDIN = BIT(28),
629 ACC_CONTROL_WR_ECC = BIT(30),
630 ACC_CONTROL_RD_ECC = BIT(31),
631 };
632
633 static inline u32 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl)
634 {
635 if (ctrl->nand_version >= 0x0600)
636 return GENMASK(6, 0);
637 else
638 return GENMASK(5, 0);
639 }
640
641 #define NAND_ACC_CONTROL_ECC_SHIFT 16
642
643 static inline u32 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl)
644 {
645 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f;
646
647 return mask << NAND_ACC_CONTROL_ECC_SHIFT;
648 }
649
650 static void brcmnand_set_ecc_enabled(struct brcmnand_host *host, int en)
651 {
652 struct brcmnand_controller *ctrl = host->ctrl;
653 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
654 u32 acc_control = nand_readreg(ctrl, offs);
655 u32 ecc_flags = ACC_CONTROL_WR_ECC | ACC_CONTROL_RD_ECC;
656
657 if (en) {
658 acc_control |= ecc_flags; /* enable RD/WR ECC */
659 acc_control |= host->hwcfg.ecc_level
660 << NAND_ACC_CONTROL_ECC_SHIFT;
661 } else {
662 acc_control &= ~ecc_flags; /* disable RD/WR ECC */
663 acc_control &= ~brcmnand_ecc_level_mask(ctrl);
664 }
665
666 nand_writereg(ctrl, offs, acc_control);
667 }
668
669 static inline int brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl)
670 {
671 if (ctrl->nand_version >= 0x0600)
672 return 7;
673 else if (ctrl->nand_version >= 0x0500)
674 return 6;
675 else
676 return -1;
677 }
678
679 static int brcmnand_get_sector_size_1k(struct brcmnand_host *host)
680 {
681 struct brcmnand_controller *ctrl = host->ctrl;
682 int shift = brcmnand_sector_1k_shift(ctrl);
683 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
684 BRCMNAND_CS_ACC_CONTROL);
685
686 if (shift < 0)
687 return 0;
688
689 return (nand_readreg(ctrl, acc_control_offs) >> shift) & 0x1;
690 }
691
692 static void brcmnand_set_sector_size_1k(struct brcmnand_host *host, int val)
693 {
694 struct brcmnand_controller *ctrl = host->ctrl;
695 int shift = brcmnand_sector_1k_shift(ctrl);
696 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
697 BRCMNAND_CS_ACC_CONTROL);
698 u32 tmp;
699
700 if (shift < 0)
701 return;
702
703 tmp = nand_readreg(ctrl, acc_control_offs);
704 tmp &= ~(1 << shift);
705 tmp |= (!!val) << shift;
706 nand_writereg(ctrl, acc_control_offs, tmp);
707 }
708
709 /***********************************************************************
710 * CS_NAND_SELECT
711 ***********************************************************************/
712
713 enum {
714 CS_SELECT_NAND_WP = BIT(29),
715 CS_SELECT_AUTO_DEVICE_ID_CFG = BIT(30),
716 };
717
718 static inline void brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en)
719 {
720 u32 val = en ? CS_SELECT_NAND_WP : 0;
721
722 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT, CS_SELECT_NAND_WP, 0, val);
723 }
724
725 /***********************************************************************
726 * Flash DMA
727 ***********************************************************************/
728
729 enum flash_dma_reg {
730 FLASH_DMA_REVISION = 0x00,
731 FLASH_DMA_FIRST_DESC = 0x04,
732 FLASH_DMA_FIRST_DESC_EXT = 0x08,
733 FLASH_DMA_CTRL = 0x0c,
734 FLASH_DMA_MODE = 0x10,
735 FLASH_DMA_STATUS = 0x14,
736 FLASH_DMA_INTERRUPT_DESC = 0x18,
737 FLASH_DMA_INTERRUPT_DESC_EXT = 0x1c,
738 FLASH_DMA_ERROR_STATUS = 0x20,
739 FLASH_DMA_CURRENT_DESC = 0x24,
740 FLASH_DMA_CURRENT_DESC_EXT = 0x28,
741 };
742
743 static inline bool has_flash_dma(struct brcmnand_controller *ctrl)
744 {
745 return ctrl->flash_dma_base;
746 }
747
748 static inline bool flash_dma_buf_ok(const void *buf)
749 {
750 return buf && !is_vmalloc_addr(buf) &&
751 likely(IS_ALIGNED((uintptr_t)buf, 4));
752 }
753
754 static inline void flash_dma_writel(struct brcmnand_controller *ctrl, u8 offs,
755 u32 val)
756 {
757 brcmnand_writel(val, ctrl->flash_dma_base + offs);
758 }
759
760 static inline u32 flash_dma_readl(struct brcmnand_controller *ctrl, u8 offs)
761 {
762 return brcmnand_readl(ctrl->flash_dma_base + offs);
763 }
764
765 /* Low-level operation types: command, address, write, or read */
766 enum brcmnand_llop_type {
767 LL_OP_CMD,
768 LL_OP_ADDR,
769 LL_OP_WR,
770 LL_OP_RD,
771 };
772
773 /***********************************************************************
774 * Internal support functions
775 ***********************************************************************/
776
777 static inline bool is_hamming_ecc(struct brcmnand_cfg *cfg)
778 {
779 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 &&
780 cfg->ecc_level == 15;
781 }
782
783 /*
784 * Returns a nand_ecclayout strucutre for the given layout/configuration.
785 * Returns NULL on failure.
786 */
787 static struct nand_ecclayout *brcmnand_create_layout(int ecc_level,
788 struct brcmnand_host *host)
789 {
790 struct brcmnand_cfg *cfg = &host->hwcfg;
791 int i, j;
792 struct nand_ecclayout *layout;
793 int req;
794 int sectors;
795 int sas;
796 int idx1, idx2;
797
798 layout = devm_kzalloc(&host->pdev->dev, sizeof(*layout), GFP_KERNEL);
799 if (!layout)
800 return NULL;
801
802 sectors = cfg->page_size / (512 << cfg->sector_size_1k);
803 sas = cfg->spare_area_size << cfg->sector_size_1k;
804
805 /* Hamming */
806 if (is_hamming_ecc(cfg)) {
807 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
808 /* First sector of each page may have BBI */
809 if (i == 0) {
810 layout->oobfree[idx2].offset = i * sas + 1;
811 /* Small-page NAND use byte 6 for BBI */
812 if (cfg->page_size == 512)
813 layout->oobfree[idx2].offset--;
814 layout->oobfree[idx2].length = 5;
815 } else {
816 layout->oobfree[idx2].offset = i * sas;
817 layout->oobfree[idx2].length = 6;
818 }
819 idx2++;
820 layout->eccpos[idx1++] = i * sas + 6;
821 layout->eccpos[idx1++] = i * sas + 7;
822 layout->eccpos[idx1++] = i * sas + 8;
823 layout->oobfree[idx2].offset = i * sas + 9;
824 layout->oobfree[idx2].length = 7;
825 idx2++;
826 /* Leave zero-terminated entry for OOBFREE */
827 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
828 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
829 break;
830 }
831
832 return layout;
833 }
834
835 /*
836 * CONTROLLER_VERSION:
837 * < v5.0: ECC_REQ = ceil(BCH_T * 13/8)
838 * >= v5.0: ECC_REQ = ceil(BCH_T * 14/8)
839 * But we will just be conservative.
840 */
841 req = DIV_ROUND_UP(ecc_level * 14, 8);
842 if (req >= sas) {
843 dev_err(&host->pdev->dev,
844 "error: ECC too large for OOB (ECC bytes %d, spare sector %d)\n",
845 req, sas);
846 return NULL;
847 }
848
849 layout->eccbytes = req * sectors;
850 for (i = 0, idx1 = 0, idx2 = 0; i < sectors; i++) {
851 for (j = sas - req; j < sas && idx1 <
852 MTD_MAX_ECCPOS_ENTRIES_LARGE; j++, idx1++)
853 layout->eccpos[idx1] = i * sas + j;
854
855 /* First sector of each page may have BBI */
856 if (i == 0) {
857 if (cfg->page_size == 512 && (sas - req >= 6)) {
858 /* Small-page NAND use byte 6 for BBI */
859 layout->oobfree[idx2].offset = 0;
860 layout->oobfree[idx2].length = 5;
861 idx2++;
862 if (sas - req > 6) {
863 layout->oobfree[idx2].offset = 6;
864 layout->oobfree[idx2].length =
865 sas - req - 6;
866 idx2++;
867 }
868 } else if (sas > req + 1) {
869 layout->oobfree[idx2].offset = i * sas + 1;
870 layout->oobfree[idx2].length = sas - req - 1;
871 idx2++;
872 }
873 } else if (sas > req) {
874 layout->oobfree[idx2].offset = i * sas;
875 layout->oobfree[idx2].length = sas - req;
876 idx2++;
877 }
878 /* Leave zero-terminated entry for OOBFREE */
879 if (idx1 >= MTD_MAX_ECCPOS_ENTRIES_LARGE ||
880 idx2 >= MTD_MAX_OOBFREE_ENTRIES_LARGE - 1)
881 break;
882 }
883
884 return layout;
885 }
886
887 static struct nand_ecclayout *brcmstb_choose_ecc_layout(
888 struct brcmnand_host *host)
889 {
890 struct nand_ecclayout *layout;
891 struct brcmnand_cfg *p = &host->hwcfg;
892 unsigned int ecc_level = p->ecc_level;
893
894 if (p->sector_size_1k)
895 ecc_level <<= 1;
896
897 layout = brcmnand_create_layout(ecc_level, host);
898 if (!layout) {
899 dev_err(&host->pdev->dev,
900 "no proper ecc_layout for this NAND cfg\n");
901 return NULL;
902 }
903
904 return layout;
905 }
906
907 static void brcmnand_wp(struct mtd_info *mtd, int wp)
908 {
909 struct nand_chip *chip = mtd_to_nand(mtd);
910 struct brcmnand_host *host = nand_get_controller_data(chip);
911 struct brcmnand_controller *ctrl = host->ctrl;
912
913 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) {
914 static int old_wp = -1;
915
916 if (old_wp != wp) {
917 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off");
918 old_wp = wp;
919 }
920 brcmnand_set_wp(ctrl, wp);
921 }
922 }
923
924 /* Helper functions for reading and writing OOB registers */
925 static inline u8 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs)
926 {
927 u16 offset0, offset10, reg_offs;
928
929 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE];
930 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE];
931
932 if (offs >= ctrl->max_oob)
933 return 0x77;
934
935 if (offs >= 16 && offset10)
936 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
937 else
938 reg_offs = offset0 + (offs & ~0x03);
939
940 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3));
941 }
942
943 static inline void oob_reg_write(struct brcmnand_controller *ctrl, u32 offs,
944 u32 data)
945 {
946 u16 offset0, offset10, reg_offs;
947
948 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE];
949 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE];
950
951 if (offs >= ctrl->max_oob)
952 return;
953
954 if (offs >= 16 && offset10)
955 reg_offs = offset10 + ((offs - 0x10) & ~0x03);
956 else
957 reg_offs = offset0 + (offs & ~0x03);
958
959 nand_writereg(ctrl, reg_offs, data);
960 }
961
962 /*
963 * read_oob_from_regs - read data from OOB registers
964 * @ctrl: NAND controller
965 * @i: sub-page sector index
966 * @oob: buffer to read to
967 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
968 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
969 */
970 static int read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob,
971 int sas, int sector_1k)
972 {
973 int tbytes = sas << sector_1k;
974 int j;
975
976 /* Adjust OOB values for 1K sector size */
977 if (sector_1k && (i & 0x01))
978 tbytes = max(0, tbytes - (int)ctrl->max_oob);
979 tbytes = min_t(int, tbytes, ctrl->max_oob);
980
981 for (j = 0; j < tbytes; j++)
982 oob[j] = oob_reg_read(ctrl, j);
983 return tbytes;
984 }
985
986 /*
987 * write_oob_to_regs - write data to OOB registers
988 * @i: sub-page sector index
989 * @oob: buffer to write from
990 * @sas: spare area sector size (i.e., OOB size per FLASH_CACHE)
991 * @sector_1k: 1 for 1KiB sectors, 0 for 512B, other values are illegal
992 */
993 static int write_oob_to_regs(struct brcmnand_controller *ctrl, int i,
994 const u8 *oob, int sas, int sector_1k)
995 {
996 int tbytes = sas << sector_1k;
997 int j;
998
999 /* Adjust OOB values for 1K sector size */
1000 if (sector_1k && (i & 0x01))
1001 tbytes = max(0, tbytes - (int)ctrl->max_oob);
1002 tbytes = min_t(int, tbytes, ctrl->max_oob);
1003
1004 for (j = 0; j < tbytes; j += 4)
1005 oob_reg_write(ctrl, j,
1006 (oob[j + 0] << 24) |
1007 (oob[j + 1] << 16) |
1008 (oob[j + 2] << 8) |
1009 (oob[j + 3] << 0));
1010 return tbytes;
1011 }
1012
1013 static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
1014 {
1015 struct brcmnand_controller *ctrl = data;
1016
1017 /* Discard all NAND_CTLRDY interrupts during DMA */
1018 if (ctrl->dma_pending)
1019 return IRQ_HANDLED;
1020
1021 complete(&ctrl->done);
1022 return IRQ_HANDLED;
1023 }
1024
1025 /* Handle SoC-specific interrupt hardware */
1026 static irqreturn_t brcmnand_irq(int irq, void *data)
1027 {
1028 struct brcmnand_controller *ctrl = data;
1029
1030 if (ctrl->soc->ctlrdy_ack(ctrl->soc))
1031 return brcmnand_ctlrdy_irq(irq, data);
1032
1033 return IRQ_NONE;
1034 }
1035
1036 static irqreturn_t brcmnand_dma_irq(int irq, void *data)
1037 {
1038 struct brcmnand_controller *ctrl = data;
1039
1040 complete(&ctrl->dma_done);
1041
1042 return IRQ_HANDLED;
1043 }
1044
1045 static void brcmnand_send_cmd(struct brcmnand_host *host, int cmd)
1046 {
1047 struct brcmnand_controller *ctrl = host->ctrl;
1048 u32 intfc;
1049
1050 dev_dbg(ctrl->dev, "send native cmd %d addr_lo 0x%x\n", cmd,
1051 brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS));
1052 BUG_ON(ctrl->cmd_pending != 0);
1053 ctrl->cmd_pending = cmd;
1054
1055 intfc = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS);
1056 BUG_ON(!(intfc & INTFC_CTLR_READY));
1057
1058 mb(); /* flush previous writes */
1059 brcmnand_write_reg(ctrl, BRCMNAND_CMD_START,
1060 cmd << brcmnand_cmd_shift(ctrl));
1061 }
1062
1063 /***********************************************************************
1064 * NAND MTD API: read/program/erase
1065 ***********************************************************************/
1066
1067 static void brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat,
1068 unsigned int ctrl)
1069 {
1070 /* intentionally left blank */
1071 }
1072
1073 static int brcmnand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
1074 {
1075 struct nand_chip *chip = mtd_to_nand(mtd);
1076 struct brcmnand_host *host = nand_get_controller_data(chip);
1077 struct brcmnand_controller *ctrl = host->ctrl;
1078 unsigned long timeo = msecs_to_jiffies(100);
1079
1080 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending);
1081 if (ctrl->cmd_pending &&
1082 wait_for_completion_timeout(&ctrl->done, timeo) <= 0) {
1083 u32 cmd = brcmnand_read_reg(ctrl, BRCMNAND_CMD_START)
1084 >> brcmnand_cmd_shift(ctrl);
1085
1086 dev_err_ratelimited(ctrl->dev,
1087 "timeout waiting for command %#02x\n", cmd);
1088 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n",
1089 brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS));
1090 }
1091 ctrl->cmd_pending = 0;
1092 return brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1093 INTFC_FLASH_STATUS;
1094 }
1095
1096 enum {
1097 LLOP_RE = BIT(16),
1098 LLOP_WE = BIT(17),
1099 LLOP_ALE = BIT(18),
1100 LLOP_CLE = BIT(19),
1101 LLOP_RETURN_IDLE = BIT(31),
1102
1103 LLOP_DATA_MASK = GENMASK(15, 0),
1104 };
1105
1106 static int brcmnand_low_level_op(struct brcmnand_host *host,
1107 enum brcmnand_llop_type type, u32 data,
1108 bool last_op)
1109 {
1110 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1111 struct nand_chip *chip = &host->chip;
1112 struct brcmnand_controller *ctrl = host->ctrl;
1113 u32 tmp;
1114
1115 tmp = data & LLOP_DATA_MASK;
1116 switch (type) {
1117 case LL_OP_CMD:
1118 tmp |= LLOP_WE | LLOP_CLE;
1119 break;
1120 case LL_OP_ADDR:
1121 /* WE | ALE */
1122 tmp |= LLOP_WE | LLOP_ALE;
1123 break;
1124 case LL_OP_WR:
1125 /* WE */
1126 tmp |= LLOP_WE;
1127 break;
1128 case LL_OP_RD:
1129 /* RE */
1130 tmp |= LLOP_RE;
1131 break;
1132 }
1133 if (last_op)
1134 /* RETURN_IDLE */
1135 tmp |= LLOP_RETURN_IDLE;
1136
1137 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp);
1138
1139 brcmnand_write_reg(ctrl, BRCMNAND_LL_OP, tmp);
1140 (void)brcmnand_read_reg(ctrl, BRCMNAND_LL_OP);
1141
1142 brcmnand_send_cmd(host, CMD_LOW_LEVEL_OP);
1143 return brcmnand_waitfunc(mtd, chip);
1144 }
1145
1146 static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
1147 int column, int page_addr)
1148 {
1149 struct nand_chip *chip = mtd_to_nand(mtd);
1150 struct brcmnand_host *host = nand_get_controller_data(chip);
1151 struct brcmnand_controller *ctrl = host->ctrl;
1152 u64 addr = (u64)page_addr << chip->page_shift;
1153 int native_cmd = 0;
1154
1155 if (command == NAND_CMD_READID || command == NAND_CMD_PARAM ||
1156 command == NAND_CMD_RNDOUT)
1157 addr = (u64)column;
1158 /* Avoid propagating a negative, don't-care address */
1159 else if (page_addr < 0)
1160 addr = 0;
1161
1162 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command,
1163 (unsigned long long)addr);
1164
1165 host->last_cmd = command;
1166 host->last_byte = 0;
1167 host->last_addr = addr;
1168
1169 switch (command) {
1170 case NAND_CMD_RESET:
1171 native_cmd = CMD_FLASH_RESET;
1172 break;
1173 case NAND_CMD_STATUS:
1174 native_cmd = CMD_STATUS_READ;
1175 break;
1176 case NAND_CMD_READID:
1177 native_cmd = CMD_DEVICE_ID_READ;
1178 break;
1179 case NAND_CMD_READOOB:
1180 native_cmd = CMD_SPARE_AREA_READ;
1181 break;
1182 case NAND_CMD_ERASE1:
1183 native_cmd = CMD_BLOCK_ERASE;
1184 brcmnand_wp(mtd, 0);
1185 break;
1186 case NAND_CMD_PARAM:
1187 native_cmd = CMD_PARAMETER_READ;
1188 break;
1189 case NAND_CMD_SET_FEATURES:
1190 case NAND_CMD_GET_FEATURES:
1191 brcmnand_low_level_op(host, LL_OP_CMD, command, false);
1192 brcmnand_low_level_op(host, LL_OP_ADDR, column, false);
1193 break;
1194 case NAND_CMD_RNDOUT:
1195 native_cmd = CMD_PARAMETER_CHANGE_COL;
1196 addr &= ~((u64)(FC_BYTES - 1));
1197 /*
1198 * HW quirk: PARAMETER_CHANGE_COL requires SECTOR_SIZE_1K=0
1199 * NB: hwcfg.sector_size_1k may not be initialized yet
1200 */
1201 if (brcmnand_get_sector_size_1k(host)) {
1202 host->hwcfg.sector_size_1k =
1203 brcmnand_get_sector_size_1k(host);
1204 brcmnand_set_sector_size_1k(host, 0);
1205 }
1206 break;
1207 }
1208
1209 if (!native_cmd)
1210 return;
1211
1212 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1213 (host->cs << 16) | ((addr >> 32) & 0xffff));
1214 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1215 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS, lower_32_bits(addr));
1216 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1217
1218 brcmnand_send_cmd(host, native_cmd);
1219 brcmnand_waitfunc(mtd, chip);
1220
1221 if (native_cmd == CMD_PARAMETER_READ ||
1222 native_cmd == CMD_PARAMETER_CHANGE_COL) {
1223 /* Copy flash cache word-wise */
1224 u32 *flash_cache = (u32 *)ctrl->flash_cache;
1225 int i;
1226
1227 brcmnand_soc_data_bus_prepare(ctrl->soc);
1228
1229 /*
1230 * Must cache the FLASH_CACHE now, since changes in
1231 * SECTOR_SIZE_1K may invalidate it
1232 */
1233 for (i = 0; i < FC_WORDS; i++)
1234 /*
1235 * Flash cache is big endian for parameter pages, at
1236 * least on STB SoCs
1237 */
1238 flash_cache[i] = be32_to_cpu(brcmnand_read_fc(ctrl, i));
1239
1240 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1241
1242 /* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
1243 if (host->hwcfg.sector_size_1k)
1244 brcmnand_set_sector_size_1k(host,
1245 host->hwcfg.sector_size_1k);
1246 }
1247
1248 /* Re-enable protection is necessary only after erase */
1249 if (command == NAND_CMD_ERASE1)
1250 brcmnand_wp(mtd, 1);
1251 }
1252
1253 static uint8_t brcmnand_read_byte(struct mtd_info *mtd)
1254 {
1255 struct nand_chip *chip = mtd_to_nand(mtd);
1256 struct brcmnand_host *host = nand_get_controller_data(chip);
1257 struct brcmnand_controller *ctrl = host->ctrl;
1258 uint8_t ret = 0;
1259 int addr, offs;
1260
1261 switch (host->last_cmd) {
1262 case NAND_CMD_READID:
1263 if (host->last_byte < 4)
1264 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID) >>
1265 (24 - (host->last_byte << 3));
1266 else if (host->last_byte < 8)
1267 ret = brcmnand_read_reg(ctrl, BRCMNAND_ID_EXT) >>
1268 (56 - (host->last_byte << 3));
1269 break;
1270
1271 case NAND_CMD_READOOB:
1272 ret = oob_reg_read(ctrl, host->last_byte);
1273 break;
1274
1275 case NAND_CMD_STATUS:
1276 ret = brcmnand_read_reg(ctrl, BRCMNAND_INTFC_STATUS) &
1277 INTFC_FLASH_STATUS;
1278 if (wp_on) /* hide WP status */
1279 ret |= NAND_STATUS_WP;
1280 break;
1281
1282 case NAND_CMD_PARAM:
1283 case NAND_CMD_RNDOUT:
1284 addr = host->last_addr + host->last_byte;
1285 offs = addr & (FC_BYTES - 1);
1286
1287 /* At FC_BYTES boundary, switch to next column */
1288 if (host->last_byte > 0 && offs == 0)
1289 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, addr, -1);
1290
1291 ret = ctrl->flash_cache[offs];
1292 break;
1293 case NAND_CMD_GET_FEATURES:
1294 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) {
1295 ret = 0;
1296 } else {
1297 bool last = host->last_byte ==
1298 ONFI_SUBFEATURE_PARAM_LEN - 1;
1299 brcmnand_low_level_op(host, LL_OP_RD, 0, last);
1300 ret = brcmnand_read_reg(ctrl, BRCMNAND_LL_RDATA) & 0xff;
1301 }
1302 }
1303
1304 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret);
1305 host->last_byte++;
1306
1307 return ret;
1308 }
1309
1310 static void brcmnand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
1311 {
1312 int i;
1313
1314 for (i = 0; i < len; i++, buf++)
1315 *buf = brcmnand_read_byte(mtd);
1316 }
1317
1318 static void brcmnand_write_buf(struct mtd_info *mtd, const uint8_t *buf,
1319 int len)
1320 {
1321 int i;
1322 struct nand_chip *chip = mtd_to_nand(mtd);
1323 struct brcmnand_host *host = nand_get_controller_data(chip);
1324
1325 switch (host->last_cmd) {
1326 case NAND_CMD_SET_FEATURES:
1327 for (i = 0; i < len; i++)
1328 brcmnand_low_level_op(host, LL_OP_WR, buf[i],
1329 (i + 1) == len);
1330 break;
1331 default:
1332 BUG();
1333 break;
1334 }
1335 }
1336
1337 /**
1338 * Construct a FLASH_DMA descriptor as part of a linked list. You must know the
1339 * following ahead of time:
1340 * - Is this descriptor the beginning or end of a linked list?
1341 * - What is the (DMA) address of the next descriptor in the linked list?
1342 */
1343 static int brcmnand_fill_dma_desc(struct brcmnand_host *host,
1344 struct brcm_nand_dma_desc *desc, u64 addr,
1345 dma_addr_t buf, u32 len, u8 dma_cmd,
1346 bool begin, bool end,
1347 dma_addr_t next_desc)
1348 {
1349 memset(desc, 0, sizeof(*desc));
1350 /* Descriptors are written in native byte order (wordwise) */
1351 desc->next_desc = lower_32_bits(next_desc);
1352 desc->next_desc_ext = upper_32_bits(next_desc);
1353 desc->cmd_irq = (dma_cmd << 24) |
1354 (end ? (0x03 << 8) : 0) | /* IRQ | STOP */
1355 (!!begin) | ((!!end) << 1); /* head, tail */
1356 #ifdef CONFIG_CPU_BIG_ENDIAN
1357 desc->cmd_irq |= 0x01 << 12;
1358 #endif
1359 desc->dram_addr = lower_32_bits(buf);
1360 desc->dram_addr_ext = upper_32_bits(buf);
1361 desc->tfr_len = len;
1362 desc->total_len = len;
1363 desc->flash_addr = lower_32_bits(addr);
1364 desc->flash_addr_ext = upper_32_bits(addr);
1365 desc->cs = host->cs;
1366 desc->status_valid = 0x01;
1367 return 0;
1368 }
1369
1370 /**
1371 * Kick the FLASH_DMA engine, with a given DMA descriptor
1372 */
1373 static void brcmnand_dma_run(struct brcmnand_host *host, dma_addr_t desc)
1374 {
1375 struct brcmnand_controller *ctrl = host->ctrl;
1376 unsigned long timeo = msecs_to_jiffies(100);
1377
1378 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC, lower_32_bits(desc));
1379 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC);
1380 flash_dma_writel(ctrl, FLASH_DMA_FIRST_DESC_EXT, upper_32_bits(desc));
1381 (void)flash_dma_readl(ctrl, FLASH_DMA_FIRST_DESC_EXT);
1382
1383 /* Start FLASH_DMA engine */
1384 ctrl->dma_pending = true;
1385 mb(); /* flush previous writes */
1386 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0x03); /* wake | run */
1387
1388 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) {
1389 dev_err(ctrl->dev,
1390 "timeout waiting for DMA; status %#x, error status %#x\n",
1391 flash_dma_readl(ctrl, FLASH_DMA_STATUS),
1392 flash_dma_readl(ctrl, FLASH_DMA_ERROR_STATUS));
1393 }
1394 ctrl->dma_pending = false;
1395 flash_dma_writel(ctrl, FLASH_DMA_CTRL, 0); /* force stop */
1396 }
1397
1398 static int brcmnand_dma_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
1399 u32 len, u8 dma_cmd)
1400 {
1401 struct brcmnand_controller *ctrl = host->ctrl;
1402 dma_addr_t buf_pa;
1403 int dir = dma_cmd == CMD_PAGE_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
1404
1405 buf_pa = dma_map_single(ctrl->dev, buf, len, dir);
1406 if (dma_mapping_error(ctrl->dev, buf_pa)) {
1407 dev_err(ctrl->dev, "unable to map buffer for DMA\n");
1408 return -ENOMEM;
1409 }
1410
1411 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len,
1412 dma_cmd, true, true, 0);
1413
1414 brcmnand_dma_run(host, ctrl->dma_pa);
1415
1416 dma_unmap_single(ctrl->dev, buf_pa, len, dir);
1417
1418 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR)
1419 return -EBADMSG;
1420 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR)
1421 return -EUCLEAN;
1422
1423 return 0;
1424 }
1425
1426 /*
1427 * Assumes proper CS is already set
1428 */
1429 static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
1430 u64 addr, unsigned int trans, u32 *buf,
1431 u8 *oob, u64 *err_addr)
1432 {
1433 struct brcmnand_host *host = nand_get_controller_data(chip);
1434 struct brcmnand_controller *ctrl = host->ctrl;
1435 int i, j, ret = 0;
1436
1437 /* Clear error addresses */
1438 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_ADDR, 0);
1439 brcmnand_write_reg(ctrl, BRCMNAND_CORR_ADDR, 0);
1440 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_EXT_ADDR, 0);
1441 brcmnand_write_reg(ctrl, BRCMNAND_CORR_EXT_ADDR, 0);
1442
1443 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1444 (host->cs << 16) | ((addr >> 32) & 0xffff));
1445 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1446
1447 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1448 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1449 lower_32_bits(addr));
1450 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1451 /* SPARE_AREA_READ does not use ECC, so just use PAGE_READ */
1452 brcmnand_send_cmd(host, CMD_PAGE_READ);
1453 brcmnand_waitfunc(mtd, chip);
1454
1455 if (likely(buf)) {
1456 brcmnand_soc_data_bus_prepare(ctrl->soc);
1457
1458 for (j = 0; j < FC_WORDS; j++, buf++)
1459 *buf = brcmnand_read_fc(ctrl, j);
1460
1461 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1462 }
1463
1464 if (oob)
1465 oob += read_oob_from_regs(ctrl, i, oob,
1466 mtd->oobsize / trans,
1467 host->hwcfg.sector_size_1k);
1468
1469 if (!ret) {
1470 *err_addr = brcmnand_read_reg(ctrl,
1471 BRCMNAND_UNCORR_ADDR) |
1472 ((u64)(brcmnand_read_reg(ctrl,
1473 BRCMNAND_UNCORR_EXT_ADDR)
1474 & 0xffff) << 32);
1475 if (*err_addr)
1476 ret = -EBADMSG;
1477 }
1478
1479 if (!ret) {
1480 *err_addr = brcmnand_read_reg(ctrl,
1481 BRCMNAND_CORR_ADDR) |
1482 ((u64)(brcmnand_read_reg(ctrl,
1483 BRCMNAND_CORR_EXT_ADDR)
1484 & 0xffff) << 32);
1485 if (*err_addr)
1486 ret = -EUCLEAN;
1487 }
1488 }
1489
1490 return ret;
1491 }
1492
1493 static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
1494 u64 addr, unsigned int trans, u32 *buf, u8 *oob)
1495 {
1496 struct brcmnand_host *host = nand_get_controller_data(chip);
1497 struct brcmnand_controller *ctrl = host->ctrl;
1498 u64 err_addr = 0;
1499 int err;
1500
1501 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
1502
1503 brcmnand_write_reg(ctrl, BRCMNAND_UNCORR_COUNT, 0);
1504
1505 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1506 err = brcmnand_dma_trans(host, addr, buf, trans * FC_BYTES,
1507 CMD_PAGE_READ);
1508 if (err) {
1509 if (mtd_is_bitflip_or_eccerr(err))
1510 err_addr = addr;
1511 else
1512 return -EIO;
1513 }
1514 } else {
1515 if (oob)
1516 memset(oob, 0x99, mtd->oobsize);
1517
1518 err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
1519 oob, &err_addr);
1520 }
1521
1522 if (mtd_is_eccerr(err)) {
1523 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n",
1524 (unsigned long long)err_addr);
1525 mtd->ecc_stats.failed++;
1526 /* NAND layer expects zero on ECC errors */
1527 return 0;
1528 }
1529
1530 if (mtd_is_bitflip(err)) {
1531 unsigned int corrected = brcmnand_count_corrected(ctrl);
1532
1533 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
1534 (unsigned long long)err_addr);
1535 mtd->ecc_stats.corrected += corrected;
1536 /* Always exceed the software-imposed threshold */
1537 return max(mtd->bitflip_threshold, corrected);
1538 }
1539
1540 return 0;
1541 }
1542
1543 static int brcmnand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1544 uint8_t *buf, int oob_required, int page)
1545 {
1546 struct brcmnand_host *host = nand_get_controller_data(chip);
1547 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1548
1549 return brcmnand_read(mtd, chip, host->last_addr,
1550 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1551 }
1552
1553 static int brcmnand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1554 uint8_t *buf, int oob_required, int page)
1555 {
1556 struct brcmnand_host *host = nand_get_controller_data(chip);
1557 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL;
1558 int ret;
1559
1560 brcmnand_set_ecc_enabled(host, 0);
1561 ret = brcmnand_read(mtd, chip, host->last_addr,
1562 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob);
1563 brcmnand_set_ecc_enabled(host, 1);
1564 return ret;
1565 }
1566
1567 static int brcmnand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1568 int page)
1569 {
1570 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1571 mtd->writesize >> FC_SHIFT,
1572 NULL, (u8 *)chip->oob_poi);
1573 }
1574
1575 static int brcmnand_read_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1576 int page)
1577 {
1578 struct brcmnand_host *host = nand_get_controller_data(chip);
1579
1580 brcmnand_set_ecc_enabled(host, 0);
1581 brcmnand_read(mtd, chip, (u64)page << chip->page_shift,
1582 mtd->writesize >> FC_SHIFT,
1583 NULL, (u8 *)chip->oob_poi);
1584 brcmnand_set_ecc_enabled(host, 1);
1585 return 0;
1586 }
1587
1588 static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
1589 u64 addr, const u32 *buf, u8 *oob)
1590 {
1591 struct brcmnand_host *host = nand_get_controller_data(chip);
1592 struct brcmnand_controller *ctrl = host->ctrl;
1593 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT;
1594 int status, ret = 0;
1595
1596 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf);
1597
1598 if (unlikely((unsigned long)buf & 0x03)) {
1599 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf);
1600 buf = (u32 *)((unsigned long)buf & ~0x03);
1601 }
1602
1603 brcmnand_wp(mtd, 0);
1604
1605 for (i = 0; i < ctrl->max_oob; i += 4)
1606 oob_reg_write(ctrl, i, 0xffffffff);
1607
1608 if (has_flash_dma(ctrl) && !oob && flash_dma_buf_ok(buf)) {
1609 if (brcmnand_dma_trans(host, addr, (u32 *)buf,
1610 mtd->writesize, CMD_PROGRAM_PAGE))
1611 ret = -EIO;
1612 goto out;
1613 }
1614
1615 brcmnand_write_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS,
1616 (host->cs << 16) | ((addr >> 32) & 0xffff));
1617 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_EXT_ADDRESS);
1618
1619 for (i = 0; i < trans; i++, addr += FC_BYTES) {
1620 /* full address MUST be set before populating FC */
1621 brcmnand_write_reg(ctrl, BRCMNAND_CMD_ADDRESS,
1622 lower_32_bits(addr));
1623 (void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
1624
1625 if (buf) {
1626 brcmnand_soc_data_bus_prepare(ctrl->soc);
1627
1628 for (j = 0; j < FC_WORDS; j++, buf++)
1629 brcmnand_write_fc(ctrl, j, *buf);
1630
1631 brcmnand_soc_data_bus_unprepare(ctrl->soc);
1632 } else if (oob) {
1633 for (j = 0; j < FC_WORDS; j++)
1634 brcmnand_write_fc(ctrl, j, 0xffffffff);
1635 }
1636
1637 if (oob) {
1638 oob += write_oob_to_regs(ctrl, i, oob,
1639 mtd->oobsize / trans,
1640 host->hwcfg.sector_size_1k);
1641 }
1642
1643 /* we cannot use SPARE_AREA_PROGRAM when PARTIAL_PAGE_EN=0 */
1644 brcmnand_send_cmd(host, CMD_PROGRAM_PAGE);
1645 status = brcmnand_waitfunc(mtd, chip);
1646
1647 if (status & NAND_STATUS_FAIL) {
1648 dev_info(ctrl->dev, "program failed at %llx\n",
1649 (unsigned long long)addr);
1650 ret = -EIO;
1651 goto out;
1652 }
1653 }
1654 out:
1655 brcmnand_wp(mtd, 1);
1656 return ret;
1657 }
1658
1659 static int brcmnand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1660 const uint8_t *buf, int oob_required, int page)
1661 {
1662 struct brcmnand_host *host = nand_get_controller_data(chip);
1663 void *oob = oob_required ? chip->oob_poi : NULL;
1664
1665 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1666 return 0;
1667 }
1668
1669 static int brcmnand_write_page_raw(struct mtd_info *mtd,
1670 struct nand_chip *chip, const uint8_t *buf,
1671 int oob_required, int page)
1672 {
1673 struct brcmnand_host *host = nand_get_controller_data(chip);
1674 void *oob = oob_required ? chip->oob_poi : NULL;
1675
1676 brcmnand_set_ecc_enabled(host, 0);
1677 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob);
1678 brcmnand_set_ecc_enabled(host, 1);
1679 return 0;
1680 }
1681
1682 static int brcmnand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1683 int page)
1684 {
1685 return brcmnand_write(mtd, chip, (u64)page << chip->page_shift,
1686 NULL, chip->oob_poi);
1687 }
1688
1689 static int brcmnand_write_oob_raw(struct mtd_info *mtd, struct nand_chip *chip,
1690 int page)
1691 {
1692 struct brcmnand_host *host = nand_get_controller_data(chip);
1693 int ret;
1694
1695 brcmnand_set_ecc_enabled(host, 0);
1696 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL,
1697 (u8 *)chip->oob_poi);
1698 brcmnand_set_ecc_enabled(host, 1);
1699
1700 return ret;
1701 }
1702
1703 /***********************************************************************
1704 * Per-CS setup (1 NAND device)
1705 ***********************************************************************/
1706
1707 static int brcmnand_set_cfg(struct brcmnand_host *host,
1708 struct brcmnand_cfg *cfg)
1709 {
1710 struct brcmnand_controller *ctrl = host->ctrl;
1711 struct nand_chip *chip = &host->chip;
1712 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1713 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
1714 BRCMNAND_CS_CFG_EXT);
1715 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
1716 BRCMNAND_CS_ACC_CONTROL);
1717 u8 block_size = 0, page_size = 0, device_size = 0;
1718 u32 tmp;
1719
1720 if (ctrl->block_sizes) {
1721 int i, found;
1722
1723 for (i = 0, found = 0; ctrl->block_sizes[i]; i++)
1724 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) {
1725 block_size = i;
1726 found = 1;
1727 }
1728 if (!found) {
1729 dev_warn(ctrl->dev, "invalid block size %u\n",
1730 cfg->block_size);
1731 return -EINVAL;
1732 }
1733 } else {
1734 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE);
1735 }
1736
1737 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size &&
1738 cfg->block_size > ctrl->max_block_size)) {
1739 dev_warn(ctrl->dev, "invalid block size %u\n",
1740 cfg->block_size);
1741 block_size = 0;
1742 }
1743
1744 if (ctrl->page_sizes) {
1745 int i, found;
1746
1747 for (i = 0, found = 0; ctrl->page_sizes[i]; i++)
1748 if (ctrl->page_sizes[i] == cfg->page_size) {
1749 page_size = i;
1750 found = 1;
1751 }
1752 if (!found) {
1753 dev_warn(ctrl->dev, "invalid page size %u\n",
1754 cfg->page_size);
1755 return -EINVAL;
1756 }
1757 } else {
1758 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE);
1759 }
1760
1761 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size &&
1762 cfg->page_size > ctrl->max_page_size)) {
1763 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size);
1764 return -EINVAL;
1765 }
1766
1767 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) {
1768 dev_warn(ctrl->dev, "invalid device size 0x%llx\n",
1769 (unsigned long long)cfg->device_size);
1770 return -EINVAL;
1771 }
1772 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE);
1773
1774 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) |
1775 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) |
1776 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) |
1777 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) |
1778 (device_size << CFG_DEVICE_SIZE_SHIFT);
1779 if (cfg_offs == cfg_ext_offs) {
1780 tmp |= (page_size << CFG_PAGE_SIZE_SHIFT) |
1781 (block_size << CFG_BLK_SIZE_SHIFT);
1782 nand_writereg(ctrl, cfg_offs, tmp);
1783 } else {
1784 nand_writereg(ctrl, cfg_offs, tmp);
1785 tmp = (page_size << CFG_EXT_PAGE_SIZE_SHIFT) |
1786 (block_size << CFG_EXT_BLK_SIZE_SHIFT);
1787 nand_writereg(ctrl, cfg_ext_offs, tmp);
1788 }
1789
1790 tmp = nand_readreg(ctrl, acc_control_offs);
1791 tmp &= ~brcmnand_ecc_level_mask(ctrl);
1792 tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
1793 tmp &= ~brcmnand_spare_area_mask(ctrl);
1794 tmp |= cfg->spare_area_size;
1795 nand_writereg(ctrl, acc_control_offs, tmp);
1796
1797 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
1798
1799 /* threshold = ceil(BCH-level * 0.75) */
1800 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4));
1801
1802 return 0;
1803 }
1804
1805 static void brcmnand_print_cfg(char *buf, struct brcmnand_cfg *cfg)
1806 {
1807 buf += sprintf(buf,
1808 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit",
1809 (unsigned long long)cfg->device_size >> 20,
1810 cfg->block_size >> 10,
1811 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size,
1812 cfg->page_size >= 1024 ? "KiB" : "B",
1813 cfg->spare_area_size, cfg->device_width);
1814
1815 /* Account for Hamming ECC and for BCH 512B vs 1KiB sectors */
1816 if (is_hamming_ecc(cfg))
1817 sprintf(buf, ", Hamming ECC");
1818 else if (cfg->sector_size_1k)
1819 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1);
1820 else
1821 sprintf(buf, ", BCH-%u", cfg->ecc_level);
1822 }
1823
1824 /*
1825 * Minimum number of bytes to address a page. Calculated as:
1826 * roundup(log2(size / page-size) / 8)
1827 *
1828 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
1829 * OK because many other things will break if 'size' is irregular...
1830 */
1831 static inline int get_blk_adr_bytes(u64 size, u32 writesize)
1832 {
1833 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3;
1834 }
1835
1836 static int brcmnand_setup_dev(struct brcmnand_host *host)
1837 {
1838 struct mtd_info *mtd = nand_to_mtd(&host->chip);
1839 struct nand_chip *chip = &host->chip;
1840 struct brcmnand_controller *ctrl = host->ctrl;
1841 struct brcmnand_cfg *cfg = &host->hwcfg;
1842 char msg[128];
1843 u32 offs, tmp, oob_sector;
1844 int ret;
1845
1846 memset(cfg, 0, sizeof(*cfg));
1847
1848 ret = of_property_read_u32(nand_get_flash_node(chip),
1849 "brcm,nand-oob-sector-size",
1850 &oob_sector);
1851 if (ret) {
1852 /* Use detected size */
1853 cfg->spare_area_size = mtd->oobsize /
1854 (mtd->writesize >> FC_SHIFT);
1855 } else {
1856 cfg->spare_area_size = oob_sector;
1857 }
1858 if (cfg->spare_area_size > ctrl->max_oob)
1859 cfg->spare_area_size = ctrl->max_oob;
1860 /*
1861 * Set oobsize to be consistent with controller's spare_area_size, as
1862 * the rest is inaccessible.
1863 */
1864 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT);
1865
1866 cfg->device_size = mtd->size;
1867 cfg->block_size = mtd->erasesize;
1868 cfg->page_size = mtd->writesize;
1869 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8;
1870 cfg->col_adr_bytes = 2;
1871 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize);
1872
1873 switch (chip->ecc.size) {
1874 case 512:
1875 if (chip->ecc.strength == 1) /* Hamming */
1876 cfg->ecc_level = 15;
1877 else
1878 cfg->ecc_level = chip->ecc.strength;
1879 cfg->sector_size_1k = 0;
1880 break;
1881 case 1024:
1882 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) {
1883 dev_err(ctrl->dev, "1KB sectors not supported\n");
1884 return -EINVAL;
1885 }
1886 if (chip->ecc.strength & 0x1) {
1887 dev_err(ctrl->dev,
1888 "odd ECC not supported with 1KB sectors\n");
1889 return -EINVAL;
1890 }
1891
1892 cfg->ecc_level = chip->ecc.strength >> 1;
1893 cfg->sector_size_1k = 1;
1894 break;
1895 default:
1896 dev_err(ctrl->dev, "unsupported ECC size: %d\n",
1897 chip->ecc.size);
1898 return -EINVAL;
1899 }
1900
1901 cfg->ful_adr_bytes = cfg->blk_adr_bytes;
1902 if (mtd->writesize > 512)
1903 cfg->ful_adr_bytes += cfg->col_adr_bytes;
1904 else
1905 cfg->ful_adr_bytes += 1;
1906
1907 ret = brcmnand_set_cfg(host, cfg);
1908 if (ret)
1909 return ret;
1910
1911 brcmnand_set_ecc_enabled(host, 1);
1912
1913 brcmnand_print_cfg(msg, cfg);
1914 dev_info(ctrl->dev, "detected %s\n", msg);
1915
1916 /* Configure ACC_CONTROL */
1917 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL);
1918 tmp = nand_readreg(ctrl, offs);
1919 tmp &= ~ACC_CONTROL_PARTIAL_PAGE;
1920 tmp &= ~ACC_CONTROL_RD_ERASED;
1921 tmp &= ~ACC_CONTROL_FAST_PGM_RDIN;
1922 if (ctrl->features & BRCMNAND_HAS_PREFETCH) {
1923 /*
1924 * FIXME: Flash DMA + prefetch may see spurious erased-page ECC
1925 * errors
1926 */
1927 if (has_flash_dma(ctrl))
1928 tmp &= ~ACC_CONTROL_PREFETCH;
1929 else
1930 tmp |= ACC_CONTROL_PREFETCH;
1931 }
1932 nand_writereg(ctrl, offs, tmp);
1933
1934 return 0;
1935 }
1936
1937 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn)
1938 {
1939 struct brcmnand_controller *ctrl = host->ctrl;
1940 struct platform_device *pdev = host->pdev;
1941 struct mtd_info *mtd;
1942 struct nand_chip *chip;
1943 int ret;
1944 u16 cfg_offs;
1945
1946 ret = of_property_read_u32(dn, "reg", &host->cs);
1947 if (ret) {
1948 dev_err(&pdev->dev, "can't get chip-select\n");
1949 return -ENXIO;
1950 }
1951
1952 mtd = nand_to_mtd(&host->chip);
1953 chip = &host->chip;
1954
1955 nand_set_flash_node(chip, dn);
1956 nand_set_controller_data(chip, host);
1957 mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d",
1958 host->cs);
1959 mtd->owner = THIS_MODULE;
1960 mtd->dev.parent = &pdev->dev;
1961
1962 chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
1963 chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
1964
1965 chip->cmd_ctrl = brcmnand_cmd_ctrl;
1966 chip->cmdfunc = brcmnand_cmdfunc;
1967 chip->waitfunc = brcmnand_waitfunc;
1968 chip->read_byte = brcmnand_read_byte;
1969 chip->read_buf = brcmnand_read_buf;
1970 chip->write_buf = brcmnand_write_buf;
1971
1972 chip->ecc.mode = NAND_ECC_HW;
1973 chip->ecc.read_page = brcmnand_read_page;
1974 chip->ecc.write_page = brcmnand_write_page;
1975 chip->ecc.read_page_raw = brcmnand_read_page_raw;
1976 chip->ecc.write_page_raw = brcmnand_write_page_raw;
1977 chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
1978 chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
1979 chip->ecc.read_oob = brcmnand_read_oob;
1980 chip->ecc.write_oob = brcmnand_write_oob;
1981
1982 chip->controller = &ctrl->controller;
1983
1984 /*
1985 * The bootloader might have configured 16bit mode but
1986 * NAND READID command only works in 8bit mode. We force
1987 * 8bit mode here to ensure that NAND READID commands works.
1988 */
1989 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
1990 nand_writereg(ctrl, cfg_offs,
1991 nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
1992
1993 if (nand_scan_ident(mtd, 1, NULL))
1994 return -ENXIO;
1995
1996 chip->options |= NAND_NO_SUBPAGE_WRITE;
1997 /*
1998 * Avoid (for instance) kmap()'d buffers from JFFS2, which we can't DMA
1999 * to/from, and have nand_base pass us a bounce buffer instead, as
2000 * needed.
2001 */
2002 chip->options |= NAND_USE_BOUNCE_BUFFER;
2003
2004 if (of_get_nand_on_flash_bbt(dn))
2005 chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
2006
2007 if (brcmnand_setup_dev(host))
2008 return -ENXIO;
2009
2010 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512;
2011 /* only use our internal HW threshold */
2012 mtd->bitflip_threshold = 1;
2013
2014 chip->ecc.layout = brcmstb_choose_ecc_layout(host);
2015 if (!chip->ecc.layout)
2016 return -ENXIO;
2017
2018 if (nand_scan_tail(mtd))
2019 return -ENXIO;
2020
2021 return mtd_device_register(mtd, NULL, 0);
2022 }
2023
2024 static void brcmnand_save_restore_cs_config(struct brcmnand_host *host,
2025 int restore)
2026 {
2027 struct brcmnand_controller *ctrl = host->ctrl;
2028 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
2029 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs,
2030 BRCMNAND_CS_CFG_EXT);
2031 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs,
2032 BRCMNAND_CS_ACC_CONTROL);
2033 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1);
2034 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2);
2035
2036 if (restore) {
2037 nand_writereg(ctrl, cfg_offs, host->hwcfg.config);
2038 if (cfg_offs != cfg_ext_offs)
2039 nand_writereg(ctrl, cfg_ext_offs,
2040 host->hwcfg.config_ext);
2041 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control);
2042 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1);
2043 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2);
2044 } else {
2045 host->hwcfg.config = nand_readreg(ctrl, cfg_offs);
2046 if (cfg_offs != cfg_ext_offs)
2047 host->hwcfg.config_ext =
2048 nand_readreg(ctrl, cfg_ext_offs);
2049 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs);
2050 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs);
2051 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs);
2052 }
2053 }
2054
2055 static int brcmnand_suspend(struct device *dev)
2056 {
2057 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2058 struct brcmnand_host *host;
2059
2060 list_for_each_entry(host, &ctrl->host_list, node)
2061 brcmnand_save_restore_cs_config(host, 0);
2062
2063 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT);
2064 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR);
2065 ctrl->corr_stat_threshold =
2066 brcmnand_read_reg(ctrl, BRCMNAND_CORR_THRESHOLD);
2067
2068 if (has_flash_dma(ctrl))
2069 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE);
2070
2071 return 0;
2072 }
2073
2074 static int brcmnand_resume(struct device *dev)
2075 {
2076 struct brcmnand_controller *ctrl = dev_get_drvdata(dev);
2077 struct brcmnand_host *host;
2078
2079 if (has_flash_dma(ctrl)) {
2080 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode);
2081 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2082 }
2083
2084 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select);
2085 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
2086 brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
2087 ctrl->corr_stat_threshold);
2088 if (ctrl->soc) {
2089 /* Clear/re-enable interrupt */
2090 ctrl->soc->ctlrdy_ack(ctrl->soc);
2091 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2092 }
2093
2094 list_for_each_entry(host, &ctrl->host_list, node) {
2095 struct nand_chip *chip = &host->chip;
2096 struct mtd_info *mtd = nand_to_mtd(chip);
2097
2098 brcmnand_save_restore_cs_config(host, 1);
2099
2100 /* Reset the chip, required by some chips after power-up */
2101 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
2102 }
2103
2104 return 0;
2105 }
2106
2107 const struct dev_pm_ops brcmnand_pm_ops = {
2108 .suspend = brcmnand_suspend,
2109 .resume = brcmnand_resume,
2110 };
2111 EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
2112
2113 static const struct of_device_id brcmnand_of_match[] = {
2114 { .compatible = "brcm,brcmnand-v4.0" },
2115 { .compatible = "brcm,brcmnand-v5.0" },
2116 { .compatible = "brcm,brcmnand-v6.0" },
2117 { .compatible = "brcm,brcmnand-v6.1" },
2118 { .compatible = "brcm,brcmnand-v7.0" },
2119 { .compatible = "brcm,brcmnand-v7.1" },
2120 {},
2121 };
2122 MODULE_DEVICE_TABLE(of, brcmnand_of_match);
2123
2124 /***********************************************************************
2125 * Platform driver setup (per controller)
2126 ***********************************************************************/
2127
2128 int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
2129 {
2130 struct device *dev = &pdev->dev;
2131 struct device_node *dn = dev->of_node, *child;
2132 struct brcmnand_controller *ctrl;
2133 struct resource *res;
2134 int ret;
2135
2136 /* We only support device-tree instantiation */
2137 if (!dn)
2138 return -ENODEV;
2139
2140 if (!of_match_node(brcmnand_of_match, dn))
2141 return -ENODEV;
2142
2143 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
2144 if (!ctrl)
2145 return -ENOMEM;
2146
2147 dev_set_drvdata(dev, ctrl);
2148 ctrl->dev = dev;
2149
2150 init_completion(&ctrl->done);
2151 init_completion(&ctrl->dma_done);
2152 spin_lock_init(&ctrl->controller.lock);
2153 init_waitqueue_head(&ctrl->controller.wq);
2154 INIT_LIST_HEAD(&ctrl->host_list);
2155
2156 /* NAND register range */
2157 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2158 ctrl->nand_base = devm_ioremap_resource(dev, res);
2159 if (IS_ERR(ctrl->nand_base))
2160 return PTR_ERR(ctrl->nand_base);
2161
2162 /* Enable clock before using NAND registers */
2163 ctrl->clk = devm_clk_get(dev, "nand");
2164 if (!IS_ERR(ctrl->clk)) {
2165 ret = clk_prepare_enable(ctrl->clk);
2166 if (ret)
2167 return ret;
2168 } else {
2169 ret = PTR_ERR(ctrl->clk);
2170 if (ret == -EPROBE_DEFER)
2171 return ret;
2172
2173 ctrl->clk = NULL;
2174 }
2175
2176 /* Initialize NAND revision */
2177 ret = brcmnand_revision_init(ctrl);
2178 if (ret)
2179 goto err;
2180
2181 /*
2182 * Most chips have this cache at a fixed offset within 'nand' block.
2183 * Some must specify this region separately.
2184 */
2185 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache");
2186 if (res) {
2187 ctrl->nand_fc = devm_ioremap_resource(dev, res);
2188 if (IS_ERR(ctrl->nand_fc)) {
2189 ret = PTR_ERR(ctrl->nand_fc);
2190 goto err;
2191 }
2192 } else {
2193 ctrl->nand_fc = ctrl->nand_base +
2194 ctrl->reg_offsets[BRCMNAND_FC_BASE];
2195 }
2196
2197 /* FLASH_DMA */
2198 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma");
2199 if (res) {
2200 ctrl->flash_dma_base = devm_ioremap_resource(dev, res);
2201 if (IS_ERR(ctrl->flash_dma_base)) {
2202 ret = PTR_ERR(ctrl->flash_dma_base);
2203 goto err;
2204 }
2205
2206 flash_dma_writel(ctrl, FLASH_DMA_MODE, 1); /* linked-list */
2207 flash_dma_writel(ctrl, FLASH_DMA_ERROR_STATUS, 0);
2208
2209 /* Allocate descriptor(s) */
2210 ctrl->dma_desc = dmam_alloc_coherent(dev,
2211 sizeof(*ctrl->dma_desc),
2212 &ctrl->dma_pa, GFP_KERNEL);
2213 if (!ctrl->dma_desc) {
2214 ret = -ENOMEM;
2215 goto err;
2216 }
2217
2218 ctrl->dma_irq = platform_get_irq(pdev, 1);
2219 if ((int)ctrl->dma_irq < 0) {
2220 dev_err(dev, "missing FLASH_DMA IRQ\n");
2221 ret = -ENODEV;
2222 goto err;
2223 }
2224
2225 ret = devm_request_irq(dev, ctrl->dma_irq,
2226 brcmnand_dma_irq, 0, DRV_NAME,
2227 ctrl);
2228 if (ret < 0) {
2229 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2230 ctrl->dma_irq, ret);
2231 goto err;
2232 }
2233
2234 dev_info(dev, "enabling FLASH_DMA\n");
2235 }
2236
2237 /* Disable automatic device ID config, direct addressing */
2238 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_SELECT,
2239 CS_SELECT_AUTO_DEVICE_ID_CFG | 0xff, 0, 0);
2240 /* Disable XOR addressing */
2241 brcmnand_rmw_reg(ctrl, BRCMNAND_CS_XOR, 0xff, 0, 0);
2242
2243 if (ctrl->features & BRCMNAND_HAS_WP) {
2244 /* Permanently disable write protection */
2245 if (wp_on == 2)
2246 brcmnand_set_wp(ctrl, false);
2247 } else {
2248 wp_on = 0;
2249 }
2250
2251 /* IRQ */
2252 ctrl->irq = platform_get_irq(pdev, 0);
2253 if ((int)ctrl->irq < 0) {
2254 dev_err(dev, "no IRQ defined\n");
2255 ret = -ENODEV;
2256 goto err;
2257 }
2258
2259 /*
2260 * Some SoCs integrate this controller (e.g., its interrupt bits) in
2261 * interesting ways
2262 */
2263 if (soc) {
2264 ctrl->soc = soc;
2265
2266 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
2267 DRV_NAME, ctrl);
2268
2269 /* Enable interrupt */
2270 ctrl->soc->ctlrdy_ack(ctrl->soc);
2271 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
2272 } else {
2273 /* Use standard interrupt infrastructure */
2274 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
2275 DRV_NAME, ctrl);
2276 }
2277 if (ret < 0) {
2278 dev_err(dev, "can't allocate IRQ %d: error %d\n",
2279 ctrl->irq, ret);
2280 goto err;
2281 }
2282
2283 for_each_available_child_of_node(dn, child) {
2284 if (of_device_is_compatible(child, "brcm,nandcs")) {
2285 struct brcmnand_host *host;
2286
2287 host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
2288 if (!host) {
2289 of_node_put(child);
2290 ret = -ENOMEM;
2291 goto err;
2292 }
2293 host->pdev = pdev;
2294 host->ctrl = ctrl;
2295
2296 ret = brcmnand_init_cs(host, child);
2297 if (ret) {
2298 devm_kfree(dev, host);
2299 continue; /* Try all chip-selects */
2300 }
2301
2302 list_add_tail(&host->node, &ctrl->host_list);
2303 }
2304 }
2305
2306 /* No chip-selects could initialize properly */
2307 if (list_empty(&ctrl->host_list)) {
2308 ret = -ENODEV;
2309 goto err;
2310 }
2311
2312 return 0;
2313
2314 err:
2315 clk_disable_unprepare(ctrl->clk);
2316 return ret;
2317
2318 }
2319 EXPORT_SYMBOL_GPL(brcmnand_probe);
2320
2321 int brcmnand_remove(struct platform_device *pdev)
2322 {
2323 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev);
2324 struct brcmnand_host *host;
2325
2326 list_for_each_entry(host, &ctrl->host_list, node)
2327 nand_release(nand_to_mtd(&host->chip));
2328
2329 clk_disable_unprepare(ctrl->clk);
2330
2331 dev_set_drvdata(&pdev->dev, NULL);
2332
2333 return 0;
2334 }
2335 EXPORT_SYMBOL_GPL(brcmnand_remove);
2336
2337 MODULE_LICENSE("GPL v2");
2338 MODULE_AUTHOR("Kevin Cernekee");
2339 MODULE_AUTHOR("Brian Norris");
2340 MODULE_DESCRIPTION("NAND driver for Broadcom chips");
2341 MODULE_ALIAS("platform:brcmnand");
Linux kernel - Deliverables
This page took 0.099713 seconds and 6 git commands to generate.