2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
4 * Copyright © 2006 Texas Instruments.
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/module.h>
29 #include <linux/platform_device.h>
30 #include <linux/err.h>
31 #include <linux/clk.h>
33 #include <linux/mtd/nand.h>
34 #include <linux/mtd/partitions.h>
36 #include <mach/nand.h>
38 #include <asm/mach-types.h>
42 * This is a device driver for the NAND flash controller found on the
43 * various DaVinci family chips. It handles up to four SoC chipselects,
44 * and some flavors of secondary chipselect (e.g. based on A12) as used
45 * with multichip packages.
47 * The 1-bit ECC hardware is supported, but not yet the newer 4-bit ECC
48 * available on chips like the DM355 and OMAP-L137 and needed with the
49 * more error-prone MLC NAND chips.
51 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
52 * outputs in a "wire-AND" configuration, with no per-chip signals.
54 struct davinci_nand_info
{
56 struct nand_chip chip
;
68 uint32_t mask_chipsel
;
72 uint32_t core_chipsel
;
75 static DEFINE_SPINLOCK(davinci_nand_lock
);
77 #define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)
80 static inline unsigned int davinci_nand_readl(struct davinci_nand_info
*info
,
83 return __raw_readl(info
->base
+ offset
);
86 static inline void davinci_nand_writel(struct davinci_nand_info
*info
,
87 int offset
, unsigned long value
)
89 __raw_writel(value
, info
->base
+ offset
);
92 /*----------------------------------------------------------------------*/
95 * Access to hardware control lines: ALE, CLE, secondary chipselect.
98 static void nand_davinci_hwcontrol(struct mtd_info
*mtd
, int cmd
,
101 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
102 uint32_t addr
= info
->current_cs
;
103 struct nand_chip
*nand
= mtd
->priv
;
105 /* Did the control lines change? */
106 if (ctrl
& NAND_CTRL_CHANGE
) {
107 if ((ctrl
& NAND_CTRL_CLE
) == NAND_CTRL_CLE
)
108 addr
|= info
->mask_cle
;
109 else if ((ctrl
& NAND_CTRL_ALE
) == NAND_CTRL_ALE
)
110 addr
|= info
->mask_ale
;
112 nand
->IO_ADDR_W
= (void __iomem __force
*)addr
;
115 if (cmd
!= NAND_CMD_NONE
)
116 iowrite8(cmd
, nand
->IO_ADDR_W
);
119 static void nand_davinci_select_chip(struct mtd_info
*mtd
, int chip
)
121 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
122 uint32_t addr
= info
->ioaddr
;
124 /* maybe kick in a second chipselect */
126 addr
|= info
->mask_chipsel
;
127 info
->current_cs
= addr
;
129 info
->chip
.IO_ADDR_W
= (void __iomem __force
*)addr
;
130 info
->chip
.IO_ADDR_R
= info
->chip
.IO_ADDR_W
;
133 /*----------------------------------------------------------------------*/
136 * 1-bit hardware ECC ... context maintained for each core chipselect
139 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info
*mtd
)
141 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
143 return davinci_nand_readl(info
, NANDF1ECC_OFFSET
144 + 4 * info
->core_chipsel
);
147 static void nand_davinci_hwctl_1bit(struct mtd_info
*mtd
, int mode
)
149 struct davinci_nand_info
*info
;
153 info
= to_davinci_nand(mtd
);
155 /* Reset ECC hardware */
156 nand_davinci_readecc_1bit(mtd
);
158 spin_lock_irqsave(&davinci_nand_lock
, flags
);
160 /* Restart ECC hardware */
161 nandcfr
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
162 nandcfr
|= BIT(8 + info
->core_chipsel
);
163 davinci_nand_writel(info
, NANDFCR_OFFSET
, nandcfr
);
165 spin_unlock_irqrestore(&davinci_nand_lock
, flags
);
169 * Read hardware ECC value and pack into three bytes
171 static int nand_davinci_calculate_1bit(struct mtd_info
*mtd
,
172 const u_char
*dat
, u_char
*ecc_code
)
174 unsigned int ecc_val
= nand_davinci_readecc_1bit(mtd
);
175 unsigned int ecc24
= (ecc_val
& 0x0fff) | ((ecc_val
& 0x0fff0000) >> 4);
177 /* invert so that erased block ecc is correct */
179 ecc_code
[0] = (u_char
)(ecc24
);
180 ecc_code
[1] = (u_char
)(ecc24
>> 8);
181 ecc_code
[2] = (u_char
)(ecc24
>> 16);
186 static int nand_davinci_correct_1bit(struct mtd_info
*mtd
, u_char
*dat
,
187 u_char
*read_ecc
, u_char
*calc_ecc
)
189 struct nand_chip
*chip
= mtd
->priv
;
190 uint32_t eccNand
= read_ecc
[0] | (read_ecc
[1] << 8) |
192 uint32_t eccCalc
= calc_ecc
[0] | (calc_ecc
[1] << 8) |
194 uint32_t diff
= eccCalc
^ eccNand
;
197 if ((((diff
>> 12) ^ diff
) & 0xfff) == 0xfff) {
198 /* Correctable error */
199 if ((diff
>> (12 + 3)) < chip
->ecc
.size
) {
200 dat
[diff
>> (12 + 3)] ^= BIT((diff
>> 12) & 7);
205 } else if (!(diff
& (diff
- 1))) {
206 /* Single bit ECC error in the ECC itself,
210 /* Uncorrectable error */
218 /*----------------------------------------------------------------------*/
221 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
222 * how these chips are normally wired. This translates to both 8 and 16
223 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
225 * For now we assume that configuration, or any other one which ignores
226 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
227 * and have that transparently morphed into multiple NAND operations.
229 static void nand_davinci_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
231 struct nand_chip
*chip
= mtd
->priv
;
233 if ((0x03 & ((unsigned)buf
)) == 0 && (0x03 & len
) == 0)
234 ioread32_rep(chip
->IO_ADDR_R
, buf
, len
>> 2);
235 else if ((0x01 & ((unsigned)buf
)) == 0 && (0x01 & len
) == 0)
236 ioread16_rep(chip
->IO_ADDR_R
, buf
, len
>> 1);
238 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
241 static void nand_davinci_write_buf(struct mtd_info
*mtd
,
242 const uint8_t *buf
, int len
)
244 struct nand_chip
*chip
= mtd
->priv
;
246 if ((0x03 & ((unsigned)buf
)) == 0 && (0x03 & len
) == 0)
247 iowrite32_rep(chip
->IO_ADDR_R
, buf
, len
>> 2);
248 else if ((0x01 & ((unsigned)buf
)) == 0 && (0x01 & len
) == 0)
249 iowrite16_rep(chip
->IO_ADDR_R
, buf
, len
>> 1);
251 iowrite8_rep(chip
->IO_ADDR_R
, buf
, len
);
255 * Check hardware register for wait status. Returns 1 if device is ready,
256 * 0 if it is still busy.
258 static int nand_davinci_dev_ready(struct mtd_info
*mtd
)
260 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
262 return davinci_nand_readl(info
, NANDFSR_OFFSET
) & BIT(0);
265 static void __init
nand_dm6446evm_flash_init(struct davinci_nand_info
*info
)
267 uint32_t regval
, a1cr
;
270 * NAND FLASH timings @ PLL1 == 459 MHz
271 * - AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz
272 * - AEMIF.CLK period = 1/76.5 MHz = 13.1 ns
275 | (0 << 31) /* selectStrobe */
276 | (0 << 30) /* extWait (never with NAND) */
277 | (1 << 26) /* writeSetup 10 ns */
278 | (3 << 20) /* writeStrobe 40 ns */
279 | (1 << 17) /* writeHold 10 ns */
280 | (0 << 13) /* readSetup 10 ns */
281 | (3 << 7) /* readStrobe 60 ns */
282 | (0 << 4) /* readHold 10 ns */
283 | (3 << 2) /* turnAround ?? ns */
284 | (0 << 0) /* asyncSize 8-bit bus */
286 a1cr
= davinci_nand_readl(info
, A1CR_OFFSET
);
287 if (a1cr
!= regval
) {
288 dev_dbg(info
->dev
, "Warning: NAND config: Set A1CR " \
289 "reg to 0x%08x, was 0x%08x, should be done by " \
290 "bootloader.\n", regval
, a1cr
);
291 davinci_nand_writel(info
, A1CR_OFFSET
, regval
);
295 /*----------------------------------------------------------------------*/
297 static int __init
nand_davinci_probe(struct platform_device
*pdev
)
299 struct davinci_nand_pdata
*pdata
= pdev
->dev
.platform_data
;
300 struct davinci_nand_info
*info
;
301 struct resource
*res1
;
302 struct resource
*res2
;
307 nand_ecc_modes_t ecc_mode
;
309 /* insist on board-specific configuration */
313 /* which external chipselect will we be managing? */
314 if (pdev
->id
< 0 || pdev
->id
> 3)
317 info
= kzalloc(sizeof(*info
), GFP_KERNEL
);
319 dev_err(&pdev
->dev
, "unable to allocate memory\n");
324 platform_set_drvdata(pdev
, info
);
326 res1
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
327 res2
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
328 if (!res1
|| !res2
) {
329 dev_err(&pdev
->dev
, "resource missing\n");
334 vaddr
= ioremap(res1
->start
, res1
->end
- res1
->start
);
335 base
= ioremap(res2
->start
, res2
->end
- res2
->start
);
336 if (!vaddr
|| !base
) {
337 dev_err(&pdev
->dev
, "ioremap failed\n");
342 info
->dev
= &pdev
->dev
;
346 info
->mtd
.priv
= &info
->chip
;
347 info
->mtd
.name
= dev_name(&pdev
->dev
);
348 info
->mtd
.owner
= THIS_MODULE
;
350 info
->mtd
.dev
.parent
= &pdev
->dev
;
352 info
->chip
.IO_ADDR_R
= vaddr
;
353 info
->chip
.IO_ADDR_W
= vaddr
;
354 info
->chip
.chip_delay
= 0;
355 info
->chip
.select_chip
= nand_davinci_select_chip
;
357 /* options such as NAND_USE_FLASH_BBT or 16-bit widths */
358 info
->chip
.options
= pdata
->options
;
360 info
->ioaddr
= (uint32_t __force
) vaddr
;
362 info
->current_cs
= info
->ioaddr
;
363 info
->core_chipsel
= pdev
->id
;
364 info
->mask_chipsel
= pdata
->mask_chipsel
;
366 /* use nandboot-capable ALE/CLE masks by default */
367 info
->mask_ale
= pdata
->mask_cle
? : MASK_ALE
;
368 info
->mask_cle
= pdata
->mask_cle
? : MASK_CLE
;
370 /* Set address of hardware control function */
371 info
->chip
.cmd_ctrl
= nand_davinci_hwcontrol
;
372 info
->chip
.dev_ready
= nand_davinci_dev_ready
;
374 /* Speed up buffer I/O */
375 info
->chip
.read_buf
= nand_davinci_read_buf
;
376 info
->chip
.write_buf
= nand_davinci_write_buf
;
378 /* Use board-specific ECC config */
379 ecc_mode
= pdata
->ecc_mode
;
386 info
->chip
.ecc
.calculate
= nand_davinci_calculate_1bit
;
387 info
->chip
.ecc
.correct
= nand_davinci_correct_1bit
;
388 info
->chip
.ecc
.hwctl
= nand_davinci_hwctl_1bit
;
389 info
->chip
.ecc
.size
= 512;
390 info
->chip
.ecc
.bytes
= 3;
392 case NAND_ECC_HW_SYNDROME
:
393 /* FIXME implement */
394 info
->chip
.ecc
.size
= 512;
395 info
->chip
.ecc
.bytes
= 10;
397 dev_warn(&pdev
->dev
, "4-bit ECC nyet supported\n");
403 info
->chip
.ecc
.mode
= ecc_mode
;
405 info
->clk
= clk_get(&pdev
->dev
, "AEMIFCLK");
406 if (IS_ERR(info
->clk
)) {
407 ret
= PTR_ERR(info
->clk
);
408 dev_dbg(&pdev
->dev
, "unable to get AEMIFCLK, err %d\n", ret
);
412 ret
= clk_enable(info
->clk
);
414 dev_dbg(&pdev
->dev
, "unable to enable AEMIFCLK, err %d\n", ret
);
418 /* EMIF timings should normally be set by the boot loader,
419 * especially after boot-from-NAND. The *only* reason to
420 * have this special casing for the DM6446 EVM is to work
421 * with boot-from-NOR ... with CS0 manually re-jumpered
422 * (after startup) so it addresses the NAND flash, not NOR.
423 * Even for dev boards, that's unusually rude...
425 if (machine_is_davinci_evm())
426 nand_dm6446evm_flash_init(info
);
428 spin_lock_irq(&davinci_nand_lock
);
430 /* put CSxNAND into NAND mode */
431 val
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
432 val
|= BIT(info
->core_chipsel
);
433 davinci_nand_writel(info
, NANDFCR_OFFSET
, val
);
435 spin_unlock_irq(&davinci_nand_lock
);
437 /* Scan to find existence of the device(s) */
438 ret
= nand_scan(&info
->mtd
, pdata
->mask_chipsel
? 2 : 1);
440 dev_dbg(&pdev
->dev
, "no NAND chip(s) found\n");
444 if (mtd_has_partitions()) {
445 struct mtd_partition
*mtd_parts
= NULL
;
446 int mtd_parts_nb
= 0;
448 if (mtd_has_cmdlinepart()) {
449 static const char *probes
[] __initconst
=
450 { "cmdlinepart", NULL
};
452 const char *master_name
;
454 /* Set info->mtd.name = 0 temporarily */
455 master_name
= info
->mtd
.name
;
456 info
->mtd
.name
= (char *)0;
458 /* info->mtd.name == 0, means: don't bother checking
460 mtd_parts_nb
= parse_mtd_partitions(&info
->mtd
, probes
,
463 /* Restore info->mtd.name */
464 info
->mtd
.name
= master_name
;
467 if (mtd_parts_nb
<= 0) {
468 mtd_parts
= pdata
->parts
;
469 mtd_parts_nb
= pdata
->nr_parts
;
472 /* Register any partitions */
473 if (mtd_parts_nb
> 0) {
474 ret
= add_mtd_partitions(&info
->mtd
,
475 mtd_parts
, mtd_parts_nb
);
477 info
->partitioned
= true;
480 } else if (pdata
->nr_parts
) {
481 dev_warn(&pdev
->dev
, "ignoring %d default partitions on %s\n",
482 pdata
->nr_parts
, info
->mtd
.name
);
485 /* If there's no partition info, just package the whole chip
486 * as a single MTD device.
488 if (!info
->partitioned
)
489 ret
= add_mtd_device(&info
->mtd
) ? -ENODEV
: 0;
494 val
= davinci_nand_readl(info
, NRCSR_OFFSET
);
495 dev_info(&pdev
->dev
, "controller rev. %d.%d\n",
496 (val
>> 8) & 0xff, val
& 0xff);
501 clk_disable(info
->clk
);
519 static int __exit
nand_davinci_remove(struct platform_device
*pdev
)
521 struct davinci_nand_info
*info
= platform_get_drvdata(pdev
);
524 if (mtd_has_partitions() && info
->partitioned
)
525 status
= del_mtd_partitions(&info
->mtd
);
527 status
= del_mtd_device(&info
->mtd
);
530 iounmap(info
->vaddr
);
532 nand_release(&info
->mtd
);
534 clk_disable(info
->clk
);
542 static struct platform_driver nand_davinci_driver
= {
543 .remove
= __exit_p(nand_davinci_remove
),
545 .name
= "davinci_nand",
548 MODULE_ALIAS("platform:davinci_nand");
550 static int __init
nand_davinci_init(void)
552 return platform_driver_probe(&nand_davinci_driver
, nand_davinci_probe
);
554 module_init(nand_davinci_init
);
556 static void __exit
nand_davinci_exit(void)
558 platform_driver_unregister(&nand_davinci_driver
);
560 module_exit(nand_davinci_exit
);
562 MODULE_LICENSE("GPL");
563 MODULE_AUTHOR("Texas Instruments");
564 MODULE_DESCRIPTION("Davinci NAND flash driver");