2 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
4 * Copyright © 2006 Texas Instruments.
6 * Port to 2.6.23 Copyright © 2008 by:
7 * Sander Huijsen <Shuijsen@optelecom-nkf.com>
8 * Troy Kisky <troy.kisky@boundarydevices.com>
9 * Dirk Behme <Dirk.Behme@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/err.h>
30 #include <linux/clk.h>
32 #include <linux/mtd/nand.h>
33 #include <linux/mtd/partitions.h>
34 #include <linux/slab.h>
35 #include <linux/of_device.h>
37 #include <linux/of_mtd.h>
39 #include <linux/platform_data/mtd-davinci.h>
40 #include <linux/platform_data/mtd-davinci-aemif.h>
43 * This is a device driver for the NAND flash controller found on the
44 * various DaVinci family chips. It handles up to four SoC chipselects,
45 * and some flavors of secondary chipselect (e.g. based on A12) as used
46 * with multichip packages.
48 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
49 * available on chips like the DM355 and OMAP-L137 and needed with the
50 * more error-prone MLC NAND chips.
52 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
53 * outputs in a "wire-AND" configuration, with no per-chip signals.
55 struct davinci_nand_info
{
56 struct nand_chip chip
;
69 uint32_t mask_chipsel
;
73 uint32_t core_chipsel
;
75 struct davinci_aemif_timing
*timing
;
78 static DEFINE_SPINLOCK(davinci_nand_lock
);
79 static bool ecc4_busy
;
81 static inline struct davinci_nand_info
*to_davinci_nand(struct mtd_info
*mtd
)
83 return container_of(mtd_to_nand(mtd
), struct davinci_nand_info
, chip
);
86 static inline unsigned int davinci_nand_readl(struct davinci_nand_info
*info
,
89 return __raw_readl(info
->base
+ offset
);
92 static inline void davinci_nand_writel(struct davinci_nand_info
*info
,
93 int offset
, unsigned long value
)
95 __raw_writel(value
, info
->base
+ offset
);
98 /*----------------------------------------------------------------------*/
101 * Access to hardware control lines: ALE, CLE, secondary chipselect.
104 static void nand_davinci_hwcontrol(struct mtd_info
*mtd
, int cmd
,
107 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
108 uint32_t addr
= info
->current_cs
;
109 struct nand_chip
*nand
= mtd_to_nand(mtd
);
111 /* Did the control lines change? */
112 if (ctrl
& NAND_CTRL_CHANGE
) {
113 if ((ctrl
& NAND_CTRL_CLE
) == NAND_CTRL_CLE
)
114 addr
|= info
->mask_cle
;
115 else if ((ctrl
& NAND_CTRL_ALE
) == NAND_CTRL_ALE
)
116 addr
|= info
->mask_ale
;
118 nand
->IO_ADDR_W
= (void __iomem __force
*)addr
;
121 if (cmd
!= NAND_CMD_NONE
)
122 iowrite8(cmd
, nand
->IO_ADDR_W
);
125 static void nand_davinci_select_chip(struct mtd_info
*mtd
, int chip
)
127 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
128 uint32_t addr
= info
->ioaddr
;
130 /* maybe kick in a second chipselect */
132 addr
|= info
->mask_chipsel
;
133 info
->current_cs
= addr
;
135 info
->chip
.IO_ADDR_W
= (void __iomem __force
*)addr
;
136 info
->chip
.IO_ADDR_R
= info
->chip
.IO_ADDR_W
;
139 /*----------------------------------------------------------------------*/
142 * 1-bit hardware ECC ... context maintained for each core chipselect
145 static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info
*mtd
)
147 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
149 return davinci_nand_readl(info
, NANDF1ECC_OFFSET
150 + 4 * info
->core_chipsel
);
153 static void nand_davinci_hwctl_1bit(struct mtd_info
*mtd
, int mode
)
155 struct davinci_nand_info
*info
;
159 info
= to_davinci_nand(mtd
);
161 /* Reset ECC hardware */
162 nand_davinci_readecc_1bit(mtd
);
164 spin_lock_irqsave(&davinci_nand_lock
, flags
);
166 /* Restart ECC hardware */
167 nandcfr
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
168 nandcfr
|= BIT(8 + info
->core_chipsel
);
169 davinci_nand_writel(info
, NANDFCR_OFFSET
, nandcfr
);
171 spin_unlock_irqrestore(&davinci_nand_lock
, flags
);
175 * Read hardware ECC value and pack into three bytes
177 static int nand_davinci_calculate_1bit(struct mtd_info
*mtd
,
178 const u_char
*dat
, u_char
*ecc_code
)
180 unsigned int ecc_val
= nand_davinci_readecc_1bit(mtd
);
181 unsigned int ecc24
= (ecc_val
& 0x0fff) | ((ecc_val
& 0x0fff0000) >> 4);
183 /* invert so that erased block ecc is correct */
185 ecc_code
[0] = (u_char
)(ecc24
);
186 ecc_code
[1] = (u_char
)(ecc24
>> 8);
187 ecc_code
[2] = (u_char
)(ecc24
>> 16);
192 static int nand_davinci_correct_1bit(struct mtd_info
*mtd
, u_char
*dat
,
193 u_char
*read_ecc
, u_char
*calc_ecc
)
195 struct nand_chip
*chip
= mtd_to_nand(mtd
);
196 uint32_t eccNand
= read_ecc
[0] | (read_ecc
[1] << 8) |
198 uint32_t eccCalc
= calc_ecc
[0] | (calc_ecc
[1] << 8) |
200 uint32_t diff
= eccCalc
^ eccNand
;
203 if ((((diff
>> 12) ^ diff
) & 0xfff) == 0xfff) {
204 /* Correctable error */
205 if ((diff
>> (12 + 3)) < chip
->ecc
.size
) {
206 dat
[diff
>> (12 + 3)] ^= BIT((diff
>> 12) & 7);
211 } else if (!(diff
& (diff
- 1))) {
212 /* Single bit ECC error in the ECC itself,
216 /* Uncorrectable error */
224 /*----------------------------------------------------------------------*/
227 * 4-bit hardware ECC ... context maintained over entire AEMIF
229 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
230 * since that forces use of a problematic "infix OOB" layout.
231 * Among other things, it trashes manufacturer bad block markers.
232 * Also, and specific to this hardware, it ECC-protects the "prepad"
233 * in the OOB ... while having ECC protection for parts of OOB would
234 * seem useful, the current MTD stack sometimes wants to update the
235 * OOB without recomputing ECC.
238 static void nand_davinci_hwctl_4bit(struct mtd_info
*mtd
, int mode
)
240 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
244 spin_lock_irqsave(&davinci_nand_lock
, flags
);
246 /* Start 4-bit ECC calculation for read/write */
247 val
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
249 val
|= (info
->core_chipsel
<< 4) | BIT(12);
250 davinci_nand_writel(info
, NANDFCR_OFFSET
, val
);
252 info
->is_readmode
= (mode
== NAND_ECC_READ
);
254 spin_unlock_irqrestore(&davinci_nand_lock
, flags
);
257 /* Read raw ECC code after writing to NAND. */
259 nand_davinci_readecc_4bit(struct davinci_nand_info
*info
, u32 code
[4])
261 const u32 mask
= 0x03ff03ff;
263 code
[0] = davinci_nand_readl(info
, NAND_4BIT_ECC1_OFFSET
) & mask
;
264 code
[1] = davinci_nand_readl(info
, NAND_4BIT_ECC2_OFFSET
) & mask
;
265 code
[2] = davinci_nand_readl(info
, NAND_4BIT_ECC3_OFFSET
) & mask
;
266 code
[3] = davinci_nand_readl(info
, NAND_4BIT_ECC4_OFFSET
) & mask
;
269 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
270 static int nand_davinci_calculate_4bit(struct mtd_info
*mtd
,
271 const u_char
*dat
, u_char
*ecc_code
)
273 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
277 /* After a read, terminate ECC calculation by a dummy read
278 * of some 4-bit ECC register. ECC covers everything that
279 * was read; correct() just uses the hardware state, so
280 * ecc_code is not needed.
282 if (info
->is_readmode
) {
283 davinci_nand_readl(info
, NAND_4BIT_ECC1_OFFSET
);
287 /* Pack eight raw 10-bit ecc values into ten bytes, making
288 * two passes which each convert four values (in upper and
289 * lower halves of two 32-bit words) into five bytes. The
290 * ROM boot loader uses this same packing scheme.
292 nand_davinci_readecc_4bit(info
, raw_ecc
);
293 for (i
= 0, p
= raw_ecc
; i
< 2; i
++, p
+= 2) {
294 *ecc_code
++ = p
[0] & 0xff;
295 *ecc_code
++ = ((p
[0] >> 8) & 0x03) | ((p
[0] >> 14) & 0xfc);
296 *ecc_code
++ = ((p
[0] >> 22) & 0x0f) | ((p
[1] << 4) & 0xf0);
297 *ecc_code
++ = ((p
[1] >> 4) & 0x3f) | ((p
[1] >> 10) & 0xc0);
298 *ecc_code
++ = (p
[1] >> 18) & 0xff;
304 /* Correct up to 4 bits in data we just read, using state left in the
305 * hardware plus the ecc_code computed when it was first written.
307 static int nand_davinci_correct_4bit(struct mtd_info
*mtd
,
308 u_char
*data
, u_char
*ecc_code
, u_char
*null
)
311 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
312 unsigned short ecc10
[8];
313 unsigned short *ecc16
;
316 unsigned num_errors
, corrected
;
319 /* Unpack ten bytes into eight 10 bit values. We know we're
320 * little-endian, and use type punning for less shifting/masking.
322 if (WARN_ON(0x01 & (unsigned) ecc_code
))
324 ecc16
= (unsigned short *)ecc_code
;
326 ecc10
[0] = (ecc16
[0] >> 0) & 0x3ff;
327 ecc10
[1] = ((ecc16
[0] >> 10) & 0x3f) | ((ecc16
[1] << 6) & 0x3c0);
328 ecc10
[2] = (ecc16
[1] >> 4) & 0x3ff;
329 ecc10
[3] = ((ecc16
[1] >> 14) & 0x3) | ((ecc16
[2] << 2) & 0x3fc);
330 ecc10
[4] = (ecc16
[2] >> 8) | ((ecc16
[3] << 8) & 0x300);
331 ecc10
[5] = (ecc16
[3] >> 2) & 0x3ff;
332 ecc10
[6] = ((ecc16
[3] >> 12) & 0xf) | ((ecc16
[4] << 4) & 0x3f0);
333 ecc10
[7] = (ecc16
[4] >> 6) & 0x3ff;
335 /* Tell ECC controller about the expected ECC codes. */
336 for (i
= 7; i
>= 0; i
--)
337 davinci_nand_writel(info
, NAND_4BIT_ECC_LOAD_OFFSET
, ecc10
[i
]);
339 /* Allow time for syndrome calculation ... then read it.
340 * A syndrome of all zeroes 0 means no detected errors.
342 davinci_nand_readl(info
, NANDFSR_OFFSET
);
343 nand_davinci_readecc_4bit(info
, syndrome
);
344 if (!(syndrome
[0] | syndrome
[1] | syndrome
[2] | syndrome
[3]))
348 * Clear any previous address calculation by doing a dummy read of an
349 * error address register.
351 davinci_nand_readl(info
, NAND_ERR_ADD1_OFFSET
);
353 /* Start address calculation, and wait for it to complete.
354 * We _could_ start reading more data while this is working,
355 * to speed up the overall page read.
357 davinci_nand_writel(info
, NANDFCR_OFFSET
,
358 davinci_nand_readl(info
, NANDFCR_OFFSET
) | BIT(13));
361 * ECC_STATE field reads 0x3 (Error correction complete) immediately
362 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
363 * begin trying to poll for the state, you may fall right out of your
364 * loop without any of the correction calculations having taken place.
365 * The recommendation from the hardware team is to initially delay as
366 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
369 timeo
= jiffies
+ usecs_to_jiffies(100);
371 ecc_state
= (davinci_nand_readl(info
,
372 NANDFSR_OFFSET
) >> 8) & 0x0f;
374 } while ((ecc_state
< 4) && time_before(jiffies
, timeo
));
377 u32 fsr
= davinci_nand_readl(info
, NANDFSR_OFFSET
);
379 switch ((fsr
>> 8) & 0x0f) {
380 case 0: /* no error, should not happen */
381 davinci_nand_readl(info
, NAND_ERR_ERRVAL1_OFFSET
);
383 case 1: /* five or more errors detected */
384 davinci_nand_readl(info
, NAND_ERR_ERRVAL1_OFFSET
);
386 case 2: /* error addresses computed */
388 num_errors
= 1 + ((fsr
>> 16) & 0x03);
390 default: /* still working on it */
397 /* correct each error */
398 for (i
= 0, corrected
= 0; i
< num_errors
; i
++) {
399 int error_address
, error_value
;
402 error_address
= davinci_nand_readl(info
,
403 NAND_ERR_ADD2_OFFSET
);
404 error_value
= davinci_nand_readl(info
,
405 NAND_ERR_ERRVAL2_OFFSET
);
407 error_address
= davinci_nand_readl(info
,
408 NAND_ERR_ADD1_OFFSET
);
409 error_value
= davinci_nand_readl(info
,
410 NAND_ERR_ERRVAL1_OFFSET
);
414 error_address
>>= 16;
417 error_address
&= 0x3ff;
418 error_address
= (512 + 7) - error_address
;
420 if (error_address
< 512) {
421 data
[error_address
] ^= error_value
;
429 /*----------------------------------------------------------------------*/
432 * NOTE: NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
433 * how these chips are normally wired. This translates to both 8 and 16
434 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
436 * For now we assume that configuration, or any other one which ignores
437 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
438 * and have that transparently morphed into multiple NAND operations.
440 static void nand_davinci_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
442 struct nand_chip
*chip
= mtd_to_nand(mtd
);
444 if ((0x03 & ((unsigned)buf
)) == 0 && (0x03 & len
) == 0)
445 ioread32_rep(chip
->IO_ADDR_R
, buf
, len
>> 2);
446 else if ((0x01 & ((unsigned)buf
)) == 0 && (0x01 & len
) == 0)
447 ioread16_rep(chip
->IO_ADDR_R
, buf
, len
>> 1);
449 ioread8_rep(chip
->IO_ADDR_R
, buf
, len
);
452 static void nand_davinci_write_buf(struct mtd_info
*mtd
,
453 const uint8_t *buf
, int len
)
455 struct nand_chip
*chip
= mtd_to_nand(mtd
);
457 if ((0x03 & ((unsigned)buf
)) == 0 && (0x03 & len
) == 0)
458 iowrite32_rep(chip
->IO_ADDR_R
, buf
, len
>> 2);
459 else if ((0x01 & ((unsigned)buf
)) == 0 && (0x01 & len
) == 0)
460 iowrite16_rep(chip
->IO_ADDR_R
, buf
, len
>> 1);
462 iowrite8_rep(chip
->IO_ADDR_R
, buf
, len
);
466 * Check hardware register for wait status. Returns 1 if device is ready,
467 * 0 if it is still busy.
469 static int nand_davinci_dev_ready(struct mtd_info
*mtd
)
471 struct davinci_nand_info
*info
= to_davinci_nand(mtd
);
473 return davinci_nand_readl(info
, NANDFSR_OFFSET
) & BIT(0);
476 /*----------------------------------------------------------------------*/
478 /* An ECC layout for using 4-bit ECC with small-page flash, storing
479 * ten ECC bytes plus the manufacturer's bad block marker byte, and
480 * and not overlapping the default BBT markers.
482 static int hwecc4_ooblayout_small_ecc(struct mtd_info
*mtd
, int section
,
483 struct mtd_oob_region
*oobregion
)
489 oobregion
->offset
= 0;
490 oobregion
->length
= 5;
491 } else if (section
== 1) {
492 oobregion
->offset
= 6;
493 oobregion
->length
= 2;
495 oobregion
->offset
= 13;
496 oobregion
->length
= 3;
502 static int hwecc4_ooblayout_small_free(struct mtd_info
*mtd
, int section
,
503 struct mtd_oob_region
*oobregion
)
509 oobregion
->offset
= 8;
510 oobregion
->length
= 5;
512 oobregion
->offset
= 16;
513 oobregion
->length
= mtd
->oobsize
- 16;
519 static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops
= {
520 .ecc
= hwecc4_ooblayout_small_ecc
,
521 .free
= hwecc4_ooblayout_small_free
,
524 #if defined(CONFIG_OF)
525 static const struct of_device_id davinci_nand_of_match
[] = {
526 {.compatible
= "ti,davinci-nand", },
527 {.compatible
= "ti,keystone-nand", },
530 MODULE_DEVICE_TABLE(of
, davinci_nand_of_match
);
532 static struct davinci_nand_pdata
533 *nand_davinci_get_pdata(struct platform_device
*pdev
)
535 if (!dev_get_platdata(&pdev
->dev
) && pdev
->dev
.of_node
) {
536 struct davinci_nand_pdata
*pdata
;
540 pdata
= devm_kzalloc(&pdev
->dev
,
541 sizeof(struct davinci_nand_pdata
),
543 pdev
->dev
.platform_data
= pdata
;
545 return ERR_PTR(-ENOMEM
);
546 if (!of_property_read_u32(pdev
->dev
.of_node
,
547 "ti,davinci-chipselect", &prop
))
550 return ERR_PTR(-EINVAL
);
552 if (!of_property_read_u32(pdev
->dev
.of_node
,
553 "ti,davinci-mask-ale", &prop
))
554 pdata
->mask_ale
= prop
;
555 if (!of_property_read_u32(pdev
->dev
.of_node
,
556 "ti,davinci-mask-cle", &prop
))
557 pdata
->mask_cle
= prop
;
558 if (!of_property_read_u32(pdev
->dev
.of_node
,
559 "ti,davinci-mask-chipsel", &prop
))
560 pdata
->mask_chipsel
= prop
;
561 if (!of_property_read_string(pdev
->dev
.of_node
,
562 "nand-ecc-mode", &mode
) ||
563 !of_property_read_string(pdev
->dev
.of_node
,
564 "ti,davinci-ecc-mode", &mode
)) {
565 if (!strncmp("none", mode
, 4))
566 pdata
->ecc_mode
= NAND_ECC_NONE
;
567 if (!strncmp("soft", mode
, 4))
568 pdata
->ecc_mode
= NAND_ECC_SOFT
;
569 if (!strncmp("hw", mode
, 2))
570 pdata
->ecc_mode
= NAND_ECC_HW
;
572 if (!of_property_read_u32(pdev
->dev
.of_node
,
573 "ti,davinci-ecc-bits", &prop
))
574 pdata
->ecc_bits
= prop
;
576 prop
= of_get_nand_bus_width(pdev
->dev
.of_node
);
577 if (0 < prop
|| !of_property_read_u32(pdev
->dev
.of_node
,
578 "ti,davinci-nand-buswidth", &prop
))
580 pdata
->options
|= NAND_BUSWIDTH_16
;
581 if (of_property_read_bool(pdev
->dev
.of_node
,
582 "nand-on-flash-bbt") ||
583 of_property_read_bool(pdev
->dev
.of_node
,
584 "ti,davinci-nand-use-bbt"))
585 pdata
->bbt_options
= NAND_BBT_USE_FLASH
;
587 if (of_device_is_compatible(pdev
->dev
.of_node
,
588 "ti,keystone-nand")) {
589 pdata
->options
|= NAND_NO_SUBPAGE_WRITE
;
593 return dev_get_platdata(&pdev
->dev
);
596 static struct davinci_nand_pdata
597 *nand_davinci_get_pdata(struct platform_device
*pdev
)
599 return dev_get_platdata(&pdev
->dev
);
603 static int nand_davinci_probe(struct platform_device
*pdev
)
605 struct davinci_nand_pdata
*pdata
;
606 struct davinci_nand_info
*info
;
607 struct resource
*res1
;
608 struct resource
*res2
;
613 nand_ecc_modes_t ecc_mode
;
614 struct mtd_info
*mtd
;
616 pdata
= nand_davinci_get_pdata(pdev
);
618 return PTR_ERR(pdata
);
620 /* insist on board-specific configuration */
624 /* which external chipselect will we be managing? */
625 if (pdev
->id
< 0 || pdev
->id
> 3)
628 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
632 platform_set_drvdata(pdev
, info
);
634 res1
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
635 res2
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
636 if (!res1
|| !res2
) {
637 dev_err(&pdev
->dev
, "resource missing\n");
641 vaddr
= devm_ioremap_resource(&pdev
->dev
, res1
);
643 return PTR_ERR(vaddr
);
646 * This registers range is used to setup NAND settings. In case with
647 * TI AEMIF driver, the same memory address range is requested already
648 * by AEMIF, so we cannot request it twice, just ioremap.
649 * The AEMIF and NAND drivers not use the same registers in this range.
651 base
= devm_ioremap(&pdev
->dev
, res2
->start
, resource_size(res2
));
653 dev_err(&pdev
->dev
, "ioremap failed for resource %pR\n", res2
);
654 return -EADDRNOTAVAIL
;
657 info
->dev
= &pdev
->dev
;
661 mtd
= nand_to_mtd(&info
->chip
);
662 mtd
->dev
.parent
= &pdev
->dev
;
663 nand_set_flash_node(&info
->chip
, pdev
->dev
.of_node
);
665 info
->chip
.IO_ADDR_R
= vaddr
;
666 info
->chip
.IO_ADDR_W
= vaddr
;
667 info
->chip
.chip_delay
= 0;
668 info
->chip
.select_chip
= nand_davinci_select_chip
;
670 /* options such as NAND_BBT_USE_FLASH */
671 info
->chip
.bbt_options
= pdata
->bbt_options
;
672 /* options such as 16-bit widths */
673 info
->chip
.options
= pdata
->options
;
674 info
->chip
.bbt_td
= pdata
->bbt_td
;
675 info
->chip
.bbt_md
= pdata
->bbt_md
;
676 info
->timing
= pdata
->timing
;
678 info
->ioaddr
= (uint32_t __force
) vaddr
;
680 info
->current_cs
= info
->ioaddr
;
681 info
->core_chipsel
= pdev
->id
;
682 info
->mask_chipsel
= pdata
->mask_chipsel
;
684 /* use nandboot-capable ALE/CLE masks by default */
685 info
->mask_ale
= pdata
->mask_ale
? : MASK_ALE
;
686 info
->mask_cle
= pdata
->mask_cle
? : MASK_CLE
;
688 /* Set address of hardware control function */
689 info
->chip
.cmd_ctrl
= nand_davinci_hwcontrol
;
690 info
->chip
.dev_ready
= nand_davinci_dev_ready
;
692 /* Speed up buffer I/O */
693 info
->chip
.read_buf
= nand_davinci_read_buf
;
694 info
->chip
.write_buf
= nand_davinci_write_buf
;
696 /* Use board-specific ECC config */
697 ecc_mode
= pdata
->ecc_mode
;
706 if (pdata
->ecc_bits
== 4) {
707 /* No sanity checks: CPUs must support this,
708 * and the chips may not use NAND_BUSWIDTH_16.
711 /* No sharing 4-bit hardware between chipselects yet */
712 spin_lock_irq(&davinci_nand_lock
);
717 spin_unlock_irq(&davinci_nand_lock
);
722 info
->chip
.ecc
.calculate
= nand_davinci_calculate_4bit
;
723 info
->chip
.ecc
.correct
= nand_davinci_correct_4bit
;
724 info
->chip
.ecc
.hwctl
= nand_davinci_hwctl_4bit
;
725 info
->chip
.ecc
.bytes
= 10;
726 info
->chip
.ecc
.options
= NAND_ECC_GENERIC_ERASED_CHECK
;
728 info
->chip
.ecc
.calculate
= nand_davinci_calculate_1bit
;
729 info
->chip
.ecc
.correct
= nand_davinci_correct_1bit
;
730 info
->chip
.ecc
.hwctl
= nand_davinci_hwctl_1bit
;
731 info
->chip
.ecc
.bytes
= 3;
733 info
->chip
.ecc
.size
= 512;
734 info
->chip
.ecc
.strength
= pdata
->ecc_bits
;
739 info
->chip
.ecc
.mode
= ecc_mode
;
741 info
->clk
= devm_clk_get(&pdev
->dev
, "aemif");
742 if (IS_ERR(info
->clk
)) {
743 ret
= PTR_ERR(info
->clk
);
744 dev_dbg(&pdev
->dev
, "unable to get AEMIF clock, err %d\n", ret
);
748 ret
= clk_prepare_enable(info
->clk
);
750 dev_dbg(&pdev
->dev
, "unable to enable AEMIF clock, err %d\n",
755 spin_lock_irq(&davinci_nand_lock
);
757 /* put CSxNAND into NAND mode */
758 val
= davinci_nand_readl(info
, NANDFCR_OFFSET
);
759 val
|= BIT(info
->core_chipsel
);
760 davinci_nand_writel(info
, NANDFCR_OFFSET
, val
);
762 spin_unlock_irq(&davinci_nand_lock
);
764 /* Scan to find existence of the device(s) */
765 ret
= nand_scan_ident(mtd
, pdata
->mask_chipsel
? 2 : 1, NULL
);
767 dev_dbg(&pdev
->dev
, "no NAND chip(s) found\n");
771 /* Update ECC layout if needed ... for 1-bit HW ECC, the default
772 * is OK, but it allocates 6 bytes when only 3 are needed (for
773 * each 512 bytes). For the 4-bit HW ECC, that default is not
774 * usable: 10 bytes are needed, not 6.
776 if (pdata
->ecc_bits
== 4) {
777 int chunks
= mtd
->writesize
/ 512;
779 if (!chunks
|| mtd
->oobsize
< 16) {
780 dev_dbg(&pdev
->dev
, "too small\n");
785 /* For small page chips, preserve the manufacturer's
786 * badblock marking data ... and make sure a flash BBT
787 * table marker fits in the free bytes.
790 mtd_set_ooblayout(mtd
, &hwecc4_small_ooblayout_ops
);
791 } else if (chunks
== 4 || chunks
== 8) {
792 mtd_set_ooblayout(mtd
, &nand_ooblayout_lp_ops
);
793 info
->chip
.ecc
.mode
= NAND_ECC_HW_OOB_FIRST
;
800 ret
= nand_scan_tail(mtd
);
805 ret
= mtd_device_parse_register(mtd
, NULL
, NULL
,
806 pdata
->parts
, pdata
->nr_parts
);
808 ret
= mtd_device_register(mtd
, NULL
, 0);
812 val
= davinci_nand_readl(info
, NRCSR_OFFSET
);
813 dev_info(&pdev
->dev
, "controller rev. %d.%d\n",
814 (val
>> 8) & 0xff, val
& 0xff);
819 clk_disable_unprepare(info
->clk
);
822 spin_lock_irq(&davinci_nand_lock
);
823 if (ecc_mode
== NAND_ECC_HW_SYNDROME
)
825 spin_unlock_irq(&davinci_nand_lock
);
829 static int nand_davinci_remove(struct platform_device
*pdev
)
831 struct davinci_nand_info
*info
= platform_get_drvdata(pdev
);
833 spin_lock_irq(&davinci_nand_lock
);
834 if (info
->chip
.ecc
.mode
== NAND_ECC_HW_SYNDROME
)
836 spin_unlock_irq(&davinci_nand_lock
);
838 nand_release(nand_to_mtd(&info
->chip
));
840 clk_disable_unprepare(info
->clk
);
845 static struct platform_driver nand_davinci_driver
= {
846 .probe
= nand_davinci_probe
,
847 .remove
= nand_davinci_remove
,
849 .name
= "davinci_nand",
850 .of_match_table
= of_match_ptr(davinci_nand_of_match
),
853 MODULE_ALIAS("platform:davinci_nand");
855 module_platform_driver(nand_davinci_driver
);
857 MODULE_LICENSE("GPL");
858 MODULE_AUTHOR("Texas Instruments");
859 MODULE_DESCRIPTION("Davinci NAND flash driver");