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mtd: denali: Remove device_info_tag structure
[deliverable/linux.git] / drivers / mtd / nand / denali.c
1 /*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/slab.h>
25 #include <linux/pci.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/module.h>
28
29 #include "denali.h"
30
31 MODULE_LICENSE("GPL");
32
33 /* We define a module parameter that allows the user to override
34 * the hardware and decide what timing mode should be used.
35 */
36 #define NAND_DEFAULT_TIMINGS -1
37
38 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39 module_param(onfi_timing_mode, int, S_IRUGO);
40 MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
41 " -1 indicates use default timings");
42
43 #define DENALI_NAND_NAME "denali-nand"
44
45 /* We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience. */
47 #define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \
48 INTR_STATUS0__ECC_TRANSACTION_DONE | \
49 INTR_STATUS0__ECC_ERR | \
50 INTR_STATUS0__PROGRAM_FAIL | \
51 INTR_STATUS0__LOAD_COMP | \
52 INTR_STATUS0__PROGRAM_COMP | \
53 INTR_STATUS0__TIME_OUT | \
54 INTR_STATUS0__ERASE_FAIL | \
55 INTR_STATUS0__RST_COMP | \
56 INTR_STATUS0__ERASE_COMP)
57
58 /* indicates whether or not the internal value for the flash bank is
59 valid or not */
60 #define CHIP_SELECT_INVALID -1
61
62 #define SUPPORT_8BITECC 1
63
64 /* This macro divides two integers and rounds fractional values up
65 * to the nearest integer value. */
66 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
67
68 /* this macro allows us to convert from an MTD structure to our own
69 * device context (denali) structure.
70 */
71 #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
72
73 /* These constants are defined by the driver to enable common driver
74 configuration options. */
75 #define SPARE_ACCESS 0x41
76 #define MAIN_ACCESS 0x42
77 #define MAIN_SPARE_ACCESS 0x43
78
79 #define DENALI_READ 0
80 #define DENALI_WRITE 0x100
81
82 /* types of device accesses. We can issue commands and get status */
83 #define COMMAND_CYCLE 0
84 #define ADDR_CYCLE 1
85 #define STATUS_CYCLE 2
86
87 /* this is a helper macro that allows us to
88 * format the bank into the proper bits for the controller */
89 #define BANK(x) ((x) << 24)
90
91 /* List of platforms this NAND controller has be integrated into */
92 static const struct pci_device_id denali_pci_ids[] = {
93 { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
94 { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
95 { /* end: all zeroes */ }
96 };
97
98
99 /* these are static lookup tables that give us easy access to
100 registers in the NAND controller.
101 */
102 static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
103 INTR_STATUS1,
104 INTR_STATUS2,
105 INTR_STATUS3};
106
107 static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
108 DEVICE_RESET__BANK1,
109 DEVICE_RESET__BANK2,
110 DEVICE_RESET__BANK3};
111
112 static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
113 INTR_STATUS1__TIME_OUT,
114 INTR_STATUS2__TIME_OUT,
115 INTR_STATUS3__TIME_OUT};
116
117 static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
118 INTR_STATUS1__RST_COMP,
119 INTR_STATUS2__RST_COMP,
120 INTR_STATUS3__RST_COMP};
121
122 /* specifies the debug level of the driver */
123 static int nand_debug_level;
124
125 /* forward declarations */
126 static void clear_interrupts(struct denali_nand_info *denali);
127 static uint32_t wait_for_irq(struct denali_nand_info *denali,
128 uint32_t irq_mask);
129 static void denali_irq_enable(struct denali_nand_info *denali,
130 uint32_t int_mask);
131 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
132
133 #define DEBUG_DENALI 0
134
135 /* This is a wrapper for writing to the denali registers.
136 * this allows us to create debug information so we can
137 * observe how the driver is programming the device.
138 * it uses standard linux convention for (val, addr) */
139 static void denali_write32(uint32_t value, void *addr)
140 {
141 iowrite32(value, addr);
142
143 #if DEBUG_DENALI
144 printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
145 (uint32_t)((uint32_t)addr & 0x1fff));
146 #endif
147 }
148
149 /* Certain operations for the denali NAND controller use
150 * an indexed mode to read/write data. The operation is
151 * performed by writing the address value of the command
152 * to the device memory followed by the data. This function
153 * abstracts this common operation.
154 */
155 static void index_addr(struct denali_nand_info *denali,
156 uint32_t address, uint32_t data)
157 {
158 denali_write32(address, denali->flash_mem);
159 denali_write32(data, denali->flash_mem + 0x10);
160 }
161
162 /* Perform an indexed read of the device */
163 static void index_addr_read_data(struct denali_nand_info *denali,
164 uint32_t address, uint32_t *pdata)
165 {
166 denali_write32(address, denali->flash_mem);
167 *pdata = ioread32(denali->flash_mem + 0x10);
168 }
169
170 /* We need to buffer some data for some of the NAND core routines.
171 * The operations manage buffering that data. */
172 static void reset_buf(struct denali_nand_info *denali)
173 {
174 denali->buf.head = denali->buf.tail = 0;
175 }
176
177 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
178 {
179 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
180 denali->buf.buf[denali->buf.tail++] = byte;
181 }
182
183 /* reads the status of the device */
184 static void read_status(struct denali_nand_info *denali)
185 {
186 uint32_t cmd = 0x0;
187
188 /* initialize the data buffer to store status */
189 reset_buf(denali);
190
191 /* initiate a device status read */
192 cmd = MODE_11 | BANK(denali->flash_bank);
193 index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
194 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
195
196 /* update buffer with status value */
197 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
198
199 #if DEBUG_DENALI
200 printk(KERN_INFO "device reporting status value of 0x%2x\n",
201 denali->buf.buf[0]);
202 #endif
203 }
204
205 /* resets a specific device connected to the core */
206 static void reset_bank(struct denali_nand_info *denali)
207 {
208 uint32_t irq_status = 0;
209 uint32_t irq_mask = reset_complete[denali->flash_bank] |
210 operation_timeout[denali->flash_bank];
211 int bank = 0;
212
213 clear_interrupts(denali);
214
215 bank = device_reset_banks[denali->flash_bank];
216 denali_write32(bank, denali->flash_reg + DEVICE_RESET);
217
218 irq_status = wait_for_irq(denali, irq_mask);
219
220 if (irq_status & operation_timeout[denali->flash_bank])
221 printk(KERN_ERR "reset bank failed.\n");
222 }
223
224 /* Reset the flash controller */
225 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
226 {
227 uint32_t i;
228
229 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
230 __FILE__, __LINE__, __func__);
231
232 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
233 denali_write32(reset_complete[i] | operation_timeout[i],
234 denali->flash_reg + intr_status_addresses[i]);
235
236 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
237 denali_write32(device_reset_banks[i],
238 denali->flash_reg + DEVICE_RESET);
239 while (!(ioread32(denali->flash_reg +
240 intr_status_addresses[i]) &
241 (reset_complete[i] | operation_timeout[i])))
242 ;
243 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
244 operation_timeout[i])
245 nand_dbg_print(NAND_DBG_WARN,
246 "NAND Reset operation timed out on bank %d\n", i);
247 }
248
249 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
250 denali_write32(reset_complete[i] | operation_timeout[i],
251 denali->flash_reg + intr_status_addresses[i]);
252
253 return PASS;
254 }
255
256 /* this routine calculates the ONFI timing values for a given mode and
257 * programs the clocking register accordingly. The mode is determined by
258 * the get_onfi_nand_para routine.
259 */
260 static void nand_onfi_timing_set(struct denali_nand_info *denali,
261 uint16_t mode)
262 {
263 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
264 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
265 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
266 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
267 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
268 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
269 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
270 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
271 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
272 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
273 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
274 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
275
276 uint16_t TclsRising = 1;
277 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
278 uint16_t dv_window = 0;
279 uint16_t en_lo, en_hi;
280 uint16_t acc_clks;
281 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
282
283 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
284 __FILE__, __LINE__, __func__);
285
286 en_lo = CEIL_DIV(Trp[mode], CLK_X);
287 en_hi = CEIL_DIV(Treh[mode], CLK_X);
288 #if ONFI_BLOOM_TIME
289 if ((en_hi * CLK_X) < (Treh[mode] + 2))
290 en_hi++;
291 #endif
292
293 if ((en_lo + en_hi) * CLK_X < Trc[mode])
294 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
295
296 if ((en_lo + en_hi) < CLK_MULTI)
297 en_lo += CLK_MULTI - en_lo - en_hi;
298
299 while (dv_window < 8) {
300 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
301
302 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
303
304 data_invalid =
305 data_invalid_rhoh <
306 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
307
308 dv_window = data_invalid - Trea[mode];
309
310 if (dv_window < 8)
311 en_lo++;
312 }
313
314 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
315
316 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
317 acc_clks++;
318
319 if ((data_invalid - acc_clks * CLK_X) < 2)
320 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n",
321 __FILE__, __LINE__);
322
323 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
324 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
325 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
326 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
327 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
328 if (!TclsRising)
329 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
330 if (cs_cnt == 0)
331 cs_cnt = 1;
332
333 if (Tcea[mode]) {
334 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
335 cs_cnt++;
336 }
337
338 #if MODE5_WORKAROUND
339 if (mode == 5)
340 acc_clks = 5;
341 #endif
342
343 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
344 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
345 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
346 acc_clks = 6;
347
348 denali_write32(acc_clks, denali->flash_reg + ACC_CLKS);
349 denali_write32(re_2_we, denali->flash_reg + RE_2_WE);
350 denali_write32(re_2_re, denali->flash_reg + RE_2_RE);
351 denali_write32(we_2_re, denali->flash_reg + WE_2_RE);
352 denali_write32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
353 denali_write32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
354 denali_write32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
355 denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
356 }
357
358 /* configures the initial ECC settings for the controller */
359 static void set_ecc_config(struct denali_nand_info *denali)
360 {
361 #if SUPPORT_8BITECC
362 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
363 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) <= 128))
364 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
365 #endif
366
367 }
368
369 /* queries the NAND device to see what ONFI modes it supports. */
370 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
371 {
372 int i;
373
374 denali_write32(DEVICE_RESET__BANK0, denali->flash_reg + DEVICE_RESET);
375
376 while (!((ioread32(denali->flash_reg + INTR_STATUS0) &
377 INTR_STATUS0__RST_COMP) |
378 (ioread32(denali->flash_reg + INTR_STATUS0) &
379 INTR_STATUS0__TIME_OUT)))
380 ;
381
382 if (ioread32(denali->flash_reg + INTR_STATUS0) &
383 INTR_STATUS0__RST_COMP) {
384 denali_write32(DEVICE_RESET__BANK1,
385 denali->flash_reg + DEVICE_RESET);
386 while (!((ioread32(denali->flash_reg + INTR_STATUS1) &
387 INTR_STATUS1__RST_COMP) |
388 (ioread32(denali->flash_reg + INTR_STATUS1) &
389 INTR_STATUS1__TIME_OUT)))
390 ;
391
392 if (ioread32(denali->flash_reg + INTR_STATUS1) &
393 INTR_STATUS1__RST_COMP) {
394 denali_write32(DEVICE_RESET__BANK2,
395 denali->flash_reg + DEVICE_RESET);
396 while (!((ioread32(denali->flash_reg + INTR_STATUS2) &
397 INTR_STATUS2__RST_COMP) |
398 (ioread32(denali->flash_reg + INTR_STATUS2) &
399 INTR_STATUS2__TIME_OUT)))
400 ;
401
402 if (ioread32(denali->flash_reg + INTR_STATUS2) &
403 INTR_STATUS2__RST_COMP) {
404 denali_write32(DEVICE_RESET__BANK3,
405 denali->flash_reg + DEVICE_RESET);
406 while (!((ioread32(denali->flash_reg +
407 INTR_STATUS3) &
408 INTR_STATUS3__RST_COMP) |
409 (ioread32(denali->flash_reg +
410 INTR_STATUS3) &
411 INTR_STATUS3__TIME_OUT)))
412 ;
413 } else {
414 printk(KERN_ERR "Getting a time out for bank 2!\n");
415 }
416 } else {
417 printk(KERN_ERR "Getting a time out for bank 1!\n");
418 }
419 }
420
421 denali_write32(INTR_STATUS0__TIME_OUT,
422 denali->flash_reg + INTR_STATUS0);
423 denali_write32(INTR_STATUS1__TIME_OUT,
424 denali->flash_reg + INTR_STATUS1);
425 denali_write32(INTR_STATUS2__TIME_OUT,
426 denali->flash_reg + INTR_STATUS2);
427 denali_write32(INTR_STATUS3__TIME_OUT,
428 denali->flash_reg + INTR_STATUS3);
429
430 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
431 ONFI_TIMING_MODE__VALUE))
432 return FAIL;
433
434 for (i = 5; i > 0; i--) {
435 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
436 (0x01 << i))
437 break;
438 }
439
440 nand_onfi_timing_set(denali, i);
441
442 /* By now, all the ONFI devices we know support the page cache */
443 /* rw feature. So here we enable the pipeline_rw_ahead feature */
444 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
445 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
446
447 return PASS;
448 }
449
450 static void get_samsung_nand_para(struct denali_nand_info *denali)
451 {
452 uint32_t id_bytes[5];
453 int i;
454
455 index_addr(denali, (uint32_t)(MODE_11 | 0), 0x90);
456 index_addr(denali, (uint32_t)(MODE_11 | 1), 0);
457 for (i = 0; i < 5; i++)
458 index_addr_read_data(denali, (uint32_t)(MODE_11 | 2),
459 &id_bytes[i]);
460
461 nand_dbg_print(NAND_DBG_DEBUG,
462 "ID bytes: 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
463 id_bytes[0], id_bytes[1], id_bytes[2],
464 id_bytes[3], id_bytes[4]);
465
466 if ((id_bytes[1] & 0xff) == 0xd3) { /* Samsung K9WAG08U1A */
467 /* Set timing register values according to datasheet */
468 denali_write32(5, denali->flash_reg + ACC_CLKS);
469 denali_write32(20, denali->flash_reg + RE_2_WE);
470 denali_write32(12, denali->flash_reg + WE_2_RE);
471 denali_write32(14, denali->flash_reg + ADDR_2_DATA);
472 denali_write32(3, denali->flash_reg + RDWR_EN_LO_CNT);
473 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
474 denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
475 }
476 }
477
478 static void get_toshiba_nand_para(struct denali_nand_info *denali)
479 {
480 uint32_t tmp;
481
482 /* Workaround to fix a controller bug which reports a wrong */
483 /* spare area size for some kind of Toshiba NAND device */
484 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
485 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
486 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
487 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
488 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
489 denali_write32(tmp,
490 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
491 #if SUPPORT_15BITECC
492 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
493 #elif SUPPORT_8BITECC
494 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
495 #endif
496 }
497 }
498
499 static void get_hynix_nand_para(struct denali_nand_info *denali,
500 uint8_t device_id)
501 {
502 uint32_t main_size, spare_size;
503
504 switch (device_id) {
505 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
506 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
507 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
508 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
509 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
510 main_size = 4096 *
511 ioread32(denali->flash_reg + DEVICES_CONNECTED);
512 spare_size = 224 *
513 ioread32(denali->flash_reg + DEVICES_CONNECTED);
514 denali_write32(main_size,
515 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
516 denali_write32(spare_size,
517 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
518 denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
519 #if SUPPORT_15BITECC
520 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
521 #elif SUPPORT_8BITECC
522 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
523 #endif
524 break;
525 default:
526 nand_dbg_print(NAND_DBG_WARN,
527 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
528 "Will use default parameter values instead.\n",
529 device_id);
530 }
531 }
532
533 /* determines how many NAND chips are connected to the controller. Note for
534 Intel CE4100 devices we don't support more than one device.
535 */
536 static void find_valid_banks(struct denali_nand_info *denali)
537 {
538 uint32_t id[LLD_MAX_FLASH_BANKS];
539 int i;
540
541 denali->total_used_banks = 1;
542 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
543 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
544 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
545 index_addr_read_data(denali,
546 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
547
548 nand_dbg_print(NAND_DBG_DEBUG,
549 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
550
551 if (i == 0) {
552 if (!(id[i] & 0x0ff))
553 break; /* WTF? */
554 } else {
555 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
556 denali->total_used_banks++;
557 else
558 break;
559 }
560 }
561
562 if (denali->platform == INTEL_CE4100) {
563 /* Platform limitations of the CE4100 device limit
564 * users to a single chip solution for NAND.
565 * Multichip support is not enabled.
566 */
567 if (denali->total_used_banks != 1) {
568 printk(KERN_ERR "Sorry, Intel CE4100 only supports "
569 "a single NAND device.\n");
570 BUG();
571 }
572 }
573 nand_dbg_print(NAND_DBG_DEBUG,
574 "denali->total_used_banks: %d\n", denali->total_used_banks);
575 }
576
577 static void detect_partition_feature(struct denali_nand_info *denali)
578 {
579 /* For MRST platform, denali->fwblks represent the
580 * number of blocks firmware is taken,
581 * FW is in protect partition and MTD driver has no
582 * permission to access it. So let driver know how many
583 * blocks it can't touch.
584 * */
585 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
586 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
587 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
588 denali->fwblks =
589 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
590 MIN_MAX_BANK_1__MIN_VALUE) *
591 denali->blksperchip)
592 +
593 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
594 MIN_BLK_ADDR_1__VALUE);
595 } else
596 denali->fwblks = SPECTRA_START_BLOCK;
597 } else
598 denali->fwblks = SPECTRA_START_BLOCK;
599 }
600
601 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
602 {
603 uint16_t status = PASS;
604 uint32_t id_bytes[5], addr;
605 uint8_t i, maf_id, device_id;
606
607 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
608 __FILE__, __LINE__, __func__);
609
610 /* Use read id method to get device ID and other
611 * params. For some NAND chips, controller can't
612 * report the correct device ID by reading from
613 * DEVICE_ID register
614 * */
615 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
616 index_addr(denali, (uint32_t)addr | 0, 0x90);
617 index_addr(denali, (uint32_t)addr | 1, 0);
618 for (i = 0; i < 5; i++)
619 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
620 maf_id = id_bytes[0];
621 device_id = id_bytes[1];
622
623 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
624 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
625 if (FAIL == get_onfi_nand_para(denali))
626 return FAIL;
627 } else if (maf_id == 0xEC) { /* Samsung NAND */
628 get_samsung_nand_para(denali);
629 } else if (maf_id == 0x98) { /* Toshiba NAND */
630 get_toshiba_nand_para(denali);
631 } else if (maf_id == 0xAD) { /* Hynix NAND */
632 get_hynix_nand_para(denali, device_id);
633 }
634
635 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
636 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
637 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
638 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
639 ioread32(denali->flash_reg + ACC_CLKS),
640 ioread32(denali->flash_reg + RE_2_WE),
641 ioread32(denali->flash_reg + WE_2_RE),
642 ioread32(denali->flash_reg + ADDR_2_DATA),
643 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
644 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
645 ioread32(denali->flash_reg + CS_SETUP_CNT));
646
647 set_ecc_config(denali);
648
649 find_valid_banks(denali);
650
651 detect_partition_feature(denali);
652
653 /* If the user specified to override the default timings
654 * with a specific ONFI mode, we apply those changes here.
655 */
656 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
657 nand_onfi_timing_set(denali, onfi_timing_mode);
658
659 return status;
660 }
661
662 static void denali_set_intr_modes(struct denali_nand_info *denali,
663 uint16_t INT_ENABLE)
664 {
665 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
666 __FILE__, __LINE__, __func__);
667
668 if (INT_ENABLE)
669 denali_write32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
670 else
671 denali_write32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
672 }
673
674 /* validation function to verify that the controlling software is making
675 a valid request
676 */
677 static inline bool is_flash_bank_valid(int flash_bank)
678 {
679 return (flash_bank >= 0 && flash_bank < 4);
680 }
681
682 static void denali_irq_init(struct denali_nand_info *denali)
683 {
684 uint32_t int_mask = 0;
685
686 /* Disable global interrupts */
687 denali_set_intr_modes(denali, false);
688
689 int_mask = DENALI_IRQ_ALL;
690
691 /* Clear all status bits */
692 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS0);
693 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS1);
694 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS2);
695 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS3);
696
697 denali_irq_enable(denali, int_mask);
698 }
699
700 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
701 {
702 denali_set_intr_modes(denali, false);
703 free_irq(irqnum, denali);
704 }
705
706 static void denali_irq_enable(struct denali_nand_info *denali,
707 uint32_t int_mask)
708 {
709 denali_write32(int_mask, denali->flash_reg + INTR_EN0);
710 denali_write32(int_mask, denali->flash_reg + INTR_EN1);
711 denali_write32(int_mask, denali->flash_reg + INTR_EN2);
712 denali_write32(int_mask, denali->flash_reg + INTR_EN3);
713 }
714
715 /* This function only returns when an interrupt that this driver cares about
716 * occurs. This is to reduce the overhead of servicing interrupts
717 */
718 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
719 {
720 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
721 }
722
723 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
724 static inline void clear_interrupt(struct denali_nand_info *denali,
725 uint32_t irq_mask)
726 {
727 uint32_t intr_status_reg = 0;
728
729 intr_status_reg = intr_status_addresses[denali->flash_bank];
730
731 denali_write32(irq_mask, denali->flash_reg + intr_status_reg);
732 }
733
734 static void clear_interrupts(struct denali_nand_info *denali)
735 {
736 uint32_t status = 0x0;
737 spin_lock_irq(&denali->irq_lock);
738
739 status = read_interrupt_status(denali);
740
741 #if DEBUG_DENALI
742 denali->irq_debug_array[denali->idx++] = 0x30000000 | status;
743 denali->idx %= 32;
744 #endif
745
746 denali->irq_status = 0x0;
747 spin_unlock_irq(&denali->irq_lock);
748 }
749
750 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
751 {
752 uint32_t intr_status_reg = 0;
753
754 intr_status_reg = intr_status_addresses[denali->flash_bank];
755
756 return ioread32(denali->flash_reg + intr_status_reg);
757 }
758
759 #if DEBUG_DENALI
760 static void print_irq_log(struct denali_nand_info *denali)
761 {
762 int i = 0;
763
764 printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
765 for (i = 0; i < 32; i++)
766 printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
767 }
768 #endif
769
770 /* This is the interrupt service routine. It handles all interrupts
771 * sent to this device. Note that on CE4100, this is a shared
772 * interrupt.
773 */
774 static irqreturn_t denali_isr(int irq, void *dev_id)
775 {
776 struct denali_nand_info *denali = dev_id;
777 uint32_t irq_status = 0x0;
778 irqreturn_t result = IRQ_NONE;
779
780 spin_lock(&denali->irq_lock);
781
782 /* check to see if a valid NAND chip has
783 * been selected.
784 */
785 if (is_flash_bank_valid(denali->flash_bank)) {
786 /* check to see if controller generated
787 * the interrupt, since this is a shared interrupt */
788 irq_status = denali_irq_detected(denali);
789 if (irq_status != 0) {
790 #if DEBUG_DENALI
791 denali->irq_debug_array[denali->idx++] =
792 0x10000000 | irq_status;
793 denali->idx %= 32;
794
795 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
796 #endif
797 /* handle interrupt */
798 /* first acknowledge it */
799 clear_interrupt(denali, irq_status);
800 /* store the status in the device context for someone
801 to read */
802 denali->irq_status |= irq_status;
803 /* notify anyone who cares that it happened */
804 complete(&denali->complete);
805 /* tell the OS that we've handled this */
806 result = IRQ_HANDLED;
807 }
808 }
809 spin_unlock(&denali->irq_lock);
810 return result;
811 }
812 #define BANK(x) ((x) << 24)
813
814 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
815 {
816 unsigned long comp_res = 0;
817 uint32_t intr_status = 0;
818 bool retry = false;
819 unsigned long timeout = msecs_to_jiffies(1000);
820
821 do {
822 #if DEBUG_DENALI
823 printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
824 #endif
825 comp_res =
826 wait_for_completion_timeout(&denali->complete, timeout);
827 spin_lock_irq(&denali->irq_lock);
828 intr_status = denali->irq_status;
829
830 #if DEBUG_DENALI
831 denali->irq_debug_array[denali->idx++] =
832 0x20000000 | (irq_mask << 16) | intr_status;
833 denali->idx %= 32;
834 #endif
835
836 if (intr_status & irq_mask) {
837 denali->irq_status &= ~irq_mask;
838 spin_unlock_irq(&denali->irq_lock);
839 #if DEBUG_DENALI
840 if (retry)
841 printk(KERN_INFO "status on retry = 0x%x\n",
842 intr_status);
843 #endif
844 /* our interrupt was detected */
845 break;
846 } else {
847 /* these are not the interrupts you are looking for -
848 * need to wait again */
849 spin_unlock_irq(&denali->irq_lock);
850 #if DEBUG_DENALI
851 print_irq_log(denali);
852 printk(KERN_INFO "received irq nobody cared:"
853 " irq_status = 0x%x, irq_mask = 0x%x,"
854 " timeout = %ld\n", intr_status,
855 irq_mask, comp_res);
856 #endif
857 retry = true;
858 }
859 } while (comp_res != 0);
860
861 if (comp_res == 0) {
862 /* timeout */
863 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
864 intr_status, irq_mask);
865
866 intr_status = 0;
867 }
868 return intr_status;
869 }
870
871 /* This helper function setups the registers for ECC and whether or not
872 the spare area will be transfered. */
873 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
874 bool transfer_spare)
875 {
876 int ecc_en_flag = 0, transfer_spare_flag = 0;
877
878 /* set ECC, transfer spare bits if needed */
879 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
880 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
881
882 /* Enable spare area/ECC per user's request. */
883 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
884 denali_write32(transfer_spare_flag,
885 denali->flash_reg + TRANSFER_SPARE_REG);
886 }
887
888 /* sends a pipeline command operation to the controller. See the Denali NAND
889 controller's user guide for more information (section 4.2.3.6).
890 */
891 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
892 bool ecc_en,
893 bool transfer_spare,
894 int access_type,
895 int op)
896 {
897 int status = PASS;
898 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
899 irq_mask = 0;
900
901 if (op == DENALI_READ)
902 irq_mask = INTR_STATUS0__LOAD_COMP;
903 else if (op == DENALI_WRITE)
904 irq_mask = 0;
905 else
906 BUG();
907
908 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
909
910 #if DEBUG_DENALI
911 spin_lock_irq(&denali->irq_lock);
912 denali->irq_debug_array[denali->idx++] =
913 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
914 (access_type << 4);
915 denali->idx %= 32;
916 spin_unlock_irq(&denali->irq_lock);
917 #endif
918
919
920 /* clear interrupts */
921 clear_interrupts(denali);
922
923 addr = BANK(denali->flash_bank) | denali->page;
924
925 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
926 cmd = MODE_01 | addr;
927 denali_write32(cmd, denali->flash_mem);
928 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
929 /* read spare area */
930 cmd = MODE_10 | addr;
931 index_addr(denali, (uint32_t)cmd, access_type);
932
933 cmd = MODE_01 | addr;
934 denali_write32(cmd, denali->flash_mem);
935 } else if (op == DENALI_READ) {
936 /* setup page read request for access type */
937 cmd = MODE_10 | addr;
938 index_addr(denali, (uint32_t)cmd, access_type);
939
940 /* page 33 of the NAND controller spec indicates we should not
941 use the pipeline commands in Spare area only mode. So we
942 don't.
943 */
944 if (access_type == SPARE_ACCESS) {
945 cmd = MODE_01 | addr;
946 denali_write32(cmd, denali->flash_mem);
947 } else {
948 index_addr(denali, (uint32_t)cmd,
949 0x2000 | op | page_count);
950
951 /* wait for command to be accepted
952 * can always use status0 bit as the
953 * mask is identical for each
954 * bank. */
955 irq_status = wait_for_irq(denali, irq_mask);
956
957 if (irq_status == 0) {
958 printk(KERN_ERR "cmd, page, addr on timeout "
959 "(0x%x, 0x%x, 0x%x)\n", cmd,
960 denali->page, addr);
961 status = FAIL;
962 } else {
963 cmd = MODE_01 | addr;
964 denali_write32(cmd, denali->flash_mem);
965 }
966 }
967 }
968 return status;
969 }
970
971 /* helper function that simply writes a buffer to the flash */
972 static int write_data_to_flash_mem(struct denali_nand_info *denali,
973 const uint8_t *buf,
974 int len)
975 {
976 uint32_t i = 0, *buf32;
977
978 /* verify that the len is a multiple of 4. see comment in
979 * read_data_from_flash_mem() */
980 BUG_ON((len % 4) != 0);
981
982 /* write the data to the flash memory */
983 buf32 = (uint32_t *)buf;
984 for (i = 0; i < len / 4; i++)
985 denali_write32(*buf32++, denali->flash_mem + 0x10);
986 return i*4; /* intent is to return the number of bytes read */
987 }
988
989 /* helper function that simply reads a buffer from the flash */
990 static int read_data_from_flash_mem(struct denali_nand_info *denali,
991 uint8_t *buf,
992 int len)
993 {
994 uint32_t i = 0, *buf32;
995
996 /* we assume that len will be a multiple of 4, if not
997 * it would be nice to know about it ASAP rather than
998 * have random failures...
999 * This assumption is based on the fact that this
1000 * function is designed to be used to read flash pages,
1001 * which are typically multiples of 4...
1002 */
1003
1004 BUG_ON((len % 4) != 0);
1005
1006 /* transfer the data from the flash */
1007 buf32 = (uint32_t *)buf;
1008 for (i = 0; i < len / 4; i++)
1009 *buf32++ = ioread32(denali->flash_mem + 0x10);
1010 return i*4; /* intent is to return the number of bytes read */
1011 }
1012
1013 /* writes OOB data to the device */
1014 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1015 {
1016 struct denali_nand_info *denali = mtd_to_denali(mtd);
1017 uint32_t irq_status = 0;
1018 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
1019 INTR_STATUS0__PROGRAM_FAIL;
1020 int status = 0;
1021
1022 denali->page = page;
1023
1024 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
1025 DENALI_WRITE) == PASS) {
1026 write_data_to_flash_mem(denali, buf, mtd->oobsize);
1027
1028 #if DEBUG_DENALI
1029 spin_lock_irq(&denali->irq_lock);
1030 denali->irq_debug_array[denali->idx++] =
1031 0x80000000 | mtd->oobsize;
1032 denali->idx %= 32;
1033 spin_unlock_irq(&denali->irq_lock);
1034 #endif
1035
1036
1037 /* wait for operation to complete */
1038 irq_status = wait_for_irq(denali, irq_mask);
1039
1040 if (irq_status == 0) {
1041 printk(KERN_ERR "OOB write failed\n");
1042 status = -EIO;
1043 }
1044 } else {
1045 printk(KERN_ERR "unable to send pipeline command\n");
1046 status = -EIO;
1047 }
1048 return status;
1049 }
1050
1051 /* reads OOB data from the device */
1052 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
1053 {
1054 struct denali_nand_info *denali = mtd_to_denali(mtd);
1055 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
1056 irq_status = 0, addr = 0x0, cmd = 0x0;
1057
1058 denali->page = page;
1059
1060 #if DEBUG_DENALI
1061 printk(KERN_INFO "read_oob %d\n", page);
1062 #endif
1063 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
1064 DENALI_READ) == PASS) {
1065 read_data_from_flash_mem(denali, buf, mtd->oobsize);
1066
1067 /* wait for command to be accepted
1068 * can always use status0 bit as the mask is identical for each
1069 * bank. */
1070 irq_status = wait_for_irq(denali, irq_mask);
1071
1072 if (irq_status == 0)
1073 printk(KERN_ERR "page on OOB timeout %d\n",
1074 denali->page);
1075
1076 /* We set the device back to MAIN_ACCESS here as I observed
1077 * instability with the controller if you do a block erase
1078 * and the last transaction was a SPARE_ACCESS. Block erase
1079 * is reliable (according to the MTD test infrastructure)
1080 * if you are in MAIN_ACCESS.
1081 */
1082 addr = BANK(denali->flash_bank) | denali->page;
1083 cmd = MODE_10 | addr;
1084 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
1085
1086 #if DEBUG_DENALI
1087 spin_lock_irq(&denali->irq_lock);
1088 denali->irq_debug_array[denali->idx++] =
1089 0x60000000 | mtd->oobsize;
1090 denali->idx %= 32;
1091 spin_unlock_irq(&denali->irq_lock);
1092 #endif
1093 }
1094 }
1095
1096 /* this function examines buffers to see if they contain data that
1097 * indicate that the buffer is part of an erased region of flash.
1098 */
1099 bool is_erased(uint8_t *buf, int len)
1100 {
1101 int i = 0;
1102 for (i = 0; i < len; i++)
1103 if (buf[i] != 0xFF)
1104 return false;
1105 return true;
1106 }
1107 #define ECC_SECTOR_SIZE 512
1108
1109 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
1110 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
1111 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
1112 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO))
1113 #define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8)
1114 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
1115
1116 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1117 uint8_t *oobbuf, uint32_t irq_status)
1118 {
1119 bool check_erased_page = false;
1120
1121 if (irq_status & INTR_STATUS0__ECC_ERR) {
1122 /* read the ECC errors. we'll ignore them for now */
1123 uint32_t err_address = 0, err_correction_info = 0;
1124 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
1125 uint32_t err_correction_value = 0;
1126
1127 do {
1128 err_address = ioread32(denali->flash_reg +
1129 ECC_ERROR_ADDRESS);
1130 err_sector = ECC_SECTOR(err_address);
1131 err_byte = ECC_BYTE(err_address);
1132
1133
1134 err_correction_info = ioread32(denali->flash_reg +
1135 ERR_CORRECTION_INFO);
1136 err_correction_value =
1137 ECC_CORRECTION_VALUE(err_correction_info);
1138 err_device = ECC_ERR_DEVICE(err_correction_info);
1139
1140 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
1141 /* offset in our buffer is computed as:
1142 sector number * sector size + offset in
1143 sector
1144 */
1145 int offset = err_sector * ECC_SECTOR_SIZE +
1146 err_byte;
1147 if (offset < denali->mtd.writesize) {
1148 /* correct the ECC error */
1149 buf[offset] ^= err_correction_value;
1150 denali->mtd.ecc_stats.corrected++;
1151 } else {
1152 /* bummer, couldn't correct the error */
1153 printk(KERN_ERR "ECC offset invalid\n");
1154 denali->mtd.ecc_stats.failed++;
1155 }
1156 } else {
1157 /* if the error is not correctable, need to
1158 * look at the page to see if it is an erased
1159 * page. if so, then it's not a real ECC error
1160 * */
1161 check_erased_page = true;
1162 }
1163
1164 #if DEBUG_DENALI
1165 printk(KERN_INFO "Detected ECC error in page %d:"
1166 " err_addr = 0x%08x, info to fix is"
1167 " 0x%08x\n", denali->page, err_address,
1168 err_correction_info);
1169 #endif
1170 } while (!ECC_LAST_ERR(err_correction_info));
1171 }
1172 return check_erased_page;
1173 }
1174
1175 /* programs the controller to either enable/disable DMA transfers */
1176 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1177 {
1178 uint32_t reg_val = 0x0;
1179
1180 if (en)
1181 reg_val = DMA_ENABLE__FLAG;
1182
1183 denali_write32(reg_val, denali->flash_reg + DMA_ENABLE);
1184 ioread32(denali->flash_reg + DMA_ENABLE);
1185 }
1186
1187 /* setups the HW to perform the data DMA */
1188 static void denali_setup_dma(struct denali_nand_info *denali, int op)
1189 {
1190 uint32_t mode = 0x0;
1191 const int page_count = 1;
1192 dma_addr_t addr = denali->buf.dma_buf;
1193
1194 mode = MODE_10 | BANK(denali->flash_bank);
1195
1196 /* DMA is a four step process */
1197
1198 /* 1. setup transfer type and # of pages */
1199 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1200
1201 /* 2. set memory high address bits 23:8 */
1202 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1203
1204 /* 3. set memory low address bits 23:8 */
1205 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1206
1207 /* 4. interrupt when complete, burst len = 64 bytes*/
1208 index_addr(denali, mode | 0x14000, 0x2400);
1209 }
1210
1211 /* writes a page. user specifies type, and this function handles the
1212 configuration details. */
1213 static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1214 const uint8_t *buf, bool raw_xfer)
1215 {
1216 struct denali_nand_info *denali = mtd_to_denali(mtd);
1217 struct pci_dev *pci_dev = denali->dev;
1218
1219 dma_addr_t addr = denali->buf.dma_buf;
1220 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1221
1222 uint32_t irq_status = 0;
1223 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
1224 INTR_STATUS0__PROGRAM_FAIL;
1225
1226 /* if it is a raw xfer, we want to disable ecc, and send
1227 * the spare area.
1228 * !raw_xfer - enable ecc
1229 * raw_xfer - transfer spare
1230 */
1231 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1232
1233 /* copy buffer into DMA buffer */
1234 memcpy(denali->buf.buf, buf, mtd->writesize);
1235
1236 if (raw_xfer) {
1237 /* transfer the data to the spare area */
1238 memcpy(denali->buf.buf + mtd->writesize,
1239 chip->oob_poi,
1240 mtd->oobsize);
1241 }
1242
1243 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1244
1245 clear_interrupts(denali);
1246 denali_enable_dma(denali, true);
1247
1248 denali_setup_dma(denali, DENALI_WRITE);
1249
1250 /* wait for operation to complete */
1251 irq_status = wait_for_irq(denali, irq_mask);
1252
1253 if (irq_status == 0) {
1254 printk(KERN_ERR "timeout on write_page"
1255 " (type = %d)\n", raw_xfer);
1256 denali->status =
1257 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1258 NAND_STATUS_FAIL : PASS;
1259 }
1260
1261 denali_enable_dma(denali, false);
1262 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1263 }
1264
1265 /* NAND core entry points */
1266
1267 /* this is the callback that the NAND core calls to write a page. Since
1268 writing a page with ECC or without is similar, all the work is done
1269 by write_page above. */
1270 static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1271 const uint8_t *buf)
1272 {
1273 /* for regular page writes, we let HW handle all the ECC
1274 * data written to the device. */
1275 write_page(mtd, chip, buf, false);
1276 }
1277
1278 /* This is the callback that the NAND core calls to write a page without ECC.
1279 raw access is similiar to ECC page writes, so all the work is done in the
1280 write_page() function above.
1281 */
1282 static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1283 const uint8_t *buf)
1284 {
1285 /* for raw page writes, we want to disable ECC and simply write
1286 whatever data is in the buffer. */
1287 write_page(mtd, chip, buf, true);
1288 }
1289
1290 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1291 int page)
1292 {
1293 return write_oob_data(mtd, chip->oob_poi, page);
1294 }
1295
1296 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1297 int page, int sndcmd)
1298 {
1299 read_oob_data(mtd, chip->oob_poi, page);
1300
1301 return 0; /* notify NAND core to send command to
1302 NAND device. */
1303 }
1304
1305 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1306 uint8_t *buf, int page)
1307 {
1308 struct denali_nand_info *denali = mtd_to_denali(mtd);
1309 struct pci_dev *pci_dev = denali->dev;
1310
1311 dma_addr_t addr = denali->buf.dma_buf;
1312 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1313
1314 uint32_t irq_status = 0;
1315 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
1316 INTR_STATUS0__ECC_ERR;
1317 bool check_erased_page = false;
1318
1319 setup_ecc_for_xfer(denali, true, false);
1320
1321 denali_enable_dma(denali, true);
1322 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1323
1324 clear_interrupts(denali);
1325 denali_setup_dma(denali, DENALI_READ);
1326
1327 /* wait for operation to complete */
1328 irq_status = wait_for_irq(denali, irq_mask);
1329
1330 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1331
1332 memcpy(buf, denali->buf.buf, mtd->writesize);
1333
1334 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
1335 denali_enable_dma(denali, false);
1336
1337 if (check_erased_page) {
1338 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1339
1340 /* check ECC failures that may have occurred on erased pages */
1341 if (check_erased_page) {
1342 if (!is_erased(buf, denali->mtd.writesize))
1343 denali->mtd.ecc_stats.failed++;
1344 if (!is_erased(buf, denali->mtd.oobsize))
1345 denali->mtd.ecc_stats.failed++;
1346 }
1347 }
1348 return 0;
1349 }
1350
1351 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1352 uint8_t *buf, int page)
1353 {
1354 struct denali_nand_info *denali = mtd_to_denali(mtd);
1355 struct pci_dev *pci_dev = denali->dev;
1356
1357 dma_addr_t addr = denali->buf.dma_buf;
1358 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1359
1360 uint32_t irq_status = 0;
1361 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
1362
1363 setup_ecc_for_xfer(denali, false, true);
1364 denali_enable_dma(denali, true);
1365
1366 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1367
1368 clear_interrupts(denali);
1369 denali_setup_dma(denali, DENALI_READ);
1370
1371 /* wait for operation to complete */
1372 irq_status = wait_for_irq(denali, irq_mask);
1373
1374 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1375
1376 denali_enable_dma(denali, false);
1377
1378 memcpy(buf, denali->buf.buf, mtd->writesize);
1379 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1380
1381 return 0;
1382 }
1383
1384 static uint8_t denali_read_byte(struct mtd_info *mtd)
1385 {
1386 struct denali_nand_info *denali = mtd_to_denali(mtd);
1387 uint8_t result = 0xff;
1388
1389 if (denali->buf.head < denali->buf.tail)
1390 result = denali->buf.buf[denali->buf.head++];
1391
1392 #if DEBUG_DENALI
1393 printk(KERN_INFO "read byte -> 0x%02x\n", result);
1394 #endif
1395 return result;
1396 }
1397
1398 static void denali_select_chip(struct mtd_info *mtd, int chip)
1399 {
1400 struct denali_nand_info *denali = mtd_to_denali(mtd);
1401 #if DEBUG_DENALI
1402 printk(KERN_INFO "denali select chip %d\n", chip);
1403 #endif
1404 spin_lock_irq(&denali->irq_lock);
1405 denali->flash_bank = chip;
1406 spin_unlock_irq(&denali->irq_lock);
1407 }
1408
1409 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1410 {
1411 struct denali_nand_info *denali = mtd_to_denali(mtd);
1412 int status = denali->status;
1413 denali->status = 0;
1414
1415 #if DEBUG_DENALI
1416 printk(KERN_INFO "waitfunc %d\n", status);
1417 #endif
1418 return status;
1419 }
1420
1421 static void denali_erase(struct mtd_info *mtd, int page)
1422 {
1423 struct denali_nand_info *denali = mtd_to_denali(mtd);
1424
1425 uint32_t cmd = 0x0, irq_status = 0;
1426
1427 #if DEBUG_DENALI
1428 printk(KERN_INFO "erase page: %d\n", page);
1429 #endif
1430 /* clear interrupts */
1431 clear_interrupts(denali);
1432
1433 /* setup page read request for access type */
1434 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1435 index_addr(denali, (uint32_t)cmd, 0x1);
1436
1437 /* wait for erase to complete or failure to occur */
1438 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
1439 INTR_STATUS0__ERASE_FAIL);
1440
1441 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1442 NAND_STATUS_FAIL : PASS;
1443 }
1444
1445 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1446 int page)
1447 {
1448 struct denali_nand_info *denali = mtd_to_denali(mtd);
1449 uint32_t addr, id;
1450 int i;
1451
1452 #if DEBUG_DENALI
1453 printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
1454 #endif
1455 switch (cmd) {
1456 case NAND_CMD_PAGEPROG:
1457 break;
1458 case NAND_CMD_STATUS:
1459 read_status(denali);
1460 break;
1461 case NAND_CMD_READID:
1462 reset_buf(denali);
1463 /*sometimes ManufactureId read from register is not right
1464 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1465 * So here we send READID cmd to NAND insteand
1466 * */
1467 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1468 index_addr(denali, (uint32_t)addr | 0, 0x90);
1469 index_addr(denali, (uint32_t)addr | 1, 0);
1470 for (i = 0; i < 5; i++) {
1471 index_addr_read_data(denali,
1472 (uint32_t)addr | 2,
1473 &id);
1474 write_byte_to_buf(denali, id);
1475 }
1476 break;
1477 case NAND_CMD_READ0:
1478 case NAND_CMD_SEQIN:
1479 denali->page = page;
1480 break;
1481 case NAND_CMD_RESET:
1482 reset_bank(denali);
1483 break;
1484 case NAND_CMD_READOOB:
1485 /* TODO: Read OOB data */
1486 break;
1487 default:
1488 printk(KERN_ERR ": unsupported command"
1489 " received 0x%x\n", cmd);
1490 break;
1491 }
1492 }
1493
1494 /* stubs for ECC functions not used by the NAND core */
1495 static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1496 uint8_t *ecc_code)
1497 {
1498 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
1499 BUG();
1500 return -EIO;
1501 }
1502
1503 static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1504 uint8_t *read_ecc, uint8_t *calc_ecc)
1505 {
1506 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
1507 BUG();
1508 return -EIO;
1509 }
1510
1511 static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1512 {
1513 printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n");
1514 BUG();
1515 }
1516 /* end NAND core entry points */
1517
1518 /* Initialization code to bring the device up to a known good state */
1519 static void denali_hw_init(struct denali_nand_info *denali)
1520 {
1521 denali_irq_init(denali);
1522 denali_nand_reset(denali);
1523 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1524 denali_write32(CHIP_EN_DONT_CARE__FLAG,
1525 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1526
1527 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1528 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1529
1530 /* Should set value for these registers when init */
1531 denali_write32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1532 denali_write32(1, denali->flash_reg + ECC_ENABLE);
1533 }
1534
1535 /* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */
1536 #define ECC_BYTES_SLC (4 * (2048 / ECC_SECTOR_SIZE))
1537 static struct nand_ecclayout nand_oob_slc = {
1538 .eccbytes = 4,
1539 .eccpos = { 0, 1, 2, 3 }, /* not used */
1540 .oobfree = {
1541 {
1542 .offset = ECC_BYTES_SLC,
1543 .length = 64 - ECC_BYTES_SLC
1544 }
1545 }
1546 };
1547
1548 #define ECC_BYTES_MLC (14 * (2048 / ECC_SECTOR_SIZE))
1549 static struct nand_ecclayout nand_oob_mlc_14bit = {
1550 .eccbytes = 14,
1551 .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
1552 .oobfree = {
1553 {
1554 .offset = ECC_BYTES_MLC,
1555 .length = 64 - ECC_BYTES_MLC
1556 }
1557 }
1558 };
1559
1560 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1561 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1562
1563 static struct nand_bbt_descr bbt_main_descr = {
1564 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1565 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1566 .offs = 8,
1567 .len = 4,
1568 .veroffs = 12,
1569 .maxblocks = 4,
1570 .pattern = bbt_pattern,
1571 };
1572
1573 static struct nand_bbt_descr bbt_mirror_descr = {
1574 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1575 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1576 .offs = 8,
1577 .len = 4,
1578 .veroffs = 12,
1579 .maxblocks = 4,
1580 .pattern = mirror_pattern,
1581 };
1582
1583 /* initalize driver data structures */
1584 void denali_drv_init(struct denali_nand_info *denali)
1585 {
1586 denali->idx = 0;
1587
1588 /* setup interrupt handler */
1589 /* the completion object will be used to notify
1590 * the callee that the interrupt is done */
1591 init_completion(&denali->complete);
1592
1593 /* the spinlock will be used to synchronize the ISR
1594 * with any element that might be access shared
1595 * data (interrupt status) */
1596 spin_lock_init(&denali->irq_lock);
1597
1598 /* indicate that MTD has not selected a valid bank yet */
1599 denali->flash_bank = CHIP_SELECT_INVALID;
1600
1601 /* initialize our irq_status variable to indicate no interrupts */
1602 denali->irq_status = 0;
1603 }
1604
1605 /* driver entry point */
1606 static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1607 {
1608 int ret = -ENODEV;
1609 resource_size_t csr_base, mem_base;
1610 unsigned long csr_len, mem_len;
1611 struct denali_nand_info *denali;
1612
1613 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
1614 __FILE__, __LINE__, __func__);
1615
1616 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1617 if (!denali)
1618 return -ENOMEM;
1619
1620 ret = pci_enable_device(dev);
1621 if (ret) {
1622 printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
1623 goto failed_enable;
1624 }
1625
1626 if (id->driver_data == INTEL_CE4100) {
1627 /* Due to a silicon limitation, we can only support
1628 * ONFI timing mode 1 and below.
1629 */
1630 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1631 printk(KERN_ERR "Intel CE4100 only supports"
1632 " ONFI timing mode 1 or below\n");
1633 ret = -EINVAL;
1634 goto failed_enable;
1635 }
1636 denali->platform = INTEL_CE4100;
1637 mem_base = pci_resource_start(dev, 0);
1638 mem_len = pci_resource_len(dev, 1);
1639 csr_base = pci_resource_start(dev, 1);
1640 csr_len = pci_resource_len(dev, 1);
1641 } else {
1642 denali->platform = INTEL_MRST;
1643 csr_base = pci_resource_start(dev, 0);
1644 csr_len = pci_resource_start(dev, 0);
1645 mem_base = pci_resource_start(dev, 1);
1646 mem_len = pci_resource_len(dev, 1);
1647 if (!mem_len) {
1648 mem_base = csr_base + csr_len;
1649 mem_len = csr_len;
1650 nand_dbg_print(NAND_DBG_WARN,
1651 "Spectra: No second"
1652 " BAR for PCI device;"
1653 " assuming %08Lx\n",
1654 (uint64_t)csr_base);
1655 }
1656 }
1657
1658 /* Is 32-bit DMA supported? */
1659 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
1660
1661 if (ret) {
1662 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1663 goto failed_enable;
1664 }
1665 denali->buf.dma_buf =
1666 pci_map_single(dev, denali->buf.buf,
1667 DENALI_BUF_SIZE,
1668 PCI_DMA_BIDIRECTIONAL);
1669
1670 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
1671 printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
1672 goto failed_enable;
1673 }
1674
1675 pci_set_master(dev);
1676 denali->dev = dev;
1677
1678 ret = pci_request_regions(dev, DENALI_NAND_NAME);
1679 if (ret) {
1680 printk(KERN_ERR "Spectra: Unable to request memory regions\n");
1681 goto failed_req_csr;
1682 }
1683
1684 denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1685 if (!denali->flash_reg) {
1686 printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1687 ret = -ENOMEM;
1688 goto failed_remap_csr;
1689 }
1690 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
1691 (uint64_t)csr_base, denali->flash_reg, csr_len);
1692
1693 denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1694 if (!denali->flash_mem) {
1695 printk(KERN_ERR "Spectra: ioremap_nocache failed!");
1696 iounmap(denali->flash_reg);
1697 ret = -ENOMEM;
1698 goto failed_remap_csr;
1699 }
1700
1701 nand_dbg_print(NAND_DBG_WARN,
1702 "Spectra: Remapped flash base address: "
1703 "0x%p, len: %ld\n",
1704 denali->flash_mem, csr_len);
1705
1706 denali_hw_init(denali);
1707 denali_drv_init(denali);
1708
1709 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq);
1710 if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1711 DENALI_NAND_NAME, denali)) {
1712 printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1713 ret = -ENODEV;
1714 goto failed_request_irq;
1715 }
1716
1717 /* now that our ISR is registered, we can enable interrupts */
1718 denali_set_intr_modes(denali, true);
1719
1720 pci_set_drvdata(dev, denali);
1721
1722 denali_nand_timing_set(denali);
1723
1724 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
1725 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
1726 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
1727 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
1728 ioread32(denali->flash_reg + ACC_CLKS),
1729 ioread32(denali->flash_reg + RE_2_WE),
1730 ioread32(denali->flash_reg + WE_2_RE),
1731 ioread32(denali->flash_reg + ADDR_2_DATA),
1732 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
1733 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
1734 ioread32(denali->flash_reg + CS_SETUP_CNT));
1735
1736 denali->mtd.name = "Denali NAND";
1737 denali->mtd.owner = THIS_MODULE;
1738 denali->mtd.priv = &denali->nand;
1739
1740 /* register the driver with the NAND core subsystem */
1741 denali->nand.select_chip = denali_select_chip;
1742 denali->nand.cmdfunc = denali_cmdfunc;
1743 denali->nand.read_byte = denali_read_byte;
1744 denali->nand.waitfunc = denali_waitfunc;
1745
1746 /* scan for NAND devices attached to the controller
1747 * this is the first stage in a two step process to register
1748 * with the nand subsystem */
1749 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
1750 ret = -ENXIO;
1751 goto failed_nand;
1752 }
1753
1754 /* MTD supported page sizes vary by kernel. We validate our
1755 * kernel supports the device here.
1756 */
1757 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1758 ret = -ENODEV;
1759 printk(KERN_ERR "Spectra: device size not supported by this "
1760 "version of MTD.");
1761 goto failed_nand;
1762 }
1763
1764 /* second stage of the NAND scan
1765 * this stage requires information regarding ECC and
1766 * bad block management. */
1767
1768 /* Bad block management */
1769 denali->nand.bbt_td = &bbt_main_descr;
1770 denali->nand.bbt_md = &bbt_mirror_descr;
1771
1772 /* skip the scan for now until we have OOB read and write support */
1773 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
1774 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1775
1776 if (denali->nand.cellinfo & 0xc) {
1777 denali->nand.ecc.layout = &nand_oob_mlc_14bit;
1778 denali->nand.ecc.bytes = ECC_BYTES_MLC;
1779 } else {/* SLC */
1780 denali->nand.ecc.layout = &nand_oob_slc;
1781 denali->nand.ecc.bytes = ECC_BYTES_SLC;
1782 }
1783
1784 /* Let driver know the total blocks number and
1785 * how many blocks contained by each nand chip.
1786 * blksperchip will help driver to know how many
1787 * blocks is taken by FW.
1788 * */
1789 denali->totalblks = denali->mtd.size >>
1790 denali->nand.phys_erase_shift;
1791 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1792
1793 /* These functions are required by the NAND core framework, otherwise,
1794 * the NAND core will assert. However, we don't need them, so we'll stub
1795 * them out. */
1796 denali->nand.ecc.calculate = denali_ecc_calculate;
1797 denali->nand.ecc.correct = denali_ecc_correct;
1798 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1799
1800 /* override the default read operations */
1801 denali->nand.ecc.size = denali->mtd.writesize;
1802 denali->nand.ecc.read_page = denali_read_page;
1803 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1804 denali->nand.ecc.write_page = denali_write_page;
1805 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1806 denali->nand.ecc.read_oob = denali_read_oob;
1807 denali->nand.ecc.write_oob = denali_write_oob;
1808 denali->nand.erase_cmd = denali_erase;
1809
1810 if (nand_scan_tail(&denali->mtd)) {
1811 ret = -ENXIO;
1812 goto failed_nand;
1813 }
1814
1815 ret = add_mtd_device(&denali->mtd);
1816 if (ret) {
1817 printk(KERN_ERR "Spectra: Failed to register"
1818 " MTD device: %d\n", ret);
1819 goto failed_nand;
1820 }
1821 return 0;
1822
1823 failed_nand:
1824 denali_irq_cleanup(dev->irq, denali);
1825 failed_request_irq:
1826 iounmap(denali->flash_reg);
1827 iounmap(denali->flash_mem);
1828 failed_remap_csr:
1829 pci_release_regions(dev);
1830 failed_req_csr:
1831 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1832 PCI_DMA_BIDIRECTIONAL);
1833 failed_enable:
1834 kfree(denali);
1835 return ret;
1836 }
1837
1838 /* driver exit point */
1839 static void denali_pci_remove(struct pci_dev *dev)
1840 {
1841 struct denali_nand_info *denali = pci_get_drvdata(dev);
1842
1843 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
1844 __FILE__, __LINE__, __func__);
1845
1846 nand_release(&denali->mtd);
1847 del_mtd_device(&denali->mtd);
1848
1849 denali_irq_cleanup(dev->irq, denali);
1850
1851 iounmap(denali->flash_reg);
1852 iounmap(denali->flash_mem);
1853 pci_release_regions(dev);
1854 pci_disable_device(dev);
1855 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1856 PCI_DMA_BIDIRECTIONAL);
1857 pci_set_drvdata(dev, NULL);
1858 kfree(denali);
1859 }
1860
1861 MODULE_DEVICE_TABLE(pci, denali_pci_ids);
1862
1863 static struct pci_driver denali_pci_driver = {
1864 .name = DENALI_NAND_NAME,
1865 .id_table = denali_pci_ids,
1866 .probe = denali_pci_probe,
1867 .remove = denali_pci_remove,
1868 };
1869
1870 static int __devinit denali_init(void)
1871 {
1872 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n",
1873 __DATE__, __TIME__);
1874 return pci_register_driver(&denali_pci_driver);
1875 }
1876
1877 /* Free memory */
1878 static void __devexit denali_exit(void)
1879 {
1880 pci_unregister_driver(&denali_pci_driver);
1881 }
1882
1883 module_init(denali_init);
1884 module_exit(denali_exit);
Linux kernel - Deliverables
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