2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/slab.h>
25 #include <linux/pci.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/module.h>
31 MODULE_LICENSE("GPL");
33 /* We define a module parameter that allows the user to override
34 * the hardware and decide what timing mode should be used.
36 #define NAND_DEFAULT_TIMINGS -1
38 static int onfi_timing_mode
= NAND_DEFAULT_TIMINGS
;
39 module_param(onfi_timing_mode
, int, S_IRUGO
);
40 MODULE_PARM_DESC(onfi_timing_mode
, "Overrides default ONFI setting."
41 " -1 indicates use default timings");
43 #define DENALI_NAND_NAME "denali-nand"
45 /* We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience. */
47 #define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \
48 INTR_STATUS0__ECC_TRANSACTION_DONE | \
49 INTR_STATUS0__ECC_ERR | \
50 INTR_STATUS0__PROGRAM_FAIL | \
51 INTR_STATUS0__LOAD_COMP | \
52 INTR_STATUS0__PROGRAM_COMP | \
53 INTR_STATUS0__TIME_OUT | \
54 INTR_STATUS0__ERASE_FAIL | \
55 INTR_STATUS0__RST_COMP | \
56 INTR_STATUS0__ERASE_COMP)
58 /* indicates whether or not the internal value for the flash bank is
60 #define CHIP_SELECT_INVALID -1
62 #define SUPPORT_8BITECC 1
64 /* This macro divides two integers and rounds fractional values up
65 * to the nearest integer value. */
66 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
68 /* this macro allows us to convert from an MTD structure to our own
69 * device context (denali) structure.
71 #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
73 /* These constants are defined by the driver to enable common driver
74 * configuration options. */
75 #define SPARE_ACCESS 0x41
76 #define MAIN_ACCESS 0x42
77 #define MAIN_SPARE_ACCESS 0x43
80 #define DENALI_WRITE 0x100
82 /* types of device accesses. We can issue commands and get status */
83 #define COMMAND_CYCLE 0
85 #define STATUS_CYCLE 2
87 /* this is a helper macro that allows us to
88 * format the bank into the proper bits for the controller */
89 #define BANK(x) ((x) << 24)
91 /* List of platforms this NAND controller has be integrated into */
92 static const struct pci_device_id denali_pci_ids
[] = {
93 { PCI_VDEVICE(INTEL
, 0x0701), INTEL_CE4100
},
94 { PCI_VDEVICE(INTEL
, 0x0809), INTEL_MRST
},
95 { /* end: all zeroes */ }
99 /* these are static lookup tables that give us easy access to
100 * registers in the NAND controller.
102 static const uint32_t intr_status_addresses
[4] = {INTR_STATUS0
,
107 static const uint32_t device_reset_banks
[4] = {DEVICE_RESET__BANK0
,
110 DEVICE_RESET__BANK3
};
112 static const uint32_t operation_timeout
[4] = {INTR_STATUS0__TIME_OUT
,
113 INTR_STATUS1__TIME_OUT
,
114 INTR_STATUS2__TIME_OUT
,
115 INTR_STATUS3__TIME_OUT
};
117 static const uint32_t reset_complete
[4] = {INTR_STATUS0__RST_COMP
,
118 INTR_STATUS1__RST_COMP
,
119 INTR_STATUS2__RST_COMP
,
120 INTR_STATUS3__RST_COMP
};
122 /* forward declarations */
123 static void clear_interrupts(struct denali_nand_info
*denali
);
124 static uint32_t wait_for_irq(struct denali_nand_info
*denali
,
126 static void denali_irq_enable(struct denali_nand_info
*denali
,
128 static uint32_t read_interrupt_status(struct denali_nand_info
*denali
);
130 /* Certain operations for the denali NAND controller use
131 * an indexed mode to read/write data. The operation is
132 * performed by writing the address value of the command
133 * to the device memory followed by the data. This function
134 * abstracts this common operation.
136 static void index_addr(struct denali_nand_info
*denali
,
137 uint32_t address
, uint32_t data
)
139 iowrite32(address
, denali
->flash_mem
);
140 iowrite32(data
, denali
->flash_mem
+ 0x10);
143 /* Perform an indexed read of the device */
144 static void index_addr_read_data(struct denali_nand_info
*denali
,
145 uint32_t address
, uint32_t *pdata
)
147 iowrite32(address
, denali
->flash_mem
);
148 *pdata
= ioread32(denali
->flash_mem
+ 0x10);
151 /* We need to buffer some data for some of the NAND core routines.
152 * The operations manage buffering that data. */
153 static void reset_buf(struct denali_nand_info
*denali
)
155 denali
->buf
.head
= denali
->buf
.tail
= 0;
158 static void write_byte_to_buf(struct denali_nand_info
*denali
, uint8_t byte
)
160 BUG_ON(denali
->buf
.tail
>= sizeof(denali
->buf
.buf
));
161 denali
->buf
.buf
[denali
->buf
.tail
++] = byte
;
164 /* reads the status of the device */
165 static void read_status(struct denali_nand_info
*denali
)
169 /* initialize the data buffer to store status */
172 /* initiate a device status read */
173 cmd
= MODE_11
| BANK(denali
->flash_bank
);
174 index_addr(denali
, cmd
| COMMAND_CYCLE
, 0x70);
175 iowrite32(cmd
| STATUS_CYCLE
, denali
->flash_mem
);
177 /* update buffer with status value */
178 write_byte_to_buf(denali
, ioread32(denali
->flash_mem
+ 0x10));
181 /* resets a specific device connected to the core */
182 static void reset_bank(struct denali_nand_info
*denali
)
184 uint32_t irq_status
= 0;
185 uint32_t irq_mask
= reset_complete
[denali
->flash_bank
] |
186 operation_timeout
[denali
->flash_bank
];
189 clear_interrupts(denali
);
191 bank
= device_reset_banks
[denali
->flash_bank
];
192 iowrite32(bank
, denali
->flash_reg
+ DEVICE_RESET
);
194 irq_status
= wait_for_irq(denali
, irq_mask
);
196 if (irq_status
& operation_timeout
[denali
->flash_bank
])
197 dev_err(&denali
->dev
->dev
, "reset bank failed.\n");
200 /* Reset the flash controller */
201 static uint16_t denali_nand_reset(struct denali_nand_info
*denali
)
205 dev_dbg(&denali
->dev
->dev
, "%s, Line %d, Function: %s\n",
206 __FILE__
, __LINE__
, __func__
);
208 for (i
= 0 ; i
< LLD_MAX_FLASH_BANKS
; i
++)
209 iowrite32(reset_complete
[i
] | operation_timeout
[i
],
210 denali
->flash_reg
+ intr_status_addresses
[i
]);
212 for (i
= 0 ; i
< LLD_MAX_FLASH_BANKS
; i
++) {
213 iowrite32(device_reset_banks
[i
],
214 denali
->flash_reg
+ DEVICE_RESET
);
215 while (!(ioread32(denali
->flash_reg
+
216 intr_status_addresses
[i
]) &
217 (reset_complete
[i
] | operation_timeout
[i
])))
219 if (ioread32(denali
->flash_reg
+ intr_status_addresses
[i
]) &
220 operation_timeout
[i
])
221 dev_dbg(&denali
->dev
->dev
,
222 "NAND Reset operation timed out on bank %d\n", i
);
225 for (i
= 0; i
< LLD_MAX_FLASH_BANKS
; i
++)
226 iowrite32(reset_complete
[i
] | operation_timeout
[i
],
227 denali
->flash_reg
+ intr_status_addresses
[i
]);
232 /* this routine calculates the ONFI timing values for a given mode and
233 * programs the clocking register accordingly. The mode is determined by
234 * the get_onfi_nand_para routine.
236 static void nand_onfi_timing_set(struct denali_nand_info
*denali
,
239 uint16_t Trea
[6] = {40, 30, 25, 20, 20, 16};
240 uint16_t Trp
[6] = {50, 25, 17, 15, 12, 10};
241 uint16_t Treh
[6] = {30, 15, 15, 10, 10, 7};
242 uint16_t Trc
[6] = {100, 50, 35, 30, 25, 20};
243 uint16_t Trhoh
[6] = {0, 15, 15, 15, 15, 15};
244 uint16_t Trloh
[6] = {0, 0, 0, 0, 5, 5};
245 uint16_t Tcea
[6] = {100, 45, 30, 25, 25, 25};
246 uint16_t Tadl
[6] = {200, 100, 100, 100, 70, 70};
247 uint16_t Trhw
[6] = {200, 100, 100, 100, 100, 100};
248 uint16_t Trhz
[6] = {200, 100, 100, 100, 100, 100};
249 uint16_t Twhr
[6] = {120, 80, 80, 60, 60, 60};
250 uint16_t Tcs
[6] = {70, 35, 25, 25, 20, 15};
252 uint16_t TclsRising
= 1;
253 uint16_t data_invalid_rhoh
, data_invalid_rloh
, data_invalid
;
254 uint16_t dv_window
= 0;
255 uint16_t en_lo
, en_hi
;
257 uint16_t addr_2_data
, re_2_we
, re_2_re
, we_2_re
, cs_cnt
;
259 dev_dbg(&denali
->dev
->dev
, "%s, Line %d, Function: %s\n",
260 __FILE__
, __LINE__
, __func__
);
262 en_lo
= CEIL_DIV(Trp
[mode
], CLK_X
);
263 en_hi
= CEIL_DIV(Treh
[mode
], CLK_X
);
265 if ((en_hi
* CLK_X
) < (Treh
[mode
] + 2))
269 if ((en_lo
+ en_hi
) * CLK_X
< Trc
[mode
])
270 en_lo
+= CEIL_DIV((Trc
[mode
] - (en_lo
+ en_hi
) * CLK_X
), CLK_X
);
272 if ((en_lo
+ en_hi
) < CLK_MULTI
)
273 en_lo
+= CLK_MULTI
- en_lo
- en_hi
;
275 while (dv_window
< 8) {
276 data_invalid_rhoh
= en_lo
* CLK_X
+ Trhoh
[mode
];
278 data_invalid_rloh
= (en_lo
+ en_hi
) * CLK_X
+ Trloh
[mode
];
282 data_invalid_rloh
? data_invalid_rhoh
: data_invalid_rloh
;
284 dv_window
= data_invalid
- Trea
[mode
];
290 acc_clks
= CEIL_DIV(Trea
[mode
], CLK_X
);
292 while (((acc_clks
* CLK_X
) - Trea
[mode
]) < 3)
295 if ((data_invalid
- acc_clks
* CLK_X
) < 2)
296 dev_warn(&denali
->dev
->dev
, "%s, Line %d: Warning!\n",
299 addr_2_data
= CEIL_DIV(Tadl
[mode
], CLK_X
);
300 re_2_we
= CEIL_DIV(Trhw
[mode
], CLK_X
);
301 re_2_re
= CEIL_DIV(Trhz
[mode
], CLK_X
);
302 we_2_re
= CEIL_DIV(Twhr
[mode
], CLK_X
);
303 cs_cnt
= CEIL_DIV((Tcs
[mode
] - Trp
[mode
]), CLK_X
);
305 cs_cnt
= CEIL_DIV(Tcs
[mode
], CLK_X
);
310 while (((cs_cnt
* CLK_X
) + Trea
[mode
]) < Tcea
[mode
])
319 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
320 if ((ioread32(denali
->flash_reg
+ MANUFACTURER_ID
) == 0) &&
321 (ioread32(denali
->flash_reg
+ DEVICE_ID
) == 0x88))
324 iowrite32(acc_clks
, denali
->flash_reg
+ ACC_CLKS
);
325 iowrite32(re_2_we
, denali
->flash_reg
+ RE_2_WE
);
326 iowrite32(re_2_re
, denali
->flash_reg
+ RE_2_RE
);
327 iowrite32(we_2_re
, denali
->flash_reg
+ WE_2_RE
);
328 iowrite32(addr_2_data
, denali
->flash_reg
+ ADDR_2_DATA
);
329 iowrite32(en_lo
, denali
->flash_reg
+ RDWR_EN_LO_CNT
);
330 iowrite32(en_hi
, denali
->flash_reg
+ RDWR_EN_HI_CNT
);
331 iowrite32(cs_cnt
, denali
->flash_reg
+ CS_SETUP_CNT
);
334 /* queries the NAND device to see what ONFI modes it supports. */
335 static uint16_t get_onfi_nand_para(struct denali_nand_info
*denali
)
338 /* we needn't to do a reset here because driver has already
339 * reset all the banks before
341 if (!(ioread32(denali
->flash_reg
+ ONFI_TIMING_MODE
) &
342 ONFI_TIMING_MODE__VALUE
))
345 for (i
= 5; i
> 0; i
--) {
346 if (ioread32(denali
->flash_reg
+ ONFI_TIMING_MODE
) &
351 nand_onfi_timing_set(denali
, i
);
353 /* By now, all the ONFI devices we know support the page cache */
354 /* rw feature. So here we enable the pipeline_rw_ahead feature */
355 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
356 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
361 static void get_samsung_nand_para(struct denali_nand_info
*denali
,
364 if (device_id
== 0xd3) { /* Samsung K9WAG08U1A */
365 /* Set timing register values according to datasheet */
366 iowrite32(5, denali
->flash_reg
+ ACC_CLKS
);
367 iowrite32(20, denali
->flash_reg
+ RE_2_WE
);
368 iowrite32(12, denali
->flash_reg
+ WE_2_RE
);
369 iowrite32(14, denali
->flash_reg
+ ADDR_2_DATA
);
370 iowrite32(3, denali
->flash_reg
+ RDWR_EN_LO_CNT
);
371 iowrite32(2, denali
->flash_reg
+ RDWR_EN_HI_CNT
);
372 iowrite32(2, denali
->flash_reg
+ CS_SETUP_CNT
);
376 static void get_toshiba_nand_para(struct denali_nand_info
*denali
)
380 /* Workaround to fix a controller bug which reports a wrong */
381 /* spare area size for some kind of Toshiba NAND device */
382 if ((ioread32(denali
->flash_reg
+ DEVICE_MAIN_AREA_SIZE
) == 4096) &&
383 (ioread32(denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
) == 64)) {
384 iowrite32(216, denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
);
385 tmp
= ioread32(denali
->flash_reg
+ DEVICES_CONNECTED
) *
386 ioread32(denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
);
388 denali
->flash_reg
+ LOGICAL_PAGE_SPARE_SIZE
);
390 iowrite32(15, denali
->flash_reg
+ ECC_CORRECTION
);
391 #elif SUPPORT_8BITECC
392 iowrite32(8, denali
->flash_reg
+ ECC_CORRECTION
);
397 static void get_hynix_nand_para(struct denali_nand_info
*denali
,
400 uint32_t main_size
, spare_size
;
403 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
404 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
405 iowrite32(128, denali
->flash_reg
+ PAGES_PER_BLOCK
);
406 iowrite32(4096, denali
->flash_reg
+ DEVICE_MAIN_AREA_SIZE
);
407 iowrite32(224, denali
->flash_reg
+ DEVICE_SPARE_AREA_SIZE
);
409 ioread32(denali
->flash_reg
+ DEVICES_CONNECTED
);
411 ioread32(denali
->flash_reg
+ DEVICES_CONNECTED
);
413 denali
->flash_reg
+ LOGICAL_PAGE_DATA_SIZE
);
414 iowrite32(spare_size
,
415 denali
->flash_reg
+ LOGICAL_PAGE_SPARE_SIZE
);
416 iowrite32(0, denali
->flash_reg
+ DEVICE_WIDTH
);
418 iowrite32(15, denali
->flash_reg
+ ECC_CORRECTION
);
419 #elif SUPPORT_8BITECC
420 iowrite32(8, denali
->flash_reg
+ ECC_CORRECTION
);
424 dev_warn(&denali
->dev
->dev
,
425 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
426 "Will use default parameter values instead.\n",
431 /* determines how many NAND chips are connected to the controller. Note for
432 * Intel CE4100 devices we don't support more than one device.
434 static void find_valid_banks(struct denali_nand_info
*denali
)
436 uint32_t id
[LLD_MAX_FLASH_BANKS
];
439 denali
->total_used_banks
= 1;
440 for (i
= 0; i
< LLD_MAX_FLASH_BANKS
; i
++) {
441 index_addr(denali
, (uint32_t)(MODE_11
| (i
<< 24) | 0), 0x90);
442 index_addr(denali
, (uint32_t)(MODE_11
| (i
<< 24) | 1), 0);
443 index_addr_read_data(denali
,
444 (uint32_t)(MODE_11
| (i
<< 24) | 2), &id
[i
]);
446 dev_dbg(&denali
->dev
->dev
,
447 "Return 1st ID for bank[%d]: %x\n", i
, id
[i
]);
450 if (!(id
[i
] & 0x0ff))
453 if ((id
[i
] & 0x0ff) == (id
[0] & 0x0ff))
454 denali
->total_used_banks
++;
460 if (denali
->platform
== INTEL_CE4100
) {
461 /* Platform limitations of the CE4100 device limit
462 * users to a single chip solution for NAND.
463 * Multichip support is not enabled.
465 if (denali
->total_used_banks
!= 1) {
466 dev_err(&denali
->dev
->dev
,
467 "Sorry, Intel CE4100 only supports "
468 "a single NAND device.\n");
472 dev_dbg(&denali
->dev
->dev
,
473 "denali->total_used_banks: %d\n", denali
->total_used_banks
);
476 static void detect_partition_feature(struct denali_nand_info
*denali
)
478 /* For MRST platform, denali->fwblks represent the
479 * number of blocks firmware is taken,
480 * FW is in protect partition and MTD driver has no
481 * permission to access it. So let driver know how many
482 * blocks it can't touch.
484 if (ioread32(denali
->flash_reg
+ FEATURES
) & FEATURES__PARTITION
) {
485 if ((ioread32(denali
->flash_reg
+ PERM_SRC_ID_1
) &
486 PERM_SRC_ID_1__SRCID
) == SPECTRA_PARTITION_ID
) {
488 ((ioread32(denali
->flash_reg
+ MIN_MAX_BANK_1
) &
489 MIN_MAX_BANK_1__MIN_VALUE
) *
492 (ioread32(denali
->flash_reg
+ MIN_BLK_ADDR_1
) &
493 MIN_BLK_ADDR_1__VALUE
);
495 denali
->fwblks
= SPECTRA_START_BLOCK
;
497 denali
->fwblks
= SPECTRA_START_BLOCK
;
500 static uint16_t denali_nand_timing_set(struct denali_nand_info
*denali
)
502 uint16_t status
= PASS
;
503 uint32_t id_bytes
[5], addr
;
504 uint8_t i
, maf_id
, device_id
;
506 dev_dbg(&denali
->dev
->dev
,
507 "%s, Line %d, Function: %s\n",
508 __FILE__
, __LINE__
, __func__
);
510 /* Use read id method to get device ID and other
511 * params. For some NAND chips, controller can't
512 * report the correct device ID by reading from
515 addr
= (uint32_t)MODE_11
| BANK(denali
->flash_bank
);
516 index_addr(denali
, (uint32_t)addr
| 0, 0x90);
517 index_addr(denali
, (uint32_t)addr
| 1, 0);
518 for (i
= 0; i
< 5; i
++)
519 index_addr_read_data(denali
, addr
| 2, &id_bytes
[i
]);
520 maf_id
= id_bytes
[0];
521 device_id
= id_bytes
[1];
523 if (ioread32(denali
->flash_reg
+ ONFI_DEVICE_NO_OF_LUNS
) &
524 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE
) { /* ONFI 1.0 NAND */
525 if (FAIL
== get_onfi_nand_para(denali
))
527 } else if (maf_id
== 0xEC) { /* Samsung NAND */
528 get_samsung_nand_para(denali
, device_id
);
529 } else if (maf_id
== 0x98) { /* Toshiba NAND */
530 get_toshiba_nand_para(denali
);
531 } else if (maf_id
== 0xAD) { /* Hynix NAND */
532 get_hynix_nand_para(denali
, device_id
);
535 dev_info(&denali
->dev
->dev
,
536 "Dump timing register values:"
537 "acc_clks: %d, re_2_we: %d, re_2_re: %d\n"
538 "we_2_re: %d, addr_2_data: %d, rdwr_en_lo_cnt: %d\n"
539 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
540 ioread32(denali
->flash_reg
+ ACC_CLKS
),
541 ioread32(denali
->flash_reg
+ RE_2_WE
),
542 ioread32(denali
->flash_reg
+ RE_2_RE
),
543 ioread32(denali
->flash_reg
+ WE_2_RE
),
544 ioread32(denali
->flash_reg
+ ADDR_2_DATA
),
545 ioread32(denali
->flash_reg
+ RDWR_EN_LO_CNT
),
546 ioread32(denali
->flash_reg
+ RDWR_EN_HI_CNT
),
547 ioread32(denali
->flash_reg
+ CS_SETUP_CNT
));
549 find_valid_banks(denali
);
551 detect_partition_feature(denali
);
553 /* If the user specified to override the default timings
554 * with a specific ONFI mode, we apply those changes here.
556 if (onfi_timing_mode
!= NAND_DEFAULT_TIMINGS
)
557 nand_onfi_timing_set(denali
, onfi_timing_mode
);
562 static void denali_set_intr_modes(struct denali_nand_info
*denali
,
565 dev_dbg(&denali
->dev
->dev
, "%s, Line %d, Function: %s\n",
566 __FILE__
, __LINE__
, __func__
);
569 iowrite32(1, denali
->flash_reg
+ GLOBAL_INT_ENABLE
);
571 iowrite32(0, denali
->flash_reg
+ GLOBAL_INT_ENABLE
);
574 /* validation function to verify that the controlling software is making
577 static inline bool is_flash_bank_valid(int flash_bank
)
579 return (flash_bank
>= 0 && flash_bank
< 4);
582 static void denali_irq_init(struct denali_nand_info
*denali
)
584 uint32_t int_mask
= 0;
586 /* Disable global interrupts */
587 denali_set_intr_modes(denali
, false);
589 int_mask
= DENALI_IRQ_ALL
;
591 /* Clear all status bits */
592 iowrite32(0xFFFF, denali
->flash_reg
+ INTR_STATUS0
);
593 iowrite32(0xFFFF, denali
->flash_reg
+ INTR_STATUS1
);
594 iowrite32(0xFFFF, denali
->flash_reg
+ INTR_STATUS2
);
595 iowrite32(0xFFFF, denali
->flash_reg
+ INTR_STATUS3
);
597 denali_irq_enable(denali
, int_mask
);
600 static void denali_irq_cleanup(int irqnum
, struct denali_nand_info
*denali
)
602 denali_set_intr_modes(denali
, false);
603 free_irq(irqnum
, denali
);
606 static void denali_irq_enable(struct denali_nand_info
*denali
,
609 iowrite32(int_mask
, denali
->flash_reg
+ INTR_EN0
);
610 iowrite32(int_mask
, denali
->flash_reg
+ INTR_EN1
);
611 iowrite32(int_mask
, denali
->flash_reg
+ INTR_EN2
);
612 iowrite32(int_mask
, denali
->flash_reg
+ INTR_EN3
);
615 /* This function only returns when an interrupt that this driver cares about
616 * occurs. This is to reduce the overhead of servicing interrupts
618 static inline uint32_t denali_irq_detected(struct denali_nand_info
*denali
)
620 return read_interrupt_status(denali
) & DENALI_IRQ_ALL
;
623 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
624 static inline void clear_interrupt(struct denali_nand_info
*denali
,
627 uint32_t intr_status_reg
= 0;
629 intr_status_reg
= intr_status_addresses
[denali
->flash_bank
];
631 iowrite32(irq_mask
, denali
->flash_reg
+ intr_status_reg
);
634 static void clear_interrupts(struct denali_nand_info
*denali
)
636 uint32_t status
= 0x0;
637 spin_lock_irq(&denali
->irq_lock
);
639 status
= read_interrupt_status(denali
);
640 clear_interrupt(denali
, status
);
642 denali
->irq_status
= 0x0;
643 spin_unlock_irq(&denali
->irq_lock
);
646 static uint32_t read_interrupt_status(struct denali_nand_info
*denali
)
648 uint32_t intr_status_reg
= 0;
650 intr_status_reg
= intr_status_addresses
[denali
->flash_bank
];
652 return ioread32(denali
->flash_reg
+ intr_status_reg
);
655 /* This is the interrupt service routine. It handles all interrupts
656 * sent to this device. Note that on CE4100, this is a shared
659 static irqreturn_t
denali_isr(int irq
, void *dev_id
)
661 struct denali_nand_info
*denali
= dev_id
;
662 uint32_t irq_status
= 0x0;
663 irqreturn_t result
= IRQ_NONE
;
665 spin_lock(&denali
->irq_lock
);
667 /* check to see if a valid NAND chip has
670 if (is_flash_bank_valid(denali
->flash_bank
)) {
671 /* check to see if controller generated
672 * the interrupt, since this is a shared interrupt */
673 irq_status
= denali_irq_detected(denali
);
674 if (irq_status
!= 0) {
675 /* handle interrupt */
676 /* first acknowledge it */
677 clear_interrupt(denali
, irq_status
);
678 /* store the status in the device context for someone
680 denali
->irq_status
|= irq_status
;
681 /* notify anyone who cares that it happened */
682 complete(&denali
->complete
);
683 /* tell the OS that we've handled this */
684 result
= IRQ_HANDLED
;
687 spin_unlock(&denali
->irq_lock
);
690 #define BANK(x) ((x) << 24)
692 static uint32_t wait_for_irq(struct denali_nand_info
*denali
, uint32_t irq_mask
)
694 unsigned long comp_res
= 0;
695 uint32_t intr_status
= 0;
697 unsigned long timeout
= msecs_to_jiffies(1000);
701 wait_for_completion_timeout(&denali
->complete
, timeout
);
702 spin_lock_irq(&denali
->irq_lock
);
703 intr_status
= denali
->irq_status
;
705 if (intr_status
& irq_mask
) {
706 denali
->irq_status
&= ~irq_mask
;
707 spin_unlock_irq(&denali
->irq_lock
);
708 /* our interrupt was detected */
711 /* these are not the interrupts you are looking for -
712 * need to wait again */
713 spin_unlock_irq(&denali
->irq_lock
);
716 } while (comp_res
!= 0);
720 printk(KERN_ERR
"timeout occurred, status = 0x%x, mask = 0x%x\n",
721 intr_status
, irq_mask
);
728 /* This helper function setups the registers for ECC and whether or not
729 * the spare area will be transfered. */
730 static void setup_ecc_for_xfer(struct denali_nand_info
*denali
, bool ecc_en
,
733 int ecc_en_flag
= 0, transfer_spare_flag
= 0;
735 /* set ECC, transfer spare bits if needed */
736 ecc_en_flag
= ecc_en
? ECC_ENABLE__FLAG
: 0;
737 transfer_spare_flag
= transfer_spare
? TRANSFER_SPARE_REG__FLAG
: 0;
739 /* Enable spare area/ECC per user's request. */
740 iowrite32(ecc_en_flag
, denali
->flash_reg
+ ECC_ENABLE
);
741 iowrite32(transfer_spare_flag
,
742 denali
->flash_reg
+ TRANSFER_SPARE_REG
);
745 /* sends a pipeline command operation to the controller. See the Denali NAND
746 * controller's user guide for more information (section 4.2.3.6).
748 static int denali_send_pipeline_cmd(struct denali_nand_info
*denali
,
755 uint32_t addr
= 0x0, cmd
= 0x0, page_count
= 1, irq_status
= 0,
758 if (op
== DENALI_READ
)
759 irq_mask
= INTR_STATUS0__LOAD_COMP
;
760 else if (op
== DENALI_WRITE
)
765 setup_ecc_for_xfer(denali
, ecc_en
, transfer_spare
);
767 /* clear interrupts */
768 clear_interrupts(denali
);
770 addr
= BANK(denali
->flash_bank
) | denali
->page
;
772 if (op
== DENALI_WRITE
&& access_type
!= SPARE_ACCESS
) {
773 cmd
= MODE_01
| addr
;
774 iowrite32(cmd
, denali
->flash_mem
);
775 } else if (op
== DENALI_WRITE
&& access_type
== SPARE_ACCESS
) {
776 /* read spare area */
777 cmd
= MODE_10
| addr
;
778 index_addr(denali
, (uint32_t)cmd
, access_type
);
780 cmd
= MODE_01
| addr
;
781 iowrite32(cmd
, denali
->flash_mem
);
782 } else if (op
== DENALI_READ
) {
783 /* setup page read request for access type */
784 cmd
= MODE_10
| addr
;
785 index_addr(denali
, (uint32_t)cmd
, access_type
);
787 /* page 33 of the NAND controller spec indicates we should not
788 use the pipeline commands in Spare area only mode. So we
791 if (access_type
== SPARE_ACCESS
) {
792 cmd
= MODE_01
| addr
;
793 iowrite32(cmd
, denali
->flash_mem
);
795 index_addr(denali
, (uint32_t)cmd
,
796 0x2000 | op
| page_count
);
798 /* wait for command to be accepted
799 * can always use status0 bit as the
800 * mask is identical for each
802 irq_status
= wait_for_irq(denali
, irq_mask
);
804 if (irq_status
== 0) {
805 dev_err(&denali
->dev
->dev
,
806 "cmd, page, addr on timeout "
807 "(0x%x, 0x%x, 0x%x)\n",
808 cmd
, denali
->page
, addr
);
811 cmd
= MODE_01
| addr
;
812 iowrite32(cmd
, denali
->flash_mem
);
819 /* helper function that simply writes a buffer to the flash */
820 static int write_data_to_flash_mem(struct denali_nand_info
*denali
,
824 uint32_t i
= 0, *buf32
;
826 /* verify that the len is a multiple of 4. see comment in
827 * read_data_from_flash_mem() */
828 BUG_ON((len
% 4) != 0);
830 /* write the data to the flash memory */
831 buf32
= (uint32_t *)buf
;
832 for (i
= 0; i
< len
/ 4; i
++)
833 iowrite32(*buf32
++, denali
->flash_mem
+ 0x10);
834 return i
*4; /* intent is to return the number of bytes read */
837 /* helper function that simply reads a buffer from the flash */
838 static int read_data_from_flash_mem(struct denali_nand_info
*denali
,
842 uint32_t i
= 0, *buf32
;
844 /* we assume that len will be a multiple of 4, if not
845 * it would be nice to know about it ASAP rather than
846 * have random failures...
847 * This assumption is based on the fact that this
848 * function is designed to be used to read flash pages,
849 * which are typically multiples of 4...
852 BUG_ON((len
% 4) != 0);
854 /* transfer the data from the flash */
855 buf32
= (uint32_t *)buf
;
856 for (i
= 0; i
< len
/ 4; i
++)
857 *buf32
++ = ioread32(denali
->flash_mem
+ 0x10);
858 return i
*4; /* intent is to return the number of bytes read */
861 /* writes OOB data to the device */
862 static int write_oob_data(struct mtd_info
*mtd
, uint8_t *buf
, int page
)
864 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
865 uint32_t irq_status
= 0;
866 uint32_t irq_mask
= INTR_STATUS0__PROGRAM_COMP
|
867 INTR_STATUS0__PROGRAM_FAIL
;
872 if (denali_send_pipeline_cmd(denali
, false, false, SPARE_ACCESS
,
873 DENALI_WRITE
) == PASS
) {
874 write_data_to_flash_mem(denali
, buf
, mtd
->oobsize
);
876 /* wait for operation to complete */
877 irq_status
= wait_for_irq(denali
, irq_mask
);
879 if (irq_status
== 0) {
880 dev_err(&denali
->dev
->dev
, "OOB write failed\n");
884 dev_err(&denali
->dev
->dev
, "unable to send pipeline command\n");
890 /* reads OOB data from the device */
891 static void read_oob_data(struct mtd_info
*mtd
, uint8_t *buf
, int page
)
893 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
894 uint32_t irq_mask
= INTR_STATUS0__LOAD_COMP
,
895 irq_status
= 0, addr
= 0x0, cmd
= 0x0;
899 if (denali_send_pipeline_cmd(denali
, false, true, SPARE_ACCESS
,
900 DENALI_READ
) == PASS
) {
901 read_data_from_flash_mem(denali
, buf
, mtd
->oobsize
);
903 /* wait for command to be accepted
904 * can always use status0 bit as the mask is identical for each
906 irq_status
= wait_for_irq(denali
, irq_mask
);
909 dev_err(&denali
->dev
->dev
, "page on OOB timeout %d\n",
912 /* We set the device back to MAIN_ACCESS here as I observed
913 * instability with the controller if you do a block erase
914 * and the last transaction was a SPARE_ACCESS. Block erase
915 * is reliable (according to the MTD test infrastructure)
916 * if you are in MAIN_ACCESS.
918 addr
= BANK(denali
->flash_bank
) | denali
->page
;
919 cmd
= MODE_10
| addr
;
920 index_addr(denali
, (uint32_t)cmd
, MAIN_ACCESS
);
924 /* this function examines buffers to see if they contain data that
925 * indicate that the buffer is part of an erased region of flash.
927 bool is_erased(uint8_t *buf
, int len
)
930 for (i
= 0; i
< len
; i
++)
935 #define ECC_SECTOR_SIZE 512
937 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
938 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
939 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
940 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
941 #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
942 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
944 static bool handle_ecc(struct denali_nand_info
*denali
, uint8_t *buf
,
947 bool check_erased_page
= false;
949 if (irq_status
& INTR_STATUS0__ECC_ERR
) {
950 /* read the ECC errors. we'll ignore them for now */
951 uint32_t err_address
= 0, err_correction_info
= 0;
952 uint32_t err_byte
= 0, err_sector
= 0, err_device
= 0;
953 uint32_t err_correction_value
= 0;
954 denali_set_intr_modes(denali
, false);
957 err_address
= ioread32(denali
->flash_reg
+
959 err_sector
= ECC_SECTOR(err_address
);
960 err_byte
= ECC_BYTE(err_address
);
962 err_correction_info
= ioread32(denali
->flash_reg
+
963 ERR_CORRECTION_INFO
);
964 err_correction_value
=
965 ECC_CORRECTION_VALUE(err_correction_info
);
966 err_device
= ECC_ERR_DEVICE(err_correction_info
);
968 if (ECC_ERROR_CORRECTABLE(err_correction_info
)) {
969 /* If err_byte is larger than ECC_SECTOR_SIZE,
970 * means error happend in OOB, so we ignore
971 * it. It's no need for us to correct it
972 * err_device is represented the NAND error
973 * bits are happened in if there are more
974 * than one NAND connected.
976 if (err_byte
< ECC_SECTOR_SIZE
) {
978 offset
= (err_sector
*
983 /* correct the ECC error */
984 buf
[offset
] ^= err_correction_value
;
985 denali
->mtd
.ecc_stats
.corrected
++;
988 /* if the error is not correctable, need to
989 * look at the page to see if it is an erased
990 * page. if so, then it's not a real ECC error
992 check_erased_page
= true;
994 } while (!ECC_LAST_ERR(err_correction_info
));
995 /* Once handle all ecc errors, controller will triger
996 * a ECC_TRANSACTION_DONE interrupt, so here just wait
997 * for a while for this interrupt
999 while (!(read_interrupt_status(denali
) &
1000 INTR_STATUS0__ECC_TRANSACTION_DONE
))
1002 clear_interrupts(denali
);
1003 denali_set_intr_modes(denali
, true);
1005 return check_erased_page
;
1008 /* programs the controller to either enable/disable DMA transfers */
1009 static void denali_enable_dma(struct denali_nand_info
*denali
, bool en
)
1011 uint32_t reg_val
= 0x0;
1014 reg_val
= DMA_ENABLE__FLAG
;
1016 iowrite32(reg_val
, denali
->flash_reg
+ DMA_ENABLE
);
1017 ioread32(denali
->flash_reg
+ DMA_ENABLE
);
1020 /* setups the HW to perform the data DMA */
1021 static void denali_setup_dma(struct denali_nand_info
*denali
, int op
)
1023 uint32_t mode
= 0x0;
1024 const int page_count
= 1;
1025 dma_addr_t addr
= denali
->buf
.dma_buf
;
1027 mode
= MODE_10
| BANK(denali
->flash_bank
);
1029 /* DMA is a four step process */
1031 /* 1. setup transfer type and # of pages */
1032 index_addr(denali
, mode
| denali
->page
, 0x2000 | op
| page_count
);
1034 /* 2. set memory high address bits 23:8 */
1035 index_addr(denali
, mode
| ((uint16_t)(addr
>> 16) << 8), 0x2200);
1037 /* 3. set memory low address bits 23:8 */
1038 index_addr(denali
, mode
| ((uint16_t)addr
<< 8), 0x2300);
1040 /* 4. interrupt when complete, burst len = 64 bytes*/
1041 index_addr(denali
, mode
| 0x14000, 0x2400);
1044 /* writes a page. user specifies type, and this function handles the
1045 * configuration details. */
1046 static void write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1047 const uint8_t *buf
, bool raw_xfer
)
1049 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1050 struct pci_dev
*pci_dev
= denali
->dev
;
1052 dma_addr_t addr
= denali
->buf
.dma_buf
;
1053 size_t size
= denali
->mtd
.writesize
+ denali
->mtd
.oobsize
;
1055 uint32_t irq_status
= 0;
1056 uint32_t irq_mask
= INTR_STATUS0__DMA_CMD_COMP
|
1057 INTR_STATUS0__PROGRAM_FAIL
;
1059 /* if it is a raw xfer, we want to disable ecc, and send
1061 * !raw_xfer - enable ecc
1062 * raw_xfer - transfer spare
1064 setup_ecc_for_xfer(denali
, !raw_xfer
, raw_xfer
);
1066 /* copy buffer into DMA buffer */
1067 memcpy(denali
->buf
.buf
, buf
, mtd
->writesize
);
1070 /* transfer the data to the spare area */
1071 memcpy(denali
->buf
.buf
+ mtd
->writesize
,
1076 pci_dma_sync_single_for_device(pci_dev
, addr
, size
, PCI_DMA_TODEVICE
);
1078 clear_interrupts(denali
);
1079 denali_enable_dma(denali
, true);
1081 denali_setup_dma(denali
, DENALI_WRITE
);
1083 /* wait for operation to complete */
1084 irq_status
= wait_for_irq(denali
, irq_mask
);
1086 if (irq_status
== 0) {
1087 dev_err(&denali
->dev
->dev
,
1088 "timeout on write_page (type = %d)\n",
1091 (irq_status
& INTR_STATUS0__PROGRAM_FAIL
) ?
1092 NAND_STATUS_FAIL
: PASS
;
1095 denali_enable_dma(denali
, false);
1096 pci_dma_sync_single_for_cpu(pci_dev
, addr
, size
, PCI_DMA_TODEVICE
);
1099 /* NAND core entry points */
1101 /* this is the callback that the NAND core calls to write a page. Since
1102 * writing a page with ECC or without is similar, all the work is done
1103 * by write_page above.
1105 static void denali_write_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1108 /* for regular page writes, we let HW handle all the ECC
1109 * data written to the device. */
1110 write_page(mtd
, chip
, buf
, false);
1113 /* This is the callback that the NAND core calls to write a page without ECC.
1114 * raw access is similiar to ECC page writes, so all the work is done in the
1115 * write_page() function above.
1117 static void denali_write_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1120 /* for raw page writes, we want to disable ECC and simply write
1121 whatever data is in the buffer. */
1122 write_page(mtd
, chip
, buf
, true);
1125 static int denali_write_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1128 return write_oob_data(mtd
, chip
->oob_poi
, page
);
1131 static int denali_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1132 int page
, int sndcmd
)
1134 read_oob_data(mtd
, chip
->oob_poi
, page
);
1136 return 0; /* notify NAND core to send command to
1140 static int denali_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1141 uint8_t *buf
, int page
)
1143 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1144 struct pci_dev
*pci_dev
= denali
->dev
;
1146 dma_addr_t addr
= denali
->buf
.dma_buf
;
1147 size_t size
= denali
->mtd
.writesize
+ denali
->mtd
.oobsize
;
1149 uint32_t irq_status
= 0;
1150 uint32_t irq_mask
= INTR_STATUS0__ECC_TRANSACTION_DONE
|
1151 INTR_STATUS0__ECC_ERR
;
1152 bool check_erased_page
= false;
1154 setup_ecc_for_xfer(denali
, true, false);
1156 denali_enable_dma(denali
, true);
1157 pci_dma_sync_single_for_device(pci_dev
, addr
, size
, PCI_DMA_FROMDEVICE
);
1159 clear_interrupts(denali
);
1160 denali_setup_dma(denali
, DENALI_READ
);
1162 /* wait for operation to complete */
1163 irq_status
= wait_for_irq(denali
, irq_mask
);
1165 pci_dma_sync_single_for_cpu(pci_dev
, addr
, size
, PCI_DMA_FROMDEVICE
);
1167 memcpy(buf
, denali
->buf
.buf
, mtd
->writesize
);
1169 check_erased_page
= handle_ecc(denali
, buf
, irq_status
);
1170 denali_enable_dma(denali
, false);
1172 if (check_erased_page
) {
1173 read_oob_data(&denali
->mtd
, chip
->oob_poi
, denali
->page
);
1175 /* check ECC failures that may have occurred on erased pages */
1176 if (check_erased_page
) {
1177 if (!is_erased(buf
, denali
->mtd
.writesize
))
1178 denali
->mtd
.ecc_stats
.failed
++;
1179 if (!is_erased(buf
, denali
->mtd
.oobsize
))
1180 denali
->mtd
.ecc_stats
.failed
++;
1186 static int denali_read_page_raw(struct mtd_info
*mtd
, struct nand_chip
*chip
,
1187 uint8_t *buf
, int page
)
1189 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1190 struct pci_dev
*pci_dev
= denali
->dev
;
1192 dma_addr_t addr
= denali
->buf
.dma_buf
;
1193 size_t size
= denali
->mtd
.writesize
+ denali
->mtd
.oobsize
;
1195 uint32_t irq_status
= 0;
1196 uint32_t irq_mask
= INTR_STATUS0__DMA_CMD_COMP
;
1198 setup_ecc_for_xfer(denali
, false, true);
1199 denali_enable_dma(denali
, true);
1201 pci_dma_sync_single_for_device(pci_dev
, addr
, size
, PCI_DMA_FROMDEVICE
);
1203 clear_interrupts(denali
);
1204 denali_setup_dma(denali
, DENALI_READ
);
1206 /* wait for operation to complete */
1207 irq_status
= wait_for_irq(denali
, irq_mask
);
1209 pci_dma_sync_single_for_cpu(pci_dev
, addr
, size
, PCI_DMA_FROMDEVICE
);
1211 denali_enable_dma(denali
, false);
1213 memcpy(buf
, denali
->buf
.buf
, mtd
->writesize
);
1214 memcpy(chip
->oob_poi
, denali
->buf
.buf
+ mtd
->writesize
, mtd
->oobsize
);
1219 static uint8_t denali_read_byte(struct mtd_info
*mtd
)
1221 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1222 uint8_t result
= 0xff;
1224 if (denali
->buf
.head
< denali
->buf
.tail
)
1225 result
= denali
->buf
.buf
[denali
->buf
.head
++];
1230 static void denali_select_chip(struct mtd_info
*mtd
, int chip
)
1232 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1234 spin_lock_irq(&denali
->irq_lock
);
1235 denali
->flash_bank
= chip
;
1236 spin_unlock_irq(&denali
->irq_lock
);
1239 static int denali_waitfunc(struct mtd_info
*mtd
, struct nand_chip
*chip
)
1241 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1242 int status
= denali
->status
;
1248 static void denali_erase(struct mtd_info
*mtd
, int page
)
1250 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1252 uint32_t cmd
= 0x0, irq_status
= 0;
1254 /* clear interrupts */
1255 clear_interrupts(denali
);
1257 /* setup page read request for access type */
1258 cmd
= MODE_10
| BANK(denali
->flash_bank
) | page
;
1259 index_addr(denali
, (uint32_t)cmd
, 0x1);
1261 /* wait for erase to complete or failure to occur */
1262 irq_status
= wait_for_irq(denali
, INTR_STATUS0__ERASE_COMP
|
1263 INTR_STATUS0__ERASE_FAIL
);
1265 denali
->status
= (irq_status
& INTR_STATUS0__ERASE_FAIL
) ?
1266 NAND_STATUS_FAIL
: PASS
;
1269 static void denali_cmdfunc(struct mtd_info
*mtd
, unsigned int cmd
, int col
,
1272 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1277 case NAND_CMD_PAGEPROG
:
1279 case NAND_CMD_STATUS
:
1280 read_status(denali
);
1282 case NAND_CMD_READID
:
1284 /*sometimes ManufactureId read from register is not right
1285 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1286 * So here we send READID cmd to NAND insteand
1288 addr
= (uint32_t)MODE_11
| BANK(denali
->flash_bank
);
1289 index_addr(denali
, (uint32_t)addr
| 0, 0x90);
1290 index_addr(denali
, (uint32_t)addr
| 1, 0);
1291 for (i
= 0; i
< 5; i
++) {
1292 index_addr_read_data(denali
,
1295 write_byte_to_buf(denali
, id
);
1298 case NAND_CMD_READ0
:
1299 case NAND_CMD_SEQIN
:
1300 denali
->page
= page
;
1302 case NAND_CMD_RESET
:
1305 case NAND_CMD_READOOB
:
1306 /* TODO: Read OOB data */
1309 printk(KERN_ERR
": unsupported command"
1310 " received 0x%x\n", cmd
);
1315 /* stubs for ECC functions not used by the NAND core */
1316 static int denali_ecc_calculate(struct mtd_info
*mtd
, const uint8_t *data
,
1319 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1320 dev_err(&denali
->dev
->dev
,
1321 "denali_ecc_calculate called unexpectedly\n");
1326 static int denali_ecc_correct(struct mtd_info
*mtd
, uint8_t *data
,
1327 uint8_t *read_ecc
, uint8_t *calc_ecc
)
1329 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1330 dev_err(&denali
->dev
->dev
,
1331 "denali_ecc_correct called unexpectedly\n");
1336 static void denali_ecc_hwctl(struct mtd_info
*mtd
, int mode
)
1338 struct denali_nand_info
*denali
= mtd_to_denali(mtd
);
1339 dev_err(&denali
->dev
->dev
,
1340 "denali_ecc_hwctl called unexpectedly\n");
1343 /* end NAND core entry points */
1345 /* Initialization code to bring the device up to a known good state */
1346 static void denali_hw_init(struct denali_nand_info
*denali
)
1348 /* tell driver how many bit controller will skip before
1349 * writing ECC code in OOB, this register may be already
1350 * set by firmware. So we read this value out.
1351 * if this value is 0, just let it be.
1353 denali
->bbtskipbytes
= ioread32(denali
->flash_reg
+
1354 SPARE_AREA_SKIP_BYTES
);
1355 denali_irq_init(denali
);
1356 denali_nand_reset(denali
);
1357 iowrite32(0x0F, denali
->flash_reg
+ RB_PIN_ENABLED
);
1358 iowrite32(CHIP_EN_DONT_CARE__FLAG
,
1359 denali
->flash_reg
+ CHIP_ENABLE_DONT_CARE
);
1361 iowrite32(0x0, denali
->flash_reg
+ SPARE_AREA_SKIP_BYTES
);
1362 iowrite32(0xffff, denali
->flash_reg
+ SPARE_AREA_MARKER
);
1364 /* Should set value for these registers when init */
1365 iowrite32(0, denali
->flash_reg
+ TWO_ROW_ADDR_CYCLES
);
1366 iowrite32(1, denali
->flash_reg
+ ECC_ENABLE
);
1369 /* Althogh controller spec said SLC ECC is forceb to be 4bit,
1370 * but denali controller in MRST only support 15bit and 8bit ECC
1373 #define ECC_8BITS 14
1374 static struct nand_ecclayout nand_8bit_oob
= {
1378 #define ECC_15BITS 26
1379 static struct nand_ecclayout nand_15bit_oob
= {
1383 static uint8_t bbt_pattern
[] = {'B', 'b', 't', '0' };
1384 static uint8_t mirror_pattern
[] = {'1', 't', 'b', 'B' };
1386 static struct nand_bbt_descr bbt_main_descr
= {
1387 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
1388 | NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1393 .pattern
= bbt_pattern
,
1396 static struct nand_bbt_descr bbt_mirror_descr
= {
1397 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
1398 | NAND_BBT_2BIT
| NAND_BBT_VERSION
| NAND_BBT_PERCHIP
,
1403 .pattern
= mirror_pattern
,
1406 /* initialize driver data structures */
1407 void denali_drv_init(struct denali_nand_info
*denali
)
1411 /* setup interrupt handler */
1412 /* the completion object will be used to notify
1413 * the callee that the interrupt is done */
1414 init_completion(&denali
->complete
);
1416 /* the spinlock will be used to synchronize the ISR
1417 * with any element that might be access shared
1418 * data (interrupt status) */
1419 spin_lock_init(&denali
->irq_lock
);
1421 /* indicate that MTD has not selected a valid bank yet */
1422 denali
->flash_bank
= CHIP_SELECT_INVALID
;
1424 /* initialize our irq_status variable to indicate no interrupts */
1425 denali
->irq_status
= 0;
1428 /* driver entry point */
1429 static int denali_pci_probe(struct pci_dev
*dev
, const struct pci_device_id
*id
)
1432 resource_size_t csr_base
, mem_base
;
1433 unsigned long csr_len
, mem_len
;
1434 struct denali_nand_info
*denali
;
1436 denali
= kzalloc(sizeof(*denali
), GFP_KERNEL
);
1440 ret
= pci_enable_device(dev
);
1442 printk(KERN_ERR
"Spectra: pci_enable_device failed.\n");
1443 goto failed_alloc_memery
;
1446 if (id
->driver_data
== INTEL_CE4100
) {
1447 /* Due to a silicon limitation, we can only support
1448 * ONFI timing mode 1 and below.
1450 if (onfi_timing_mode
< -1 || onfi_timing_mode
> 1) {
1451 printk(KERN_ERR
"Intel CE4100 only supports"
1452 " ONFI timing mode 1 or below\n");
1454 goto failed_enable_dev
;
1456 denali
->platform
= INTEL_CE4100
;
1457 mem_base
= pci_resource_start(dev
, 0);
1458 mem_len
= pci_resource_len(dev
, 1);
1459 csr_base
= pci_resource_start(dev
, 1);
1460 csr_len
= pci_resource_len(dev
, 1);
1462 denali
->platform
= INTEL_MRST
;
1463 csr_base
= pci_resource_start(dev
, 0);
1464 csr_len
= pci_resource_len(dev
, 0);
1465 mem_base
= pci_resource_start(dev
, 1);
1466 mem_len
= pci_resource_len(dev
, 1);
1468 mem_base
= csr_base
+ csr_len
;
1473 /* Is 32-bit DMA supported? */
1474 ret
= pci_set_dma_mask(dev
, DMA_BIT_MASK(32));
1477 printk(KERN_ERR
"Spectra: no usable DMA configuration\n");
1478 goto failed_enable_dev
;
1480 denali
->buf
.dma_buf
=
1481 pci_map_single(dev
, denali
->buf
.buf
,
1483 PCI_DMA_BIDIRECTIONAL
);
1485 if (pci_dma_mapping_error(dev
, denali
->buf
.dma_buf
)) {
1486 dev_err(&dev
->dev
, "Spectra: failed to map DMA buffer\n");
1487 goto failed_enable_dev
;
1490 pci_set_master(dev
);
1493 ret
= pci_request_regions(dev
, DENALI_NAND_NAME
);
1495 printk(KERN_ERR
"Spectra: Unable to request memory regions\n");
1496 goto failed_dma_map
;
1499 denali
->flash_reg
= ioremap_nocache(csr_base
, csr_len
);
1500 if (!denali
->flash_reg
) {
1501 printk(KERN_ERR
"Spectra: Unable to remap memory region\n");
1503 goto failed_req_regions
;
1506 denali
->flash_mem
= ioremap_nocache(mem_base
, mem_len
);
1507 if (!denali
->flash_mem
) {
1508 printk(KERN_ERR
"Spectra: ioremap_nocache failed!");
1510 goto failed_remap_reg
;
1513 denali_hw_init(denali
);
1514 denali_drv_init(denali
);
1516 if (request_irq(dev
->irq
, denali_isr
, IRQF_SHARED
,
1517 DENALI_NAND_NAME
, denali
)) {
1518 printk(KERN_ERR
"Spectra: Unable to allocate IRQ\n");
1520 goto failed_remap_mem
;
1523 /* now that our ISR is registered, we can enable interrupts */
1524 denali_set_intr_modes(denali
, true);
1526 pci_set_drvdata(dev
, denali
);
1528 denali_nand_timing_set(denali
);
1530 denali
->mtd
.name
= "Denali NAND";
1531 denali
->mtd
.owner
= THIS_MODULE
;
1532 denali
->mtd
.priv
= &denali
->nand
;
1534 /* register the driver with the NAND core subsystem */
1535 denali
->nand
.select_chip
= denali_select_chip
;
1536 denali
->nand
.cmdfunc
= denali_cmdfunc
;
1537 denali
->nand
.read_byte
= denali_read_byte
;
1538 denali
->nand
.waitfunc
= denali_waitfunc
;
1540 /* scan for NAND devices attached to the controller
1541 * this is the first stage in a two step process to register
1542 * with the nand subsystem */
1543 if (nand_scan_ident(&denali
->mtd
, LLD_MAX_FLASH_BANKS
, NULL
)) {
1545 goto failed_req_irq
;
1548 /* MTD supported page sizes vary by kernel. We validate our
1549 * kernel supports the device here.
1551 if (denali
->mtd
.writesize
> NAND_MAX_PAGESIZE
+ NAND_MAX_OOBSIZE
) {
1553 printk(KERN_ERR
"Spectra: device size not supported by this "
1555 goto failed_req_irq
;
1558 /* support for multi nand
1559 * MTD known nothing about multi nand,
1560 * so we should tell it the real pagesize
1561 * and anything necessery
1563 denali
->devnum
= ioread32(denali
->flash_reg
+ DEVICES_CONNECTED
);
1564 denali
->nand
.chipsize
<<= (denali
->devnum
- 1);
1565 denali
->nand
.page_shift
+= (denali
->devnum
- 1);
1566 denali
->nand
.pagemask
= (denali
->nand
.chipsize
>>
1567 denali
->nand
.page_shift
) - 1;
1568 denali
->nand
.bbt_erase_shift
+= (denali
->devnum
- 1);
1569 denali
->nand
.phys_erase_shift
= denali
->nand
.bbt_erase_shift
;
1570 denali
->nand
.chip_shift
+= (denali
->devnum
- 1);
1571 denali
->mtd
.writesize
<<= (denali
->devnum
- 1);
1572 denali
->mtd
.oobsize
<<= (denali
->devnum
- 1);
1573 denali
->mtd
.erasesize
<<= (denali
->devnum
- 1);
1574 denali
->mtd
.size
= denali
->nand
.numchips
* denali
->nand
.chipsize
;
1575 denali
->bbtskipbytes
*= denali
->devnum
;
1577 /* second stage of the NAND scan
1578 * this stage requires information regarding ECC and
1579 * bad block management. */
1581 /* Bad block management */
1582 denali
->nand
.bbt_td
= &bbt_main_descr
;
1583 denali
->nand
.bbt_md
= &bbt_mirror_descr
;
1585 /* skip the scan for now until we have OOB read and write support */
1586 denali
->nand
.options
|= NAND_USE_FLASH_BBT
| NAND_SKIP_BBTSCAN
;
1587 denali
->nand
.ecc
.mode
= NAND_ECC_HW_SYNDROME
;
1589 /* Denali Controller only support 15bit and 8bit ECC in MRST,
1590 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1593 if (denali
->nand
.cellinfo
& 0xc &&
1594 (denali
->mtd
.oobsize
> (denali
->bbtskipbytes
+
1595 ECC_15BITS
* (denali
->mtd
.writesize
/
1596 ECC_SECTOR_SIZE
)))) {
1597 /* if MLC OOB size is large enough, use 15bit ECC*/
1598 denali
->nand
.ecc
.layout
= &nand_15bit_oob
;
1599 denali
->nand
.ecc
.bytes
= ECC_15BITS
;
1600 iowrite32(15, denali
->flash_reg
+ ECC_CORRECTION
);
1601 } else if (denali
->mtd
.oobsize
< (denali
->bbtskipbytes
+
1602 ECC_8BITS
* (denali
->mtd
.writesize
/
1603 ECC_SECTOR_SIZE
))) {
1604 printk(KERN_ERR
"Your NAND chip OOB is not large enough to"
1605 " contain 8bit ECC correction codes");
1606 goto failed_req_irq
;
1608 denali
->nand
.ecc
.layout
= &nand_8bit_oob
;
1609 denali
->nand
.ecc
.bytes
= ECC_8BITS
;
1610 iowrite32(8, denali
->flash_reg
+ ECC_CORRECTION
);
1613 denali
->nand
.ecc
.bytes
*= denali
->devnum
;
1614 denali
->nand
.ecc
.layout
->eccbytes
*=
1615 denali
->mtd
.writesize
/ ECC_SECTOR_SIZE
;
1616 denali
->nand
.ecc
.layout
->oobfree
[0].offset
=
1617 denali
->bbtskipbytes
+ denali
->nand
.ecc
.layout
->eccbytes
;
1618 denali
->nand
.ecc
.layout
->oobfree
[0].length
=
1619 denali
->mtd
.oobsize
- denali
->nand
.ecc
.layout
->eccbytes
-
1620 denali
->bbtskipbytes
;
1622 /* Let driver know the total blocks number and
1623 * how many blocks contained by each nand chip.
1624 * blksperchip will help driver to know how many
1625 * blocks is taken by FW.
1627 denali
->totalblks
= denali
->mtd
.size
>>
1628 denali
->nand
.phys_erase_shift
;
1629 denali
->blksperchip
= denali
->totalblks
/ denali
->nand
.numchips
;
1631 /* These functions are required by the NAND core framework, otherwise,
1632 * the NAND core will assert. However, we don't need them, so we'll stub
1634 denali
->nand
.ecc
.calculate
= denali_ecc_calculate
;
1635 denali
->nand
.ecc
.correct
= denali_ecc_correct
;
1636 denali
->nand
.ecc
.hwctl
= denali_ecc_hwctl
;
1638 /* override the default read operations */
1639 denali
->nand
.ecc
.size
= ECC_SECTOR_SIZE
* denali
->devnum
;
1640 denali
->nand
.ecc
.read_page
= denali_read_page
;
1641 denali
->nand
.ecc
.read_page_raw
= denali_read_page_raw
;
1642 denali
->nand
.ecc
.write_page
= denali_write_page
;
1643 denali
->nand
.ecc
.write_page_raw
= denali_write_page_raw
;
1644 denali
->nand
.ecc
.read_oob
= denali_read_oob
;
1645 denali
->nand
.ecc
.write_oob
= denali_write_oob
;
1646 denali
->nand
.erase_cmd
= denali_erase
;
1648 if (nand_scan_tail(&denali
->mtd
)) {
1650 goto failed_req_irq
;
1653 ret
= add_mtd_device(&denali
->mtd
);
1655 dev_err(&dev
->dev
, "Spectra: Failed to register MTD: %d\n",
1657 goto failed_req_irq
;
1662 denali_irq_cleanup(dev
->irq
, denali
);
1664 iounmap(denali
->flash_mem
);
1666 iounmap(denali
->flash_reg
);
1668 pci_release_regions(dev
);
1670 pci_unmap_single(dev
, denali
->buf
.dma_buf
, DENALI_BUF_SIZE
,
1671 PCI_DMA_BIDIRECTIONAL
);
1673 pci_disable_device(dev
);
1674 failed_alloc_memery
:
1679 /* driver exit point */
1680 static void denali_pci_remove(struct pci_dev
*dev
)
1682 struct denali_nand_info
*denali
= pci_get_drvdata(dev
);
1684 nand_release(&denali
->mtd
);
1685 del_mtd_device(&denali
->mtd
);
1687 denali_irq_cleanup(dev
->irq
, denali
);
1689 iounmap(denali
->flash_reg
);
1690 iounmap(denali
->flash_mem
);
1691 pci_release_regions(dev
);
1692 pci_disable_device(dev
);
1693 pci_unmap_single(dev
, denali
->buf
.dma_buf
, DENALI_BUF_SIZE
,
1694 PCI_DMA_BIDIRECTIONAL
);
1695 pci_set_drvdata(dev
, NULL
);
1699 MODULE_DEVICE_TABLE(pci
, denali_pci_ids
);
1701 static struct pci_driver denali_pci_driver
= {
1702 .name
= DENALI_NAND_NAME
,
1703 .id_table
= denali_pci_ids
,
1704 .probe
= denali_pci_probe
,
1705 .remove
= denali_pci_remove
,
1708 static int __devinit
denali_init(void)
1710 printk(KERN_INFO
"Spectra MTD driver built on %s @ %s\n",
1711 __DATE__
, __TIME__
);
1712 return pci_register_driver(&denali_pci_driver
);
1716 static void __devexit
denali_exit(void)
1718 pci_unregister_driver(&denali_pci_driver
);
1721 module_init(denali_init
);
1722 module_exit(denali_exit
);