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mtd: denali: Remove unuseful code in get_xx_nand_para functions
[deliverable/linux.git] / drivers / mtd / nand / denali.c
1 /*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/slab.h>
25 #include <linux/pci.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/module.h>
28
29 #include "denali.h"
30
31 MODULE_LICENSE("GPL");
32
33 /* We define a module parameter that allows the user to override
34 * the hardware and decide what timing mode should be used.
35 */
36 #define NAND_DEFAULT_TIMINGS -1
37
38 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39 module_param(onfi_timing_mode, int, S_IRUGO);
40 MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
41 " -1 indicates use default timings");
42
43 #define DENALI_NAND_NAME "denali-nand"
44
45 /* We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience. */
47 #define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \
48 INTR_STATUS0__ECC_TRANSACTION_DONE | \
49 INTR_STATUS0__ECC_ERR | \
50 INTR_STATUS0__PROGRAM_FAIL | \
51 INTR_STATUS0__LOAD_COMP | \
52 INTR_STATUS0__PROGRAM_COMP | \
53 INTR_STATUS0__TIME_OUT | \
54 INTR_STATUS0__ERASE_FAIL | \
55 INTR_STATUS0__RST_COMP | \
56 INTR_STATUS0__ERASE_COMP)
57
58 /* indicates whether or not the internal value for the flash bank is
59 valid or not */
60 #define CHIP_SELECT_INVALID -1
61
62 #define SUPPORT_8BITECC 1
63
64 /* This macro divides two integers and rounds fractional values up
65 * to the nearest integer value. */
66 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
67
68 /* this macro allows us to convert from an MTD structure to our own
69 * device context (denali) structure.
70 */
71 #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
72
73 /* These constants are defined by the driver to enable common driver
74 configuration options. */
75 #define SPARE_ACCESS 0x41
76 #define MAIN_ACCESS 0x42
77 #define MAIN_SPARE_ACCESS 0x43
78
79 #define DENALI_READ 0
80 #define DENALI_WRITE 0x100
81
82 /* types of device accesses. We can issue commands and get status */
83 #define COMMAND_CYCLE 0
84 #define ADDR_CYCLE 1
85 #define STATUS_CYCLE 2
86
87 /* this is a helper macro that allows us to
88 * format the bank into the proper bits for the controller */
89 #define BANK(x) ((x) << 24)
90
91 /* List of platforms this NAND controller has be integrated into */
92 static const struct pci_device_id denali_pci_ids[] = {
93 { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
94 { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
95 { /* end: all zeroes */ }
96 };
97
98
99 /* these are static lookup tables that give us easy access to
100 registers in the NAND controller.
101 */
102 static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
103 INTR_STATUS1,
104 INTR_STATUS2,
105 INTR_STATUS3};
106
107 static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
108 DEVICE_RESET__BANK1,
109 DEVICE_RESET__BANK2,
110 DEVICE_RESET__BANK3};
111
112 static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
113 INTR_STATUS1__TIME_OUT,
114 INTR_STATUS2__TIME_OUT,
115 INTR_STATUS3__TIME_OUT};
116
117 static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
118 INTR_STATUS1__RST_COMP,
119 INTR_STATUS2__RST_COMP,
120 INTR_STATUS3__RST_COMP};
121
122 /* specifies the debug level of the driver */
123 static int nand_debug_level;
124
125 /* forward declarations */
126 static void clear_interrupts(struct denali_nand_info *denali);
127 static uint32_t wait_for_irq(struct denali_nand_info *denali,
128 uint32_t irq_mask);
129 static void denali_irq_enable(struct denali_nand_info *denali,
130 uint32_t int_mask);
131 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
132
133 #define DEBUG_DENALI 0
134
135 /* This is a wrapper for writing to the denali registers.
136 * this allows us to create debug information so we can
137 * observe how the driver is programming the device.
138 * it uses standard linux convention for (val, addr) */
139 static void denali_write32(uint32_t value, void *addr)
140 {
141 iowrite32(value, addr);
142
143 #if DEBUG_DENALI
144 printk(KERN_INFO "wrote: 0x%x -> 0x%x\n", value,
145 (uint32_t)((uint32_t)addr & 0x1fff));
146 #endif
147 }
148
149 /* Certain operations for the denali NAND controller use
150 * an indexed mode to read/write data. The operation is
151 * performed by writing the address value of the command
152 * to the device memory followed by the data. This function
153 * abstracts this common operation.
154 */
155 static void index_addr(struct denali_nand_info *denali,
156 uint32_t address, uint32_t data)
157 {
158 denali_write32(address, denali->flash_mem);
159 denali_write32(data, denali->flash_mem + 0x10);
160 }
161
162 /* Perform an indexed read of the device */
163 static void index_addr_read_data(struct denali_nand_info *denali,
164 uint32_t address, uint32_t *pdata)
165 {
166 denali_write32(address, denali->flash_mem);
167 *pdata = ioread32(denali->flash_mem + 0x10);
168 }
169
170 /* We need to buffer some data for some of the NAND core routines.
171 * The operations manage buffering that data. */
172 static void reset_buf(struct denali_nand_info *denali)
173 {
174 denali->buf.head = denali->buf.tail = 0;
175 }
176
177 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
178 {
179 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
180 denali->buf.buf[denali->buf.tail++] = byte;
181 }
182
183 /* reads the status of the device */
184 static void read_status(struct denali_nand_info *denali)
185 {
186 uint32_t cmd = 0x0;
187
188 /* initialize the data buffer to store status */
189 reset_buf(denali);
190
191 /* initiate a device status read */
192 cmd = MODE_11 | BANK(denali->flash_bank);
193 index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
194 denali_write32(cmd | STATUS_CYCLE, denali->flash_mem);
195
196 /* update buffer with status value */
197 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
198
199 #if DEBUG_DENALI
200 printk(KERN_INFO "device reporting status value of 0x%2x\n",
201 denali->buf.buf[0]);
202 #endif
203 }
204
205 /* resets a specific device connected to the core */
206 static void reset_bank(struct denali_nand_info *denali)
207 {
208 uint32_t irq_status = 0;
209 uint32_t irq_mask = reset_complete[denali->flash_bank] |
210 operation_timeout[denali->flash_bank];
211 int bank = 0;
212
213 clear_interrupts(denali);
214
215 bank = device_reset_banks[denali->flash_bank];
216 denali_write32(bank, denali->flash_reg + DEVICE_RESET);
217
218 irq_status = wait_for_irq(denali, irq_mask);
219
220 if (irq_status & operation_timeout[denali->flash_bank])
221 printk(KERN_ERR "reset bank failed.\n");
222 }
223
224 /* Reset the flash controller */
225 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
226 {
227 uint32_t i;
228
229 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
230 __FILE__, __LINE__, __func__);
231
232 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
233 denali_write32(reset_complete[i] | operation_timeout[i],
234 denali->flash_reg + intr_status_addresses[i]);
235
236 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
237 denali_write32(device_reset_banks[i],
238 denali->flash_reg + DEVICE_RESET);
239 while (!(ioread32(denali->flash_reg +
240 intr_status_addresses[i]) &
241 (reset_complete[i] | operation_timeout[i])))
242 ;
243 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
244 operation_timeout[i])
245 nand_dbg_print(NAND_DBG_WARN,
246 "NAND Reset operation timed out on bank %d\n", i);
247 }
248
249 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
250 denali_write32(reset_complete[i] | operation_timeout[i],
251 denali->flash_reg + intr_status_addresses[i]);
252
253 return PASS;
254 }
255
256 /* this routine calculates the ONFI timing values for a given mode and
257 * programs the clocking register accordingly. The mode is determined by
258 * the get_onfi_nand_para routine.
259 */
260 static void nand_onfi_timing_set(struct denali_nand_info *denali,
261 uint16_t mode)
262 {
263 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
264 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
265 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
266 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
267 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
268 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
269 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
270 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
271 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
272 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
273 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
274 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
275
276 uint16_t TclsRising = 1;
277 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
278 uint16_t dv_window = 0;
279 uint16_t en_lo, en_hi;
280 uint16_t acc_clks;
281 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
282
283 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
284 __FILE__, __LINE__, __func__);
285
286 en_lo = CEIL_DIV(Trp[mode], CLK_X);
287 en_hi = CEIL_DIV(Treh[mode], CLK_X);
288 #if ONFI_BLOOM_TIME
289 if ((en_hi * CLK_X) < (Treh[mode] + 2))
290 en_hi++;
291 #endif
292
293 if ((en_lo + en_hi) * CLK_X < Trc[mode])
294 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
295
296 if ((en_lo + en_hi) < CLK_MULTI)
297 en_lo += CLK_MULTI - en_lo - en_hi;
298
299 while (dv_window < 8) {
300 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
301
302 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
303
304 data_invalid =
305 data_invalid_rhoh <
306 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
307
308 dv_window = data_invalid - Trea[mode];
309
310 if (dv_window < 8)
311 en_lo++;
312 }
313
314 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
315
316 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
317 acc_clks++;
318
319 if ((data_invalid - acc_clks * CLK_X) < 2)
320 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n",
321 __FILE__, __LINE__);
322
323 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
324 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
325 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
326 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
327 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
328 if (!TclsRising)
329 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
330 if (cs_cnt == 0)
331 cs_cnt = 1;
332
333 if (Tcea[mode]) {
334 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
335 cs_cnt++;
336 }
337
338 #if MODE5_WORKAROUND
339 if (mode == 5)
340 acc_clks = 5;
341 #endif
342
343 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
344 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
345 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
346 acc_clks = 6;
347
348 denali_write32(acc_clks, denali->flash_reg + ACC_CLKS);
349 denali_write32(re_2_we, denali->flash_reg + RE_2_WE);
350 denali_write32(re_2_re, denali->flash_reg + RE_2_RE);
351 denali_write32(we_2_re, denali->flash_reg + WE_2_RE);
352 denali_write32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
353 denali_write32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
354 denali_write32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
355 denali_write32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
356 }
357
358 /* configures the initial ECC settings for the controller */
359 static void set_ecc_config(struct denali_nand_info *denali)
360 {
361 #if SUPPORT_8BITECC
362 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) < 4096) ||
363 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) <= 128))
364 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
365 #endif
366
367 }
368
369 /* queries the NAND device to see what ONFI modes it supports. */
370 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
371 {
372 int i;
373 /* we needn't to do a reset here because driver has already
374 * reset all the banks before
375 * */
376 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
377 ONFI_TIMING_MODE__VALUE))
378 return FAIL;
379
380 for (i = 5; i > 0; i--) {
381 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
382 (0x01 << i))
383 break;
384 }
385
386 nand_onfi_timing_set(denali, i);
387
388 /* By now, all the ONFI devices we know support the page cache */
389 /* rw feature. So here we enable the pipeline_rw_ahead feature */
390 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
391 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
392
393 return PASS;
394 }
395
396 static void get_samsung_nand_para(struct denali_nand_info *denali,
397 uint8_t device_id)
398 {
399 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
400 /* Set timing register values according to datasheet */
401 denali_write32(5, denali->flash_reg + ACC_CLKS);
402 denali_write32(20, denali->flash_reg + RE_2_WE);
403 denali_write32(12, denali->flash_reg + WE_2_RE);
404 denali_write32(14, denali->flash_reg + ADDR_2_DATA);
405 denali_write32(3, denali->flash_reg + RDWR_EN_LO_CNT);
406 denali_write32(2, denali->flash_reg + RDWR_EN_HI_CNT);
407 denali_write32(2, denali->flash_reg + CS_SETUP_CNT);
408 }
409 }
410
411 static void get_toshiba_nand_para(struct denali_nand_info *denali)
412 {
413 uint32_t tmp;
414
415 /* Workaround to fix a controller bug which reports a wrong */
416 /* spare area size for some kind of Toshiba NAND device */
417 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
418 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
419 denali_write32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
420 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
421 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
422 denali_write32(tmp,
423 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
424 #if SUPPORT_15BITECC
425 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
426 #elif SUPPORT_8BITECC
427 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
428 #endif
429 }
430 }
431
432 static void get_hynix_nand_para(struct denali_nand_info *denali,
433 uint8_t device_id)
434 {
435 uint32_t main_size, spare_size;
436
437 switch (device_id) {
438 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
439 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
440 denali_write32(128, denali->flash_reg + PAGES_PER_BLOCK);
441 denali_write32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
442 denali_write32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
443 main_size = 4096 *
444 ioread32(denali->flash_reg + DEVICES_CONNECTED);
445 spare_size = 224 *
446 ioread32(denali->flash_reg + DEVICES_CONNECTED);
447 denali_write32(main_size,
448 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
449 denali_write32(spare_size,
450 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
451 denali_write32(0, denali->flash_reg + DEVICE_WIDTH);
452 #if SUPPORT_15BITECC
453 denali_write32(15, denali->flash_reg + ECC_CORRECTION);
454 #elif SUPPORT_8BITECC
455 denali_write32(8, denali->flash_reg + ECC_CORRECTION);
456 #endif
457 break;
458 default:
459 nand_dbg_print(NAND_DBG_WARN,
460 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
461 "Will use default parameter values instead.\n",
462 device_id);
463 }
464 }
465
466 /* determines how many NAND chips are connected to the controller. Note for
467 Intel CE4100 devices we don't support more than one device.
468 */
469 static void find_valid_banks(struct denali_nand_info *denali)
470 {
471 uint32_t id[LLD_MAX_FLASH_BANKS];
472 int i;
473
474 denali->total_used_banks = 1;
475 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
476 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
477 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
478 index_addr_read_data(denali,
479 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
480
481 nand_dbg_print(NAND_DBG_DEBUG,
482 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
483
484 if (i == 0) {
485 if (!(id[i] & 0x0ff))
486 break; /* WTF? */
487 } else {
488 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
489 denali->total_used_banks++;
490 else
491 break;
492 }
493 }
494
495 if (denali->platform == INTEL_CE4100) {
496 /* Platform limitations of the CE4100 device limit
497 * users to a single chip solution for NAND.
498 * Multichip support is not enabled.
499 */
500 if (denali->total_used_banks != 1) {
501 printk(KERN_ERR "Sorry, Intel CE4100 only supports "
502 "a single NAND device.\n");
503 BUG();
504 }
505 }
506 nand_dbg_print(NAND_DBG_DEBUG,
507 "denali->total_used_banks: %d\n", denali->total_used_banks);
508 }
509
510 static void detect_partition_feature(struct denali_nand_info *denali)
511 {
512 /* For MRST platform, denali->fwblks represent the
513 * number of blocks firmware is taken,
514 * FW is in protect partition and MTD driver has no
515 * permission to access it. So let driver know how many
516 * blocks it can't touch.
517 * */
518 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
519 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
520 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
521 denali->fwblks =
522 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
523 MIN_MAX_BANK_1__MIN_VALUE) *
524 denali->blksperchip)
525 +
526 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
527 MIN_BLK_ADDR_1__VALUE);
528 } else
529 denali->fwblks = SPECTRA_START_BLOCK;
530 } else
531 denali->fwblks = SPECTRA_START_BLOCK;
532 }
533
534 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
535 {
536 uint16_t status = PASS;
537 uint32_t id_bytes[5], addr;
538 uint8_t i, maf_id, device_id;
539
540 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
541 __FILE__, __LINE__, __func__);
542
543 /* Use read id method to get device ID and other
544 * params. For some NAND chips, controller can't
545 * report the correct device ID by reading from
546 * DEVICE_ID register
547 * */
548 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
549 index_addr(denali, (uint32_t)addr | 0, 0x90);
550 index_addr(denali, (uint32_t)addr | 1, 0);
551 for (i = 0; i < 5; i++)
552 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
553 maf_id = id_bytes[0];
554 device_id = id_bytes[1];
555
556 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
557 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
558 if (FAIL == get_onfi_nand_para(denali))
559 return FAIL;
560 } else if (maf_id == 0xEC) { /* Samsung NAND */
561 get_samsung_nand_para(denali, device_id);
562 } else if (maf_id == 0x98) { /* Toshiba NAND */
563 get_toshiba_nand_para(denali);
564 } else if (maf_id == 0xAD) { /* Hynix NAND */
565 get_hynix_nand_para(denali, device_id);
566 }
567
568 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
569 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
570 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
571 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
572 ioread32(denali->flash_reg + ACC_CLKS),
573 ioread32(denali->flash_reg + RE_2_WE),
574 ioread32(denali->flash_reg + WE_2_RE),
575 ioread32(denali->flash_reg + ADDR_2_DATA),
576 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
577 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
578 ioread32(denali->flash_reg + CS_SETUP_CNT));
579
580 set_ecc_config(denali);
581
582 find_valid_banks(denali);
583
584 detect_partition_feature(denali);
585
586 /* If the user specified to override the default timings
587 * with a specific ONFI mode, we apply those changes here.
588 */
589 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
590 nand_onfi_timing_set(denali, onfi_timing_mode);
591
592 return status;
593 }
594
595 static void denali_set_intr_modes(struct denali_nand_info *denali,
596 uint16_t INT_ENABLE)
597 {
598 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
599 __FILE__, __LINE__, __func__);
600
601 if (INT_ENABLE)
602 denali_write32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
603 else
604 denali_write32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
605 }
606
607 /* validation function to verify that the controlling software is making
608 a valid request
609 */
610 static inline bool is_flash_bank_valid(int flash_bank)
611 {
612 return (flash_bank >= 0 && flash_bank < 4);
613 }
614
615 static void denali_irq_init(struct denali_nand_info *denali)
616 {
617 uint32_t int_mask = 0;
618
619 /* Disable global interrupts */
620 denali_set_intr_modes(denali, false);
621
622 int_mask = DENALI_IRQ_ALL;
623
624 /* Clear all status bits */
625 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS0);
626 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS1);
627 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS2);
628 denali_write32(0xFFFF, denali->flash_reg + INTR_STATUS3);
629
630 denali_irq_enable(denali, int_mask);
631 }
632
633 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
634 {
635 denali_set_intr_modes(denali, false);
636 free_irq(irqnum, denali);
637 }
638
639 static void denali_irq_enable(struct denali_nand_info *denali,
640 uint32_t int_mask)
641 {
642 denali_write32(int_mask, denali->flash_reg + INTR_EN0);
643 denali_write32(int_mask, denali->flash_reg + INTR_EN1);
644 denali_write32(int_mask, denali->flash_reg + INTR_EN2);
645 denali_write32(int_mask, denali->flash_reg + INTR_EN3);
646 }
647
648 /* This function only returns when an interrupt that this driver cares about
649 * occurs. This is to reduce the overhead of servicing interrupts
650 */
651 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
652 {
653 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
654 }
655
656 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
657 static inline void clear_interrupt(struct denali_nand_info *denali,
658 uint32_t irq_mask)
659 {
660 uint32_t intr_status_reg = 0;
661
662 intr_status_reg = intr_status_addresses[denali->flash_bank];
663
664 denali_write32(irq_mask, denali->flash_reg + intr_status_reg);
665 }
666
667 static void clear_interrupts(struct denali_nand_info *denali)
668 {
669 uint32_t status = 0x0;
670 spin_lock_irq(&denali->irq_lock);
671
672 status = read_interrupt_status(denali);
673
674 #if DEBUG_DENALI
675 denali->irq_debug_array[denali->idx++] = 0x30000000 | status;
676 denali->idx %= 32;
677 #endif
678
679 denali->irq_status = 0x0;
680 spin_unlock_irq(&denali->irq_lock);
681 }
682
683 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
684 {
685 uint32_t intr_status_reg = 0;
686
687 intr_status_reg = intr_status_addresses[denali->flash_bank];
688
689 return ioread32(denali->flash_reg + intr_status_reg);
690 }
691
692 #if DEBUG_DENALI
693 static void print_irq_log(struct denali_nand_info *denali)
694 {
695 int i = 0;
696
697 printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
698 for (i = 0; i < 32; i++)
699 printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
700 }
701 #endif
702
703 /* This is the interrupt service routine. It handles all interrupts
704 * sent to this device. Note that on CE4100, this is a shared
705 * interrupt.
706 */
707 static irqreturn_t denali_isr(int irq, void *dev_id)
708 {
709 struct denali_nand_info *denali = dev_id;
710 uint32_t irq_status = 0x0;
711 irqreturn_t result = IRQ_NONE;
712
713 spin_lock(&denali->irq_lock);
714
715 /* check to see if a valid NAND chip has
716 * been selected.
717 */
718 if (is_flash_bank_valid(denali->flash_bank)) {
719 /* check to see if controller generated
720 * the interrupt, since this is a shared interrupt */
721 irq_status = denali_irq_detected(denali);
722 if (irq_status != 0) {
723 #if DEBUG_DENALI
724 denali->irq_debug_array[denali->idx++] =
725 0x10000000 | irq_status;
726 denali->idx %= 32;
727
728 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
729 #endif
730 /* handle interrupt */
731 /* first acknowledge it */
732 clear_interrupt(denali, irq_status);
733 /* store the status in the device context for someone
734 to read */
735 denali->irq_status |= irq_status;
736 /* notify anyone who cares that it happened */
737 complete(&denali->complete);
738 /* tell the OS that we've handled this */
739 result = IRQ_HANDLED;
740 }
741 }
742 spin_unlock(&denali->irq_lock);
743 return result;
744 }
745 #define BANK(x) ((x) << 24)
746
747 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
748 {
749 unsigned long comp_res = 0;
750 uint32_t intr_status = 0;
751 bool retry = false;
752 unsigned long timeout = msecs_to_jiffies(1000);
753
754 do {
755 #if DEBUG_DENALI
756 printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
757 #endif
758 comp_res =
759 wait_for_completion_timeout(&denali->complete, timeout);
760 spin_lock_irq(&denali->irq_lock);
761 intr_status = denali->irq_status;
762
763 #if DEBUG_DENALI
764 denali->irq_debug_array[denali->idx++] =
765 0x20000000 | (irq_mask << 16) | intr_status;
766 denali->idx %= 32;
767 #endif
768
769 if (intr_status & irq_mask) {
770 denali->irq_status &= ~irq_mask;
771 spin_unlock_irq(&denali->irq_lock);
772 #if DEBUG_DENALI
773 if (retry)
774 printk(KERN_INFO "status on retry = 0x%x\n",
775 intr_status);
776 #endif
777 /* our interrupt was detected */
778 break;
779 } else {
780 /* these are not the interrupts you are looking for -
781 * need to wait again */
782 spin_unlock_irq(&denali->irq_lock);
783 #if DEBUG_DENALI
784 print_irq_log(denali);
785 printk(KERN_INFO "received irq nobody cared:"
786 " irq_status = 0x%x, irq_mask = 0x%x,"
787 " timeout = %ld\n", intr_status,
788 irq_mask, comp_res);
789 #endif
790 retry = true;
791 }
792 } while (comp_res != 0);
793
794 if (comp_res == 0) {
795 /* timeout */
796 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
797 intr_status, irq_mask);
798
799 intr_status = 0;
800 }
801 return intr_status;
802 }
803
804 /* This helper function setups the registers for ECC and whether or not
805 the spare area will be transfered. */
806 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
807 bool transfer_spare)
808 {
809 int ecc_en_flag = 0, transfer_spare_flag = 0;
810
811 /* set ECC, transfer spare bits if needed */
812 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
813 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
814
815 /* Enable spare area/ECC per user's request. */
816 denali_write32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
817 denali_write32(transfer_spare_flag,
818 denali->flash_reg + TRANSFER_SPARE_REG);
819 }
820
821 /* sends a pipeline command operation to the controller. See the Denali NAND
822 controller's user guide for more information (section 4.2.3.6).
823 */
824 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
825 bool ecc_en,
826 bool transfer_spare,
827 int access_type,
828 int op)
829 {
830 int status = PASS;
831 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
832 irq_mask = 0;
833
834 if (op == DENALI_READ)
835 irq_mask = INTR_STATUS0__LOAD_COMP;
836 else if (op == DENALI_WRITE)
837 irq_mask = 0;
838 else
839 BUG();
840
841 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
842
843 #if DEBUG_DENALI
844 spin_lock_irq(&denali->irq_lock);
845 denali->irq_debug_array[denali->idx++] =
846 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
847 (access_type << 4);
848 denali->idx %= 32;
849 spin_unlock_irq(&denali->irq_lock);
850 #endif
851
852
853 /* clear interrupts */
854 clear_interrupts(denali);
855
856 addr = BANK(denali->flash_bank) | denali->page;
857
858 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
859 cmd = MODE_01 | addr;
860 denali_write32(cmd, denali->flash_mem);
861 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
862 /* read spare area */
863 cmd = MODE_10 | addr;
864 index_addr(denali, (uint32_t)cmd, access_type);
865
866 cmd = MODE_01 | addr;
867 denali_write32(cmd, denali->flash_mem);
868 } else if (op == DENALI_READ) {
869 /* setup page read request for access type */
870 cmd = MODE_10 | addr;
871 index_addr(denali, (uint32_t)cmd, access_type);
872
873 /* page 33 of the NAND controller spec indicates we should not
874 use the pipeline commands in Spare area only mode. So we
875 don't.
876 */
877 if (access_type == SPARE_ACCESS) {
878 cmd = MODE_01 | addr;
879 denali_write32(cmd, denali->flash_mem);
880 } else {
881 index_addr(denali, (uint32_t)cmd,
882 0x2000 | op | page_count);
883
884 /* wait for command to be accepted
885 * can always use status0 bit as the
886 * mask is identical for each
887 * bank. */
888 irq_status = wait_for_irq(denali, irq_mask);
889
890 if (irq_status == 0) {
891 printk(KERN_ERR "cmd, page, addr on timeout "
892 "(0x%x, 0x%x, 0x%x)\n", cmd,
893 denali->page, addr);
894 status = FAIL;
895 } else {
896 cmd = MODE_01 | addr;
897 denali_write32(cmd, denali->flash_mem);
898 }
899 }
900 }
901 return status;
902 }
903
904 /* helper function that simply writes a buffer to the flash */
905 static int write_data_to_flash_mem(struct denali_nand_info *denali,
906 const uint8_t *buf,
907 int len)
908 {
909 uint32_t i = 0, *buf32;
910
911 /* verify that the len is a multiple of 4. see comment in
912 * read_data_from_flash_mem() */
913 BUG_ON((len % 4) != 0);
914
915 /* write the data to the flash memory */
916 buf32 = (uint32_t *)buf;
917 for (i = 0; i < len / 4; i++)
918 denali_write32(*buf32++, denali->flash_mem + 0x10);
919 return i*4; /* intent is to return the number of bytes read */
920 }
921
922 /* helper function that simply reads a buffer from the flash */
923 static int read_data_from_flash_mem(struct denali_nand_info *denali,
924 uint8_t *buf,
925 int len)
926 {
927 uint32_t i = 0, *buf32;
928
929 /* we assume that len will be a multiple of 4, if not
930 * it would be nice to know about it ASAP rather than
931 * have random failures...
932 * This assumption is based on the fact that this
933 * function is designed to be used to read flash pages,
934 * which are typically multiples of 4...
935 */
936
937 BUG_ON((len % 4) != 0);
938
939 /* transfer the data from the flash */
940 buf32 = (uint32_t *)buf;
941 for (i = 0; i < len / 4; i++)
942 *buf32++ = ioread32(denali->flash_mem + 0x10);
943 return i*4; /* intent is to return the number of bytes read */
944 }
945
946 /* writes OOB data to the device */
947 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
948 {
949 struct denali_nand_info *denali = mtd_to_denali(mtd);
950 uint32_t irq_status = 0;
951 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
952 INTR_STATUS0__PROGRAM_FAIL;
953 int status = 0;
954
955 denali->page = page;
956
957 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
958 DENALI_WRITE) == PASS) {
959 write_data_to_flash_mem(denali, buf, mtd->oobsize);
960
961 #if DEBUG_DENALI
962 spin_lock_irq(&denali->irq_lock);
963 denali->irq_debug_array[denali->idx++] =
964 0x80000000 | mtd->oobsize;
965 denali->idx %= 32;
966 spin_unlock_irq(&denali->irq_lock);
967 #endif
968
969
970 /* wait for operation to complete */
971 irq_status = wait_for_irq(denali, irq_mask);
972
973 if (irq_status == 0) {
974 printk(KERN_ERR "OOB write failed\n");
975 status = -EIO;
976 }
977 } else {
978 printk(KERN_ERR "unable to send pipeline command\n");
979 status = -EIO;
980 }
981 return status;
982 }
983
984 /* reads OOB data from the device */
985 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
986 {
987 struct denali_nand_info *denali = mtd_to_denali(mtd);
988 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
989 irq_status = 0, addr = 0x0, cmd = 0x0;
990
991 denali->page = page;
992
993 #if DEBUG_DENALI
994 printk(KERN_INFO "read_oob %d\n", page);
995 #endif
996 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
997 DENALI_READ) == PASS) {
998 read_data_from_flash_mem(denali, buf, mtd->oobsize);
999
1000 /* wait for command to be accepted
1001 * can always use status0 bit as the mask is identical for each
1002 * bank. */
1003 irq_status = wait_for_irq(denali, irq_mask);
1004
1005 if (irq_status == 0)
1006 printk(KERN_ERR "page on OOB timeout %d\n",
1007 denali->page);
1008
1009 /* We set the device back to MAIN_ACCESS here as I observed
1010 * instability with the controller if you do a block erase
1011 * and the last transaction was a SPARE_ACCESS. Block erase
1012 * is reliable (according to the MTD test infrastructure)
1013 * if you are in MAIN_ACCESS.
1014 */
1015 addr = BANK(denali->flash_bank) | denali->page;
1016 cmd = MODE_10 | addr;
1017 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
1018
1019 #if DEBUG_DENALI
1020 spin_lock_irq(&denali->irq_lock);
1021 denali->irq_debug_array[denali->idx++] =
1022 0x60000000 | mtd->oobsize;
1023 denali->idx %= 32;
1024 spin_unlock_irq(&denali->irq_lock);
1025 #endif
1026 }
1027 }
1028
1029 /* this function examines buffers to see if they contain data that
1030 * indicate that the buffer is part of an erased region of flash.
1031 */
1032 bool is_erased(uint8_t *buf, int len)
1033 {
1034 int i = 0;
1035 for (i = 0; i < len; i++)
1036 if (buf[i] != 0xFF)
1037 return false;
1038 return true;
1039 }
1040 #define ECC_SECTOR_SIZE 512
1041
1042 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
1043 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
1044 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
1045 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO))
1046 #define ECC_ERR_DEVICE(x) ((x) & ERR_CORRECTION_INFO__DEVICE_NR >> 8)
1047 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
1048
1049 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1050 uint8_t *oobbuf, uint32_t irq_status)
1051 {
1052 bool check_erased_page = false;
1053
1054 if (irq_status & INTR_STATUS0__ECC_ERR) {
1055 /* read the ECC errors. we'll ignore them for now */
1056 uint32_t err_address = 0, err_correction_info = 0;
1057 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
1058 uint32_t err_correction_value = 0;
1059
1060 do {
1061 err_address = ioread32(denali->flash_reg +
1062 ECC_ERROR_ADDRESS);
1063 err_sector = ECC_SECTOR(err_address);
1064 err_byte = ECC_BYTE(err_address);
1065
1066
1067 err_correction_info = ioread32(denali->flash_reg +
1068 ERR_CORRECTION_INFO);
1069 err_correction_value =
1070 ECC_CORRECTION_VALUE(err_correction_info);
1071 err_device = ECC_ERR_DEVICE(err_correction_info);
1072
1073 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
1074 /* offset in our buffer is computed as:
1075 sector number * sector size + offset in
1076 sector
1077 */
1078 int offset = err_sector * ECC_SECTOR_SIZE +
1079 err_byte;
1080 if (offset < denali->mtd.writesize) {
1081 /* correct the ECC error */
1082 buf[offset] ^= err_correction_value;
1083 denali->mtd.ecc_stats.corrected++;
1084 } else {
1085 /* bummer, couldn't correct the error */
1086 printk(KERN_ERR "ECC offset invalid\n");
1087 denali->mtd.ecc_stats.failed++;
1088 }
1089 } else {
1090 /* if the error is not correctable, need to
1091 * look at the page to see if it is an erased
1092 * page. if so, then it's not a real ECC error
1093 * */
1094 check_erased_page = true;
1095 }
1096
1097 #if DEBUG_DENALI
1098 printk(KERN_INFO "Detected ECC error in page %d:"
1099 " err_addr = 0x%08x, info to fix is"
1100 " 0x%08x\n", denali->page, err_address,
1101 err_correction_info);
1102 #endif
1103 } while (!ECC_LAST_ERR(err_correction_info));
1104 }
1105 return check_erased_page;
1106 }
1107
1108 /* programs the controller to either enable/disable DMA transfers */
1109 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1110 {
1111 uint32_t reg_val = 0x0;
1112
1113 if (en)
1114 reg_val = DMA_ENABLE__FLAG;
1115
1116 denali_write32(reg_val, denali->flash_reg + DMA_ENABLE);
1117 ioread32(denali->flash_reg + DMA_ENABLE);
1118 }
1119
1120 /* setups the HW to perform the data DMA */
1121 static void denali_setup_dma(struct denali_nand_info *denali, int op)
1122 {
1123 uint32_t mode = 0x0;
1124 const int page_count = 1;
1125 dma_addr_t addr = denali->buf.dma_buf;
1126
1127 mode = MODE_10 | BANK(denali->flash_bank);
1128
1129 /* DMA is a four step process */
1130
1131 /* 1. setup transfer type and # of pages */
1132 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1133
1134 /* 2. set memory high address bits 23:8 */
1135 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1136
1137 /* 3. set memory low address bits 23:8 */
1138 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1139
1140 /* 4. interrupt when complete, burst len = 64 bytes*/
1141 index_addr(denali, mode | 0x14000, 0x2400);
1142 }
1143
1144 /* writes a page. user specifies type, and this function handles the
1145 configuration details. */
1146 static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1147 const uint8_t *buf, bool raw_xfer)
1148 {
1149 struct denali_nand_info *denali = mtd_to_denali(mtd);
1150 struct pci_dev *pci_dev = denali->dev;
1151
1152 dma_addr_t addr = denali->buf.dma_buf;
1153 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1154
1155 uint32_t irq_status = 0;
1156 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
1157 INTR_STATUS0__PROGRAM_FAIL;
1158
1159 /* if it is a raw xfer, we want to disable ecc, and send
1160 * the spare area.
1161 * !raw_xfer - enable ecc
1162 * raw_xfer - transfer spare
1163 */
1164 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1165
1166 /* copy buffer into DMA buffer */
1167 memcpy(denali->buf.buf, buf, mtd->writesize);
1168
1169 if (raw_xfer) {
1170 /* transfer the data to the spare area */
1171 memcpy(denali->buf.buf + mtd->writesize,
1172 chip->oob_poi,
1173 mtd->oobsize);
1174 }
1175
1176 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1177
1178 clear_interrupts(denali);
1179 denali_enable_dma(denali, true);
1180
1181 denali_setup_dma(denali, DENALI_WRITE);
1182
1183 /* wait for operation to complete */
1184 irq_status = wait_for_irq(denali, irq_mask);
1185
1186 if (irq_status == 0) {
1187 printk(KERN_ERR "timeout on write_page"
1188 " (type = %d)\n", raw_xfer);
1189 denali->status =
1190 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1191 NAND_STATUS_FAIL : PASS;
1192 }
1193
1194 denali_enable_dma(denali, false);
1195 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1196 }
1197
1198 /* NAND core entry points */
1199
1200 /* this is the callback that the NAND core calls to write a page. Since
1201 writing a page with ECC or without is similar, all the work is done
1202 by write_page above. */
1203 static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1204 const uint8_t *buf)
1205 {
1206 /* for regular page writes, we let HW handle all the ECC
1207 * data written to the device. */
1208 write_page(mtd, chip, buf, false);
1209 }
1210
1211 /* This is the callback that the NAND core calls to write a page without ECC.
1212 raw access is similiar to ECC page writes, so all the work is done in the
1213 write_page() function above.
1214 */
1215 static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1216 const uint8_t *buf)
1217 {
1218 /* for raw page writes, we want to disable ECC and simply write
1219 whatever data is in the buffer. */
1220 write_page(mtd, chip, buf, true);
1221 }
1222
1223 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1224 int page)
1225 {
1226 return write_oob_data(mtd, chip->oob_poi, page);
1227 }
1228
1229 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1230 int page, int sndcmd)
1231 {
1232 read_oob_data(mtd, chip->oob_poi, page);
1233
1234 return 0; /* notify NAND core to send command to
1235 NAND device. */
1236 }
1237
1238 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1239 uint8_t *buf, int page)
1240 {
1241 struct denali_nand_info *denali = mtd_to_denali(mtd);
1242 struct pci_dev *pci_dev = denali->dev;
1243
1244 dma_addr_t addr = denali->buf.dma_buf;
1245 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1246
1247 uint32_t irq_status = 0;
1248 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
1249 INTR_STATUS0__ECC_ERR;
1250 bool check_erased_page = false;
1251
1252 setup_ecc_for_xfer(denali, true, false);
1253
1254 denali_enable_dma(denali, true);
1255 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1256
1257 clear_interrupts(denali);
1258 denali_setup_dma(denali, DENALI_READ);
1259
1260 /* wait for operation to complete */
1261 irq_status = wait_for_irq(denali, irq_mask);
1262
1263 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1264
1265 memcpy(buf, denali->buf.buf, mtd->writesize);
1266
1267 check_erased_page = handle_ecc(denali, buf, chip->oob_poi, irq_status);
1268 denali_enable_dma(denali, false);
1269
1270 if (check_erased_page) {
1271 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1272
1273 /* check ECC failures that may have occurred on erased pages */
1274 if (check_erased_page) {
1275 if (!is_erased(buf, denali->mtd.writesize))
1276 denali->mtd.ecc_stats.failed++;
1277 if (!is_erased(buf, denali->mtd.oobsize))
1278 denali->mtd.ecc_stats.failed++;
1279 }
1280 }
1281 return 0;
1282 }
1283
1284 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1285 uint8_t *buf, int page)
1286 {
1287 struct denali_nand_info *denali = mtd_to_denali(mtd);
1288 struct pci_dev *pci_dev = denali->dev;
1289
1290 dma_addr_t addr = denali->buf.dma_buf;
1291 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1292
1293 uint32_t irq_status = 0;
1294 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
1295
1296 setup_ecc_for_xfer(denali, false, true);
1297 denali_enable_dma(denali, true);
1298
1299 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1300
1301 clear_interrupts(denali);
1302 denali_setup_dma(denali, DENALI_READ);
1303
1304 /* wait for operation to complete */
1305 irq_status = wait_for_irq(denali, irq_mask);
1306
1307 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1308
1309 denali_enable_dma(denali, false);
1310
1311 memcpy(buf, denali->buf.buf, mtd->writesize);
1312 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1313
1314 return 0;
1315 }
1316
1317 static uint8_t denali_read_byte(struct mtd_info *mtd)
1318 {
1319 struct denali_nand_info *denali = mtd_to_denali(mtd);
1320 uint8_t result = 0xff;
1321
1322 if (denali->buf.head < denali->buf.tail)
1323 result = denali->buf.buf[denali->buf.head++];
1324
1325 #if DEBUG_DENALI
1326 printk(KERN_INFO "read byte -> 0x%02x\n", result);
1327 #endif
1328 return result;
1329 }
1330
1331 static void denali_select_chip(struct mtd_info *mtd, int chip)
1332 {
1333 struct denali_nand_info *denali = mtd_to_denali(mtd);
1334 #if DEBUG_DENALI
1335 printk(KERN_INFO "denali select chip %d\n", chip);
1336 #endif
1337 spin_lock_irq(&denali->irq_lock);
1338 denali->flash_bank = chip;
1339 spin_unlock_irq(&denali->irq_lock);
1340 }
1341
1342 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1343 {
1344 struct denali_nand_info *denali = mtd_to_denali(mtd);
1345 int status = denali->status;
1346 denali->status = 0;
1347
1348 #if DEBUG_DENALI
1349 printk(KERN_INFO "waitfunc %d\n", status);
1350 #endif
1351 return status;
1352 }
1353
1354 static void denali_erase(struct mtd_info *mtd, int page)
1355 {
1356 struct denali_nand_info *denali = mtd_to_denali(mtd);
1357
1358 uint32_t cmd = 0x0, irq_status = 0;
1359
1360 #if DEBUG_DENALI
1361 printk(KERN_INFO "erase page: %d\n", page);
1362 #endif
1363 /* clear interrupts */
1364 clear_interrupts(denali);
1365
1366 /* setup page read request for access type */
1367 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1368 index_addr(denali, (uint32_t)cmd, 0x1);
1369
1370 /* wait for erase to complete or failure to occur */
1371 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
1372 INTR_STATUS0__ERASE_FAIL);
1373
1374 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1375 NAND_STATUS_FAIL : PASS;
1376 }
1377
1378 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1379 int page)
1380 {
1381 struct denali_nand_info *denali = mtd_to_denali(mtd);
1382 uint32_t addr, id;
1383 int i;
1384
1385 #if DEBUG_DENALI
1386 printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
1387 #endif
1388 switch (cmd) {
1389 case NAND_CMD_PAGEPROG:
1390 break;
1391 case NAND_CMD_STATUS:
1392 read_status(denali);
1393 break;
1394 case NAND_CMD_READID:
1395 reset_buf(denali);
1396 /*sometimes ManufactureId read from register is not right
1397 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1398 * So here we send READID cmd to NAND insteand
1399 * */
1400 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1401 index_addr(denali, (uint32_t)addr | 0, 0x90);
1402 index_addr(denali, (uint32_t)addr | 1, 0);
1403 for (i = 0; i < 5; i++) {
1404 index_addr_read_data(denali,
1405 (uint32_t)addr | 2,
1406 &id);
1407 write_byte_to_buf(denali, id);
1408 }
1409 break;
1410 case NAND_CMD_READ0:
1411 case NAND_CMD_SEQIN:
1412 denali->page = page;
1413 break;
1414 case NAND_CMD_RESET:
1415 reset_bank(denali);
1416 break;
1417 case NAND_CMD_READOOB:
1418 /* TODO: Read OOB data */
1419 break;
1420 default:
1421 printk(KERN_ERR ": unsupported command"
1422 " received 0x%x\n", cmd);
1423 break;
1424 }
1425 }
1426
1427 /* stubs for ECC functions not used by the NAND core */
1428 static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1429 uint8_t *ecc_code)
1430 {
1431 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
1432 BUG();
1433 return -EIO;
1434 }
1435
1436 static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1437 uint8_t *read_ecc, uint8_t *calc_ecc)
1438 {
1439 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
1440 BUG();
1441 return -EIO;
1442 }
1443
1444 static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1445 {
1446 printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n");
1447 BUG();
1448 }
1449 /* end NAND core entry points */
1450
1451 /* Initialization code to bring the device up to a known good state */
1452 static void denali_hw_init(struct denali_nand_info *denali)
1453 {
1454 denali_irq_init(denali);
1455 denali_nand_reset(denali);
1456 denali_write32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1457 denali_write32(CHIP_EN_DONT_CARE__FLAG,
1458 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1459
1460 denali_write32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1461 denali_write32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1462
1463 /* Should set value for these registers when init */
1464 denali_write32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1465 denali_write32(1, denali->flash_reg + ECC_ENABLE);
1466 }
1467
1468 /* ECC layout for SLC devices. Denali spec indicates SLC fixed at 4 bytes */
1469 #define ECC_BYTES_SLC (4 * (2048 / ECC_SECTOR_SIZE))
1470 static struct nand_ecclayout nand_oob_slc = {
1471 .eccbytes = 4,
1472 .eccpos = { 0, 1, 2, 3 }, /* not used */
1473 .oobfree = {
1474 {
1475 .offset = ECC_BYTES_SLC,
1476 .length = 64 - ECC_BYTES_SLC
1477 }
1478 }
1479 };
1480
1481 #define ECC_BYTES_MLC (14 * (2048 / ECC_SECTOR_SIZE))
1482 static struct nand_ecclayout nand_oob_mlc_14bit = {
1483 .eccbytes = 14,
1484 .eccpos = { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13 }, /* not used */
1485 .oobfree = {
1486 {
1487 .offset = ECC_BYTES_MLC,
1488 .length = 64 - ECC_BYTES_MLC
1489 }
1490 }
1491 };
1492
1493 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1494 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1495
1496 static struct nand_bbt_descr bbt_main_descr = {
1497 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1498 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1499 .offs = 8,
1500 .len = 4,
1501 .veroffs = 12,
1502 .maxblocks = 4,
1503 .pattern = bbt_pattern,
1504 };
1505
1506 static struct nand_bbt_descr bbt_mirror_descr = {
1507 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1508 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1509 .offs = 8,
1510 .len = 4,
1511 .veroffs = 12,
1512 .maxblocks = 4,
1513 .pattern = mirror_pattern,
1514 };
1515
1516 /* initalize driver data structures */
1517 void denali_drv_init(struct denali_nand_info *denali)
1518 {
1519 denali->idx = 0;
1520
1521 /* setup interrupt handler */
1522 /* the completion object will be used to notify
1523 * the callee that the interrupt is done */
1524 init_completion(&denali->complete);
1525
1526 /* the spinlock will be used to synchronize the ISR
1527 * with any element that might be access shared
1528 * data (interrupt status) */
1529 spin_lock_init(&denali->irq_lock);
1530
1531 /* indicate that MTD has not selected a valid bank yet */
1532 denali->flash_bank = CHIP_SELECT_INVALID;
1533
1534 /* initialize our irq_status variable to indicate no interrupts */
1535 denali->irq_status = 0;
1536 }
1537
1538 /* driver entry point */
1539 static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1540 {
1541 int ret = -ENODEV;
1542 resource_size_t csr_base, mem_base;
1543 unsigned long csr_len, mem_len;
1544 struct denali_nand_info *denali;
1545
1546 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
1547 __FILE__, __LINE__, __func__);
1548
1549 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1550 if (!denali)
1551 return -ENOMEM;
1552
1553 ret = pci_enable_device(dev);
1554 if (ret) {
1555 printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
1556 goto failed_enable;
1557 }
1558
1559 if (id->driver_data == INTEL_CE4100) {
1560 /* Due to a silicon limitation, we can only support
1561 * ONFI timing mode 1 and below.
1562 */
1563 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1564 printk(KERN_ERR "Intel CE4100 only supports"
1565 " ONFI timing mode 1 or below\n");
1566 ret = -EINVAL;
1567 goto failed_enable;
1568 }
1569 denali->platform = INTEL_CE4100;
1570 mem_base = pci_resource_start(dev, 0);
1571 mem_len = pci_resource_len(dev, 1);
1572 csr_base = pci_resource_start(dev, 1);
1573 csr_len = pci_resource_len(dev, 1);
1574 } else {
1575 denali->platform = INTEL_MRST;
1576 csr_base = pci_resource_start(dev, 0);
1577 csr_len = pci_resource_start(dev, 0);
1578 mem_base = pci_resource_start(dev, 1);
1579 mem_len = pci_resource_len(dev, 1);
1580 if (!mem_len) {
1581 mem_base = csr_base + csr_len;
1582 mem_len = csr_len;
1583 nand_dbg_print(NAND_DBG_WARN,
1584 "Spectra: No second"
1585 " BAR for PCI device;"
1586 " assuming %08Lx\n",
1587 (uint64_t)csr_base);
1588 }
1589 }
1590
1591 /* Is 32-bit DMA supported? */
1592 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
1593
1594 if (ret) {
1595 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1596 goto failed_enable;
1597 }
1598 denali->buf.dma_buf =
1599 pci_map_single(dev, denali->buf.buf,
1600 DENALI_BUF_SIZE,
1601 PCI_DMA_BIDIRECTIONAL);
1602
1603 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
1604 printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
1605 goto failed_enable;
1606 }
1607
1608 pci_set_master(dev);
1609 denali->dev = dev;
1610
1611 ret = pci_request_regions(dev, DENALI_NAND_NAME);
1612 if (ret) {
1613 printk(KERN_ERR "Spectra: Unable to request memory regions\n");
1614 goto failed_req_csr;
1615 }
1616
1617 denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1618 if (!denali->flash_reg) {
1619 printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1620 ret = -ENOMEM;
1621 goto failed_remap_csr;
1622 }
1623 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
1624 (uint64_t)csr_base, denali->flash_reg, csr_len);
1625
1626 denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1627 if (!denali->flash_mem) {
1628 printk(KERN_ERR "Spectra: ioremap_nocache failed!");
1629 iounmap(denali->flash_reg);
1630 ret = -ENOMEM;
1631 goto failed_remap_csr;
1632 }
1633
1634 nand_dbg_print(NAND_DBG_WARN,
1635 "Spectra: Remapped flash base address: "
1636 "0x%p, len: %ld\n",
1637 denali->flash_mem, csr_len);
1638
1639 denali_hw_init(denali);
1640 denali_drv_init(denali);
1641
1642 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq);
1643 if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1644 DENALI_NAND_NAME, denali)) {
1645 printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1646 ret = -ENODEV;
1647 goto failed_request_irq;
1648 }
1649
1650 /* now that our ISR is registered, we can enable interrupts */
1651 denali_set_intr_modes(denali, true);
1652
1653 pci_set_drvdata(dev, denali);
1654
1655 denali_nand_timing_set(denali);
1656
1657 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
1658 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
1659 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
1660 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
1661 ioread32(denali->flash_reg + ACC_CLKS),
1662 ioread32(denali->flash_reg + RE_2_WE),
1663 ioread32(denali->flash_reg + WE_2_RE),
1664 ioread32(denali->flash_reg + ADDR_2_DATA),
1665 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
1666 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
1667 ioread32(denali->flash_reg + CS_SETUP_CNT));
1668
1669 denali->mtd.name = "Denali NAND";
1670 denali->mtd.owner = THIS_MODULE;
1671 denali->mtd.priv = &denali->nand;
1672
1673 /* register the driver with the NAND core subsystem */
1674 denali->nand.select_chip = denali_select_chip;
1675 denali->nand.cmdfunc = denali_cmdfunc;
1676 denali->nand.read_byte = denali_read_byte;
1677 denali->nand.waitfunc = denali_waitfunc;
1678
1679 /* scan for NAND devices attached to the controller
1680 * this is the first stage in a two step process to register
1681 * with the nand subsystem */
1682 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
1683 ret = -ENXIO;
1684 goto failed_nand;
1685 }
1686
1687 /* MTD supported page sizes vary by kernel. We validate our
1688 * kernel supports the device here.
1689 */
1690 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1691 ret = -ENODEV;
1692 printk(KERN_ERR "Spectra: device size not supported by this "
1693 "version of MTD.");
1694 goto failed_nand;
1695 }
1696
1697 /* second stage of the NAND scan
1698 * this stage requires information regarding ECC and
1699 * bad block management. */
1700
1701 /* Bad block management */
1702 denali->nand.bbt_td = &bbt_main_descr;
1703 denali->nand.bbt_md = &bbt_mirror_descr;
1704
1705 /* skip the scan for now until we have OOB read and write support */
1706 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
1707 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1708
1709 if (denali->nand.cellinfo & 0xc) {
1710 denali->nand.ecc.layout = &nand_oob_mlc_14bit;
1711 denali->nand.ecc.bytes = ECC_BYTES_MLC;
1712 } else {/* SLC */
1713 denali->nand.ecc.layout = &nand_oob_slc;
1714 denali->nand.ecc.bytes = ECC_BYTES_SLC;
1715 }
1716
1717 /* Let driver know the total blocks number and
1718 * how many blocks contained by each nand chip.
1719 * blksperchip will help driver to know how many
1720 * blocks is taken by FW.
1721 * */
1722 denali->totalblks = denali->mtd.size >>
1723 denali->nand.phys_erase_shift;
1724 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1725
1726 /* These functions are required by the NAND core framework, otherwise,
1727 * the NAND core will assert. However, we don't need them, so we'll stub
1728 * them out. */
1729 denali->nand.ecc.calculate = denali_ecc_calculate;
1730 denali->nand.ecc.correct = denali_ecc_correct;
1731 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1732
1733 /* override the default read operations */
1734 denali->nand.ecc.size = denali->mtd.writesize;
1735 denali->nand.ecc.read_page = denali_read_page;
1736 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1737 denali->nand.ecc.write_page = denali_write_page;
1738 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1739 denali->nand.ecc.read_oob = denali_read_oob;
1740 denali->nand.ecc.write_oob = denali_write_oob;
1741 denali->nand.erase_cmd = denali_erase;
1742
1743 if (nand_scan_tail(&denali->mtd)) {
1744 ret = -ENXIO;
1745 goto failed_nand;
1746 }
1747
1748 ret = add_mtd_device(&denali->mtd);
1749 if (ret) {
1750 printk(KERN_ERR "Spectra: Failed to register"
1751 " MTD device: %d\n", ret);
1752 goto failed_nand;
1753 }
1754 return 0;
1755
1756 failed_nand:
1757 denali_irq_cleanup(dev->irq, denali);
1758 failed_request_irq:
1759 iounmap(denali->flash_reg);
1760 iounmap(denali->flash_mem);
1761 failed_remap_csr:
1762 pci_release_regions(dev);
1763 failed_req_csr:
1764 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1765 PCI_DMA_BIDIRECTIONAL);
1766 failed_enable:
1767 kfree(denali);
1768 return ret;
1769 }
1770
1771 /* driver exit point */
1772 static void denali_pci_remove(struct pci_dev *dev)
1773 {
1774 struct denali_nand_info *denali = pci_get_drvdata(dev);
1775
1776 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
1777 __FILE__, __LINE__, __func__);
1778
1779 nand_release(&denali->mtd);
1780 del_mtd_device(&denali->mtd);
1781
1782 denali_irq_cleanup(dev->irq, denali);
1783
1784 iounmap(denali->flash_reg);
1785 iounmap(denali->flash_mem);
1786 pci_release_regions(dev);
1787 pci_disable_device(dev);
1788 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1789 PCI_DMA_BIDIRECTIONAL);
1790 pci_set_drvdata(dev, NULL);
1791 kfree(denali);
1792 }
1793
1794 MODULE_DEVICE_TABLE(pci, denali_pci_ids);
1795
1796 static struct pci_driver denali_pci_driver = {
1797 .name = DENALI_NAND_NAME,
1798 .id_table = denali_pci_ids,
1799 .probe = denali_pci_probe,
1800 .remove = denali_pci_remove,
1801 };
1802
1803 static int __devinit denali_init(void)
1804 {
1805 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n",
1806 __DATE__, __TIME__);
1807 return pci_register_driver(&denali_pci_driver);
1808 }
1809
1810 /* Free memory */
1811 static void __devexit denali_exit(void)
1812 {
1813 pci_unregister_driver(&denali_pci_driver);
1814 }
1815
1816 module_init(denali_init);
1817 module_exit(denali_exit);
Linux kernel - Deliverables
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