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nand/denali: Fixed handle ECC error bugs
[deliverable/linux.git] / drivers / mtd / nand / denali.c
1 /*
2 * NAND Flash Controller Device Driver
3 * Copyright © 2009-2010, Intel Corporation and its suppliers.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 */
19
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include <linux/wait.h>
23 #include <linux/mutex.h>
24 #include <linux/slab.h>
25 #include <linux/pci.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/module.h>
28
29 #include "denali.h"
30
31 MODULE_LICENSE("GPL");
32
33 /* We define a module parameter that allows the user to override
34 * the hardware and decide what timing mode should be used.
35 */
36 #define NAND_DEFAULT_TIMINGS -1
37
38 static int onfi_timing_mode = NAND_DEFAULT_TIMINGS;
39 module_param(onfi_timing_mode, int, S_IRUGO);
40 MODULE_PARM_DESC(onfi_timing_mode, "Overrides default ONFI setting."
41 " -1 indicates use default timings");
42
43 #define DENALI_NAND_NAME "denali-nand"
44
45 /* We define a macro here that combines all interrupts this driver uses into
46 * a single constant value, for convenience. */
47 #define DENALI_IRQ_ALL (INTR_STATUS0__DMA_CMD_COMP | \
48 INTR_STATUS0__ECC_TRANSACTION_DONE | \
49 INTR_STATUS0__ECC_ERR | \
50 INTR_STATUS0__PROGRAM_FAIL | \
51 INTR_STATUS0__LOAD_COMP | \
52 INTR_STATUS0__PROGRAM_COMP | \
53 INTR_STATUS0__TIME_OUT | \
54 INTR_STATUS0__ERASE_FAIL | \
55 INTR_STATUS0__RST_COMP | \
56 INTR_STATUS0__ERASE_COMP)
57
58 /* indicates whether or not the internal value for the flash bank is
59 valid or not */
60 #define CHIP_SELECT_INVALID -1
61
62 #define SUPPORT_8BITECC 1
63
64 /* This macro divides two integers and rounds fractional values up
65 * to the nearest integer value. */
66 #define CEIL_DIV(X, Y) (((X)%(Y)) ? ((X)/(Y)+1) : ((X)/(Y)))
67
68 /* this macro allows us to convert from an MTD structure to our own
69 * device context (denali) structure.
70 */
71 #define mtd_to_denali(m) container_of(m, struct denali_nand_info, mtd)
72
73 /* These constants are defined by the driver to enable common driver
74 configuration options. */
75 #define SPARE_ACCESS 0x41
76 #define MAIN_ACCESS 0x42
77 #define MAIN_SPARE_ACCESS 0x43
78
79 #define DENALI_READ 0
80 #define DENALI_WRITE 0x100
81
82 /* types of device accesses. We can issue commands and get status */
83 #define COMMAND_CYCLE 0
84 #define ADDR_CYCLE 1
85 #define STATUS_CYCLE 2
86
87 /* this is a helper macro that allows us to
88 * format the bank into the proper bits for the controller */
89 #define BANK(x) ((x) << 24)
90
91 /* List of platforms this NAND controller has be integrated into */
92 static const struct pci_device_id denali_pci_ids[] = {
93 { PCI_VDEVICE(INTEL, 0x0701), INTEL_CE4100 },
94 { PCI_VDEVICE(INTEL, 0x0809), INTEL_MRST },
95 { /* end: all zeroes */ }
96 };
97
98
99 /* these are static lookup tables that give us easy access to
100 registers in the NAND controller.
101 */
102 static const uint32_t intr_status_addresses[4] = {INTR_STATUS0,
103 INTR_STATUS1,
104 INTR_STATUS2,
105 INTR_STATUS3};
106
107 static const uint32_t device_reset_banks[4] = {DEVICE_RESET__BANK0,
108 DEVICE_RESET__BANK1,
109 DEVICE_RESET__BANK2,
110 DEVICE_RESET__BANK3};
111
112 static const uint32_t operation_timeout[4] = {INTR_STATUS0__TIME_OUT,
113 INTR_STATUS1__TIME_OUT,
114 INTR_STATUS2__TIME_OUT,
115 INTR_STATUS3__TIME_OUT};
116
117 static const uint32_t reset_complete[4] = {INTR_STATUS0__RST_COMP,
118 INTR_STATUS1__RST_COMP,
119 INTR_STATUS2__RST_COMP,
120 INTR_STATUS3__RST_COMP};
121
122 /* specifies the debug level of the driver */
123 static int nand_debug_level;
124
125 /* forward declarations */
126 static void clear_interrupts(struct denali_nand_info *denali);
127 static uint32_t wait_for_irq(struct denali_nand_info *denali,
128 uint32_t irq_mask);
129 static void denali_irq_enable(struct denali_nand_info *denali,
130 uint32_t int_mask);
131 static uint32_t read_interrupt_status(struct denali_nand_info *denali);
132
133 #define DEBUG_DENALI 0
134
135 /* Certain operations for the denali NAND controller use
136 * an indexed mode to read/write data. The operation is
137 * performed by writing the address value of the command
138 * to the device memory followed by the data. This function
139 * abstracts this common operation.
140 */
141 static void index_addr(struct denali_nand_info *denali,
142 uint32_t address, uint32_t data)
143 {
144 iowrite32(address, denali->flash_mem);
145 iowrite32(data, denali->flash_mem + 0x10);
146 }
147
148 /* Perform an indexed read of the device */
149 static void index_addr_read_data(struct denali_nand_info *denali,
150 uint32_t address, uint32_t *pdata)
151 {
152 iowrite32(address, denali->flash_mem);
153 *pdata = ioread32(denali->flash_mem + 0x10);
154 }
155
156 /* We need to buffer some data for some of the NAND core routines.
157 * The operations manage buffering that data. */
158 static void reset_buf(struct denali_nand_info *denali)
159 {
160 denali->buf.head = denali->buf.tail = 0;
161 }
162
163 static void write_byte_to_buf(struct denali_nand_info *denali, uint8_t byte)
164 {
165 BUG_ON(denali->buf.tail >= sizeof(denali->buf.buf));
166 denali->buf.buf[denali->buf.tail++] = byte;
167 }
168
169 /* reads the status of the device */
170 static void read_status(struct denali_nand_info *denali)
171 {
172 uint32_t cmd = 0x0;
173
174 /* initialize the data buffer to store status */
175 reset_buf(denali);
176
177 /* initiate a device status read */
178 cmd = MODE_11 | BANK(denali->flash_bank);
179 index_addr(denali, cmd | COMMAND_CYCLE, 0x70);
180 iowrite32(cmd | STATUS_CYCLE, denali->flash_mem);
181
182 /* update buffer with status value */
183 write_byte_to_buf(denali, ioread32(denali->flash_mem + 0x10));
184
185 #if DEBUG_DENALI
186 printk(KERN_INFO "device reporting status value of 0x%2x\n",
187 denali->buf.buf[0]);
188 #endif
189 }
190
191 /* resets a specific device connected to the core */
192 static void reset_bank(struct denali_nand_info *denali)
193 {
194 uint32_t irq_status = 0;
195 uint32_t irq_mask = reset_complete[denali->flash_bank] |
196 operation_timeout[denali->flash_bank];
197 int bank = 0;
198
199 clear_interrupts(denali);
200
201 bank = device_reset_banks[denali->flash_bank];
202 iowrite32(bank, denali->flash_reg + DEVICE_RESET);
203
204 irq_status = wait_for_irq(denali, irq_mask);
205
206 if (irq_status & operation_timeout[denali->flash_bank])
207 printk(KERN_ERR "reset bank failed.\n");
208 }
209
210 /* Reset the flash controller */
211 static uint16_t denali_nand_reset(struct denali_nand_info *denali)
212 {
213 uint32_t i;
214
215 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
216 __FILE__, __LINE__, __func__);
217
218 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++)
219 iowrite32(reset_complete[i] | operation_timeout[i],
220 denali->flash_reg + intr_status_addresses[i]);
221
222 for (i = 0 ; i < LLD_MAX_FLASH_BANKS; i++) {
223 iowrite32(device_reset_banks[i],
224 denali->flash_reg + DEVICE_RESET);
225 while (!(ioread32(denali->flash_reg +
226 intr_status_addresses[i]) &
227 (reset_complete[i] | operation_timeout[i])))
228 ;
229 if (ioread32(denali->flash_reg + intr_status_addresses[i]) &
230 operation_timeout[i])
231 nand_dbg_print(NAND_DBG_WARN,
232 "NAND Reset operation timed out on bank %d\n", i);
233 }
234
235 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++)
236 iowrite32(reset_complete[i] | operation_timeout[i],
237 denali->flash_reg + intr_status_addresses[i]);
238
239 return PASS;
240 }
241
242 /* this routine calculates the ONFI timing values for a given mode and
243 * programs the clocking register accordingly. The mode is determined by
244 * the get_onfi_nand_para routine.
245 */
246 static void nand_onfi_timing_set(struct denali_nand_info *denali,
247 uint16_t mode)
248 {
249 uint16_t Trea[6] = {40, 30, 25, 20, 20, 16};
250 uint16_t Trp[6] = {50, 25, 17, 15, 12, 10};
251 uint16_t Treh[6] = {30, 15, 15, 10, 10, 7};
252 uint16_t Trc[6] = {100, 50, 35, 30, 25, 20};
253 uint16_t Trhoh[6] = {0, 15, 15, 15, 15, 15};
254 uint16_t Trloh[6] = {0, 0, 0, 0, 5, 5};
255 uint16_t Tcea[6] = {100, 45, 30, 25, 25, 25};
256 uint16_t Tadl[6] = {200, 100, 100, 100, 70, 70};
257 uint16_t Trhw[6] = {200, 100, 100, 100, 100, 100};
258 uint16_t Trhz[6] = {200, 100, 100, 100, 100, 100};
259 uint16_t Twhr[6] = {120, 80, 80, 60, 60, 60};
260 uint16_t Tcs[6] = {70, 35, 25, 25, 20, 15};
261
262 uint16_t TclsRising = 1;
263 uint16_t data_invalid_rhoh, data_invalid_rloh, data_invalid;
264 uint16_t dv_window = 0;
265 uint16_t en_lo, en_hi;
266 uint16_t acc_clks;
267 uint16_t addr_2_data, re_2_we, re_2_re, we_2_re, cs_cnt;
268
269 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
270 __FILE__, __LINE__, __func__);
271
272 en_lo = CEIL_DIV(Trp[mode], CLK_X);
273 en_hi = CEIL_DIV(Treh[mode], CLK_X);
274 #if ONFI_BLOOM_TIME
275 if ((en_hi * CLK_X) < (Treh[mode] + 2))
276 en_hi++;
277 #endif
278
279 if ((en_lo + en_hi) * CLK_X < Trc[mode])
280 en_lo += CEIL_DIV((Trc[mode] - (en_lo + en_hi) * CLK_X), CLK_X);
281
282 if ((en_lo + en_hi) < CLK_MULTI)
283 en_lo += CLK_MULTI - en_lo - en_hi;
284
285 while (dv_window < 8) {
286 data_invalid_rhoh = en_lo * CLK_X + Trhoh[mode];
287
288 data_invalid_rloh = (en_lo + en_hi) * CLK_X + Trloh[mode];
289
290 data_invalid =
291 data_invalid_rhoh <
292 data_invalid_rloh ? data_invalid_rhoh : data_invalid_rloh;
293
294 dv_window = data_invalid - Trea[mode];
295
296 if (dv_window < 8)
297 en_lo++;
298 }
299
300 acc_clks = CEIL_DIV(Trea[mode], CLK_X);
301
302 while (((acc_clks * CLK_X) - Trea[mode]) < 3)
303 acc_clks++;
304
305 if ((data_invalid - acc_clks * CLK_X) < 2)
306 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d: Warning!\n",
307 __FILE__, __LINE__);
308
309 addr_2_data = CEIL_DIV(Tadl[mode], CLK_X);
310 re_2_we = CEIL_DIV(Trhw[mode], CLK_X);
311 re_2_re = CEIL_DIV(Trhz[mode], CLK_X);
312 we_2_re = CEIL_DIV(Twhr[mode], CLK_X);
313 cs_cnt = CEIL_DIV((Tcs[mode] - Trp[mode]), CLK_X);
314 if (!TclsRising)
315 cs_cnt = CEIL_DIV(Tcs[mode], CLK_X);
316 if (cs_cnt == 0)
317 cs_cnt = 1;
318
319 if (Tcea[mode]) {
320 while (((cs_cnt * CLK_X) + Trea[mode]) < Tcea[mode])
321 cs_cnt++;
322 }
323
324 #if MODE5_WORKAROUND
325 if (mode == 5)
326 acc_clks = 5;
327 #endif
328
329 /* Sighting 3462430: Temporary hack for MT29F128G08CJABAWP:B */
330 if ((ioread32(denali->flash_reg + MANUFACTURER_ID) == 0) &&
331 (ioread32(denali->flash_reg + DEVICE_ID) == 0x88))
332 acc_clks = 6;
333
334 iowrite32(acc_clks, denali->flash_reg + ACC_CLKS);
335 iowrite32(re_2_we, denali->flash_reg + RE_2_WE);
336 iowrite32(re_2_re, denali->flash_reg + RE_2_RE);
337 iowrite32(we_2_re, denali->flash_reg + WE_2_RE);
338 iowrite32(addr_2_data, denali->flash_reg + ADDR_2_DATA);
339 iowrite32(en_lo, denali->flash_reg + RDWR_EN_LO_CNT);
340 iowrite32(en_hi, denali->flash_reg + RDWR_EN_HI_CNT);
341 iowrite32(cs_cnt, denali->flash_reg + CS_SETUP_CNT);
342 }
343
344 /* queries the NAND device to see what ONFI modes it supports. */
345 static uint16_t get_onfi_nand_para(struct denali_nand_info *denali)
346 {
347 int i;
348 /* we needn't to do a reset here because driver has already
349 * reset all the banks before
350 * */
351 if (!(ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
352 ONFI_TIMING_MODE__VALUE))
353 return FAIL;
354
355 for (i = 5; i > 0; i--) {
356 if (ioread32(denali->flash_reg + ONFI_TIMING_MODE) &
357 (0x01 << i))
358 break;
359 }
360
361 nand_onfi_timing_set(denali, i);
362
363 /* By now, all the ONFI devices we know support the page cache */
364 /* rw feature. So here we enable the pipeline_rw_ahead feature */
365 /* iowrite32(1, denali->flash_reg + CACHE_WRITE_ENABLE); */
366 /* iowrite32(1, denali->flash_reg + CACHE_READ_ENABLE); */
367
368 return PASS;
369 }
370
371 static void get_samsung_nand_para(struct denali_nand_info *denali,
372 uint8_t device_id)
373 {
374 if (device_id == 0xd3) { /* Samsung K9WAG08U1A */
375 /* Set timing register values according to datasheet */
376 iowrite32(5, denali->flash_reg + ACC_CLKS);
377 iowrite32(20, denali->flash_reg + RE_2_WE);
378 iowrite32(12, denali->flash_reg + WE_2_RE);
379 iowrite32(14, denali->flash_reg + ADDR_2_DATA);
380 iowrite32(3, denali->flash_reg + RDWR_EN_LO_CNT);
381 iowrite32(2, denali->flash_reg + RDWR_EN_HI_CNT);
382 iowrite32(2, denali->flash_reg + CS_SETUP_CNT);
383 }
384 }
385
386 static void get_toshiba_nand_para(struct denali_nand_info *denali)
387 {
388 uint32_t tmp;
389
390 /* Workaround to fix a controller bug which reports a wrong */
391 /* spare area size for some kind of Toshiba NAND device */
392 if ((ioread32(denali->flash_reg + DEVICE_MAIN_AREA_SIZE) == 4096) &&
393 (ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE) == 64)) {
394 iowrite32(216, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
395 tmp = ioread32(denali->flash_reg + DEVICES_CONNECTED) *
396 ioread32(denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
397 iowrite32(tmp,
398 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
399 #if SUPPORT_15BITECC
400 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
401 #elif SUPPORT_8BITECC
402 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
403 #endif
404 }
405 }
406
407 static void get_hynix_nand_para(struct denali_nand_info *denali,
408 uint8_t device_id)
409 {
410 uint32_t main_size, spare_size;
411
412 switch (device_id) {
413 case 0xD5: /* Hynix H27UAG8T2A, H27UBG8U5A or H27UCG8VFA */
414 case 0xD7: /* Hynix H27UDG8VEM, H27UCG8UDM or H27UCG8V5A */
415 iowrite32(128, denali->flash_reg + PAGES_PER_BLOCK);
416 iowrite32(4096, denali->flash_reg + DEVICE_MAIN_AREA_SIZE);
417 iowrite32(224, denali->flash_reg + DEVICE_SPARE_AREA_SIZE);
418 main_size = 4096 *
419 ioread32(denali->flash_reg + DEVICES_CONNECTED);
420 spare_size = 224 *
421 ioread32(denali->flash_reg + DEVICES_CONNECTED);
422 iowrite32(main_size,
423 denali->flash_reg + LOGICAL_PAGE_DATA_SIZE);
424 iowrite32(spare_size,
425 denali->flash_reg + LOGICAL_PAGE_SPARE_SIZE);
426 iowrite32(0, denali->flash_reg + DEVICE_WIDTH);
427 #if SUPPORT_15BITECC
428 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
429 #elif SUPPORT_8BITECC
430 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
431 #endif
432 break;
433 default:
434 nand_dbg_print(NAND_DBG_WARN,
435 "Spectra: Unknown Hynix NAND (Device ID: 0x%x)."
436 "Will use default parameter values instead.\n",
437 device_id);
438 }
439 }
440
441 /* determines how many NAND chips are connected to the controller. Note for
442 Intel CE4100 devices we don't support more than one device.
443 */
444 static void find_valid_banks(struct denali_nand_info *denali)
445 {
446 uint32_t id[LLD_MAX_FLASH_BANKS];
447 int i;
448
449 denali->total_used_banks = 1;
450 for (i = 0; i < LLD_MAX_FLASH_BANKS; i++) {
451 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 0), 0x90);
452 index_addr(denali, (uint32_t)(MODE_11 | (i << 24) | 1), 0);
453 index_addr_read_data(denali,
454 (uint32_t)(MODE_11 | (i << 24) | 2), &id[i]);
455
456 nand_dbg_print(NAND_DBG_DEBUG,
457 "Return 1st ID for bank[%d]: %x\n", i, id[i]);
458
459 if (i == 0) {
460 if (!(id[i] & 0x0ff))
461 break; /* WTF? */
462 } else {
463 if ((id[i] & 0x0ff) == (id[0] & 0x0ff))
464 denali->total_used_banks++;
465 else
466 break;
467 }
468 }
469
470 if (denali->platform == INTEL_CE4100) {
471 /* Platform limitations of the CE4100 device limit
472 * users to a single chip solution for NAND.
473 * Multichip support is not enabled.
474 */
475 if (denali->total_used_banks != 1) {
476 printk(KERN_ERR "Sorry, Intel CE4100 only supports "
477 "a single NAND device.\n");
478 BUG();
479 }
480 }
481 nand_dbg_print(NAND_DBG_DEBUG,
482 "denali->total_used_banks: %d\n", denali->total_used_banks);
483 }
484
485 static void detect_partition_feature(struct denali_nand_info *denali)
486 {
487 /* For MRST platform, denali->fwblks represent the
488 * number of blocks firmware is taken,
489 * FW is in protect partition and MTD driver has no
490 * permission to access it. So let driver know how many
491 * blocks it can't touch.
492 * */
493 if (ioread32(denali->flash_reg + FEATURES) & FEATURES__PARTITION) {
494 if ((ioread32(denali->flash_reg + PERM_SRC_ID_1) &
495 PERM_SRC_ID_1__SRCID) == SPECTRA_PARTITION_ID) {
496 denali->fwblks =
497 ((ioread32(denali->flash_reg + MIN_MAX_BANK_1) &
498 MIN_MAX_BANK_1__MIN_VALUE) *
499 denali->blksperchip)
500 +
501 (ioread32(denali->flash_reg + MIN_BLK_ADDR_1) &
502 MIN_BLK_ADDR_1__VALUE);
503 } else
504 denali->fwblks = SPECTRA_START_BLOCK;
505 } else
506 denali->fwblks = SPECTRA_START_BLOCK;
507 }
508
509 static uint16_t denali_nand_timing_set(struct denali_nand_info *denali)
510 {
511 uint16_t status = PASS;
512 uint32_t id_bytes[5], addr;
513 uint8_t i, maf_id, device_id;
514
515 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
516 __FILE__, __LINE__, __func__);
517
518 /* Use read id method to get device ID and other
519 * params. For some NAND chips, controller can't
520 * report the correct device ID by reading from
521 * DEVICE_ID register
522 * */
523 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
524 index_addr(denali, (uint32_t)addr | 0, 0x90);
525 index_addr(denali, (uint32_t)addr | 1, 0);
526 for (i = 0; i < 5; i++)
527 index_addr_read_data(denali, addr | 2, &id_bytes[i]);
528 maf_id = id_bytes[0];
529 device_id = id_bytes[1];
530
531 if (ioread32(denali->flash_reg + ONFI_DEVICE_NO_OF_LUNS) &
532 ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE) { /* ONFI 1.0 NAND */
533 if (FAIL == get_onfi_nand_para(denali))
534 return FAIL;
535 } else if (maf_id == 0xEC) { /* Samsung NAND */
536 get_samsung_nand_para(denali, device_id);
537 } else if (maf_id == 0x98) { /* Toshiba NAND */
538 get_toshiba_nand_para(denali);
539 } else if (maf_id == 0xAD) { /* Hynix NAND */
540 get_hynix_nand_para(denali, device_id);
541 }
542
543 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
544 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
545 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
546 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
547 ioread32(denali->flash_reg + ACC_CLKS),
548 ioread32(denali->flash_reg + RE_2_WE),
549 ioread32(denali->flash_reg + WE_2_RE),
550 ioread32(denali->flash_reg + ADDR_2_DATA),
551 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
552 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
553 ioread32(denali->flash_reg + CS_SETUP_CNT));
554
555 find_valid_banks(denali);
556
557 detect_partition_feature(denali);
558
559 /* If the user specified to override the default timings
560 * with a specific ONFI mode, we apply those changes here.
561 */
562 if (onfi_timing_mode != NAND_DEFAULT_TIMINGS)
563 nand_onfi_timing_set(denali, onfi_timing_mode);
564
565 return status;
566 }
567
568 static void denali_set_intr_modes(struct denali_nand_info *denali,
569 uint16_t INT_ENABLE)
570 {
571 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
572 __FILE__, __LINE__, __func__);
573
574 if (INT_ENABLE)
575 iowrite32(1, denali->flash_reg + GLOBAL_INT_ENABLE);
576 else
577 iowrite32(0, denali->flash_reg + GLOBAL_INT_ENABLE);
578 }
579
580 /* validation function to verify that the controlling software is making
581 a valid request
582 */
583 static inline bool is_flash_bank_valid(int flash_bank)
584 {
585 return (flash_bank >= 0 && flash_bank < 4);
586 }
587
588 static void denali_irq_init(struct denali_nand_info *denali)
589 {
590 uint32_t int_mask = 0;
591
592 /* Disable global interrupts */
593 denali_set_intr_modes(denali, false);
594
595 int_mask = DENALI_IRQ_ALL;
596
597 /* Clear all status bits */
598 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS0);
599 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS1);
600 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS2);
601 iowrite32(0xFFFF, denali->flash_reg + INTR_STATUS3);
602
603 denali_irq_enable(denali, int_mask);
604 }
605
606 static void denali_irq_cleanup(int irqnum, struct denali_nand_info *denali)
607 {
608 denali_set_intr_modes(denali, false);
609 free_irq(irqnum, denali);
610 }
611
612 static void denali_irq_enable(struct denali_nand_info *denali,
613 uint32_t int_mask)
614 {
615 iowrite32(int_mask, denali->flash_reg + INTR_EN0);
616 iowrite32(int_mask, denali->flash_reg + INTR_EN1);
617 iowrite32(int_mask, denali->flash_reg + INTR_EN2);
618 iowrite32(int_mask, denali->flash_reg + INTR_EN3);
619 }
620
621 /* This function only returns when an interrupt that this driver cares about
622 * occurs. This is to reduce the overhead of servicing interrupts
623 */
624 static inline uint32_t denali_irq_detected(struct denali_nand_info *denali)
625 {
626 return read_interrupt_status(denali) & DENALI_IRQ_ALL;
627 }
628
629 /* Interrupts are cleared by writing a 1 to the appropriate status bit */
630 static inline void clear_interrupt(struct denali_nand_info *denali,
631 uint32_t irq_mask)
632 {
633 uint32_t intr_status_reg = 0;
634
635 intr_status_reg = intr_status_addresses[denali->flash_bank];
636
637 iowrite32(irq_mask, denali->flash_reg + intr_status_reg);
638 }
639
640 static void clear_interrupts(struct denali_nand_info *denali)
641 {
642 uint32_t status = 0x0;
643 spin_lock_irq(&denali->irq_lock);
644
645 status = read_interrupt_status(denali);
646 clear_interrupt(denali, status);
647
648 #if DEBUG_DENALI
649 denali->irq_debug_array[denali->idx++] = 0x30000000 | status;
650 denali->idx %= 32;
651 #endif
652
653 denali->irq_status = 0x0;
654 spin_unlock_irq(&denali->irq_lock);
655 }
656
657 static uint32_t read_interrupt_status(struct denali_nand_info *denali)
658 {
659 uint32_t intr_status_reg = 0;
660
661 intr_status_reg = intr_status_addresses[denali->flash_bank];
662
663 return ioread32(denali->flash_reg + intr_status_reg);
664 }
665
666 #if DEBUG_DENALI
667 static void print_irq_log(struct denali_nand_info *denali)
668 {
669 int i = 0;
670
671 printk(KERN_INFO "ISR debug log index = %X\n", denali->idx);
672 for (i = 0; i < 32; i++)
673 printk(KERN_INFO "%08X: %08X\n", i, denali->irq_debug_array[i]);
674 }
675 #endif
676
677 /* This is the interrupt service routine. It handles all interrupts
678 * sent to this device. Note that on CE4100, this is a shared
679 * interrupt.
680 */
681 static irqreturn_t denali_isr(int irq, void *dev_id)
682 {
683 struct denali_nand_info *denali = dev_id;
684 uint32_t irq_status = 0x0;
685 irqreturn_t result = IRQ_NONE;
686
687 spin_lock(&denali->irq_lock);
688
689 /* check to see if a valid NAND chip has
690 * been selected.
691 */
692 if (is_flash_bank_valid(denali->flash_bank)) {
693 /* check to see if controller generated
694 * the interrupt, since this is a shared interrupt */
695 irq_status = denali_irq_detected(denali);
696 if (irq_status != 0) {
697 #if DEBUG_DENALI
698 denali->irq_debug_array[denali->idx++] =
699 0x10000000 | irq_status;
700 denali->idx %= 32;
701
702 printk(KERN_INFO "IRQ status = 0x%04x\n", irq_status);
703 #endif
704 /* handle interrupt */
705 /* first acknowledge it */
706 clear_interrupt(denali, irq_status);
707 /* store the status in the device context for someone
708 to read */
709 denali->irq_status |= irq_status;
710 /* notify anyone who cares that it happened */
711 complete(&denali->complete);
712 /* tell the OS that we've handled this */
713 result = IRQ_HANDLED;
714 }
715 }
716 spin_unlock(&denali->irq_lock);
717 return result;
718 }
719 #define BANK(x) ((x) << 24)
720
721 static uint32_t wait_for_irq(struct denali_nand_info *denali, uint32_t irq_mask)
722 {
723 unsigned long comp_res = 0;
724 uint32_t intr_status = 0;
725 bool retry = false;
726 unsigned long timeout = msecs_to_jiffies(1000);
727
728 do {
729 #if DEBUG_DENALI
730 printk(KERN_INFO "waiting for 0x%x\n", irq_mask);
731 #endif
732 comp_res =
733 wait_for_completion_timeout(&denali->complete, timeout);
734 spin_lock_irq(&denali->irq_lock);
735 intr_status = denali->irq_status;
736
737 #if DEBUG_DENALI
738 denali->irq_debug_array[denali->idx++] =
739 0x20000000 | (irq_mask << 16) | intr_status;
740 denali->idx %= 32;
741 #endif
742
743 if (intr_status & irq_mask) {
744 denali->irq_status &= ~irq_mask;
745 spin_unlock_irq(&denali->irq_lock);
746 #if DEBUG_DENALI
747 if (retry)
748 printk(KERN_INFO "status on retry = 0x%x\n",
749 intr_status);
750 #endif
751 /* our interrupt was detected */
752 break;
753 } else {
754 /* these are not the interrupts you are looking for -
755 * need to wait again */
756 spin_unlock_irq(&denali->irq_lock);
757 #if DEBUG_DENALI
758 print_irq_log(denali);
759 printk(KERN_INFO "received irq nobody cared:"
760 " irq_status = 0x%x, irq_mask = 0x%x,"
761 " timeout = %ld\n", intr_status,
762 irq_mask, comp_res);
763 #endif
764 retry = true;
765 }
766 } while (comp_res != 0);
767
768 if (comp_res == 0) {
769 /* timeout */
770 printk(KERN_ERR "timeout occurred, status = 0x%x, mask = 0x%x\n",
771 intr_status, irq_mask);
772
773 intr_status = 0;
774 }
775 return intr_status;
776 }
777
778 /* This helper function setups the registers for ECC and whether or not
779 the spare area will be transfered. */
780 static void setup_ecc_for_xfer(struct denali_nand_info *denali, bool ecc_en,
781 bool transfer_spare)
782 {
783 int ecc_en_flag = 0, transfer_spare_flag = 0;
784
785 /* set ECC, transfer spare bits if needed */
786 ecc_en_flag = ecc_en ? ECC_ENABLE__FLAG : 0;
787 transfer_spare_flag = transfer_spare ? TRANSFER_SPARE_REG__FLAG : 0;
788
789 /* Enable spare area/ECC per user's request. */
790 iowrite32(ecc_en_flag, denali->flash_reg + ECC_ENABLE);
791 iowrite32(transfer_spare_flag,
792 denali->flash_reg + TRANSFER_SPARE_REG);
793 }
794
795 /* sends a pipeline command operation to the controller. See the Denali NAND
796 controller's user guide for more information (section 4.2.3.6).
797 */
798 static int denali_send_pipeline_cmd(struct denali_nand_info *denali,
799 bool ecc_en,
800 bool transfer_spare,
801 int access_type,
802 int op)
803 {
804 int status = PASS;
805 uint32_t addr = 0x0, cmd = 0x0, page_count = 1, irq_status = 0,
806 irq_mask = 0;
807
808 if (op == DENALI_READ)
809 irq_mask = INTR_STATUS0__LOAD_COMP;
810 else if (op == DENALI_WRITE)
811 irq_mask = 0;
812 else
813 BUG();
814
815 setup_ecc_for_xfer(denali, ecc_en, transfer_spare);
816
817 #if DEBUG_DENALI
818 spin_lock_irq(&denali->irq_lock);
819 denali->irq_debug_array[denali->idx++] =
820 0x40000000 | ioread32(denali->flash_reg + ECC_ENABLE) |
821 (access_type << 4);
822 denali->idx %= 32;
823 spin_unlock_irq(&denali->irq_lock);
824 #endif
825
826
827 /* clear interrupts */
828 clear_interrupts(denali);
829
830 addr = BANK(denali->flash_bank) | denali->page;
831
832 if (op == DENALI_WRITE && access_type != SPARE_ACCESS) {
833 cmd = MODE_01 | addr;
834 iowrite32(cmd, denali->flash_mem);
835 } else if (op == DENALI_WRITE && access_type == SPARE_ACCESS) {
836 /* read spare area */
837 cmd = MODE_10 | addr;
838 index_addr(denali, (uint32_t)cmd, access_type);
839
840 cmd = MODE_01 | addr;
841 iowrite32(cmd, denali->flash_mem);
842 } else if (op == DENALI_READ) {
843 /* setup page read request for access type */
844 cmd = MODE_10 | addr;
845 index_addr(denali, (uint32_t)cmd, access_type);
846
847 /* page 33 of the NAND controller spec indicates we should not
848 use the pipeline commands in Spare area only mode. So we
849 don't.
850 */
851 if (access_type == SPARE_ACCESS) {
852 cmd = MODE_01 | addr;
853 iowrite32(cmd, denali->flash_mem);
854 } else {
855 index_addr(denali, (uint32_t)cmd,
856 0x2000 | op | page_count);
857
858 /* wait for command to be accepted
859 * can always use status0 bit as the
860 * mask is identical for each
861 * bank. */
862 irq_status = wait_for_irq(denali, irq_mask);
863
864 if (irq_status == 0) {
865 printk(KERN_ERR "cmd, page, addr on timeout "
866 "(0x%x, 0x%x, 0x%x)\n", cmd,
867 denali->page, addr);
868 status = FAIL;
869 } else {
870 cmd = MODE_01 | addr;
871 iowrite32(cmd, denali->flash_mem);
872 }
873 }
874 }
875 return status;
876 }
877
878 /* helper function that simply writes a buffer to the flash */
879 static int write_data_to_flash_mem(struct denali_nand_info *denali,
880 const uint8_t *buf,
881 int len)
882 {
883 uint32_t i = 0, *buf32;
884
885 /* verify that the len is a multiple of 4. see comment in
886 * read_data_from_flash_mem() */
887 BUG_ON((len % 4) != 0);
888
889 /* write the data to the flash memory */
890 buf32 = (uint32_t *)buf;
891 for (i = 0; i < len / 4; i++)
892 iowrite32(*buf32++, denali->flash_mem + 0x10);
893 return i*4; /* intent is to return the number of bytes read */
894 }
895
896 /* helper function that simply reads a buffer from the flash */
897 static int read_data_from_flash_mem(struct denali_nand_info *denali,
898 uint8_t *buf,
899 int len)
900 {
901 uint32_t i = 0, *buf32;
902
903 /* we assume that len will be a multiple of 4, if not
904 * it would be nice to know about it ASAP rather than
905 * have random failures...
906 * This assumption is based on the fact that this
907 * function is designed to be used to read flash pages,
908 * which are typically multiples of 4...
909 */
910
911 BUG_ON((len % 4) != 0);
912
913 /* transfer the data from the flash */
914 buf32 = (uint32_t *)buf;
915 for (i = 0; i < len / 4; i++)
916 *buf32++ = ioread32(denali->flash_mem + 0x10);
917 return i*4; /* intent is to return the number of bytes read */
918 }
919
920 /* writes OOB data to the device */
921 static int write_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
922 {
923 struct denali_nand_info *denali = mtd_to_denali(mtd);
924 uint32_t irq_status = 0;
925 uint32_t irq_mask = INTR_STATUS0__PROGRAM_COMP |
926 INTR_STATUS0__PROGRAM_FAIL;
927 int status = 0;
928
929 denali->page = page;
930
931 if (denali_send_pipeline_cmd(denali, false, false, SPARE_ACCESS,
932 DENALI_WRITE) == PASS) {
933 write_data_to_flash_mem(denali, buf, mtd->oobsize);
934
935 #if DEBUG_DENALI
936 spin_lock_irq(&denali->irq_lock);
937 denali->irq_debug_array[denali->idx++] =
938 0x80000000 | mtd->oobsize;
939 denali->idx %= 32;
940 spin_unlock_irq(&denali->irq_lock);
941 #endif
942
943
944 /* wait for operation to complete */
945 irq_status = wait_for_irq(denali, irq_mask);
946
947 if (irq_status == 0) {
948 printk(KERN_ERR "OOB write failed\n");
949 status = -EIO;
950 }
951 } else {
952 printk(KERN_ERR "unable to send pipeline command\n");
953 status = -EIO;
954 }
955 return status;
956 }
957
958 /* reads OOB data from the device */
959 static void read_oob_data(struct mtd_info *mtd, uint8_t *buf, int page)
960 {
961 struct denali_nand_info *denali = mtd_to_denali(mtd);
962 uint32_t irq_mask = INTR_STATUS0__LOAD_COMP,
963 irq_status = 0, addr = 0x0, cmd = 0x0;
964
965 denali->page = page;
966
967 #if DEBUG_DENALI
968 printk(KERN_INFO "read_oob %d\n", page);
969 #endif
970 if (denali_send_pipeline_cmd(denali, false, true, SPARE_ACCESS,
971 DENALI_READ) == PASS) {
972 read_data_from_flash_mem(denali, buf, mtd->oobsize);
973
974 /* wait for command to be accepted
975 * can always use status0 bit as the mask is identical for each
976 * bank. */
977 irq_status = wait_for_irq(denali, irq_mask);
978
979 if (irq_status == 0)
980 printk(KERN_ERR "page on OOB timeout %d\n",
981 denali->page);
982
983 /* We set the device back to MAIN_ACCESS here as I observed
984 * instability with the controller if you do a block erase
985 * and the last transaction was a SPARE_ACCESS. Block erase
986 * is reliable (according to the MTD test infrastructure)
987 * if you are in MAIN_ACCESS.
988 */
989 addr = BANK(denali->flash_bank) | denali->page;
990 cmd = MODE_10 | addr;
991 index_addr(denali, (uint32_t)cmd, MAIN_ACCESS);
992
993 #if DEBUG_DENALI
994 spin_lock_irq(&denali->irq_lock);
995 denali->irq_debug_array[denali->idx++] =
996 0x60000000 | mtd->oobsize;
997 denali->idx %= 32;
998 spin_unlock_irq(&denali->irq_lock);
999 #endif
1000 }
1001 }
1002
1003 /* this function examines buffers to see if they contain data that
1004 * indicate that the buffer is part of an erased region of flash.
1005 */
1006 bool is_erased(uint8_t *buf, int len)
1007 {
1008 int i = 0;
1009 for (i = 0; i < len; i++)
1010 if (buf[i] != 0xFF)
1011 return false;
1012 return true;
1013 }
1014 #define ECC_SECTOR_SIZE 512
1015
1016 #define ECC_SECTOR(x) (((x) & ECC_ERROR_ADDRESS__SECTOR_NR) >> 12)
1017 #define ECC_BYTE(x) (((x) & ECC_ERROR_ADDRESS__OFFSET))
1018 #define ECC_CORRECTION_VALUE(x) ((x) & ERR_CORRECTION_INFO__BYTEMASK)
1019 #define ECC_ERROR_CORRECTABLE(x) (!((x) & ERR_CORRECTION_INFO__ERROR_TYPE))
1020 #define ECC_ERR_DEVICE(x) (((x) & ERR_CORRECTION_INFO__DEVICE_NR) >> 8)
1021 #define ECC_LAST_ERR(x) ((x) & ERR_CORRECTION_INFO__LAST_ERR_INFO)
1022
1023 static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
1024 uint32_t irq_status)
1025 {
1026 bool check_erased_page = false;
1027
1028 if (irq_status & INTR_STATUS0__ECC_ERR) {
1029 /* read the ECC errors. we'll ignore them for now */
1030 uint32_t err_address = 0, err_correction_info = 0;
1031 uint32_t err_byte = 0, err_sector = 0, err_device = 0;
1032 uint32_t err_correction_value = 0;
1033 denali_set_intr_modes(denali, false);
1034
1035 do {
1036 err_address = ioread32(denali->flash_reg +
1037 ECC_ERROR_ADDRESS);
1038 err_sector = ECC_SECTOR(err_address);
1039 err_byte = ECC_BYTE(err_address);
1040
1041 err_correction_info = ioread32(denali->flash_reg +
1042 ERR_CORRECTION_INFO);
1043 err_correction_value =
1044 ECC_CORRECTION_VALUE(err_correction_info);
1045 err_device = ECC_ERR_DEVICE(err_correction_info);
1046
1047 if (ECC_ERROR_CORRECTABLE(err_correction_info)) {
1048 /* If err_byte is larger than ECC_SECTOR_SIZE,
1049 * means error happend in OOB, so we ignore
1050 * it. It's no need for us to correct it
1051 * err_device is represented the NAND error
1052 * bits are happened in if there are more
1053 * than one NAND connected.
1054 * */
1055 if (err_byte < ECC_SECTOR_SIZE) {
1056 int offset;
1057 offset = (err_sector *
1058 ECC_SECTOR_SIZE +
1059 err_byte) *
1060 denali->devnum +
1061 err_device;
1062 /* correct the ECC error */
1063 buf[offset] ^= err_correction_value;
1064 denali->mtd.ecc_stats.corrected++;
1065 }
1066 } else {
1067 /* if the error is not correctable, need to
1068 * look at the page to see if it is an erased
1069 * page. if so, then it's not a real ECC error
1070 * */
1071 check_erased_page = true;
1072 }
1073
1074 #if DEBUG_DENALI
1075 printk(KERN_INFO "Detected ECC error in page %d:"
1076 " err_addr = 0x%08x, info to fix is"
1077 " 0x%08x\n", denali->page, err_address,
1078 err_correction_info);
1079 #endif
1080 } while (!ECC_LAST_ERR(err_correction_info));
1081 /* Once handle all ecc errors, controller will triger
1082 * a ECC_TRANSACTION_DONE interrupt, so here just wait
1083 * for a while for this interrupt
1084 * */
1085 while (!(read_interrupt_status(denali) &
1086 INTR_STATUS0__ECC_TRANSACTION_DONE))
1087 cpu_relax();
1088 clear_interrupts(denali);
1089 denali_set_intr_modes(denali, true);
1090 }
1091 return check_erased_page;
1092 }
1093
1094 /* programs the controller to either enable/disable DMA transfers */
1095 static void denali_enable_dma(struct denali_nand_info *denali, bool en)
1096 {
1097 uint32_t reg_val = 0x0;
1098
1099 if (en)
1100 reg_val = DMA_ENABLE__FLAG;
1101
1102 iowrite32(reg_val, denali->flash_reg + DMA_ENABLE);
1103 ioread32(denali->flash_reg + DMA_ENABLE);
1104 }
1105
1106 /* setups the HW to perform the data DMA */
1107 static void denali_setup_dma(struct denali_nand_info *denali, int op)
1108 {
1109 uint32_t mode = 0x0;
1110 const int page_count = 1;
1111 dma_addr_t addr = denali->buf.dma_buf;
1112
1113 mode = MODE_10 | BANK(denali->flash_bank);
1114
1115 /* DMA is a four step process */
1116
1117 /* 1. setup transfer type and # of pages */
1118 index_addr(denali, mode | denali->page, 0x2000 | op | page_count);
1119
1120 /* 2. set memory high address bits 23:8 */
1121 index_addr(denali, mode | ((uint16_t)(addr >> 16) << 8), 0x2200);
1122
1123 /* 3. set memory low address bits 23:8 */
1124 index_addr(denali, mode | ((uint16_t)addr << 8), 0x2300);
1125
1126 /* 4. interrupt when complete, burst len = 64 bytes*/
1127 index_addr(denali, mode | 0x14000, 0x2400);
1128 }
1129
1130 /* writes a page. user specifies type, and this function handles the
1131 configuration details. */
1132 static void write_page(struct mtd_info *mtd, struct nand_chip *chip,
1133 const uint8_t *buf, bool raw_xfer)
1134 {
1135 struct denali_nand_info *denali = mtd_to_denali(mtd);
1136 struct pci_dev *pci_dev = denali->dev;
1137
1138 dma_addr_t addr = denali->buf.dma_buf;
1139 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1140
1141 uint32_t irq_status = 0;
1142 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP |
1143 INTR_STATUS0__PROGRAM_FAIL;
1144
1145 /* if it is a raw xfer, we want to disable ecc, and send
1146 * the spare area.
1147 * !raw_xfer - enable ecc
1148 * raw_xfer - transfer spare
1149 */
1150 setup_ecc_for_xfer(denali, !raw_xfer, raw_xfer);
1151
1152 /* copy buffer into DMA buffer */
1153 memcpy(denali->buf.buf, buf, mtd->writesize);
1154
1155 if (raw_xfer) {
1156 /* transfer the data to the spare area */
1157 memcpy(denali->buf.buf + mtd->writesize,
1158 chip->oob_poi,
1159 mtd->oobsize);
1160 }
1161
1162 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_TODEVICE);
1163
1164 clear_interrupts(denali);
1165 denali_enable_dma(denali, true);
1166
1167 denali_setup_dma(denali, DENALI_WRITE);
1168
1169 /* wait for operation to complete */
1170 irq_status = wait_for_irq(denali, irq_mask);
1171
1172 if (irq_status == 0) {
1173 printk(KERN_ERR "timeout on write_page"
1174 " (type = %d)\n", raw_xfer);
1175 denali->status =
1176 (irq_status & INTR_STATUS0__PROGRAM_FAIL) ?
1177 NAND_STATUS_FAIL : PASS;
1178 }
1179
1180 denali_enable_dma(denali, false);
1181 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_TODEVICE);
1182 }
1183
1184 /* NAND core entry points */
1185
1186 /* this is the callback that the NAND core calls to write a page. Since
1187 writing a page with ECC or without is similar, all the work is done
1188 by write_page above. */
1189 static void denali_write_page(struct mtd_info *mtd, struct nand_chip *chip,
1190 const uint8_t *buf)
1191 {
1192 /* for regular page writes, we let HW handle all the ECC
1193 * data written to the device. */
1194 write_page(mtd, chip, buf, false);
1195 }
1196
1197 /* This is the callback that the NAND core calls to write a page without ECC.
1198 raw access is similiar to ECC page writes, so all the work is done in the
1199 write_page() function above.
1200 */
1201 static void denali_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1202 const uint8_t *buf)
1203 {
1204 /* for raw page writes, we want to disable ECC and simply write
1205 whatever data is in the buffer. */
1206 write_page(mtd, chip, buf, true);
1207 }
1208
1209 static int denali_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
1210 int page)
1211 {
1212 return write_oob_data(mtd, chip->oob_poi, page);
1213 }
1214
1215 static int denali_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
1216 int page, int sndcmd)
1217 {
1218 read_oob_data(mtd, chip->oob_poi, page);
1219
1220 return 0; /* notify NAND core to send command to
1221 NAND device. */
1222 }
1223
1224 static int denali_read_page(struct mtd_info *mtd, struct nand_chip *chip,
1225 uint8_t *buf, int page)
1226 {
1227 struct denali_nand_info *denali = mtd_to_denali(mtd);
1228 struct pci_dev *pci_dev = denali->dev;
1229
1230 dma_addr_t addr = denali->buf.dma_buf;
1231 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1232
1233 uint32_t irq_status = 0;
1234 uint32_t irq_mask = INTR_STATUS0__ECC_TRANSACTION_DONE |
1235 INTR_STATUS0__ECC_ERR;
1236 bool check_erased_page = false;
1237
1238 setup_ecc_for_xfer(denali, true, false);
1239
1240 denali_enable_dma(denali, true);
1241 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1242
1243 clear_interrupts(denali);
1244 denali_setup_dma(denali, DENALI_READ);
1245
1246 /* wait for operation to complete */
1247 irq_status = wait_for_irq(denali, irq_mask);
1248
1249 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1250
1251 memcpy(buf, denali->buf.buf, mtd->writesize);
1252
1253 check_erased_page = handle_ecc(denali, buf, irq_status);
1254 denali_enable_dma(denali, false);
1255
1256 if (check_erased_page) {
1257 read_oob_data(&denali->mtd, chip->oob_poi, denali->page);
1258
1259 /* check ECC failures that may have occurred on erased pages */
1260 if (check_erased_page) {
1261 if (!is_erased(buf, denali->mtd.writesize))
1262 denali->mtd.ecc_stats.failed++;
1263 if (!is_erased(buf, denali->mtd.oobsize))
1264 denali->mtd.ecc_stats.failed++;
1265 }
1266 }
1267 return 0;
1268 }
1269
1270 static int denali_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1271 uint8_t *buf, int page)
1272 {
1273 struct denali_nand_info *denali = mtd_to_denali(mtd);
1274 struct pci_dev *pci_dev = denali->dev;
1275
1276 dma_addr_t addr = denali->buf.dma_buf;
1277 size_t size = denali->mtd.writesize + denali->mtd.oobsize;
1278
1279 uint32_t irq_status = 0;
1280 uint32_t irq_mask = INTR_STATUS0__DMA_CMD_COMP;
1281
1282 setup_ecc_for_xfer(denali, false, true);
1283 denali_enable_dma(denali, true);
1284
1285 pci_dma_sync_single_for_device(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1286
1287 clear_interrupts(denali);
1288 denali_setup_dma(denali, DENALI_READ);
1289
1290 /* wait for operation to complete */
1291 irq_status = wait_for_irq(denali, irq_mask);
1292
1293 pci_dma_sync_single_for_cpu(pci_dev, addr, size, PCI_DMA_FROMDEVICE);
1294
1295 denali_enable_dma(denali, false);
1296
1297 memcpy(buf, denali->buf.buf, mtd->writesize);
1298 memcpy(chip->oob_poi, denali->buf.buf + mtd->writesize, mtd->oobsize);
1299
1300 return 0;
1301 }
1302
1303 static uint8_t denali_read_byte(struct mtd_info *mtd)
1304 {
1305 struct denali_nand_info *denali = mtd_to_denali(mtd);
1306 uint8_t result = 0xff;
1307
1308 if (denali->buf.head < denali->buf.tail)
1309 result = denali->buf.buf[denali->buf.head++];
1310
1311 #if DEBUG_DENALI
1312 printk(KERN_INFO "read byte -> 0x%02x\n", result);
1313 #endif
1314 return result;
1315 }
1316
1317 static void denali_select_chip(struct mtd_info *mtd, int chip)
1318 {
1319 struct denali_nand_info *denali = mtd_to_denali(mtd);
1320 #if DEBUG_DENALI
1321 printk(KERN_INFO "denali select chip %d\n", chip);
1322 #endif
1323 spin_lock_irq(&denali->irq_lock);
1324 denali->flash_bank = chip;
1325 spin_unlock_irq(&denali->irq_lock);
1326 }
1327
1328 static int denali_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
1329 {
1330 struct denali_nand_info *denali = mtd_to_denali(mtd);
1331 int status = denali->status;
1332 denali->status = 0;
1333
1334 #if DEBUG_DENALI
1335 printk(KERN_INFO "waitfunc %d\n", status);
1336 #endif
1337 return status;
1338 }
1339
1340 static void denali_erase(struct mtd_info *mtd, int page)
1341 {
1342 struct denali_nand_info *denali = mtd_to_denali(mtd);
1343
1344 uint32_t cmd = 0x0, irq_status = 0;
1345
1346 #if DEBUG_DENALI
1347 printk(KERN_INFO "erase page: %d\n", page);
1348 #endif
1349 /* clear interrupts */
1350 clear_interrupts(denali);
1351
1352 /* setup page read request for access type */
1353 cmd = MODE_10 | BANK(denali->flash_bank) | page;
1354 index_addr(denali, (uint32_t)cmd, 0x1);
1355
1356 /* wait for erase to complete or failure to occur */
1357 irq_status = wait_for_irq(denali, INTR_STATUS0__ERASE_COMP |
1358 INTR_STATUS0__ERASE_FAIL);
1359
1360 denali->status = (irq_status & INTR_STATUS0__ERASE_FAIL) ?
1361 NAND_STATUS_FAIL : PASS;
1362 }
1363
1364 static void denali_cmdfunc(struct mtd_info *mtd, unsigned int cmd, int col,
1365 int page)
1366 {
1367 struct denali_nand_info *denali = mtd_to_denali(mtd);
1368 uint32_t addr, id;
1369 int i;
1370
1371 #if DEBUG_DENALI
1372 printk(KERN_INFO "cmdfunc: 0x%x %d %d\n", cmd, col, page);
1373 #endif
1374 switch (cmd) {
1375 case NAND_CMD_PAGEPROG:
1376 break;
1377 case NAND_CMD_STATUS:
1378 read_status(denali);
1379 break;
1380 case NAND_CMD_READID:
1381 reset_buf(denali);
1382 /*sometimes ManufactureId read from register is not right
1383 * e.g. some of Micron MT29F32G08QAA MLC NAND chips
1384 * So here we send READID cmd to NAND insteand
1385 * */
1386 addr = (uint32_t)MODE_11 | BANK(denali->flash_bank);
1387 index_addr(denali, (uint32_t)addr | 0, 0x90);
1388 index_addr(denali, (uint32_t)addr | 1, 0);
1389 for (i = 0; i < 5; i++) {
1390 index_addr_read_data(denali,
1391 (uint32_t)addr | 2,
1392 &id);
1393 write_byte_to_buf(denali, id);
1394 }
1395 break;
1396 case NAND_CMD_READ0:
1397 case NAND_CMD_SEQIN:
1398 denali->page = page;
1399 break;
1400 case NAND_CMD_RESET:
1401 reset_bank(denali);
1402 break;
1403 case NAND_CMD_READOOB:
1404 /* TODO: Read OOB data */
1405 break;
1406 default:
1407 printk(KERN_ERR ": unsupported command"
1408 " received 0x%x\n", cmd);
1409 break;
1410 }
1411 }
1412
1413 /* stubs for ECC functions not used by the NAND core */
1414 static int denali_ecc_calculate(struct mtd_info *mtd, const uint8_t *data,
1415 uint8_t *ecc_code)
1416 {
1417 printk(KERN_ERR "denali_ecc_calculate called unexpectedly\n");
1418 BUG();
1419 return -EIO;
1420 }
1421
1422 static int denali_ecc_correct(struct mtd_info *mtd, uint8_t *data,
1423 uint8_t *read_ecc, uint8_t *calc_ecc)
1424 {
1425 printk(KERN_ERR "denali_ecc_correct called unexpectedly\n");
1426 BUG();
1427 return -EIO;
1428 }
1429
1430 static void denali_ecc_hwctl(struct mtd_info *mtd, int mode)
1431 {
1432 printk(KERN_ERR "denali_ecc_hwctl called unexpectedly\n");
1433 BUG();
1434 }
1435 /* end NAND core entry points */
1436
1437 /* Initialization code to bring the device up to a known good state */
1438 static void denali_hw_init(struct denali_nand_info *denali)
1439 {
1440 /* tell driver how many bit controller will skip before
1441 * writing ECC code in OOB, this register may be already
1442 * set by firmware. So we read this value out.
1443 * if this value is 0, just let it be.
1444 * */
1445 denali->bbtskipbytes = ioread32(denali->flash_reg +
1446 SPARE_AREA_SKIP_BYTES);
1447 denali_irq_init(denali);
1448 denali_nand_reset(denali);
1449 iowrite32(0x0F, denali->flash_reg + RB_PIN_ENABLED);
1450 iowrite32(CHIP_EN_DONT_CARE__FLAG,
1451 denali->flash_reg + CHIP_ENABLE_DONT_CARE);
1452
1453 iowrite32(0x0, denali->flash_reg + SPARE_AREA_SKIP_BYTES);
1454 iowrite32(0xffff, denali->flash_reg + SPARE_AREA_MARKER);
1455
1456 /* Should set value for these registers when init */
1457 iowrite32(0, denali->flash_reg + TWO_ROW_ADDR_CYCLES);
1458 iowrite32(1, denali->flash_reg + ECC_ENABLE);
1459 }
1460
1461 /* Althogh controller spec said SLC ECC is forceb to be 4bit,
1462 * but denali controller in MRST only support 15bit and 8bit ECC
1463 * correction
1464 * */
1465 #define ECC_8BITS 14
1466 static struct nand_ecclayout nand_8bit_oob = {
1467 .eccbytes = 14,
1468 };
1469
1470 #define ECC_15BITS 26
1471 static struct nand_ecclayout nand_15bit_oob = {
1472 .eccbytes = 26,
1473 };
1474
1475 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
1476 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
1477
1478 static struct nand_bbt_descr bbt_main_descr = {
1479 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1480 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1481 .offs = 8,
1482 .len = 4,
1483 .veroffs = 12,
1484 .maxblocks = 4,
1485 .pattern = bbt_pattern,
1486 };
1487
1488 static struct nand_bbt_descr bbt_mirror_descr = {
1489 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1490 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1491 .offs = 8,
1492 .len = 4,
1493 .veroffs = 12,
1494 .maxblocks = 4,
1495 .pattern = mirror_pattern,
1496 };
1497
1498 /* initialize driver data structures */
1499 void denali_drv_init(struct denali_nand_info *denali)
1500 {
1501 denali->idx = 0;
1502
1503 /* setup interrupt handler */
1504 /* the completion object will be used to notify
1505 * the callee that the interrupt is done */
1506 init_completion(&denali->complete);
1507
1508 /* the spinlock will be used to synchronize the ISR
1509 * with any element that might be access shared
1510 * data (interrupt status) */
1511 spin_lock_init(&denali->irq_lock);
1512
1513 /* indicate that MTD has not selected a valid bank yet */
1514 denali->flash_bank = CHIP_SELECT_INVALID;
1515
1516 /* initialize our irq_status variable to indicate no interrupts */
1517 denali->irq_status = 0;
1518 }
1519
1520 /* driver entry point */
1521 static int denali_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
1522 {
1523 int ret = -ENODEV;
1524 resource_size_t csr_base, mem_base;
1525 unsigned long csr_len, mem_len;
1526 struct denali_nand_info *denali;
1527
1528 nand_dbg_print(NAND_DBG_TRACE, "%s, Line %d, Function: %s\n",
1529 __FILE__, __LINE__, __func__);
1530
1531 denali = kzalloc(sizeof(*denali), GFP_KERNEL);
1532 if (!denali)
1533 return -ENOMEM;
1534
1535 ret = pci_enable_device(dev);
1536 if (ret) {
1537 printk(KERN_ERR "Spectra: pci_enable_device failed.\n");
1538 goto failed_alloc_memery;
1539 }
1540
1541 if (id->driver_data == INTEL_CE4100) {
1542 /* Due to a silicon limitation, we can only support
1543 * ONFI timing mode 1 and below.
1544 */
1545 if (onfi_timing_mode < -1 || onfi_timing_mode > 1) {
1546 printk(KERN_ERR "Intel CE4100 only supports"
1547 " ONFI timing mode 1 or below\n");
1548 ret = -EINVAL;
1549 goto failed_enable_dev;
1550 }
1551 denali->platform = INTEL_CE4100;
1552 mem_base = pci_resource_start(dev, 0);
1553 mem_len = pci_resource_len(dev, 1);
1554 csr_base = pci_resource_start(dev, 1);
1555 csr_len = pci_resource_len(dev, 1);
1556 } else {
1557 denali->platform = INTEL_MRST;
1558 csr_base = pci_resource_start(dev, 0);
1559 csr_len = pci_resource_len(dev, 0);
1560 mem_base = pci_resource_start(dev, 1);
1561 mem_len = pci_resource_len(dev, 1);
1562 if (!mem_len) {
1563 mem_base = csr_base + csr_len;
1564 mem_len = csr_len;
1565 nand_dbg_print(NAND_DBG_WARN,
1566 "Spectra: No second"
1567 " BAR for PCI device;"
1568 " assuming %08Lx\n",
1569 (uint64_t)csr_base);
1570 }
1571 }
1572
1573 /* Is 32-bit DMA supported? */
1574 ret = pci_set_dma_mask(dev, DMA_BIT_MASK(32));
1575
1576 if (ret) {
1577 printk(KERN_ERR "Spectra: no usable DMA configuration\n");
1578 goto failed_enable_dev;
1579 }
1580 denali->buf.dma_buf =
1581 pci_map_single(dev, denali->buf.buf,
1582 DENALI_BUF_SIZE,
1583 PCI_DMA_BIDIRECTIONAL);
1584
1585 if (pci_dma_mapping_error(dev, denali->buf.dma_buf)) {
1586 printk(KERN_ERR "Spectra: failed to map DMA buffer\n");
1587 goto failed_enable_dev;
1588 }
1589
1590 pci_set_master(dev);
1591 denali->dev = dev;
1592
1593 ret = pci_request_regions(dev, DENALI_NAND_NAME);
1594 if (ret) {
1595 printk(KERN_ERR "Spectra: Unable to request memory regions\n");
1596 goto failed_dma_map;
1597 }
1598
1599 denali->flash_reg = ioremap_nocache(csr_base, csr_len);
1600 if (!denali->flash_reg) {
1601 printk(KERN_ERR "Spectra: Unable to remap memory region\n");
1602 ret = -ENOMEM;
1603 goto failed_req_regions;
1604 }
1605 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: CSR 0x%08Lx -> 0x%p (0x%lx)\n",
1606 (uint64_t)csr_base, denali->flash_reg, csr_len);
1607
1608 denali->flash_mem = ioremap_nocache(mem_base, mem_len);
1609 if (!denali->flash_mem) {
1610 printk(KERN_ERR "Spectra: ioremap_nocache failed!");
1611 ret = -ENOMEM;
1612 goto failed_remap_reg;
1613 }
1614
1615 nand_dbg_print(NAND_DBG_WARN,
1616 "Spectra: Remapped flash base address: "
1617 "0x%p, len: %ld\n",
1618 denali->flash_mem, csr_len);
1619
1620 denali_hw_init(denali);
1621 denali_drv_init(denali);
1622
1623 nand_dbg_print(NAND_DBG_DEBUG, "Spectra: IRQ %d\n", dev->irq);
1624 if (request_irq(dev->irq, denali_isr, IRQF_SHARED,
1625 DENALI_NAND_NAME, denali)) {
1626 printk(KERN_ERR "Spectra: Unable to allocate IRQ\n");
1627 ret = -ENODEV;
1628 goto failed_remap_mem;
1629 }
1630
1631 /* now that our ISR is registered, we can enable interrupts */
1632 denali_set_intr_modes(denali, true);
1633
1634 pci_set_drvdata(dev, denali);
1635
1636 denali_nand_timing_set(denali);
1637
1638 nand_dbg_print(NAND_DBG_DEBUG, "Dump timing register values:"
1639 "acc_clks: %d, re_2_we: %d, we_2_re: %d,"
1640 "addr_2_data: %d, rdwr_en_lo_cnt: %d, "
1641 "rdwr_en_hi_cnt: %d, cs_setup_cnt: %d\n",
1642 ioread32(denali->flash_reg + ACC_CLKS),
1643 ioread32(denali->flash_reg + RE_2_WE),
1644 ioread32(denali->flash_reg + WE_2_RE),
1645 ioread32(denali->flash_reg + ADDR_2_DATA),
1646 ioread32(denali->flash_reg + RDWR_EN_LO_CNT),
1647 ioread32(denali->flash_reg + RDWR_EN_HI_CNT),
1648 ioread32(denali->flash_reg + CS_SETUP_CNT));
1649
1650 denali->mtd.name = "Denali NAND";
1651 denali->mtd.owner = THIS_MODULE;
1652 denali->mtd.priv = &denali->nand;
1653
1654 /* register the driver with the NAND core subsystem */
1655 denali->nand.select_chip = denali_select_chip;
1656 denali->nand.cmdfunc = denali_cmdfunc;
1657 denali->nand.read_byte = denali_read_byte;
1658 denali->nand.waitfunc = denali_waitfunc;
1659
1660 /* scan for NAND devices attached to the controller
1661 * this is the first stage in a two step process to register
1662 * with the nand subsystem */
1663 if (nand_scan_ident(&denali->mtd, LLD_MAX_FLASH_BANKS, NULL)) {
1664 ret = -ENXIO;
1665 goto failed_req_irq;
1666 }
1667
1668 /* MTD supported page sizes vary by kernel. We validate our
1669 * kernel supports the device here.
1670 */
1671 if (denali->mtd.writesize > NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE) {
1672 ret = -ENODEV;
1673 printk(KERN_ERR "Spectra: device size not supported by this "
1674 "version of MTD.");
1675 goto failed_req_irq;
1676 }
1677
1678 /* support for multi nand
1679 * MTD known nothing about multi nand,
1680 * so we should tell it the real pagesize
1681 * and anything necessery
1682 */
1683 denali->devnum = ioread32(denali->flash_reg + DEVICES_CONNECTED);
1684 denali->nand.chipsize <<= (denali->devnum - 1);
1685 denali->nand.page_shift += (denali->devnum - 1);
1686 denali->nand.pagemask = (denali->nand.chipsize >>
1687 denali->nand.page_shift) - 1;
1688 denali->nand.bbt_erase_shift += (denali->devnum - 1);
1689 denali->nand.phys_erase_shift = denali->nand.bbt_erase_shift;
1690 denali->nand.chip_shift += (denali->devnum - 1);
1691 denali->mtd.writesize <<= (denali->devnum - 1);
1692 denali->mtd.oobsize <<= (denali->devnum - 1);
1693 denali->mtd.erasesize <<= (denali->devnum - 1);
1694 denali->mtd.size = denali->nand.numchips * denali->nand.chipsize;
1695 denali->bbtskipbytes *= denali->devnum;
1696
1697 /* second stage of the NAND scan
1698 * this stage requires information regarding ECC and
1699 * bad block management. */
1700
1701 /* Bad block management */
1702 denali->nand.bbt_td = &bbt_main_descr;
1703 denali->nand.bbt_md = &bbt_mirror_descr;
1704
1705 /* skip the scan for now until we have OOB read and write support */
1706 denali->nand.options |= NAND_USE_FLASH_BBT | NAND_SKIP_BBTSCAN;
1707 denali->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
1708
1709 /* Denali Controller only support 15bit and 8bit ECC in MRST,
1710 * so just let controller do 15bit ECC for MLC and 8bit ECC for
1711 * SLC if possible.
1712 * */
1713 if (denali->nand.cellinfo & 0xc &&
1714 (denali->mtd.oobsize > (denali->bbtskipbytes +
1715 ECC_15BITS * (denali->mtd.writesize /
1716 ECC_SECTOR_SIZE)))) {
1717 /* if MLC OOB size is large enough, use 15bit ECC*/
1718 denali->nand.ecc.layout = &nand_15bit_oob;
1719 denali->nand.ecc.bytes = ECC_15BITS;
1720 iowrite32(15, denali->flash_reg + ECC_CORRECTION);
1721 } else if (denali->mtd.oobsize < (denali->bbtskipbytes +
1722 ECC_8BITS * (denali->mtd.writesize /
1723 ECC_SECTOR_SIZE))) {
1724 printk(KERN_ERR "Your NAND chip OOB is not large enough to"
1725 " contain 8bit ECC correction codes");
1726 goto failed_req_irq;
1727 } else {
1728 denali->nand.ecc.layout = &nand_8bit_oob;
1729 denali->nand.ecc.bytes = ECC_8BITS;
1730 iowrite32(8, denali->flash_reg + ECC_CORRECTION);
1731 }
1732
1733 denali->nand.ecc.bytes *= denali->devnum;
1734 denali->nand.ecc.layout->eccbytes *=
1735 denali->mtd.writesize / ECC_SECTOR_SIZE;
1736 denali->nand.ecc.layout->oobfree[0].offset =
1737 denali->bbtskipbytes + denali->nand.ecc.layout->eccbytes;
1738 denali->nand.ecc.layout->oobfree[0].length =
1739 denali->mtd.oobsize - denali->nand.ecc.layout->eccbytes -
1740 denali->bbtskipbytes;
1741
1742 /* Let driver know the total blocks number and
1743 * how many blocks contained by each nand chip.
1744 * blksperchip will help driver to know how many
1745 * blocks is taken by FW.
1746 * */
1747 denali->totalblks = denali->mtd.size >>
1748 denali->nand.phys_erase_shift;
1749 denali->blksperchip = denali->totalblks / denali->nand.numchips;
1750
1751 /* These functions are required by the NAND core framework, otherwise,
1752 * the NAND core will assert. However, we don't need them, so we'll stub
1753 * them out. */
1754 denali->nand.ecc.calculate = denali_ecc_calculate;
1755 denali->nand.ecc.correct = denali_ecc_correct;
1756 denali->nand.ecc.hwctl = denali_ecc_hwctl;
1757
1758 /* override the default read operations */
1759 denali->nand.ecc.size = ECC_SECTOR_SIZE * denali->devnum;
1760 denali->nand.ecc.read_page = denali_read_page;
1761 denali->nand.ecc.read_page_raw = denali_read_page_raw;
1762 denali->nand.ecc.write_page = denali_write_page;
1763 denali->nand.ecc.write_page_raw = denali_write_page_raw;
1764 denali->nand.ecc.read_oob = denali_read_oob;
1765 denali->nand.ecc.write_oob = denali_write_oob;
1766 denali->nand.erase_cmd = denali_erase;
1767
1768 if (nand_scan_tail(&denali->mtd)) {
1769 ret = -ENXIO;
1770 goto failed_req_irq;
1771 }
1772
1773 ret = add_mtd_device(&denali->mtd);
1774 if (ret) {
1775 printk(KERN_ERR "Spectra: Failed to register"
1776 " MTD device: %d\n", ret);
1777 goto failed_req_irq;
1778 }
1779 return 0;
1780
1781 failed_req_irq:
1782 denali_irq_cleanup(dev->irq, denali);
1783 failed_remap_mem:
1784 iounmap(denali->flash_mem);
1785 failed_remap_reg:
1786 iounmap(denali->flash_reg);
1787 failed_req_regions:
1788 pci_release_regions(dev);
1789 failed_dma_map:
1790 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1791 PCI_DMA_BIDIRECTIONAL);
1792 failed_enable_dev:
1793 pci_disable_device(dev);
1794 failed_alloc_memery:
1795 kfree(denali);
1796 return ret;
1797 }
1798
1799 /* driver exit point */
1800 static void denali_pci_remove(struct pci_dev *dev)
1801 {
1802 struct denali_nand_info *denali = pci_get_drvdata(dev);
1803
1804 nand_dbg_print(NAND_DBG_WARN, "%s, Line %d, Function: %s\n",
1805 __FILE__, __LINE__, __func__);
1806
1807 nand_release(&denali->mtd);
1808 del_mtd_device(&denali->mtd);
1809
1810 denali_irq_cleanup(dev->irq, denali);
1811
1812 iounmap(denali->flash_reg);
1813 iounmap(denali->flash_mem);
1814 pci_release_regions(dev);
1815 pci_disable_device(dev);
1816 pci_unmap_single(dev, denali->buf.dma_buf, DENALI_BUF_SIZE,
1817 PCI_DMA_BIDIRECTIONAL);
1818 pci_set_drvdata(dev, NULL);
1819 kfree(denali);
1820 }
1821
1822 MODULE_DEVICE_TABLE(pci, denali_pci_ids);
1823
1824 static struct pci_driver denali_pci_driver = {
1825 .name = DENALI_NAND_NAME,
1826 .id_table = denali_pci_ids,
1827 .probe = denali_pci_probe,
1828 .remove = denali_pci_remove,
1829 };
1830
1831 static int __devinit denali_init(void)
1832 {
1833 printk(KERN_INFO "Spectra MTD driver built on %s @ %s\n",
1834 __DATE__, __TIME__);
1835 return pci_register_driver(&denali_pci_driver);
1836 }
1837
1838 /* Free memory */
1839 static void __devexit denali_exit(void)
1840 {
1841 pci_unregister_driver(&denali_pci_driver);
1842 }
1843
1844 module_init(denali_init);
1845 module_exit(denali_exit);
Linux kernel - Deliverables
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