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mtd: nand: make use of mtd_to_nand() in NAND drivers
[deliverable/linux.git] / drivers / mtd / nand / fsl_ifc_nand.c
1 /*
2 * Freescale Integrated Flash Controller NAND driver
3 *
4 * Copyright 2011-2012 Freescale Semiconductor, Inc
5 *
6 * Author: Dipen Dudhat <Dipen.Dudhat@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 #include <linux/mtd/mtd.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/mtd/partitions.h>
31 #include <linux/mtd/nand_ecc.h>
32 #include <linux/fsl_ifc.h>
33
34 #define ERR_BYTE 0xFF /* Value returned for read
35 bytes when read failed */
36 #define IFC_TIMEOUT_MSECS 500 /* Maximum number of mSecs to wait
37 for IFC NAND Machine */
38
39 struct fsl_ifc_ctrl;
40
41 /* mtd information per set */
42 struct fsl_ifc_mtd {
43 struct mtd_info mtd;
44 struct nand_chip chip;
45 struct fsl_ifc_ctrl *ctrl;
46
47 struct device *dev;
48 int bank; /* Chip select bank number */
49 unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
50 u8 __iomem *vbase; /* Chip select base virtual address */
51 };
52
53 /* overview of the fsl ifc controller */
54 struct fsl_ifc_nand_ctrl {
55 struct nand_hw_control controller;
56 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
57
58 void __iomem *addr; /* Address of assigned IFC buffer */
59 unsigned int page; /* Last page written to / read from */
60 unsigned int read_bytes;/* Number of bytes read during command */
61 unsigned int column; /* Saved column from SEQIN */
62 unsigned int index; /* Pointer to next byte to 'read' */
63 unsigned int oob; /* Non zero if operating on OOB data */
64 unsigned int eccread; /* Non zero for a full-page ECC read */
65 unsigned int counter; /* counter for the initializations */
66 unsigned int max_bitflips; /* Saved during READ0 cmd */
67 };
68
69 static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
70
71 /* 512-byte page with 4-bit ECC, 8-bit */
72 static struct nand_ecclayout oob_512_8bit_ecc4 = {
73 .eccbytes = 8,
74 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
75 .oobfree = { {0, 5}, {6, 2} },
76 };
77
78 /* 512-byte page with 4-bit ECC, 16-bit */
79 static struct nand_ecclayout oob_512_16bit_ecc4 = {
80 .eccbytes = 8,
81 .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
82 .oobfree = { {2, 6}, },
83 };
84
85 /* 2048-byte page size with 4-bit ECC */
86 static struct nand_ecclayout oob_2048_ecc4 = {
87 .eccbytes = 32,
88 .eccpos = {
89 8, 9, 10, 11, 12, 13, 14, 15,
90 16, 17, 18, 19, 20, 21, 22, 23,
91 24, 25, 26, 27, 28, 29, 30, 31,
92 32, 33, 34, 35, 36, 37, 38, 39,
93 },
94 .oobfree = { {2, 6}, {40, 24} },
95 };
96
97 /* 4096-byte page size with 4-bit ECC */
98 static struct nand_ecclayout oob_4096_ecc4 = {
99 .eccbytes = 64,
100 .eccpos = {
101 8, 9, 10, 11, 12, 13, 14, 15,
102 16, 17, 18, 19, 20, 21, 22, 23,
103 24, 25, 26, 27, 28, 29, 30, 31,
104 32, 33, 34, 35, 36, 37, 38, 39,
105 40, 41, 42, 43, 44, 45, 46, 47,
106 48, 49, 50, 51, 52, 53, 54, 55,
107 56, 57, 58, 59, 60, 61, 62, 63,
108 64, 65, 66, 67, 68, 69, 70, 71,
109 },
110 .oobfree = { {2, 6}, {72, 56} },
111 };
112
113 /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
114 static struct nand_ecclayout oob_4096_ecc8 = {
115 .eccbytes = 128,
116 .eccpos = {
117 8, 9, 10, 11, 12, 13, 14, 15,
118 16, 17, 18, 19, 20, 21, 22, 23,
119 24, 25, 26, 27, 28, 29, 30, 31,
120 32, 33, 34, 35, 36, 37, 38, 39,
121 40, 41, 42, 43, 44, 45, 46, 47,
122 48, 49, 50, 51, 52, 53, 54, 55,
123 56, 57, 58, 59, 60, 61, 62, 63,
124 64, 65, 66, 67, 68, 69, 70, 71,
125 72, 73, 74, 75, 76, 77, 78, 79,
126 80, 81, 82, 83, 84, 85, 86, 87,
127 88, 89, 90, 91, 92, 93, 94, 95,
128 96, 97, 98, 99, 100, 101, 102, 103,
129 104, 105, 106, 107, 108, 109, 110, 111,
130 112, 113, 114, 115, 116, 117, 118, 119,
131 120, 121, 122, 123, 124, 125, 126, 127,
132 128, 129, 130, 131, 132, 133, 134, 135,
133 },
134 .oobfree = { {2, 6}, {136, 82} },
135 };
136
137 /* 8192-byte page size with 4-bit ECC */
138 static struct nand_ecclayout oob_8192_ecc4 = {
139 .eccbytes = 128,
140 .eccpos = {
141 8, 9, 10, 11, 12, 13, 14, 15,
142 16, 17, 18, 19, 20, 21, 22, 23,
143 24, 25, 26, 27, 28, 29, 30, 31,
144 32, 33, 34, 35, 36, 37, 38, 39,
145 40, 41, 42, 43, 44, 45, 46, 47,
146 48, 49, 50, 51, 52, 53, 54, 55,
147 56, 57, 58, 59, 60, 61, 62, 63,
148 64, 65, 66, 67, 68, 69, 70, 71,
149 72, 73, 74, 75, 76, 77, 78, 79,
150 80, 81, 82, 83, 84, 85, 86, 87,
151 88, 89, 90, 91, 92, 93, 94, 95,
152 96, 97, 98, 99, 100, 101, 102, 103,
153 104, 105, 106, 107, 108, 109, 110, 111,
154 112, 113, 114, 115, 116, 117, 118, 119,
155 120, 121, 122, 123, 124, 125, 126, 127,
156 128, 129, 130, 131, 132, 133, 134, 135,
157 },
158 .oobfree = { {2, 6}, {136, 208} },
159 };
160
161 /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
162 static struct nand_ecclayout oob_8192_ecc8 = {
163 .eccbytes = 256,
164 .eccpos = {
165 8, 9, 10, 11, 12, 13, 14, 15,
166 16, 17, 18, 19, 20, 21, 22, 23,
167 24, 25, 26, 27, 28, 29, 30, 31,
168 32, 33, 34, 35, 36, 37, 38, 39,
169 40, 41, 42, 43, 44, 45, 46, 47,
170 48, 49, 50, 51, 52, 53, 54, 55,
171 56, 57, 58, 59, 60, 61, 62, 63,
172 64, 65, 66, 67, 68, 69, 70, 71,
173 72, 73, 74, 75, 76, 77, 78, 79,
174 80, 81, 82, 83, 84, 85, 86, 87,
175 88, 89, 90, 91, 92, 93, 94, 95,
176 96, 97, 98, 99, 100, 101, 102, 103,
177 104, 105, 106, 107, 108, 109, 110, 111,
178 112, 113, 114, 115, 116, 117, 118, 119,
179 120, 121, 122, 123, 124, 125, 126, 127,
180 128, 129, 130, 131, 132, 133, 134, 135,
181 136, 137, 138, 139, 140, 141, 142, 143,
182 144, 145, 146, 147, 148, 149, 150, 151,
183 152, 153, 154, 155, 156, 157, 158, 159,
184 160, 161, 162, 163, 164, 165, 166, 167,
185 168, 169, 170, 171, 172, 173, 174, 175,
186 176, 177, 178, 179, 180, 181, 182, 183,
187 184, 185, 186, 187, 188, 189, 190, 191,
188 192, 193, 194, 195, 196, 197, 198, 199,
189 200, 201, 202, 203, 204, 205, 206, 207,
190 208, 209, 210, 211, 212, 213, 214, 215,
191 216, 217, 218, 219, 220, 221, 222, 223,
192 224, 225, 226, 227, 228, 229, 230, 231,
193 232, 233, 234, 235, 236, 237, 238, 239,
194 240, 241, 242, 243, 244, 245, 246, 247,
195 248, 249, 250, 251, 252, 253, 254, 255,
196 256, 257, 258, 259, 260, 261, 262, 263,
197 },
198 .oobfree = { {2, 6}, {264, 80} },
199 };
200
201 /*
202 * Generic flash bbt descriptors
203 */
204 static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
205 static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
206
207 static struct nand_bbt_descr bbt_main_descr = {
208 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
209 NAND_BBT_2BIT | NAND_BBT_VERSION,
210 .offs = 2, /* 0 on 8-bit small page */
211 .len = 4,
212 .veroffs = 6,
213 .maxblocks = 4,
214 .pattern = bbt_pattern,
215 };
216
217 static struct nand_bbt_descr bbt_mirror_descr = {
218 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
219 NAND_BBT_2BIT | NAND_BBT_VERSION,
220 .offs = 2, /* 0 on 8-bit small page */
221 .len = 4,
222 .veroffs = 6,
223 .maxblocks = 4,
224 .pattern = mirror_pattern,
225 };
226
227 /*
228 * Set up the IFC hardware block and page address fields, and the ifc nand
229 * structure addr field to point to the correct IFC buffer in memory
230 */
231 static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
232 {
233 struct nand_chip *chip = mtd_to_nand(mtd);
234 struct fsl_ifc_mtd *priv = chip->priv;
235 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
236 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
237 int buf_num;
238
239 ifc_nand_ctrl->page = page_addr;
240 /* Program ROW0/COL0 */
241 ifc_out32(page_addr, &ifc->ifc_nand.row0);
242 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
243
244 buf_num = page_addr & priv->bufnum_mask;
245
246 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
247 ifc_nand_ctrl->index = column;
248
249 /* for OOB data point to the second half of the buffer */
250 if (oob)
251 ifc_nand_ctrl->index += mtd->writesize;
252 }
253
254 static int is_blank(struct mtd_info *mtd, unsigned int bufnum)
255 {
256 struct nand_chip *chip = mtd_to_nand(mtd);
257 struct fsl_ifc_mtd *priv = chip->priv;
258 u8 __iomem *addr = priv->vbase + bufnum * (mtd->writesize * 2);
259 u32 __iomem *mainarea = (u32 __iomem *)addr;
260 u8 __iomem *oob = addr + mtd->writesize;
261 int i;
262
263 for (i = 0; i < mtd->writesize / 4; i++) {
264 if (__raw_readl(&mainarea[i]) != 0xffffffff)
265 return 0;
266 }
267
268 for (i = 0; i < chip->ecc.layout->eccbytes; i++) {
269 int pos = chip->ecc.layout->eccpos[i];
270
271 if (__raw_readb(&oob[pos]) != 0xff)
272 return 0;
273 }
274
275 return 1;
276 }
277
278 /* returns nonzero if entire page is blank */
279 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
280 u32 *eccstat, unsigned int bufnum)
281 {
282 u32 reg = eccstat[bufnum / 4];
283 int errors;
284
285 errors = (reg >> ((3 - bufnum % 4) * 8)) & 15;
286
287 return errors;
288 }
289
290 /*
291 * execute IFC NAND command and wait for it to complete
292 */
293 static void fsl_ifc_run_command(struct mtd_info *mtd)
294 {
295 struct nand_chip *chip = mtd_to_nand(mtd);
296 struct fsl_ifc_mtd *priv = chip->priv;
297 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
298 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
299 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
300 u32 eccstat[4];
301 int i;
302
303 /* set the chip select for NAND Transaction */
304 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
305 &ifc->ifc_nand.nand_csel);
306
307 dev_vdbg(priv->dev,
308 "%s: fir0=%08x fcr0=%08x\n",
309 __func__,
310 ifc_in32(&ifc->ifc_nand.nand_fir0),
311 ifc_in32(&ifc->ifc_nand.nand_fcr0));
312
313 ctrl->nand_stat = 0;
314
315 /* start read/write seq */
316 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
317
318 /* wait for command complete flag or timeout */
319 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
320 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
321
322 /* ctrl->nand_stat will be updated from IRQ context */
323 if (!ctrl->nand_stat)
324 dev_err(priv->dev, "Controller is not responding\n");
325 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
326 dev_err(priv->dev, "NAND Flash Timeout Error\n");
327 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
328 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
329
330 nctrl->max_bitflips = 0;
331
332 if (nctrl->eccread) {
333 int errors;
334 int bufnum = nctrl->page & priv->bufnum_mask;
335 int sector = bufnum * chip->ecc.steps;
336 int sector_end = sector + chip->ecc.steps - 1;
337
338 for (i = sector / 4; i <= sector_end / 4; i++)
339 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
340
341 for (i = sector; i <= sector_end; i++) {
342 errors = check_read_ecc(mtd, ctrl, eccstat, i);
343
344 if (errors == 15) {
345 /*
346 * Uncorrectable error.
347 * OK only if the whole page is blank.
348 *
349 * We disable ECCER reporting due to...
350 * erratum IFC-A002770 -- so report it now if we
351 * see an uncorrectable error in ECCSTAT.
352 */
353 if (!is_blank(mtd, bufnum))
354 ctrl->nand_stat |=
355 IFC_NAND_EVTER_STAT_ECCER;
356 break;
357 }
358
359 mtd->ecc_stats.corrected += errors;
360 nctrl->max_bitflips = max_t(unsigned int,
361 nctrl->max_bitflips,
362 errors);
363 }
364
365 nctrl->eccread = 0;
366 }
367 }
368
369 static void fsl_ifc_do_read(struct nand_chip *chip,
370 int oob,
371 struct mtd_info *mtd)
372 {
373 struct fsl_ifc_mtd *priv = chip->priv;
374 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
375 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
376
377 /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
378 if (mtd->writesize > 512) {
379 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
380 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
381 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
382 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
383 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
384 &ifc->ifc_nand.nand_fir0);
385 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
386
387 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
388 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
389 &ifc->ifc_nand.nand_fcr0);
390 } else {
391 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
392 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
393 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
394 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
395 &ifc->ifc_nand.nand_fir0);
396 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
397
398 if (oob)
399 ifc_out32(NAND_CMD_READOOB <<
400 IFC_NAND_FCR0_CMD0_SHIFT,
401 &ifc->ifc_nand.nand_fcr0);
402 else
403 ifc_out32(NAND_CMD_READ0 <<
404 IFC_NAND_FCR0_CMD0_SHIFT,
405 &ifc->ifc_nand.nand_fcr0);
406 }
407 }
408
409 /* cmdfunc send commands to the IFC NAND Machine */
410 static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
411 int column, int page_addr) {
412 struct nand_chip *chip = mtd_to_nand(mtd);
413 struct fsl_ifc_mtd *priv = chip->priv;
414 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
415 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
416
417 /* clear the read buffer */
418 ifc_nand_ctrl->read_bytes = 0;
419 if (command != NAND_CMD_PAGEPROG)
420 ifc_nand_ctrl->index = 0;
421
422 switch (command) {
423 /* READ0 read the entire buffer to use hardware ECC. */
424 case NAND_CMD_READ0:
425 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
426 set_addr(mtd, 0, page_addr, 0);
427
428 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
429 ifc_nand_ctrl->index += column;
430
431 if (chip->ecc.mode == NAND_ECC_HW)
432 ifc_nand_ctrl->eccread = 1;
433
434 fsl_ifc_do_read(chip, 0, mtd);
435 fsl_ifc_run_command(mtd);
436 return;
437
438 /* READOOB reads only the OOB because no ECC is performed. */
439 case NAND_CMD_READOOB:
440 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
441 set_addr(mtd, column, page_addr, 1);
442
443 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
444
445 fsl_ifc_do_read(chip, 1, mtd);
446 fsl_ifc_run_command(mtd);
447
448 return;
449
450 case NAND_CMD_READID:
451 case NAND_CMD_PARAM: {
452 int timing = IFC_FIR_OP_RB;
453 if (command == NAND_CMD_PARAM)
454 timing = IFC_FIR_OP_RBCD;
455
456 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
457 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
458 (timing << IFC_NAND_FIR0_OP2_SHIFT),
459 &ifc->ifc_nand.nand_fir0);
460 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
461 &ifc->ifc_nand.nand_fcr0);
462 ifc_out32(column, &ifc->ifc_nand.row3);
463
464 /*
465 * although currently it's 8 bytes for READID, we always read
466 * the maximum 256 bytes(for PARAM)
467 */
468 ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
469 ifc_nand_ctrl->read_bytes = 256;
470
471 set_addr(mtd, 0, 0, 0);
472 fsl_ifc_run_command(mtd);
473 return;
474 }
475
476 /* ERASE1 stores the block and page address */
477 case NAND_CMD_ERASE1:
478 set_addr(mtd, 0, page_addr, 0);
479 return;
480
481 /* ERASE2 uses the block and page address from ERASE1 */
482 case NAND_CMD_ERASE2:
483 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
484 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
485 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
486 &ifc->ifc_nand.nand_fir0);
487
488 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
489 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
490 &ifc->ifc_nand.nand_fcr0);
491
492 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
493 ifc_nand_ctrl->read_bytes = 0;
494 fsl_ifc_run_command(mtd);
495 return;
496
497 /* SEQIN sets up the addr buffer and all registers except the length */
498 case NAND_CMD_SEQIN: {
499 u32 nand_fcr0;
500 ifc_nand_ctrl->column = column;
501 ifc_nand_ctrl->oob = 0;
502
503 if (mtd->writesize > 512) {
504 nand_fcr0 =
505 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
506 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
507 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
508
509 ifc_out32(
510 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
511 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
512 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
513 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
514 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
515 &ifc->ifc_nand.nand_fir0);
516 ifc_out32(
517 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
518 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
519 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
520 &ifc->ifc_nand.nand_fir1);
521 } else {
522 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
523 IFC_NAND_FCR0_CMD1_SHIFT) |
524 (NAND_CMD_SEQIN <<
525 IFC_NAND_FCR0_CMD2_SHIFT) |
526 (NAND_CMD_STATUS <<
527 IFC_NAND_FCR0_CMD3_SHIFT));
528
529 ifc_out32(
530 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
531 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
532 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
533 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
534 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
535 &ifc->ifc_nand.nand_fir0);
536 ifc_out32(
537 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
538 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
539 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
540 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
541 &ifc->ifc_nand.nand_fir1);
542
543 if (column >= mtd->writesize)
544 nand_fcr0 |=
545 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
546 else
547 nand_fcr0 |=
548 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
549 }
550
551 if (column >= mtd->writesize) {
552 /* OOB area --> READOOB */
553 column -= mtd->writesize;
554 ifc_nand_ctrl->oob = 1;
555 }
556 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
557 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
558 return;
559 }
560
561 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
562 case NAND_CMD_PAGEPROG: {
563 if (ifc_nand_ctrl->oob) {
564 ifc_out32(ifc_nand_ctrl->index -
565 ifc_nand_ctrl->column,
566 &ifc->ifc_nand.nand_fbcr);
567 } else {
568 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
569 }
570
571 fsl_ifc_run_command(mtd);
572 return;
573 }
574
575 case NAND_CMD_STATUS: {
576 void __iomem *addr;
577
578 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
579 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
580 &ifc->ifc_nand.nand_fir0);
581 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
582 &ifc->ifc_nand.nand_fcr0);
583 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
584 set_addr(mtd, 0, 0, 0);
585 ifc_nand_ctrl->read_bytes = 1;
586
587 fsl_ifc_run_command(mtd);
588
589 /*
590 * The chip always seems to report that it is
591 * write-protected, even when it is not.
592 */
593 addr = ifc_nand_ctrl->addr;
594 if (chip->options & NAND_BUSWIDTH_16)
595 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
596 else
597 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
598 return;
599 }
600
601 case NAND_CMD_RESET:
602 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
603 &ifc->ifc_nand.nand_fir0);
604 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
605 &ifc->ifc_nand.nand_fcr0);
606 fsl_ifc_run_command(mtd);
607 return;
608
609 default:
610 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
611 __func__, command);
612 }
613 }
614
615 static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
616 {
617 /* The hardware does not seem to support multiple
618 * chips per bank.
619 */
620 }
621
622 /*
623 * Write buf to the IFC NAND Controller Data Buffer
624 */
625 static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
626 {
627 struct nand_chip *chip = mtd_to_nand(mtd);
628 struct fsl_ifc_mtd *priv = chip->priv;
629 unsigned int bufsize = mtd->writesize + mtd->oobsize;
630
631 if (len <= 0) {
632 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
633 return;
634 }
635
636 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
637 dev_err(priv->dev,
638 "%s: beyond end of buffer (%d requested, %u available)\n",
639 __func__, len, bufsize - ifc_nand_ctrl->index);
640 len = bufsize - ifc_nand_ctrl->index;
641 }
642
643 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
644 ifc_nand_ctrl->index += len;
645 }
646
647 /*
648 * Read a byte from either the IFC hardware buffer
649 * read function for 8-bit buswidth
650 */
651 static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
652 {
653 struct nand_chip *chip = mtd_to_nand(mtd);
654 struct fsl_ifc_mtd *priv = chip->priv;
655 unsigned int offset;
656
657 /*
658 * If there are still bytes in the IFC buffer, then use the
659 * next byte.
660 */
661 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
662 offset = ifc_nand_ctrl->index++;
663 return ifc_in8(ifc_nand_ctrl->addr + offset);
664 }
665
666 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
667 return ERR_BYTE;
668 }
669
670 /*
671 * Read two bytes from the IFC hardware buffer
672 * read function for 16-bit buswith
673 */
674 static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
675 {
676 struct nand_chip *chip = mtd_to_nand(mtd);
677 struct fsl_ifc_mtd *priv = chip->priv;
678 uint16_t data;
679
680 /*
681 * If there are still bytes in the IFC buffer, then use the
682 * next byte.
683 */
684 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
685 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
686 ifc_nand_ctrl->index += 2;
687 return (uint8_t) data;
688 }
689
690 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
691 return ERR_BYTE;
692 }
693
694 /*
695 * Read from the IFC Controller Data Buffer
696 */
697 static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
698 {
699 struct nand_chip *chip = mtd_to_nand(mtd);
700 struct fsl_ifc_mtd *priv = chip->priv;
701 int avail;
702
703 if (len < 0) {
704 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
705 return;
706 }
707
708 avail = min((unsigned int)len,
709 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
710 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
711 ifc_nand_ctrl->index += avail;
712
713 if (len > avail)
714 dev_err(priv->dev,
715 "%s: beyond end of buffer (%d requested, %d available)\n",
716 __func__, len, avail);
717 }
718
719 /*
720 * This function is called after Program and Erase Operations to
721 * check for success or failure.
722 */
723 static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
724 {
725 struct fsl_ifc_mtd *priv = chip->priv;
726 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
727 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
728 u32 nand_fsr;
729
730 /* Use READ_STATUS command, but wait for the device to be ready */
731 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
732 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
733 &ifc->ifc_nand.nand_fir0);
734 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
735 &ifc->ifc_nand.nand_fcr0);
736 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
737 set_addr(mtd, 0, 0, 0);
738 ifc_nand_ctrl->read_bytes = 1;
739
740 fsl_ifc_run_command(mtd);
741
742 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
743
744 /*
745 * The chip always seems to report that it is
746 * write-protected, even when it is not.
747 */
748 return nand_fsr | NAND_STATUS_WP;
749 }
750
751 static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
752 uint8_t *buf, int oob_required, int page)
753 {
754 struct fsl_ifc_mtd *priv = chip->priv;
755 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
756 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
757
758 fsl_ifc_read_buf(mtd, buf, mtd->writesize);
759 if (oob_required)
760 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
761
762 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER)
763 dev_err(priv->dev, "NAND Flash ECC Uncorrectable Error\n");
764
765 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
766 mtd->ecc_stats.failed++;
767
768 return nctrl->max_bitflips;
769 }
770
771 /* ECC will be calculated automatically, and errors will be detected in
772 * waitfunc.
773 */
774 static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
775 const uint8_t *buf, int oob_required, int page)
776 {
777 fsl_ifc_write_buf(mtd, buf, mtd->writesize);
778 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
779
780 return 0;
781 }
782
783 static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
784 {
785 struct nand_chip *chip = mtd_to_nand(mtd);
786 struct fsl_ifc_mtd *priv = chip->priv;
787
788 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
789 chip->numchips);
790 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
791 chip->chipsize);
792 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
793 chip->pagemask);
794 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
795 chip->chip_delay);
796 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
797 chip->badblockpos);
798 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
799 chip->chip_shift);
800 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
801 chip->page_shift);
802 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
803 chip->phys_erase_shift);
804 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
805 chip->ecc.mode);
806 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
807 chip->ecc.steps);
808 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
809 chip->ecc.bytes);
810 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
811 chip->ecc.total);
812 dev_dbg(priv->dev, "%s: nand->ecc.layout = %p\n", __func__,
813 chip->ecc.layout);
814 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
815 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
816 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
817 mtd->erasesize);
818 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
819 mtd->writesize);
820 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
821 mtd->oobsize);
822
823 return 0;
824 }
825
826 static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
827 {
828 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
829 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
830 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
831 uint32_t cs = priv->bank;
832
833 /* Save CSOR and CSOR_ext */
834 csor = ifc_in32(&ifc->csor_cs[cs].csor);
835 csor_ext = ifc_in32(&ifc->csor_cs[cs].csor_ext);
836
837 /* chage PageSize 8K and SpareSize 1K*/
838 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
839 ifc_out32(csor_8k, &ifc->csor_cs[cs].csor);
840 ifc_out32(0x0000400, &ifc->csor_cs[cs].csor_ext);
841
842 /* READID */
843 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
844 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
845 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
846 &ifc->ifc_nand.nand_fir0);
847 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
848 &ifc->ifc_nand.nand_fcr0);
849 ifc_out32(0x0, &ifc->ifc_nand.row3);
850
851 ifc_out32(0x0, &ifc->ifc_nand.nand_fbcr);
852
853 /* Program ROW0/COL0 */
854 ifc_out32(0x0, &ifc->ifc_nand.row0);
855 ifc_out32(0x0, &ifc->ifc_nand.col0);
856
857 /* set the chip select for NAND Transaction */
858 ifc_out32(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
859
860 /* start read seq */
861 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
862
863 /* wait for command complete flag or timeout */
864 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
865 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
866
867 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
868 printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
869
870 /* Restore CSOR and CSOR_ext */
871 ifc_out32(csor, &ifc->csor_cs[cs].csor);
872 ifc_out32(csor_ext, &ifc->csor_cs[cs].csor_ext);
873 }
874
875 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
876 {
877 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
878 struct fsl_ifc_regs __iomem *ifc = ctrl->regs;
879 struct nand_chip *chip = &priv->chip;
880 struct nand_ecclayout *layout;
881 u32 csor;
882
883 /* Fill in fsl_ifc_mtd structure */
884 priv->mtd.priv = chip;
885 priv->mtd.dev.parent = priv->dev;
886 nand_set_flash_node(chip, priv->dev->of_node);
887
888 /* fill in nand_chip structure */
889 /* set up function call table */
890 if ((ifc_in32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
891 chip->read_byte = fsl_ifc_read_byte16;
892 else
893 chip->read_byte = fsl_ifc_read_byte;
894
895 chip->write_buf = fsl_ifc_write_buf;
896 chip->read_buf = fsl_ifc_read_buf;
897 chip->select_chip = fsl_ifc_select_chip;
898 chip->cmdfunc = fsl_ifc_cmdfunc;
899 chip->waitfunc = fsl_ifc_wait;
900
901 chip->bbt_td = &bbt_main_descr;
902 chip->bbt_md = &bbt_mirror_descr;
903
904 ifc_out32(0x0, &ifc->ifc_nand.ncfgr);
905
906 /* set up nand options */
907 chip->bbt_options = NAND_BBT_USE_FLASH;
908 chip->options = NAND_NO_SUBPAGE_WRITE;
909
910 if (ifc_in32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
911 chip->read_byte = fsl_ifc_read_byte16;
912 chip->options |= NAND_BUSWIDTH_16;
913 } else {
914 chip->read_byte = fsl_ifc_read_byte;
915 }
916
917 chip->controller = &ifc_nand_ctrl->controller;
918 chip->priv = priv;
919
920 chip->ecc.read_page = fsl_ifc_read_page;
921 chip->ecc.write_page = fsl_ifc_write_page;
922
923 csor = ifc_in32(&ifc->csor_cs[priv->bank].csor);
924
925 /* Hardware generates ECC per 512 Bytes */
926 chip->ecc.size = 512;
927 chip->ecc.bytes = 8;
928 chip->ecc.strength = 4;
929
930 switch (csor & CSOR_NAND_PGS_MASK) {
931 case CSOR_NAND_PGS_512:
932 if (chip->options & NAND_BUSWIDTH_16) {
933 layout = &oob_512_16bit_ecc4;
934 } else {
935 layout = &oob_512_8bit_ecc4;
936
937 /* Avoid conflict with bad block marker */
938 bbt_main_descr.offs = 0;
939 bbt_mirror_descr.offs = 0;
940 }
941
942 priv->bufnum_mask = 15;
943 break;
944
945 case CSOR_NAND_PGS_2K:
946 layout = &oob_2048_ecc4;
947 priv->bufnum_mask = 3;
948 break;
949
950 case CSOR_NAND_PGS_4K:
951 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
952 CSOR_NAND_ECC_MODE_4) {
953 layout = &oob_4096_ecc4;
954 } else {
955 layout = &oob_4096_ecc8;
956 chip->ecc.bytes = 16;
957 chip->ecc.strength = 8;
958 }
959
960 priv->bufnum_mask = 1;
961 break;
962
963 case CSOR_NAND_PGS_8K:
964 if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
965 CSOR_NAND_ECC_MODE_4) {
966 layout = &oob_8192_ecc4;
967 } else {
968 layout = &oob_8192_ecc8;
969 chip->ecc.bytes = 16;
970 chip->ecc.strength = 8;
971 }
972
973 priv->bufnum_mask = 0;
974 break;
975
976 default:
977 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
978 return -ENODEV;
979 }
980
981 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
982 if (csor & CSOR_NAND_ECC_DEC_EN) {
983 chip->ecc.mode = NAND_ECC_HW;
984 chip->ecc.layout = layout;
985 } else {
986 chip->ecc.mode = NAND_ECC_SOFT;
987 }
988
989 if (ctrl->version == FSL_IFC_VERSION_1_1_0)
990 fsl_ifc_sram_init(priv);
991
992 return 0;
993 }
994
995 static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
996 {
997 nand_release(&priv->mtd);
998
999 kfree(priv->mtd.name);
1000
1001 if (priv->vbase)
1002 iounmap(priv->vbase);
1003
1004 ifc_nand_ctrl->chips[priv->bank] = NULL;
1005
1006 return 0;
1007 }
1008
1009 static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
1010 phys_addr_t addr)
1011 {
1012 u32 cspr = ifc_in32(&ifc->cspr_cs[bank].cspr);
1013
1014 if (!(cspr & CSPR_V))
1015 return 0;
1016 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
1017 return 0;
1018
1019 return (cspr & CSPR_BA) == convert_ifc_address(addr);
1020 }
1021
1022 static DEFINE_MUTEX(fsl_ifc_nand_mutex);
1023
1024 static int fsl_ifc_nand_probe(struct platform_device *dev)
1025 {
1026 struct fsl_ifc_regs __iomem *ifc;
1027 struct fsl_ifc_mtd *priv;
1028 struct resource res;
1029 static const char *part_probe_types[]
1030 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
1031 int ret;
1032 int bank;
1033 struct device_node *node = dev->dev.of_node;
1034
1035 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->regs)
1036 return -ENODEV;
1037 ifc = fsl_ifc_ctrl_dev->regs;
1038
1039 /* get, allocate and map the memory resource */
1040 ret = of_address_to_resource(node, 0, &res);
1041 if (ret) {
1042 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
1043 return ret;
1044 }
1045
1046 /* find which chip select it is connected to */
1047 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
1048 if (match_bank(ifc, bank, res.start))
1049 break;
1050 }
1051
1052 if (bank >= fsl_ifc_ctrl_dev->banks) {
1053 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
1054 __func__);
1055 return -ENODEV;
1056 }
1057
1058 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1059 if (!priv)
1060 return -ENOMEM;
1061
1062 mutex_lock(&fsl_ifc_nand_mutex);
1063 if (!fsl_ifc_ctrl_dev->nand) {
1064 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
1065 if (!ifc_nand_ctrl) {
1066 mutex_unlock(&fsl_ifc_nand_mutex);
1067 return -ENOMEM;
1068 }
1069
1070 ifc_nand_ctrl->read_bytes = 0;
1071 ifc_nand_ctrl->index = 0;
1072 ifc_nand_ctrl->addr = NULL;
1073 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1074
1075 spin_lock_init(&ifc_nand_ctrl->controller.lock);
1076 init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
1077 } else {
1078 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1079 }
1080 mutex_unlock(&fsl_ifc_nand_mutex);
1081
1082 ifc_nand_ctrl->chips[bank] = priv;
1083 priv->bank = bank;
1084 priv->ctrl = fsl_ifc_ctrl_dev;
1085 priv->dev = &dev->dev;
1086
1087 priv->vbase = ioremap(res.start, resource_size(&res));
1088 if (!priv->vbase) {
1089 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1090 ret = -ENOMEM;
1091 goto err;
1092 }
1093
1094 dev_set_drvdata(priv->dev, priv);
1095
1096 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1097 IFC_NAND_EVTER_EN_FTOER_EN |
1098 IFC_NAND_EVTER_EN_WPER_EN,
1099 &ifc->ifc_nand.nand_evter_en);
1100
1101 /* enable NAND Machine Interrupts */
1102 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1103 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1104 IFC_NAND_EVTER_INTR_WPERIR_EN,
1105 &ifc->ifc_nand.nand_evter_intr_en);
1106 priv->mtd.name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1107 if (!priv->mtd.name) {
1108 ret = -ENOMEM;
1109 goto err;
1110 }
1111
1112 ret = fsl_ifc_chip_init(priv);
1113 if (ret)
1114 goto err;
1115
1116 ret = nand_scan_ident(&priv->mtd, 1, NULL);
1117 if (ret)
1118 goto err;
1119
1120 ret = fsl_ifc_chip_init_tail(&priv->mtd);
1121 if (ret)
1122 goto err;
1123
1124 ret = nand_scan_tail(&priv->mtd);
1125 if (ret)
1126 goto err;
1127
1128 /* First look for RedBoot table or partitions on the command
1129 * line, these take precedence over device tree information */
1130 mtd_device_parse_register(&priv->mtd, part_probe_types, NULL,
1131 NULL, 0);
1132
1133 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1134 (unsigned long long)res.start, priv->bank);
1135 return 0;
1136
1137 err:
1138 fsl_ifc_chip_remove(priv);
1139 return ret;
1140 }
1141
1142 static int fsl_ifc_nand_remove(struct platform_device *dev)
1143 {
1144 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1145
1146 fsl_ifc_chip_remove(priv);
1147
1148 mutex_lock(&fsl_ifc_nand_mutex);
1149 ifc_nand_ctrl->counter--;
1150 if (!ifc_nand_ctrl->counter) {
1151 fsl_ifc_ctrl_dev->nand = NULL;
1152 kfree(ifc_nand_ctrl);
1153 }
1154 mutex_unlock(&fsl_ifc_nand_mutex);
1155
1156 return 0;
1157 }
1158
1159 static const struct of_device_id fsl_ifc_nand_match[] = {
1160 {
1161 .compatible = "fsl,ifc-nand",
1162 },
1163 {}
1164 };
1165 MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1166
1167 static struct platform_driver fsl_ifc_nand_driver = {
1168 .driver = {
1169 .name = "fsl,ifc-nand",
1170 .of_match_table = fsl_ifc_nand_match,
1171 },
1172 .probe = fsl_ifc_nand_probe,
1173 .remove = fsl_ifc_nand_remove,
1174 };
1175
1176 module_platform_driver(fsl_ifc_nand_driver);
1177
1178 MODULE_LICENSE("GPL");
1179 MODULE_AUTHOR("Freescale");
1180 MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
Linux kernel - Deliverables
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