drivers/mtd/nand/fsl_upm.c

   1 /*
   2  * Freescale UPM NAND driver.
   3  *
   4  * Copyright © 2007-2008  MontaVista Software, Inc.
   5  *
   6  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/delay.h>
  17 #include <linux/mtd/nand.h>
  18 #include <linux/mtd/nand_ecc.h>
  19 #include <linux/mtd/partitions.h>
  20 #include <linux/mtd/mtd.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <asm/fsl_lbc.h>
  26
  27 #define FSL_UPM_WAIT_RUN_PATTERN  0x1
  28 #define FSL_UPM_WAIT_WRITE_BYTE   0x2
  29 #define FSL_UPM_WAIT_WRITE_BUFFER 0x4
  30
  31 struct fsl_upm_nand {
  32         struct device *dev;
  33         struct mtd_info mtd;
  34         struct nand_chip chip;
  35         int last_ctrl;
  36 #ifdef CONFIG_MTD_PARTITIONS
  37         struct mtd_partition *parts;
  38 #endif
  39
  40         struct fsl_upm upm;
  41         uint8_t upm_addr_offset;
  42         uint8_t upm_cmd_offset;
  43         void __iomem *io_base;
  44         int rnb_gpio[NAND_MAX_CHIPS];
  45         uint32_t mchip_offsets[NAND_MAX_CHIPS];
  46         uint32_t mchip_count;
  47         uint32_t mchip_number;
  48         int chip_delay;
  49         uint32_t wait_flags;
  50 };
  51
  52 static inline struct fsl_upm_nand *to_fsl_upm_nand(struct mtd_info *mtdinfo)
  53 {
  54         return container_of(mtdinfo, struct fsl_upm_nand, mtd);
  55 }
  56
  57 static int fun_chip_ready(struct mtd_info *mtd)
  58 {
  59         struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  60
  61         if (gpio_get_value(fun->rnb_gpio[fun->mchip_number]))
  62                 return 1;
  63
  64         dev_vdbg(fun->dev, "busy\n");
  65         return 0;
  66 }
  67
  68 static void fun_wait_rnb(struct fsl_upm_nand *fun)
  69 {
  70         if (fun->rnb_gpio[fun->mchip_number] >= 0) {
  71                 int cnt = 1000000;
  72
  73                 while (--cnt && !fun_chip_ready(&fun->mtd))
  74                         cpu_relax();
  75                 if (!cnt)
  76                         dev_err(fun->dev, "tired waiting for RNB\n");
  77         } else {
  78                 ndelay(100);
  79         }
  80 }
  81
  82 static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  83 {
  84         struct nand_chip *chip = mtd->priv;
  85         struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
  86         u32 mar;
  87
  88         if (!(ctrl & fun->last_ctrl)) {
  89                 fsl_upm_end_pattern(&fun->upm);
  90
  91                 if (cmd == NAND_CMD_NONE)
  92                         return;
  93
  94                 fun->last_ctrl = ctrl & (NAND_ALE | NAND_CLE);
  95         }
  96
  97         if (ctrl & NAND_CTRL_CHANGE) {
  98                 if (ctrl & NAND_ALE)
  99                         fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset);
 100                 else if (ctrl & NAND_CLE)
 101                         fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset);
 102         }
 103
 104         mar = (cmd << (32 - fun->upm.width)) |
 105                 fun->mchip_offsets[fun->mchip_number];
 106         fsl_upm_run_pattern(&fun->upm, chip->IO_ADDR_R, mar);
 107
 108         if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
 109                 fun_wait_rnb(fun);
 110 }
 111
 112 static void fun_select_chip(struct mtd_info *mtd, int mchip_nr)
 113 {
 114         struct nand_chip *chip = mtd->priv;
 115         struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
 116
 117         if (mchip_nr == -1) {
 118                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 119         } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
 120                 fun->mchip_number = mchip_nr;
 121                 chip->IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
 122                 chip->IO_ADDR_W = chip->IO_ADDR_R;
 123         } else {
 124                 BUG();
 125         }
 126 }
 127
 128 static uint8_t fun_read_byte(struct mtd_info *mtd)
 129 {
 130         struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
 131
 132         return in_8(fun->chip.IO_ADDR_R);
 133 }
 134
 135 static void fun_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 136 {
 137         struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
 138         int i;
 139
 140         for (i = 0; i < len; i++)
 141                 buf[i] = in_8(fun->chip.IO_ADDR_R);
 142 }
 143
 144 static void fun_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 145 {
 146         struct fsl_upm_nand *fun = to_fsl_upm_nand(mtd);
 147         int i;
 148
 149         for (i = 0; i < len; i++) {
 150                 out_8(fun->chip.IO_ADDR_W, buf[i]);
 151                 if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BYTE)
 152                         fun_wait_rnb(fun);
 153         }
 154         if (fun->wait_flags & FSL_UPM_WAIT_WRITE_BUFFER)
 155                 fun_wait_rnb(fun);
 156 }
 157
 158 static int __devinit fun_chip_init(struct fsl_upm_nand *fun,
 159                                    const struct device_node *upm_np,
 160                                    const struct resource *io_res)
 161 {
 162         int ret;
 163         struct device_node *flash_np;
 164 #ifdef CONFIG_MTD_PARTITIONS
 165         static const char *part_types[] = { "cmdlinepart", NULL, };
 166 #endif
 167
 168         fun->chip.IO_ADDR_R = fun->io_base;
 169         fun->chip.IO_ADDR_W = fun->io_base;
 170         fun->chip.cmd_ctrl = fun_cmd_ctrl;
 171         fun->chip.chip_delay = fun->chip_delay;
 172         fun->chip.read_byte = fun_read_byte;
 173         fun->chip.read_buf = fun_read_buf;
 174         fun->chip.write_buf = fun_write_buf;
 175         fun->chip.ecc.mode = NAND_ECC_SOFT;
 176         if (fun->mchip_count > 1)
 177                 fun->chip.select_chip = fun_select_chip;
 178
 179         if (fun->rnb_gpio[0] >= 0)
 180                 fun->chip.dev_ready = fun_chip_ready;
 181
 182         fun->mtd.priv = &fun->chip;
 183         fun->mtd.owner = THIS_MODULE;
 184
 185         flash_np = of_get_next_child(upm_np, NULL);
 186         if (!flash_np)
 187                 return -ENODEV;
 188
 189         fun->mtd.name = kasprintf(GFP_KERNEL, "0x%llx.%s", (u64)io_res->start,
 190                                   flash_np->name);
 191         if (!fun->mtd.name) {
 192                 ret = -ENOMEM;
 193                 goto err;
 194         }
 195
 196         ret = nand_scan(&fun->mtd, fun->mchip_count);
 197         if (ret)
 198                 goto err;
 199
 200 #ifdef CONFIG_MTD_PARTITIONS
 201         ret = parse_mtd_partitions(&fun->mtd, part_types, &fun->parts, 0);
 202
 203 #ifdef CONFIG_MTD_OF_PARTS
 204         if (ret == 0) {
 205                 ret = of_mtd_parse_partitions(fun->dev, flash_np, &fun->parts);
 206                 if (ret < 0)
 207                         goto err;
 208         }
 209 #endif
 210         if (ret > 0)
 211                 ret = add_mtd_partitions(&fun->mtd, fun->parts, ret);
 212         else
 213 #endif
 214                 ret = add_mtd_device(&fun->mtd);
 215 err:
 216         of_node_put(flash_np);
 217         return ret;
 218 }
 219
 220 static int __devinit fun_probe(struct platform_device *ofdev,
 221                                const struct of_device_id *ofid)
 222 {
 223         struct fsl_upm_nand *fun;
 224         struct resource io_res;
 225         const __be32 *prop;
 226         int rnb_gpio;
 227         int ret;
 228         int size;
 229         int i;
 230
 231         fun = kzalloc(sizeof(*fun), GFP_KERNEL);
 232         if (!fun)
 233                 return -ENOMEM;
 234
 235         ret = of_address_to_resource(ofdev->dev.of_node, 0, &io_res);
 236         if (ret) {
 237                 dev_err(&ofdev->dev, "can't get IO base\n");
 238                 goto err1;
 239         }
 240
 241         ret = fsl_upm_find(io_res.start, &fun->upm);
 242         if (ret) {
 243                 dev_err(&ofdev->dev, "can't find UPM\n");
 244                 goto err1;
 245         }
 246
 247         prop = of_get_property(ofdev->dev.of_node, "fsl,upm-addr-offset",
 248                                &size);
 249         if (!prop || size != sizeof(uint32_t)) {
 250                 dev_err(&ofdev->dev, "can't get UPM address offset\n");
 251                 ret = -EINVAL;
 252                 goto err1;
 253         }
 254         fun->upm_addr_offset = *prop;
 255
 256         prop = of_get_property(ofdev->dev.of_node, "fsl,upm-cmd-offset", &size);
 257         if (!prop || size != sizeof(uint32_t)) {
 258                 dev_err(&ofdev->dev, "can't get UPM command offset\n");
 259                 ret = -EINVAL;
 260                 goto err1;
 261         }
 262         fun->upm_cmd_offset = *prop;
 263
 264         prop = of_get_property(ofdev->dev.of_node,
 265                                "fsl,upm-addr-line-cs-offsets", &size);
 266         if (prop && (size / sizeof(uint32_t)) > 0) {
 267                 fun->mchip_count = size / sizeof(uint32_t);
 268                 if (fun->mchip_count >= NAND_MAX_CHIPS) {
 269                         dev_err(&ofdev->dev, "too much multiple chips\n");
 270                         goto err1;
 271                 }
 272                 for (i = 0; i < fun->mchip_count; i++)
 273                         fun->mchip_offsets[i] = be32_to_cpu(prop[i]);
 274         } else {
 275                 fun->mchip_count = 1;
 276         }
 277
 278         for (i = 0; i < fun->mchip_count; i++) {
 279                 fun->rnb_gpio[i] = -1;
 280                 rnb_gpio = of_get_gpio(ofdev->dev.of_node, i);
 281                 if (rnb_gpio >= 0) {
 282                         ret = gpio_request(rnb_gpio, dev_name(&ofdev->dev));
 283                         if (ret) {
 284                                 dev_err(&ofdev->dev,
 285                                         "can't request RNB gpio #%d\n", i);
 286                                 goto err2;
 287                         }
 288                         gpio_direction_input(rnb_gpio);
 289                         fun->rnb_gpio[i] = rnb_gpio;
 290                 } else if (rnb_gpio == -EINVAL) {
 291                         dev_err(&ofdev->dev, "RNB gpio #%d is invalid\n", i);
 292                         goto err2;
 293                 }
 294         }
 295
 296         prop = of_get_property(ofdev->dev.of_node, "chip-delay", NULL);
 297         if (prop)
 298                 fun->chip_delay = be32_to_cpup(prop);
 299         else
 300                 fun->chip_delay = 50;
 301
 302         prop = of_get_property(ofdev->dev.of_node, "fsl,upm-wait-flags", &size);
 303         if (prop && size == sizeof(uint32_t))
 304                 fun->wait_flags = be32_to_cpup(prop);
 305         else
 306                 fun->wait_flags = FSL_UPM_WAIT_RUN_PATTERN |
 307                                   FSL_UPM_WAIT_WRITE_BYTE;
 308
 309         fun->io_base = devm_ioremap_nocache(&ofdev->dev, io_res.start,
 310                                             resource_size(&io_res));
 311         if (!fun->io_base) {
 312                 ret = -ENOMEM;
 313                 goto err2;
 314         }
 315
 316         fun->dev = &ofdev->dev;
 317         fun->last_ctrl = NAND_CLE;
 318
 319         ret = fun_chip_init(fun, ofdev->dev.of_node, &io_res);
 320         if (ret)
 321                 goto err2;
 322
 323         dev_set_drvdata(&ofdev->dev, fun);
 324
 325         return 0;
 326 err2:
 327         for (i = 0; i < fun->mchip_count; i++) {
 328                 if (fun->rnb_gpio[i] < 0)
 329                         break;
 330                 gpio_free(fun->rnb_gpio[i]);
 331         }
 332 err1:
 333         kfree(fun);
 334
 335         return ret;
 336 }
 337
 338 static int __devexit fun_remove(struct platform_device *ofdev)
 339 {
 340         struct fsl_upm_nand *fun = dev_get_drvdata(&ofdev->dev);
 341         int i;
 342
 343         nand_release(&fun->mtd);
 344         kfree(fun->mtd.name);
 345
 346         for (i = 0; i < fun->mchip_count; i++) {
 347                 if (fun->rnb_gpio[i] < 0)
 348                         break;
 349                 gpio_free(fun->rnb_gpio[i]);
 350         }
 351
 352         kfree(fun);
 353
 354         return 0;
 355 }
 356
 357 static const struct of_device_id of_fun_match[] = {
 358         { .compatible = "fsl,upm-nand" },
 359         {},
 360 };
 361 MODULE_DEVICE_TABLE(of, of_fun_match);
 362
 363 static struct of_platform_driver of_fun_driver = {
 364         .driver = {
 365                 .name = "fsl,upm-nand",
 366                 .owner = THIS_MODULE,
 367                 .of_match_table = of_fun_match,
 368         },
 369         .probe          = fun_probe,
 370         .remove         = __devexit_p(fun_remove),
 371 };
 372
 373 static int __init fun_module_init(void)
 374 {
 375         return of_register_platform_driver(&of_fun_driver);
 376 }
 377 module_init(fun_module_init);
 378
 379 static void __exit fun_module_exit(void)
 380 {
 381         of_unregister_platform_driver(&of_fun_driver);
 382 }
 383 module_exit(fun_module_exit);
 384
 385 MODULE_LICENSE("GPL");
 386 MODULE_AUTHOR("Anton Vorontsov <avorontsov@ru.mvista.com>");
 387 MODULE_DESCRIPTION("Driver for NAND chips working through Freescale "
 388                    "LocalBus User-Programmable Machine");