2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/module.h>
23 #include <linux/resource.h>
24 #include <linux/sched.h>
25 #include <linux/types.h>
26 #include <linux/mtd/mtd.h>
27 #include <linux/mtd/nand.h>
28 #include <linux/mtd/nand_ecc.h>
29 #include <linux/platform_device.h>
30 #include <linux/mtd/partitions.h>
32 #include <linux/slab.h>
33 #include <linux/mtd/fsmc.h>
34 #include <linux/amba/bus.h>
35 #include <mtd/mtd-abi.h>
37 static struct nand_ecclayout fsmc_ecc1_128_layout
= {
39 .eccpos
= {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52,
40 66, 67, 68, 82, 83, 84, 98, 99, 100, 114, 115, 116},
42 {.offset
= 8, .length
= 8},
43 {.offset
= 24, .length
= 8},
44 {.offset
= 40, .length
= 8},
45 {.offset
= 56, .length
= 8},
46 {.offset
= 72, .length
= 8},
47 {.offset
= 88, .length
= 8},
48 {.offset
= 104, .length
= 8},
49 {.offset
= 120, .length
= 8}
53 static struct nand_ecclayout fsmc_ecc1_64_layout
= {
55 .eccpos
= {2, 3, 4, 18, 19, 20, 34, 35, 36, 50, 51, 52},
57 {.offset
= 8, .length
= 8},
58 {.offset
= 24, .length
= 8},
59 {.offset
= 40, .length
= 8},
60 {.offset
= 56, .length
= 8},
64 static struct nand_ecclayout fsmc_ecc1_16_layout
= {
68 {.offset
= 8, .length
= 8},
73 * ECC4 layout for NAND of pagesize 8192 bytes & OOBsize 256 bytes. 13*16 bytes
74 * of OB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 46
75 * bytes are free for use.
77 static struct nand_ecclayout fsmc_ecc4_256_layout
= {
79 .eccpos
= { 2, 3, 4, 5, 6, 7, 8,
80 9, 10, 11, 12, 13, 14,
81 18, 19, 20, 21, 22, 23, 24,
82 25, 26, 27, 28, 29, 30,
83 34, 35, 36, 37, 38, 39, 40,
84 41, 42, 43, 44, 45, 46,
85 50, 51, 52, 53, 54, 55, 56,
86 57, 58, 59, 60, 61, 62,
87 66, 67, 68, 69, 70, 71, 72,
88 73, 74, 75, 76, 77, 78,
89 82, 83, 84, 85, 86, 87, 88,
90 89, 90, 91, 92, 93, 94,
91 98, 99, 100, 101, 102, 103, 104,
92 105, 106, 107, 108, 109, 110,
93 114, 115, 116, 117, 118, 119, 120,
94 121, 122, 123, 124, 125, 126,
95 130, 131, 132, 133, 134, 135, 136,
96 137, 138, 139, 140, 141, 142,
97 146, 147, 148, 149, 150, 151, 152,
98 153, 154, 155, 156, 157, 158,
99 162, 163, 164, 165, 166, 167, 168,
100 169, 170, 171, 172, 173, 174,
101 178, 179, 180, 181, 182, 183, 184,
102 185, 186, 187, 188, 189, 190,
103 194, 195, 196, 197, 198, 199, 200,
104 201, 202, 203, 204, 205, 206,
105 210, 211, 212, 213, 214, 215, 216,
106 217, 218, 219, 220, 221, 222,
107 226, 227, 228, 229, 230, 231, 232,
108 233, 234, 235, 236, 237, 238,
109 242, 243, 244, 245, 246, 247, 248,
110 249, 250, 251, 252, 253, 254
113 {.offset
= 15, .length
= 3},
114 {.offset
= 31, .length
= 3},
115 {.offset
= 47, .length
= 3},
116 {.offset
= 63, .length
= 3},
117 {.offset
= 79, .length
= 3},
118 {.offset
= 95, .length
= 3},
119 {.offset
= 111, .length
= 3},
120 {.offset
= 127, .length
= 3},
121 {.offset
= 143, .length
= 3},
122 {.offset
= 159, .length
= 3},
123 {.offset
= 175, .length
= 3},
124 {.offset
= 191, .length
= 3},
125 {.offset
= 207, .length
= 3},
126 {.offset
= 223, .length
= 3},
127 {.offset
= 239, .length
= 3},
128 {.offset
= 255, .length
= 1}
133 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 224 bytes. 13*8 bytes
134 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 118
135 * bytes are free for use.
137 static struct nand_ecclayout fsmc_ecc4_224_layout
= {
139 .eccpos
= { 2, 3, 4, 5, 6, 7, 8,
140 9, 10, 11, 12, 13, 14,
141 18, 19, 20, 21, 22, 23, 24,
142 25, 26, 27, 28, 29, 30,
143 34, 35, 36, 37, 38, 39, 40,
144 41, 42, 43, 44, 45, 46,
145 50, 51, 52, 53, 54, 55, 56,
146 57, 58, 59, 60, 61, 62,
147 66, 67, 68, 69, 70, 71, 72,
148 73, 74, 75, 76, 77, 78,
149 82, 83, 84, 85, 86, 87, 88,
150 89, 90, 91, 92, 93, 94,
151 98, 99, 100, 101, 102, 103, 104,
152 105, 106, 107, 108, 109, 110,
153 114, 115, 116, 117, 118, 119, 120,
154 121, 122, 123, 124, 125, 126
157 {.offset
= 15, .length
= 3},
158 {.offset
= 31, .length
= 3},
159 {.offset
= 47, .length
= 3},
160 {.offset
= 63, .length
= 3},
161 {.offset
= 79, .length
= 3},
162 {.offset
= 95, .length
= 3},
163 {.offset
= 111, .length
= 3},
164 {.offset
= 127, .length
= 97}
169 * ECC4 layout for NAND of pagesize 4096 bytes & OOBsize 128 bytes. 13*8 bytes
170 * of OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block & 22
171 * bytes are free for use.
173 static struct nand_ecclayout fsmc_ecc4_128_layout
= {
175 .eccpos
= { 2, 3, 4, 5, 6, 7, 8,
176 9, 10, 11, 12, 13, 14,
177 18, 19, 20, 21, 22, 23, 24,
178 25, 26, 27, 28, 29, 30,
179 34, 35, 36, 37, 38, 39, 40,
180 41, 42, 43, 44, 45, 46,
181 50, 51, 52, 53, 54, 55, 56,
182 57, 58, 59, 60, 61, 62,
183 66, 67, 68, 69, 70, 71, 72,
184 73, 74, 75, 76, 77, 78,
185 82, 83, 84, 85, 86, 87, 88,
186 89, 90, 91, 92, 93, 94,
187 98, 99, 100, 101, 102, 103, 104,
188 105, 106, 107, 108, 109, 110,
189 114, 115, 116, 117, 118, 119, 120,
190 121, 122, 123, 124, 125, 126
193 {.offset
= 15, .length
= 3},
194 {.offset
= 31, .length
= 3},
195 {.offset
= 47, .length
= 3},
196 {.offset
= 63, .length
= 3},
197 {.offset
= 79, .length
= 3},
198 {.offset
= 95, .length
= 3},
199 {.offset
= 111, .length
= 3},
200 {.offset
= 127, .length
= 1}
205 * ECC4 layout for NAND of pagesize 2048 bytes & OOBsize 64 bytes. 13*4 bytes of
206 * OOB size is reserved for ECC, Byte no. 0 & 1 reserved for bad block and 10
207 * bytes are free for use.
209 static struct nand_ecclayout fsmc_ecc4_64_layout
= {
211 .eccpos
= { 2, 3, 4, 5, 6, 7, 8,
212 9, 10, 11, 12, 13, 14,
213 18, 19, 20, 21, 22, 23, 24,
214 25, 26, 27, 28, 29, 30,
215 34, 35, 36, 37, 38, 39, 40,
216 41, 42, 43, 44, 45, 46,
217 50, 51, 52, 53, 54, 55, 56,
218 57, 58, 59, 60, 61, 62,
221 {.offset
= 15, .length
= 3},
222 {.offset
= 31, .length
= 3},
223 {.offset
= 47, .length
= 3},
224 {.offset
= 63, .length
= 1},
229 * ECC4 layout for NAND of pagesize 512 bytes & OOBsize 16 bytes. 13 bytes of
230 * OOB size is reserved for ECC, Byte no. 4 & 5 reserved for bad block and One
231 * byte is free for use.
233 static struct nand_ecclayout fsmc_ecc4_16_layout
= {
235 .eccpos
= { 0, 1, 2, 3, 6, 7, 8,
236 9, 10, 11, 12, 13, 14
239 {.offset
= 15, .length
= 1},
244 * ECC placement definitions in oobfree type format.
245 * There are 13 bytes of ecc for every 512 byte block and it has to be read
246 * consecutively and immediately after the 512 byte data block for hardware to
247 * generate the error bit offsets in 512 byte data.
248 * Managing the ecc bytes in the following way makes it easier for software to
249 * read ecc bytes consecutive to data bytes. This way is similar to
250 * oobfree structure maintained already in generic nand driver
252 static struct fsmc_eccplace fsmc_ecc4_lp_place
= {
254 {.offset
= 2, .length
= 13},
255 {.offset
= 18, .length
= 13},
256 {.offset
= 34, .length
= 13},
257 {.offset
= 50, .length
= 13},
258 {.offset
= 66, .length
= 13},
259 {.offset
= 82, .length
= 13},
260 {.offset
= 98, .length
= 13},
261 {.offset
= 114, .length
= 13}
265 static struct fsmc_eccplace fsmc_ecc4_sp_place
= {
267 {.offset
= 0, .length
= 4},
268 {.offset
= 6, .length
= 9}
273 * struct fsmc_nand_data - structure for FSMC NAND device state
275 * @pid: Part ID on the AMBA PrimeCell format
276 * @mtd: MTD info for a NAND flash.
277 * @nand: Chip related info for a NAND flash.
278 * @partitions: Partition info for a NAND Flash.
279 * @nr_partitions: Total number of partition of a NAND flash.
281 * @ecc_place: ECC placing locations in oobfree type format.
282 * @bank: Bank number for probed device.
283 * @clk: Clock structure for FSMC.
285 * @data_va: NAND port for Data.
286 * @cmd_va: NAND port for Command.
287 * @addr_va: NAND port for Address.
288 * @regs_va: FSMC regs base address.
290 struct fsmc_nand_data
{
293 struct nand_chip nand
;
294 struct mtd_partition
*partitions
;
295 unsigned int nr_partitions
;
297 struct fsmc_eccplace
*ecc_place
;
301 struct resource
*resregs
;
302 struct resource
*rescmd
;
303 struct resource
*resaddr
;
304 struct resource
*resdata
;
306 void __iomem
*data_va
;
307 void __iomem
*cmd_va
;
308 void __iomem
*addr_va
;
309 void __iomem
*regs_va
;
311 void (*select_chip
)(uint32_t bank
, uint32_t busw
);
314 /* Assert CS signal based on chipnr */
315 static void fsmc_select_chip(struct mtd_info
*mtd
, int chipnr
)
317 struct nand_chip
*chip
= mtd
->priv
;
318 struct fsmc_nand_data
*host
;
320 host
= container_of(mtd
, struct fsmc_nand_data
, mtd
);
324 chip
->cmd_ctrl(mtd
, NAND_CMD_NONE
, 0 | NAND_CTRL_CHANGE
);
330 if (host
->select_chip
)
331 host
->select_chip(chipnr
,
332 chip
->options
& NAND_BUSWIDTH_16
);
341 * fsmc_cmd_ctrl - For facilitaing Hardware access
342 * This routine allows hardware specific access to control-lines(ALE,CLE)
344 static void fsmc_cmd_ctrl(struct mtd_info
*mtd
, int cmd
, unsigned int ctrl
)
346 struct nand_chip
*this = mtd
->priv
;
347 struct fsmc_nand_data
*host
= container_of(mtd
,
348 struct fsmc_nand_data
, mtd
);
349 struct fsmc_regs
*regs
= host
->regs_va
;
350 unsigned int bank
= host
->bank
;
352 if (ctrl
& NAND_CTRL_CHANGE
) {
353 if (ctrl
& NAND_CLE
) {
354 this->IO_ADDR_R
= (void __iomem
*)host
->cmd_va
;
355 this->IO_ADDR_W
= (void __iomem
*)host
->cmd_va
;
356 } else if (ctrl
& NAND_ALE
) {
357 this->IO_ADDR_R
= (void __iomem
*)host
->addr_va
;
358 this->IO_ADDR_W
= (void __iomem
*)host
->addr_va
;
360 this->IO_ADDR_R
= (void __iomem
*)host
->data_va
;
361 this->IO_ADDR_W
= (void __iomem
*)host
->data_va
;
364 if (ctrl
& NAND_NCE
) {
365 writel(readl(®s
->bank_regs
[bank
].pc
) | FSMC_ENABLE
,
366 ®s
->bank_regs
[bank
].pc
);
368 writel(readl(®s
->bank_regs
[bank
].pc
) & ~FSMC_ENABLE
,
369 ®s
->bank_regs
[bank
].pc
);
375 if (cmd
!= NAND_CMD_NONE
)
376 writeb(cmd
, this->IO_ADDR_W
);
380 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
382 * This routine initializes timing parameters related to NAND memory access in
385 static void __init
fsmc_nand_setup(struct fsmc_regs
*regs
, uint32_t bank
,
388 uint32_t value
= FSMC_DEVTYPE_NAND
| FSMC_ENABLE
| FSMC_WAITON
;
391 writel(value
| FSMC_DEVWID_16
, ®s
->bank_regs
[bank
].pc
);
393 writel(value
| FSMC_DEVWID_8
, ®s
->bank_regs
[bank
].pc
);
395 writel(readl(®s
->bank_regs
[bank
].pc
) | FSMC_TCLR_1
| FSMC_TAR_1
,
396 ®s
->bank_regs
[bank
].pc
);
397 writel(FSMC_THIZ_1
| FSMC_THOLD_4
| FSMC_TWAIT_6
| FSMC_TSET_0
,
398 ®s
->bank_regs
[bank
].comm
);
399 writel(FSMC_THIZ_1
| FSMC_THOLD_4
| FSMC_TWAIT_6
| FSMC_TSET_0
,
400 ®s
->bank_regs
[bank
].attrib
);
404 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
406 static void fsmc_enable_hwecc(struct mtd_info
*mtd
, int mode
)
408 struct fsmc_nand_data
*host
= container_of(mtd
,
409 struct fsmc_nand_data
, mtd
);
410 struct fsmc_regs
*regs
= host
->regs_va
;
411 uint32_t bank
= host
->bank
;
413 writel(readl(®s
->bank_regs
[bank
].pc
) & ~FSMC_ECCPLEN_256
,
414 ®s
->bank_regs
[bank
].pc
);
415 writel(readl(®s
->bank_regs
[bank
].pc
) & ~FSMC_ECCEN
,
416 ®s
->bank_regs
[bank
].pc
);
417 writel(readl(®s
->bank_regs
[bank
].pc
) | FSMC_ECCEN
,
418 ®s
->bank_regs
[bank
].pc
);
422 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
423 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
426 static int fsmc_read_hwecc_ecc4(struct mtd_info
*mtd
, const uint8_t *data
,
429 struct fsmc_nand_data
*host
= container_of(mtd
,
430 struct fsmc_nand_data
, mtd
);
431 struct fsmc_regs
*regs
= host
->regs_va
;
432 uint32_t bank
= host
->bank
;
434 unsigned long deadline
= jiffies
+ FSMC_BUSY_WAIT_TIMEOUT
;
437 if (readl(®s
->bank_regs
[bank
].sts
) & FSMC_CODE_RDY
)
441 } while (!time_after_eq(jiffies
, deadline
));
443 ecc_tmp
= readl(®s
->bank_regs
[bank
].ecc1
);
444 ecc
[0] = (uint8_t) (ecc_tmp
>> 0);
445 ecc
[1] = (uint8_t) (ecc_tmp
>> 8);
446 ecc
[2] = (uint8_t) (ecc_tmp
>> 16);
447 ecc
[3] = (uint8_t) (ecc_tmp
>> 24);
449 ecc_tmp
= readl(®s
->bank_regs
[bank
].ecc2
);
450 ecc
[4] = (uint8_t) (ecc_tmp
>> 0);
451 ecc
[5] = (uint8_t) (ecc_tmp
>> 8);
452 ecc
[6] = (uint8_t) (ecc_tmp
>> 16);
453 ecc
[7] = (uint8_t) (ecc_tmp
>> 24);
455 ecc_tmp
= readl(®s
->bank_regs
[bank
].ecc3
);
456 ecc
[8] = (uint8_t) (ecc_tmp
>> 0);
457 ecc
[9] = (uint8_t) (ecc_tmp
>> 8);
458 ecc
[10] = (uint8_t) (ecc_tmp
>> 16);
459 ecc
[11] = (uint8_t) (ecc_tmp
>> 24);
461 ecc_tmp
= readl(®s
->bank_regs
[bank
].sts
);
462 ecc
[12] = (uint8_t) (ecc_tmp
>> 16);
468 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
469 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
472 static int fsmc_read_hwecc_ecc1(struct mtd_info
*mtd
, const uint8_t *data
,
475 struct fsmc_nand_data
*host
= container_of(mtd
,
476 struct fsmc_nand_data
, mtd
);
477 struct fsmc_regs
*regs
= host
->regs_va
;
478 uint32_t bank
= host
->bank
;
481 ecc_tmp
= readl(®s
->bank_regs
[bank
].ecc1
);
482 ecc
[0] = (uint8_t) (ecc_tmp
>> 0);
483 ecc
[1] = (uint8_t) (ecc_tmp
>> 8);
484 ecc
[2] = (uint8_t) (ecc_tmp
>> 16);
489 /* Count the number of 0's in buff upto a max of max_bits */
490 static int count_written_bits(uint8_t *buff
, int size
, int max_bits
)
492 int k
, written_bits
= 0;
494 for (k
= 0; k
< size
; k
++) {
495 written_bits
+= hweight8(~buff
[k
]);
496 if (written_bits
> max_bits
)
504 * fsmc_read_page_hwecc
505 * @mtd: mtd info structure
506 * @chip: nand chip info structure
507 * @buf: buffer to store read data
508 * @page: page number to read
510 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
511 * performed in a strict sequence as follows:
512 * data(512 byte) -> ecc(13 byte)
513 * After this read, fsmc hardware generates and reports error data bits(up to a
516 static int fsmc_read_page_hwecc(struct mtd_info
*mtd
, struct nand_chip
*chip
,
517 uint8_t *buf
, int page
)
519 struct fsmc_nand_data
*host
= container_of(mtd
,
520 struct fsmc_nand_data
, mtd
);
521 struct fsmc_eccplace
*ecc_place
= host
->ecc_place
;
522 int i
, j
, s
, stat
, eccsize
= chip
->ecc
.size
;
523 int eccbytes
= chip
->ecc
.bytes
;
524 int eccsteps
= chip
->ecc
.steps
;
526 uint8_t *ecc_calc
= chip
->buffers
->ecccalc
;
527 uint8_t *ecc_code
= chip
->buffers
->ecccode
;
528 int off
, len
, group
= 0;
530 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
531 * end up reading 14 bytes (7 words) from oob. The local array is
532 * to maintain word alignment
535 uint8_t *oob
= (uint8_t *)&ecc_oob
[0];
537 for (i
= 0, s
= 0; s
< eccsteps
; s
++, i
+= eccbytes
, p
+= eccsize
) {
538 chip
->cmdfunc(mtd
, NAND_CMD_READ0
, s
* eccsize
, page
);
539 chip
->ecc
.hwctl(mtd
, NAND_ECC_READ
);
540 chip
->read_buf(mtd
, p
, eccsize
);
542 for (j
= 0; j
< eccbytes
;) {
543 off
= ecc_place
->eccplace
[group
].offset
;
544 len
= ecc_place
->eccplace
[group
].length
;
548 * length is intentionally kept a higher multiple of 2
549 * to read at least 13 bytes even in case of 16 bit NAND
552 if (chip
->options
& NAND_BUSWIDTH_16
)
553 len
= roundup(len
, 2);
555 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, off
, page
);
556 chip
->read_buf(mtd
, oob
+ j
, len
);
560 memcpy(&ecc_code
[i
], oob
, chip
->ecc
.bytes
);
561 chip
->ecc
.calculate(mtd
, p
, &ecc_calc
[i
]);
563 stat
= chip
->ecc
.correct(mtd
, p
, &ecc_code
[i
], &ecc_calc
[i
]);
565 mtd
->ecc_stats
.failed
++;
567 mtd
->ecc_stats
.corrected
+= stat
;
574 * fsmc_bch8_correct_data
575 * @mtd: mtd info structure
576 * @dat: buffer of read data
577 * @read_ecc: ecc read from device spare area
578 * @calc_ecc: ecc calculated from read data
580 * calc_ecc is a 104 bit information containing maximum of 8 error
581 * offset informations of 13 bits each in 512 bytes of read data.
583 static int fsmc_bch8_correct_data(struct mtd_info
*mtd
, uint8_t *dat
,
584 uint8_t *read_ecc
, uint8_t *calc_ecc
)
586 struct fsmc_nand_data
*host
= container_of(mtd
,
587 struct fsmc_nand_data
, mtd
);
588 struct nand_chip
*chip
= mtd
->priv
;
589 struct fsmc_regs
*regs
= host
->regs_va
;
590 unsigned int bank
= host
->bank
;
593 uint32_t ecc1
, ecc2
, ecc3
, ecc4
;
595 num_err
= (readl(®s
->bank_regs
[bank
].sts
) >> 10) & 0xF;
597 /* no bit flipping */
598 if (likely(num_err
== 0))
601 /* too many errors */
602 if (unlikely(num_err
> 8)) {
604 * This is a temporary erase check. A newly erased page read
605 * would result in an ecc error because the oob data is also
606 * erased to FF and the calculated ecc for an FF data is not
608 * This is a workaround to skip performing correction in case
612 * For every page, each bit written as 0 is counted until these
613 * number of bits are greater than 8 (the maximum correction
614 * capability of FSMC for each 512 + 13 bytes)
617 int bits_ecc
= count_written_bits(read_ecc
, chip
->ecc
.bytes
, 8);
618 int bits_data
= count_written_bits(dat
, chip
->ecc
.size
, 8);
620 if ((bits_ecc
+ bits_data
) <= 8) {
622 memset(dat
, 0xff, chip
->ecc
.size
);
630 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
631 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
633 * calc_ecc is a 104 bit information containing maximum of 8 error
634 * offset informations of 13 bits each. calc_ecc is copied into a
635 * uint64_t array and error offset indexes are populated in err_idx
638 ecc1
= readl(®s
->bank_regs
[bank
].ecc1
);
639 ecc2
= readl(®s
->bank_regs
[bank
].ecc2
);
640 ecc3
= readl(®s
->bank_regs
[bank
].ecc3
);
641 ecc4
= readl(®s
->bank_regs
[bank
].sts
);
643 err_idx
[0] = (ecc1
>> 0) & 0x1FFF;
644 err_idx
[1] = (ecc1
>> 13) & 0x1FFF;
645 err_idx
[2] = (((ecc2
>> 0) & 0x7F) << 6) | ((ecc1
>> 26) & 0x3F);
646 err_idx
[3] = (ecc2
>> 7) & 0x1FFF;
647 err_idx
[4] = (((ecc3
>> 0) & 0x1) << 12) | ((ecc2
>> 20) & 0xFFF);
648 err_idx
[5] = (ecc3
>> 1) & 0x1FFF;
649 err_idx
[6] = (ecc3
>> 14) & 0x1FFF;
650 err_idx
[7] = (((ecc4
>> 16) & 0xFF) << 5) | ((ecc3
>> 27) & 0x1F);
654 change_bit(0, (unsigned long *)&err_idx
[i
]);
655 change_bit(1, (unsigned long *)&err_idx
[i
]);
657 if (err_idx
[i
] < chip
->ecc
.size
* 8) {
658 change_bit(err_idx
[i
], (unsigned long *)dat
);
666 * fsmc_nand_probe - Probe function
667 * @pdev: platform device structure
669 static int __init
fsmc_nand_probe(struct platform_device
*pdev
)
671 struct fsmc_nand_platform_data
*pdata
= dev_get_platdata(&pdev
->dev
);
672 struct fsmc_nand_data
*host
;
673 struct mtd_info
*mtd
;
674 struct nand_chip
*nand
;
675 struct fsmc_regs
*regs
;
676 struct resource
*res
;
682 dev_err(&pdev
->dev
, "platform data is NULL\n");
686 /* Allocate memory for the device structure (and zero it) */
687 host
= kzalloc(sizeof(*host
), GFP_KERNEL
);
689 dev_err(&pdev
->dev
, "failed to allocate device structure\n");
693 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "nand_data");
699 host
->resdata
= request_mem_region(res
->start
, resource_size(res
),
701 if (!host
->resdata
) {
706 host
->data_va
= ioremap(res
->start
, resource_size(res
));
707 if (!host
->data_va
) {
712 host
->resaddr
= request_mem_region(res
->start
+ pdata
->ale_off
,
713 resource_size(res
), pdev
->name
);
714 if (!host
->resaddr
) {
719 host
->addr_va
= ioremap(res
->start
+ pdata
->ale_off
,
721 if (!host
->addr_va
) {
726 host
->rescmd
= request_mem_region(res
->start
+ pdata
->cle_off
,
727 resource_size(res
), pdev
->name
);
733 host
->cmd_va
= ioremap(res
->start
+ pdata
->cle_off
, resource_size(res
));
739 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "fsmc_regs");
745 host
->resregs
= request_mem_region(res
->start
, resource_size(res
),
747 if (!host
->resregs
) {
752 host
->regs_va
= ioremap(res
->start
, resource_size(res
));
753 if (!host
->regs_va
) {
758 host
->clk
= clk_get(&pdev
->dev
, NULL
);
759 if (IS_ERR(host
->clk
)) {
760 dev_err(&pdev
->dev
, "failed to fetch block clock\n");
761 ret
= PTR_ERR(host
->clk
);
766 ret
= clk_enable(host
->clk
);
771 * This device ID is actually a common AMBA ID as used on the
772 * AMBA PrimeCell bus. However it is not a PrimeCell.
774 for (pid
= 0, i
= 0; i
< 4; i
++)
775 pid
|= (readl(host
->regs_va
+ resource_size(res
) - 0x20 + 4 * i
) & 255) << (i
* 8);
777 dev_info(&pdev
->dev
, "FSMC device partno %03x, manufacturer %02x, "
778 "revision %02x, config %02x\n",
779 AMBA_PART_BITS(pid
), AMBA_MANF_BITS(pid
),
780 AMBA_REV_BITS(pid
), AMBA_CONFIG_BITS(pid
));
782 host
->bank
= pdata
->bank
;
783 host
->select_chip
= pdata
->select_bank
;
784 host
->partitions
= pdata
->partitions
;
785 host
->nr_partitions
= pdata
->nr_partitions
;
786 regs
= host
->regs_va
;
788 /* Link all private pointers */
794 host
->mtd
.owner
= THIS_MODULE
;
795 nand
->IO_ADDR_R
= host
->data_va
;
796 nand
->IO_ADDR_W
= host
->data_va
;
797 nand
->cmd_ctrl
= fsmc_cmd_ctrl
;
798 nand
->chip_delay
= 30;
800 nand
->ecc
.mode
= NAND_ECC_HW
;
801 nand
->ecc
.hwctl
= fsmc_enable_hwecc
;
802 nand
->ecc
.size
= 512;
803 nand
->options
= pdata
->options
;
804 nand
->select_chip
= fsmc_select_chip
;
806 if (pdata
->width
== FSMC_NAND_BW16
)
807 nand
->options
|= NAND_BUSWIDTH_16
;
809 fsmc_nand_setup(regs
, host
->bank
, nand
->options
& NAND_BUSWIDTH_16
);
811 if (AMBA_REV_BITS(host
->pid
) >= 8) {
812 nand
->ecc
.read_page
= fsmc_read_page_hwecc
;
813 nand
->ecc
.calculate
= fsmc_read_hwecc_ecc4
;
814 nand
->ecc
.correct
= fsmc_bch8_correct_data
;
815 nand
->ecc
.bytes
= 13;
816 nand
->ecc
.strength
= 8;
818 nand
->ecc
.calculate
= fsmc_read_hwecc_ecc1
;
819 nand
->ecc
.correct
= nand_correct_data
;
821 nand
->ecc
.strength
= 1;
825 * Scan to find existence of the device
827 if (nand_scan_ident(&host
->mtd
, 1, NULL
)) {
829 dev_err(&pdev
->dev
, "No NAND Device found!\n");
833 if (AMBA_REV_BITS(host
->pid
) >= 8) {
834 switch (host
->mtd
.oobsize
) {
836 nand
->ecc
.layout
= &fsmc_ecc4_16_layout
;
837 host
->ecc_place
= &fsmc_ecc4_sp_place
;
840 nand
->ecc
.layout
= &fsmc_ecc4_64_layout
;
841 host
->ecc_place
= &fsmc_ecc4_lp_place
;
844 nand
->ecc
.layout
= &fsmc_ecc4_128_layout
;
845 host
->ecc_place
= &fsmc_ecc4_lp_place
;
848 nand
->ecc
.layout
= &fsmc_ecc4_224_layout
;
849 host
->ecc_place
= &fsmc_ecc4_lp_place
;
852 nand
->ecc
.layout
= &fsmc_ecc4_256_layout
;
853 host
->ecc_place
= &fsmc_ecc4_lp_place
;
856 printk(KERN_WARNING
"No oob scheme defined for "
857 "oobsize %d\n", mtd
->oobsize
);
861 switch (host
->mtd
.oobsize
) {
863 nand
->ecc
.layout
= &fsmc_ecc1_16_layout
;
866 nand
->ecc
.layout
= &fsmc_ecc1_64_layout
;
869 nand
->ecc
.layout
= &fsmc_ecc1_128_layout
;
872 printk(KERN_WARNING
"No oob scheme defined for "
873 "oobsize %d\n", mtd
->oobsize
);
878 /* Second stage of scan to fill MTD data-structures */
879 if (nand_scan_tail(&host
->mtd
)) {
885 * The partition information can is accessed by (in the same precedence)
887 * command line through Bootloader,
889 * default partition information present in driver.
892 * Check for partition info passed
894 host
->mtd
.name
= "nand";
895 ret
= mtd_device_parse_register(&host
->mtd
, NULL
, NULL
,
896 host
->partitions
, host
->nr_partitions
);
900 platform_set_drvdata(pdev
, host
);
901 dev_info(&pdev
->dev
, "FSMC NAND driver registration successful\n");
905 clk_disable(host
->clk
);
910 iounmap(host
->regs_va
);
912 release_mem_region(host
->resregs
->start
,
913 resource_size(host
->resregs
));
915 iounmap(host
->cmd_va
);
917 release_mem_region(host
->rescmd
->start
,
918 resource_size(host
->rescmd
));
920 iounmap(host
->addr_va
);
922 release_mem_region(host
->resaddr
->start
,
923 resource_size(host
->resaddr
));
925 iounmap(host
->data_va
);
927 release_mem_region(host
->resdata
->start
,
928 resource_size(host
->resdata
));
937 static int fsmc_nand_remove(struct platform_device
*pdev
)
939 struct fsmc_nand_data
*host
= platform_get_drvdata(pdev
);
941 platform_set_drvdata(pdev
, NULL
);
944 nand_release(&host
->mtd
);
945 clk_disable(host
->clk
);
948 iounmap(host
->regs_va
);
949 release_mem_region(host
->resregs
->start
,
950 resource_size(host
->resregs
));
951 iounmap(host
->cmd_va
);
952 release_mem_region(host
->rescmd
->start
,
953 resource_size(host
->rescmd
));
954 iounmap(host
->addr_va
);
955 release_mem_region(host
->resaddr
->start
,
956 resource_size(host
->resaddr
));
957 iounmap(host
->data_va
);
958 release_mem_region(host
->resdata
->start
,
959 resource_size(host
->resdata
));
967 static int fsmc_nand_suspend(struct device
*dev
)
969 struct fsmc_nand_data
*host
= dev_get_drvdata(dev
);
971 clk_disable(host
->clk
);
975 static int fsmc_nand_resume(struct device
*dev
)
977 struct fsmc_nand_data
*host
= dev_get_drvdata(dev
);
979 clk_enable(host
->clk
);
983 static const struct dev_pm_ops fsmc_nand_pm_ops
= {
984 .suspend
= fsmc_nand_suspend
,
985 .resume
= fsmc_nand_resume
,
989 static struct platform_driver fsmc_nand_driver
= {
990 .remove
= fsmc_nand_remove
,
992 .owner
= THIS_MODULE
,
995 .pm
= &fsmc_nand_pm_ops
,
1000 static int __init
fsmc_nand_init(void)
1002 return platform_driver_probe(&fsmc_nand_driver
,
1005 module_init(fsmc_nand_init
);
1007 static void __exit
fsmc_nand_exit(void)
1009 platform_driver_unregister(&fsmc_nand_driver
);
1011 module_exit(fsmc_nand_exit
);
1013 MODULE_LICENSE("GPL");
1014 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1015 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");