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mtd: gpmi: simplify the DLL setting code
[deliverable/linux.git] / drivers / mtd / nand / gpmi-nand / gpmi-lib.c
1 /*
2 * Freescale GPMI NAND Flash Driver
3 *
4 * Copyright (C) 2008-2011 Freescale Semiconductor, Inc.
5 * Copyright (C) 2008 Embedded Alley Solutions, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21 #include <linux/mtd/gpmi-nand.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24
25 #include "gpmi-nand.h"
26 #include "gpmi-regs.h"
27 #include "bch-regs.h"
28
29 static struct timing_threshod timing_default_threshold = {
30 .max_data_setup_cycles = (BM_GPMI_TIMING0_DATA_SETUP >>
31 BP_GPMI_TIMING0_DATA_SETUP),
32 .internal_data_setup_in_ns = 0,
33 .max_sample_delay_factor = (BM_GPMI_CTRL1_RDN_DELAY >>
34 BP_GPMI_CTRL1_RDN_DELAY),
35 .max_dll_clock_period_in_ns = 32,
36 .max_dll_delay_in_ns = 16,
37 };
38
39 #define MXS_SET_ADDR 0x4
40 #define MXS_CLR_ADDR 0x8
41 /*
42 * Clear the bit and poll it cleared. This is usually called with
43 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
44 * (bit 30).
45 */
46 static int clear_poll_bit(void __iomem *addr, u32 mask)
47 {
48 int timeout = 0x400;
49
50 /* clear the bit */
51 writel(mask, addr + MXS_CLR_ADDR);
52
53 /*
54 * SFTRST needs 3 GPMI clocks to settle, the reference manual
55 * recommends to wait 1us.
56 */
57 udelay(1);
58
59 /* poll the bit becoming clear */
60 while ((readl(addr) & mask) && --timeout)
61 /* nothing */;
62
63 return !timeout;
64 }
65
66 #define MODULE_CLKGATE (1 << 30)
67 #define MODULE_SFTRST (1 << 31)
68 /*
69 * The current mxs_reset_block() will do two things:
70 * [1] enable the module.
71 * [2] reset the module.
72 *
73 * In most of the cases, it's ok.
74 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
75 * If you try to soft reset the BCH block, it becomes unusable until
76 * the next hard reset. This case occurs in the NAND boot mode. When the board
77 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
78 * So If the driver tries to reset the BCH again, the BCH will not work anymore.
79 * You will see a DMA timeout in this case. The bug has been fixed
80 * in the following chips, such as MX28.
81 *
82 * To avoid this bug, just add a new parameter `just_enable` for
83 * the mxs_reset_block(), and rewrite it here.
84 */
85 static int gpmi_reset_block(void __iomem *reset_addr, bool just_enable)
86 {
87 int ret;
88 int timeout = 0x400;
89
90 /* clear and poll SFTRST */
91 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
92 if (unlikely(ret))
93 goto error;
94
95 /* clear CLKGATE */
96 writel(MODULE_CLKGATE, reset_addr + MXS_CLR_ADDR);
97
98 if (!just_enable) {
99 /* set SFTRST to reset the block */
100 writel(MODULE_SFTRST, reset_addr + MXS_SET_ADDR);
101 udelay(1);
102
103 /* poll CLKGATE becoming set */
104 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout)
105 /* nothing */;
106 if (unlikely(!timeout))
107 goto error;
108 }
109
110 /* clear and poll SFTRST */
111 ret = clear_poll_bit(reset_addr, MODULE_SFTRST);
112 if (unlikely(ret))
113 goto error;
114
115 /* clear and poll CLKGATE */
116 ret = clear_poll_bit(reset_addr, MODULE_CLKGATE);
117 if (unlikely(ret))
118 goto error;
119
120 return 0;
121
122 error:
123 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
124 return -ETIMEDOUT;
125 }
126
127 static int __gpmi_enable_clk(struct gpmi_nand_data *this, bool v)
128 {
129 struct clk *clk;
130 int ret;
131 int i;
132
133 for (i = 0; i < GPMI_CLK_MAX; i++) {
134 clk = this->resources.clock[i];
135 if (!clk)
136 break;
137
138 if (v) {
139 ret = clk_prepare_enable(clk);
140 if (ret)
141 goto err_clk;
142 } else {
143 clk_disable_unprepare(clk);
144 }
145 }
146 return 0;
147
148 err_clk:
149 for (; i > 0; i--)
150 clk_disable_unprepare(this->resources.clock[i - 1]);
151 return ret;
152 }
153
154 #define gpmi_enable_clk(x) __gpmi_enable_clk(x, true)
155 #define gpmi_disable_clk(x) __gpmi_enable_clk(x, false)
156
157 int gpmi_init(struct gpmi_nand_data *this)
158 {
159 struct resources *r = &this->resources;
160 int ret;
161
162 ret = gpmi_enable_clk(this);
163 if (ret)
164 goto err_out;
165 ret = gpmi_reset_block(r->gpmi_regs, false);
166 if (ret)
167 goto err_out;
168
169 /* Choose NAND mode. */
170 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR);
171
172 /* Set the IRQ polarity. */
173 writel(BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY,
174 r->gpmi_regs + HW_GPMI_CTRL1_SET);
175
176 /* Disable Write-Protection. */
177 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET);
178
179 /* Select BCH ECC. */
180 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET);
181
182 gpmi_disable_clk(this);
183 return 0;
184 err_out:
185 return ret;
186 }
187
188 /* This function is very useful. It is called only when the bug occur. */
189 void gpmi_dump_info(struct gpmi_nand_data *this)
190 {
191 struct resources *r = &this->resources;
192 struct bch_geometry *geo = &this->bch_geometry;
193 u32 reg;
194 int i;
195
196 pr_err("Show GPMI registers :\n");
197 for (i = 0; i <= HW_GPMI_DEBUG / 0x10 + 1; i++) {
198 reg = readl(r->gpmi_regs + i * 0x10);
199 pr_err("offset 0x%.3x : 0x%.8x\n", i * 0x10, reg);
200 }
201
202 /* start to print out the BCH info */
203 pr_err("BCH Geometry :\n");
204 pr_err("GF length : %u\n", geo->gf_len);
205 pr_err("ECC Strength : %u\n", geo->ecc_strength);
206 pr_err("Page Size in Bytes : %u\n", geo->page_size);
207 pr_err("Metadata Size in Bytes : %u\n", geo->metadata_size);
208 pr_err("ECC Chunk Size in Bytes: %u\n", geo->ecc_chunk_size);
209 pr_err("ECC Chunk Count : %u\n", geo->ecc_chunk_count);
210 pr_err("Payload Size in Bytes : %u\n", geo->payload_size);
211 pr_err("Auxiliary Size in Bytes: %u\n", geo->auxiliary_size);
212 pr_err("Auxiliary Status Offset: %u\n", geo->auxiliary_status_offset);
213 pr_err("Block Mark Byte Offset : %u\n", geo->block_mark_byte_offset);
214 pr_err("Block Mark Bit Offset : %u\n", geo->block_mark_bit_offset);
215 }
216
217 /* Configures the geometry for BCH. */
218 int bch_set_geometry(struct gpmi_nand_data *this)
219 {
220 struct resources *r = &this->resources;
221 struct bch_geometry *bch_geo = &this->bch_geometry;
222 unsigned int block_count;
223 unsigned int block_size;
224 unsigned int metadata_size;
225 unsigned int ecc_strength;
226 unsigned int page_size;
227 int ret;
228
229 if (common_nfc_set_geometry(this))
230 return !0;
231
232 block_count = bch_geo->ecc_chunk_count - 1;
233 block_size = bch_geo->ecc_chunk_size;
234 metadata_size = bch_geo->metadata_size;
235 ecc_strength = bch_geo->ecc_strength >> 1;
236 page_size = bch_geo->page_size;
237
238 ret = gpmi_enable_clk(this);
239 if (ret)
240 goto err_out;
241
242 /*
243 * Due to erratum #2847 of the MX23, the BCH cannot be soft reset on this
244 * chip, otherwise it will lock up. So we skip resetting BCH on the MX23.
245 * On the other hand, the MX28 needs the reset, because one case has been
246 * seen where the BCH produced ECC errors constantly after 10000
247 * consecutive reboots. The latter case has not been seen on the MX23 yet,
248 * still we don't know if it could happen there as well.
249 */
250 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MX23(this));
251 if (ret)
252 goto err_out;
253
254 /* Configure layout 0. */
255 writel(BF_BCH_FLASH0LAYOUT0_NBLOCKS(block_count)
256 | BF_BCH_FLASH0LAYOUT0_META_SIZE(metadata_size)
257 | BF_BCH_FLASH0LAYOUT0_ECC0(ecc_strength, this)
258 | BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(block_size, this),
259 r->bch_regs + HW_BCH_FLASH0LAYOUT0);
260
261 writel(BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size)
262 | BF_BCH_FLASH0LAYOUT1_ECCN(ecc_strength, this)
263 | BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(block_size, this),
264 r->bch_regs + HW_BCH_FLASH0LAYOUT1);
265
266 /* Set *all* chip selects to use layout 0. */
267 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT);
268
269 /* Enable interrupts. */
270 writel(BM_BCH_CTRL_COMPLETE_IRQ_EN,
271 r->bch_regs + HW_BCH_CTRL_SET);
272
273 gpmi_disable_clk(this);
274 return 0;
275 err_out:
276 return ret;
277 }
278
279 /* Converts time in nanoseconds to cycles. */
280 static unsigned int ns_to_cycles(unsigned int time,
281 unsigned int period, unsigned int min)
282 {
283 unsigned int k;
284
285 k = (time + period - 1) / period;
286 return max(k, min);
287 }
288
289 #define DEF_MIN_PROP_DELAY 5
290 #define DEF_MAX_PROP_DELAY 9
291 /* Apply timing to current hardware conditions. */
292 static int gpmi_nfc_compute_hardware_timing(struct gpmi_nand_data *this,
293 struct gpmi_nfc_hardware_timing *hw)
294 {
295 struct timing_threshod *nfc = &timing_default_threshold;
296 struct resources *r = &this->resources;
297 struct nand_chip *nand = &this->nand;
298 struct nand_timing target = this->timing;
299 bool improved_timing_is_available;
300 unsigned long clock_frequency_in_hz;
301 unsigned int clock_period_in_ns;
302 bool dll_use_half_periods;
303 unsigned int dll_delay_shift;
304 unsigned int max_sample_delay_in_ns;
305 unsigned int address_setup_in_cycles;
306 unsigned int data_setup_in_ns;
307 unsigned int data_setup_in_cycles;
308 unsigned int data_hold_in_cycles;
309 int ideal_sample_delay_in_ns;
310 unsigned int sample_delay_factor;
311 int tEYE;
312 unsigned int min_prop_delay_in_ns = DEF_MIN_PROP_DELAY;
313 unsigned int max_prop_delay_in_ns = DEF_MAX_PROP_DELAY;
314
315 /*
316 * If there are multiple chips, we need to relax the timings to allow
317 * for signal distortion due to higher capacitance.
318 */
319 if (nand->numchips > 2) {
320 target.data_setup_in_ns += 10;
321 target.data_hold_in_ns += 10;
322 target.address_setup_in_ns += 10;
323 } else if (nand->numchips > 1) {
324 target.data_setup_in_ns += 5;
325 target.data_hold_in_ns += 5;
326 target.address_setup_in_ns += 5;
327 }
328
329 /* Check if improved timing information is available. */
330 improved_timing_is_available =
331 (target.tREA_in_ns >= 0) &&
332 (target.tRLOH_in_ns >= 0) &&
333 (target.tRHOH_in_ns >= 0) ;
334
335 /* Inspect the clock. */
336 nfc->clock_frequency_in_hz = clk_get_rate(r->clock[0]);
337 clock_frequency_in_hz = nfc->clock_frequency_in_hz;
338 clock_period_in_ns = NSEC_PER_SEC / clock_frequency_in_hz;
339
340 /*
341 * The NFC quantizes setup and hold parameters in terms of clock cycles.
342 * Here, we quantize the setup and hold timing parameters to the
343 * next-highest clock period to make sure we apply at least the
344 * specified times.
345 *
346 * For data setup and data hold, the hardware interprets a value of zero
347 * as the largest possible delay. This is not what's intended by a zero
348 * in the input parameter, so we impose a minimum of one cycle.
349 */
350 data_setup_in_cycles = ns_to_cycles(target.data_setup_in_ns,
351 clock_period_in_ns, 1);
352 data_hold_in_cycles = ns_to_cycles(target.data_hold_in_ns,
353 clock_period_in_ns, 1);
354 address_setup_in_cycles = ns_to_cycles(target.address_setup_in_ns,
355 clock_period_in_ns, 0);
356
357 /*
358 * The clock's period affects the sample delay in a number of ways:
359 *
360 * (1) The NFC HAL tells us the maximum clock period the sample delay
361 * DLL can tolerate. If the clock period is greater than half that
362 * maximum, we must configure the DLL to be driven by half periods.
363 *
364 * (2) We need to convert from an ideal sample delay, in ns, to a
365 * "sample delay factor," which the NFC uses. This factor depends on
366 * whether we're driving the DLL with full or half periods.
367 * Paraphrasing the reference manual:
368 *
369 * AD = SDF x 0.125 x RP
370 *
371 * where:
372 *
373 * AD is the applied delay, in ns.
374 * SDF is the sample delay factor, which is dimensionless.
375 * RP is the reference period, in ns, which is a full clock period
376 * if the DLL is being driven by full periods, or half that if
377 * the DLL is being driven by half periods.
378 *
379 * Let's re-arrange this in a way that's more useful to us:
380 *
381 * 8
382 * SDF = AD x ----
383 * RP
384 *
385 * The reference period is either the clock period or half that, so this
386 * is:
387 *
388 * 8 AD x DDF
389 * SDF = AD x ----- = --------
390 * f x P P
391 *
392 * where:
393 *
394 * f is 1 or 1/2, depending on how we're driving the DLL.
395 * P is the clock period.
396 * DDF is the DLL Delay Factor, a dimensionless value that
397 * incorporates all the constants in the conversion.
398 *
399 * DDF will be either 8 or 16, both of which are powers of two. We can
400 * reduce the cost of this conversion by using bit shifts instead of
401 * multiplication or division. Thus:
402 *
403 * AD << DDS
404 * SDF = ---------
405 * P
406 *
407 * or
408 *
409 * AD = (SDF >> DDS) x P
410 *
411 * where:
412 *
413 * DDS is the DLL Delay Shift, the logarithm to base 2 of the DDF.
414 */
415 if (clock_period_in_ns > (nfc->max_dll_clock_period_in_ns >> 1)) {
416 dll_use_half_periods = true;
417 dll_delay_shift = 3 + 1;
418 } else {
419 dll_use_half_periods = false;
420 dll_delay_shift = 3;
421 }
422
423 /*
424 * Compute the maximum sample delay the NFC allows, under current
425 * conditions. If the clock is running too slowly, no sample delay is
426 * possible.
427 */
428 if (clock_period_in_ns > nfc->max_dll_clock_period_in_ns)
429 max_sample_delay_in_ns = 0;
430 else {
431 /*
432 * Compute the delay implied by the largest sample delay factor
433 * the NFC allows.
434 */
435 max_sample_delay_in_ns =
436 (nfc->max_sample_delay_factor * clock_period_in_ns) >>
437 dll_delay_shift;
438
439 /*
440 * Check if the implied sample delay larger than the NFC
441 * actually allows.
442 */
443 if (max_sample_delay_in_ns > nfc->max_dll_delay_in_ns)
444 max_sample_delay_in_ns = nfc->max_dll_delay_in_ns;
445 }
446
447 /*
448 * Check if improved timing information is available. If not, we have to
449 * use a less-sophisticated algorithm.
450 */
451 if (!improved_timing_is_available) {
452 /*
453 * Fold the read setup time required by the NFC into the ideal
454 * sample delay.
455 */
456 ideal_sample_delay_in_ns = target.gpmi_sample_delay_in_ns +
457 nfc->internal_data_setup_in_ns;
458
459 /*
460 * The ideal sample delay may be greater than the maximum
461 * allowed by the NFC. If so, we can trade off sample delay time
462 * for more data setup time.
463 *
464 * In each iteration of the following loop, we add a cycle to
465 * the data setup time and subtract a corresponding amount from
466 * the sample delay until we've satisified the constraints or
467 * can't do any better.
468 */
469 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
470 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
471
472 data_setup_in_cycles++;
473 ideal_sample_delay_in_ns -= clock_period_in_ns;
474
475 if (ideal_sample_delay_in_ns < 0)
476 ideal_sample_delay_in_ns = 0;
477
478 }
479
480 /*
481 * Compute the sample delay factor that corresponds most closely
482 * to the ideal sample delay. If the result is too large for the
483 * NFC, use the maximum value.
484 *
485 * Notice that we use the ns_to_cycles function to compute the
486 * sample delay factor. We do this because the form of the
487 * computation is the same as that for calculating cycles.
488 */
489 sample_delay_factor =
490 ns_to_cycles(
491 ideal_sample_delay_in_ns << dll_delay_shift,
492 clock_period_in_ns, 0);
493
494 if (sample_delay_factor > nfc->max_sample_delay_factor)
495 sample_delay_factor = nfc->max_sample_delay_factor;
496
497 /* Skip to the part where we return our results. */
498 goto return_results;
499 }
500
501 /*
502 * If control arrives here, we have more detailed timing information,
503 * so we can use a better algorithm.
504 */
505
506 /*
507 * Fold the read setup time required by the NFC into the maximum
508 * propagation delay.
509 */
510 max_prop_delay_in_ns += nfc->internal_data_setup_in_ns;
511
512 /*
513 * Earlier, we computed the number of clock cycles required to satisfy
514 * the data setup time. Now, we need to know the actual nanoseconds.
515 */
516 data_setup_in_ns = clock_period_in_ns * data_setup_in_cycles;
517
518 /*
519 * Compute tEYE, the width of the data eye when reading from the NAND
520 * Flash. The eye width is fundamentally determined by the data setup
521 * time, perturbed by propagation delays and some characteristics of the
522 * NAND Flash device.
523 *
524 * start of the eye = max_prop_delay + tREA
525 * end of the eye = min_prop_delay + tRHOH + data_setup
526 */
527 tEYE = (int)min_prop_delay_in_ns + (int)target.tRHOH_in_ns +
528 (int)data_setup_in_ns;
529
530 tEYE -= (int)max_prop_delay_in_ns + (int)target.tREA_in_ns;
531
532 /*
533 * The eye must be open. If it's not, we can try to open it by
534 * increasing its main forcer, the data setup time.
535 *
536 * In each iteration of the following loop, we increase the data setup
537 * time by a single clock cycle. We do this until either the eye is
538 * open or we run into NFC limits.
539 */
540 while ((tEYE <= 0) &&
541 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
542 /* Give a cycle to data setup. */
543 data_setup_in_cycles++;
544 /* Synchronize the data setup time with the cycles. */
545 data_setup_in_ns += clock_period_in_ns;
546 /* Adjust tEYE accordingly. */
547 tEYE += clock_period_in_ns;
548 }
549
550 /*
551 * When control arrives here, the eye is open. The ideal time to sample
552 * the data is in the center of the eye:
553 *
554 * end of the eye + start of the eye
555 * --------------------------------- - data_setup
556 * 2
557 *
558 * After some algebra, this simplifies to the code immediately below.
559 */
560 ideal_sample_delay_in_ns =
561 ((int)max_prop_delay_in_ns +
562 (int)target.tREA_in_ns +
563 (int)min_prop_delay_in_ns +
564 (int)target.tRHOH_in_ns -
565 (int)data_setup_in_ns) >> 1;
566
567 /*
568 * The following figure illustrates some aspects of a NAND Flash read:
569 *
570 *
571 * __ _____________________________________
572 * RDN \_________________/
573 *
574 * <---- tEYE ----->
575 * /-----------------\
576 * Read Data ----------------------------< >---------
577 * \-----------------/
578 * ^ ^ ^ ^
579 * | | | |
580 * |<--Data Setup -->|<--Delay Time -->| |
581 * | | | |
582 * | | |
583 * | |<-- Quantized Delay Time -->|
584 * | | |
585 *
586 *
587 * We have some issues we must now address:
588 *
589 * (1) The *ideal* sample delay time must not be negative. If it is, we
590 * jam it to zero.
591 *
592 * (2) The *ideal* sample delay time must not be greater than that
593 * allowed by the NFC. If it is, we can increase the data setup
594 * time, which will reduce the delay between the end of the data
595 * setup and the center of the eye. It will also make the eye
596 * larger, which might help with the next issue...
597 *
598 * (3) The *quantized* sample delay time must not fall either before the
599 * eye opens or after it closes (the latter is the problem
600 * illustrated in the above figure).
601 */
602
603 /* Jam a negative ideal sample delay to zero. */
604 if (ideal_sample_delay_in_ns < 0)
605 ideal_sample_delay_in_ns = 0;
606
607 /*
608 * Extend the data setup as needed to reduce the ideal sample delay
609 * below the maximum permitted by the NFC.
610 */
611 while ((ideal_sample_delay_in_ns > max_sample_delay_in_ns) &&
612 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
613
614 /* Give a cycle to data setup. */
615 data_setup_in_cycles++;
616 /* Synchronize the data setup time with the cycles. */
617 data_setup_in_ns += clock_period_in_ns;
618 /* Adjust tEYE accordingly. */
619 tEYE += clock_period_in_ns;
620
621 /*
622 * Decrease the ideal sample delay by one half cycle, to keep it
623 * in the middle of the eye.
624 */
625 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
626
627 /* Jam a negative ideal sample delay to zero. */
628 if (ideal_sample_delay_in_ns < 0)
629 ideal_sample_delay_in_ns = 0;
630 }
631
632 /*
633 * Compute the sample delay factor that corresponds to the ideal sample
634 * delay. If the result is too large, then use the maximum allowed
635 * value.
636 *
637 * Notice that we use the ns_to_cycles function to compute the sample
638 * delay factor. We do this because the form of the computation is the
639 * same as that for calculating cycles.
640 */
641 sample_delay_factor =
642 ns_to_cycles(ideal_sample_delay_in_ns << dll_delay_shift,
643 clock_period_in_ns, 0);
644
645 if (sample_delay_factor > nfc->max_sample_delay_factor)
646 sample_delay_factor = nfc->max_sample_delay_factor;
647
648 /*
649 * These macros conveniently encapsulate a computation we'll use to
650 * continuously evaluate whether or not the data sample delay is inside
651 * the eye.
652 */
653 #define IDEAL_DELAY ((int) ideal_sample_delay_in_ns)
654
655 #define QUANTIZED_DELAY \
656 ((int) ((sample_delay_factor * clock_period_in_ns) >> \
657 dll_delay_shift))
658
659 #define DELAY_ERROR (abs(QUANTIZED_DELAY - IDEAL_DELAY))
660
661 #define SAMPLE_IS_NOT_WITHIN_THE_EYE (DELAY_ERROR > (tEYE >> 1))
662
663 /*
664 * While the quantized sample time falls outside the eye, reduce the
665 * sample delay or extend the data setup to move the sampling point back
666 * toward the eye. Do not allow the number of data setup cycles to
667 * exceed the maximum allowed by the NFC.
668 */
669 while (SAMPLE_IS_NOT_WITHIN_THE_EYE &&
670 (data_setup_in_cycles < nfc->max_data_setup_cycles)) {
671 /*
672 * If control arrives here, the quantized sample delay falls
673 * outside the eye. Check if it's before the eye opens, or after
674 * the eye closes.
675 */
676 if (QUANTIZED_DELAY > IDEAL_DELAY) {
677 /*
678 * If control arrives here, the quantized sample delay
679 * falls after the eye closes. Decrease the quantized
680 * delay time and then go back to re-evaluate.
681 */
682 if (sample_delay_factor != 0)
683 sample_delay_factor--;
684 continue;
685 }
686
687 /*
688 * If control arrives here, the quantized sample delay falls
689 * before the eye opens. Shift the sample point by increasing
690 * data setup time. This will also make the eye larger.
691 */
692
693 /* Give a cycle to data setup. */
694 data_setup_in_cycles++;
695 /* Synchronize the data setup time with the cycles. */
696 data_setup_in_ns += clock_period_in_ns;
697 /* Adjust tEYE accordingly. */
698 tEYE += clock_period_in_ns;
699
700 /*
701 * Decrease the ideal sample delay by one half cycle, to keep it
702 * in the middle of the eye.
703 */
704 ideal_sample_delay_in_ns -= (clock_period_in_ns >> 1);
705
706 /* ...and one less period for the delay time. */
707 ideal_sample_delay_in_ns -= clock_period_in_ns;
708
709 /* Jam a negative ideal sample delay to zero. */
710 if (ideal_sample_delay_in_ns < 0)
711 ideal_sample_delay_in_ns = 0;
712
713 /*
714 * We have a new ideal sample delay, so re-compute the quantized
715 * delay.
716 */
717 sample_delay_factor =
718 ns_to_cycles(
719 ideal_sample_delay_in_ns << dll_delay_shift,
720 clock_period_in_ns, 0);
721
722 if (sample_delay_factor > nfc->max_sample_delay_factor)
723 sample_delay_factor = nfc->max_sample_delay_factor;
724 }
725
726 /* Control arrives here when we're ready to return our results. */
727 return_results:
728 hw->data_setup_in_cycles = data_setup_in_cycles;
729 hw->data_hold_in_cycles = data_hold_in_cycles;
730 hw->address_setup_in_cycles = address_setup_in_cycles;
731 hw->use_half_periods = dll_use_half_periods;
732 hw->sample_delay_factor = sample_delay_factor;
733 hw->device_busy_timeout = GPMI_DEFAULT_BUSY_TIMEOUT;
734 hw->wrn_dly_sel = BV_GPMI_CTRL1_WRN_DLY_SEL_4_TO_8NS;
735
736 /* Return success. */
737 return 0;
738 }
739
740 /* Begin the I/O */
741 void gpmi_begin(struct gpmi_nand_data *this)
742 {
743 struct resources *r = &this->resources;
744 void __iomem *gpmi_regs = r->gpmi_regs;
745 unsigned int clock_period_in_ns;
746 uint32_t reg;
747 unsigned int dll_wait_time_in_us;
748 struct gpmi_nfc_hardware_timing hw;
749 int ret;
750
751 /* Enable the clock. */
752 ret = gpmi_enable_clk(this);
753 if (ret) {
754 pr_err("We failed in enable the clk\n");
755 goto err_out;
756 }
757
758 gpmi_nfc_compute_hardware_timing(this, &hw);
759
760 /* [1] Set HW_GPMI_TIMING0 */
761 reg = BF_GPMI_TIMING0_ADDRESS_SETUP(hw.address_setup_in_cycles) |
762 BF_GPMI_TIMING0_DATA_HOLD(hw.data_hold_in_cycles) |
763 BF_GPMI_TIMING0_DATA_SETUP(hw.data_setup_in_cycles) ;
764
765 writel(reg, gpmi_regs + HW_GPMI_TIMING0);
766
767 /* [2] Set HW_GPMI_TIMING1 */
768 writel(BF_GPMI_TIMING1_BUSY_TIMEOUT(hw.device_busy_timeout),
769 gpmi_regs + HW_GPMI_TIMING1);
770
771 /* [3] The following code is to set the HW_GPMI_CTRL1. */
772
773 /* Set the WRN_DLY_SEL */
774 writel(BM_GPMI_CTRL1_WRN_DLY_SEL, gpmi_regs + HW_GPMI_CTRL1_CLR);
775 writel(BF_GPMI_CTRL1_WRN_DLY_SEL(hw.wrn_dly_sel),
776 gpmi_regs + HW_GPMI_CTRL1_SET);
777
778 /* DLL_ENABLE must be set to 0 when setting RDN_DELAY or HALF_PERIOD. */
779 writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_CLR);
780
781 /* Clear out the DLL control fields. */
782 reg = BM_GPMI_CTRL1_RDN_DELAY | BM_GPMI_CTRL1_HALF_PERIOD;
783 writel(reg, gpmi_regs + HW_GPMI_CTRL1_CLR);
784
785 /* If no sample delay is called for, return immediately. */
786 if (!hw.sample_delay_factor)
787 return;
788
789 /* Set RDN_DELAY or HALF_PERIOD. */
790 reg = ((hw.use_half_periods) ? BM_GPMI_CTRL1_HALF_PERIOD : 0)
791 | BF_GPMI_CTRL1_RDN_DELAY(hw.sample_delay_factor);
792
793 writel(reg, gpmi_regs + HW_GPMI_CTRL1_SET);
794
795 /* At last, we enable the DLL. */
796 writel(BM_GPMI_CTRL1_DLL_ENABLE, gpmi_regs + HW_GPMI_CTRL1_SET);
797
798 /*
799 * After we enable the GPMI DLL, we have to wait 64 clock cycles before
800 * we can use the GPMI. Calculate the amount of time we need to wait,
801 * in microseconds.
802 */
803 clock_period_in_ns = NSEC_PER_SEC / clk_get_rate(r->clock[0]);
804 dll_wait_time_in_us = (clock_period_in_ns * 64) / 1000;
805
806 if (!dll_wait_time_in_us)
807 dll_wait_time_in_us = 1;
808
809 /* Wait for the DLL to settle. */
810 udelay(dll_wait_time_in_us);
811
812 err_out:
813 return;
814 }
815
816 void gpmi_end(struct gpmi_nand_data *this)
817 {
818 gpmi_disable_clk(this);
819 }
820
821 /* Clears a BCH interrupt. */
822 void gpmi_clear_bch(struct gpmi_nand_data *this)
823 {
824 struct resources *r = &this->resources;
825 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR);
826 }
827
828 /* Returns the Ready/Busy status of the given chip. */
829 int gpmi_is_ready(struct gpmi_nand_data *this, unsigned chip)
830 {
831 struct resources *r = &this->resources;
832 uint32_t mask = 0;
833 uint32_t reg = 0;
834
835 if (GPMI_IS_MX23(this)) {
836 mask = MX23_BM_GPMI_DEBUG_READY0 << chip;
837 reg = readl(r->gpmi_regs + HW_GPMI_DEBUG);
838 } else if (GPMI_IS_MX28(this) || GPMI_IS_MX6Q(this)) {
839 /* MX28 shares the same R/B register as MX6Q. */
840 mask = MX28_BF_GPMI_STAT_READY_BUSY(1 << chip);
841 reg = readl(r->gpmi_regs + HW_GPMI_STAT);
842 } else
843 pr_err("unknow arch.\n");
844 return reg & mask;
845 }
846
847 static inline void set_dma_type(struct gpmi_nand_data *this,
848 enum dma_ops_type type)
849 {
850 this->last_dma_type = this->dma_type;
851 this->dma_type = type;
852 }
853
854 int gpmi_send_command(struct gpmi_nand_data *this)
855 {
856 struct dma_chan *channel = get_dma_chan(this);
857 struct dma_async_tx_descriptor *desc;
858 struct scatterlist *sgl;
859 int chip = this->current_chip;
860 u32 pio[3];
861
862 /* [1] send out the PIO words */
863 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__WRITE)
864 | BM_GPMI_CTRL0_WORD_LENGTH
865 | BF_GPMI_CTRL0_CS(chip, this)
866 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
867 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_CLE)
868 | BM_GPMI_CTRL0_ADDRESS_INCREMENT
869 | BF_GPMI_CTRL0_XFER_COUNT(this->command_length);
870 pio[1] = pio[2] = 0;
871 desc = dmaengine_prep_slave_sg(channel,
872 (struct scatterlist *)pio,
873 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
874 if (!desc) {
875 pr_err("step 1 error\n");
876 return -1;
877 }
878
879 /* [2] send out the COMMAND + ADDRESS string stored in @buffer */
880 sgl = &this->cmd_sgl;
881
882 sg_init_one(sgl, this->cmd_buffer, this->command_length);
883 dma_map_sg(this->dev, sgl, 1, DMA_TO_DEVICE);
884 desc = dmaengine_prep_slave_sg(channel,
885 sgl, 1, DMA_MEM_TO_DEV,
886 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
887
888 if (!desc) {
889 pr_err("step 2 error\n");
890 return -1;
891 }
892
893 /* [3] submit the DMA */
894 set_dma_type(this, DMA_FOR_COMMAND);
895 return start_dma_without_bch_irq(this, desc);
896 }
897
898 int gpmi_send_data(struct gpmi_nand_data *this)
899 {
900 struct dma_async_tx_descriptor *desc;
901 struct dma_chan *channel = get_dma_chan(this);
902 int chip = this->current_chip;
903 uint32_t command_mode;
904 uint32_t address;
905 u32 pio[2];
906
907 /* [1] PIO */
908 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
909 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
910
911 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
912 | BM_GPMI_CTRL0_WORD_LENGTH
913 | BF_GPMI_CTRL0_CS(chip, this)
914 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
915 | BF_GPMI_CTRL0_ADDRESS(address)
916 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
917 pio[1] = 0;
918 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
919 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
920 if (!desc) {
921 pr_err("step 1 error\n");
922 return -1;
923 }
924
925 /* [2] send DMA request */
926 prepare_data_dma(this, DMA_TO_DEVICE);
927 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
928 1, DMA_MEM_TO_DEV,
929 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
930 if (!desc) {
931 pr_err("step 2 error\n");
932 return -1;
933 }
934 /* [3] submit the DMA */
935 set_dma_type(this, DMA_FOR_WRITE_DATA);
936 return start_dma_without_bch_irq(this, desc);
937 }
938
939 int gpmi_read_data(struct gpmi_nand_data *this)
940 {
941 struct dma_async_tx_descriptor *desc;
942 struct dma_chan *channel = get_dma_chan(this);
943 int chip = this->current_chip;
944 u32 pio[2];
945
946 /* [1] : send PIO */
947 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(BV_GPMI_CTRL0_COMMAND_MODE__READ)
948 | BM_GPMI_CTRL0_WORD_LENGTH
949 | BF_GPMI_CTRL0_CS(chip, this)
950 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
951 | BF_GPMI_CTRL0_ADDRESS(BV_GPMI_CTRL0_ADDRESS__NAND_DATA)
952 | BF_GPMI_CTRL0_XFER_COUNT(this->upper_len);
953 pio[1] = 0;
954 desc = dmaengine_prep_slave_sg(channel,
955 (struct scatterlist *)pio,
956 ARRAY_SIZE(pio), DMA_TRANS_NONE, 0);
957 if (!desc) {
958 pr_err("step 1 error\n");
959 return -1;
960 }
961
962 /* [2] : send DMA request */
963 prepare_data_dma(this, DMA_FROM_DEVICE);
964 desc = dmaengine_prep_slave_sg(channel, &this->data_sgl,
965 1, DMA_DEV_TO_MEM,
966 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
967 if (!desc) {
968 pr_err("step 2 error\n");
969 return -1;
970 }
971
972 /* [3] : submit the DMA */
973 set_dma_type(this, DMA_FOR_READ_DATA);
974 return start_dma_without_bch_irq(this, desc);
975 }
976
977 int gpmi_send_page(struct gpmi_nand_data *this,
978 dma_addr_t payload, dma_addr_t auxiliary)
979 {
980 struct bch_geometry *geo = &this->bch_geometry;
981 uint32_t command_mode;
982 uint32_t address;
983 uint32_t ecc_command;
984 uint32_t buffer_mask;
985 struct dma_async_tx_descriptor *desc;
986 struct dma_chan *channel = get_dma_chan(this);
987 int chip = this->current_chip;
988 u32 pio[6];
989
990 /* A DMA descriptor that does an ECC page read. */
991 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WRITE;
992 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
993 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_ENCODE;
994 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE |
995 BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
996
997 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
998 | BM_GPMI_CTRL0_WORD_LENGTH
999 | BF_GPMI_CTRL0_CS(chip, this)
1000 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1001 | BF_GPMI_CTRL0_ADDRESS(address)
1002 | BF_GPMI_CTRL0_XFER_COUNT(0);
1003 pio[1] = 0;
1004 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1005 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1006 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1007 pio[3] = geo->page_size;
1008 pio[4] = payload;
1009 pio[5] = auxiliary;
1010
1011 desc = dmaengine_prep_slave_sg(channel,
1012 (struct scatterlist *)pio,
1013 ARRAY_SIZE(pio), DMA_TRANS_NONE,
1014 DMA_CTRL_ACK);
1015 if (!desc) {
1016 pr_err("step 2 error\n");
1017 return -1;
1018 }
1019 set_dma_type(this, DMA_FOR_WRITE_ECC_PAGE);
1020 return start_dma_with_bch_irq(this, desc);
1021 }
1022
1023 int gpmi_read_page(struct gpmi_nand_data *this,
1024 dma_addr_t payload, dma_addr_t auxiliary)
1025 {
1026 struct bch_geometry *geo = &this->bch_geometry;
1027 uint32_t command_mode;
1028 uint32_t address;
1029 uint32_t ecc_command;
1030 uint32_t buffer_mask;
1031 struct dma_async_tx_descriptor *desc;
1032 struct dma_chan *channel = get_dma_chan(this);
1033 int chip = this->current_chip;
1034 u32 pio[6];
1035
1036 /* [1] Wait for the chip to report ready. */
1037 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1038 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1039
1040 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1041 | BM_GPMI_CTRL0_WORD_LENGTH
1042 | BF_GPMI_CTRL0_CS(chip, this)
1043 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1044 | BF_GPMI_CTRL0_ADDRESS(address)
1045 | BF_GPMI_CTRL0_XFER_COUNT(0);
1046 pio[1] = 0;
1047 desc = dmaengine_prep_slave_sg(channel,
1048 (struct scatterlist *)pio, 2,
1049 DMA_TRANS_NONE, 0);
1050 if (!desc) {
1051 pr_err("step 1 error\n");
1052 return -1;
1053 }
1054
1055 /* [2] Enable the BCH block and read. */
1056 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__READ;
1057 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1058 ecc_command = BV_GPMI_ECCCTRL_ECC_CMD__BCH_DECODE;
1059 buffer_mask = BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE
1060 | BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY;
1061
1062 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1063 | BM_GPMI_CTRL0_WORD_LENGTH
1064 | BF_GPMI_CTRL0_CS(chip, this)
1065 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1066 | BF_GPMI_CTRL0_ADDRESS(address)
1067 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1068
1069 pio[1] = 0;
1070 pio[2] = BM_GPMI_ECCCTRL_ENABLE_ECC
1071 | BF_GPMI_ECCCTRL_ECC_CMD(ecc_command)
1072 | BF_GPMI_ECCCTRL_BUFFER_MASK(buffer_mask);
1073 pio[3] = geo->page_size;
1074 pio[4] = payload;
1075 pio[5] = auxiliary;
1076 desc = dmaengine_prep_slave_sg(channel,
1077 (struct scatterlist *)pio,
1078 ARRAY_SIZE(pio), DMA_TRANS_NONE,
1079 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1080 if (!desc) {
1081 pr_err("step 2 error\n");
1082 return -1;
1083 }
1084
1085 /* [3] Disable the BCH block */
1086 command_mode = BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY;
1087 address = BV_GPMI_CTRL0_ADDRESS__NAND_DATA;
1088
1089 pio[0] = BF_GPMI_CTRL0_COMMAND_MODE(command_mode)
1090 | BM_GPMI_CTRL0_WORD_LENGTH
1091 | BF_GPMI_CTRL0_CS(chip, this)
1092 | BF_GPMI_CTRL0_LOCK_CS(LOCK_CS_ENABLE, this)
1093 | BF_GPMI_CTRL0_ADDRESS(address)
1094 | BF_GPMI_CTRL0_XFER_COUNT(geo->page_size);
1095 pio[1] = 0;
1096 pio[2] = 0; /* clear GPMI_HW_GPMI_ECCCTRL, disable the BCH. */
1097 desc = dmaengine_prep_slave_sg(channel,
1098 (struct scatterlist *)pio, 3,
1099 DMA_TRANS_NONE,
1100 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1101 if (!desc) {
1102 pr_err("step 3 error\n");
1103 return -1;
1104 }
1105
1106 /* [4] submit the DMA */
1107 set_dma_type(this, DMA_FOR_READ_ECC_PAGE);
1108 return start_dma_with_bch_irq(this, desc);
1109 }
Linux kernel - Deliverables
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