2 * Hisilicon NAND Flash controller driver
4 * Copyright © 2012-2014 HiSilicon Technologies Co., Ltd.
5 * http://www.hisilicon.com
7 * Author: Zhou Wang <wangzhou.bry@gmail.com>
8 * The initial developer of the original code is Zhiyong Cai
9 * <caizhiyong@huawei.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/mtd/mtd.h>
23 #include <linux/sizes.h>
24 #include <linux/clk.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/interrupt.h>
29 #include <linux/mtd/nand.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/platform_device.h>
32 #include <linux/mtd/partitions.h>
34 #define HINFC504_MAX_CHIP (4)
35 #define HINFC504_W_LATCH (5)
36 #define HINFC504_R_LATCH (7)
37 #define HINFC504_RW_LATCH (3)
39 #define HINFC504_NFC_TIMEOUT (2 * HZ)
40 #define HINFC504_NFC_PM_TIMEOUT (1 * HZ)
41 #define HINFC504_NFC_DMA_TIMEOUT (5 * HZ)
42 #define HINFC504_CHIP_DELAY (25)
44 #define HINFC504_REG_BASE_ADDRESS_LEN (0x100)
45 #define HINFC504_BUFFER_BASE_ADDRESS_LEN (2048 + 128)
47 #define HINFC504_ADDR_CYCLE_MASK 0x4
49 #define HINFC504_CON 0x00
50 #define HINFC504_CON_OP_MODE_NORMAL BIT(0)
51 #define HINFC504_CON_PAGEISZE_SHIFT (1)
52 #define HINFC504_CON_PAGESIZE_MASK (0x07)
53 #define HINFC504_CON_BUS_WIDTH BIT(4)
54 #define HINFC504_CON_READY_BUSY_SEL BIT(8)
55 #define HINFC504_CON_ECCTYPE_SHIFT (9)
56 #define HINFC504_CON_ECCTYPE_MASK (0x07)
58 #define HINFC504_PWIDTH 0x04
59 #define SET_HINFC504_PWIDTH(_w_lcnt, _r_lcnt, _rw_hcnt) \
60 ((_w_lcnt) | (((_r_lcnt) & 0x0F) << 4) | (((_rw_hcnt) & 0x0F) << 8))
62 #define HINFC504_CMD 0x0C
63 #define HINFC504_ADDRL 0x10
64 #define HINFC504_ADDRH 0x14
65 #define HINFC504_DATA_NUM 0x18
67 #define HINFC504_OP 0x1C
68 #define HINFC504_OP_READ_DATA_EN BIT(1)
69 #define HINFC504_OP_WAIT_READY_EN BIT(2)
70 #define HINFC504_OP_CMD2_EN BIT(3)
71 #define HINFC504_OP_WRITE_DATA_EN BIT(4)
72 #define HINFC504_OP_ADDR_EN BIT(5)
73 #define HINFC504_OP_CMD1_EN BIT(6)
74 #define HINFC504_OP_NF_CS_SHIFT (7)
75 #define HINFC504_OP_NF_CS_MASK (3)
76 #define HINFC504_OP_ADDR_CYCLE_SHIFT (9)
77 #define HINFC504_OP_ADDR_CYCLE_MASK (7)
79 #define HINFC504_STATUS 0x20
80 #define HINFC504_READY BIT(0)
82 #define HINFC504_INTEN 0x24
83 #define HINFC504_INTEN_DMA BIT(9)
84 #define HINFC504_INTEN_UE BIT(6)
85 #define HINFC504_INTEN_CE BIT(5)
87 #define HINFC504_INTS 0x28
88 #define HINFC504_INTS_DMA BIT(9)
89 #define HINFC504_INTS_UE BIT(6)
90 #define HINFC504_INTS_CE BIT(5)
92 #define HINFC504_INTCLR 0x2C
93 #define HINFC504_INTCLR_DMA BIT(9)
94 #define HINFC504_INTCLR_UE BIT(6)
95 #define HINFC504_INTCLR_CE BIT(5)
97 #define HINFC504_ECC_STATUS 0x5C
98 #define HINFC504_ECC_16_BIT_SHIFT 12
100 #define HINFC504_DMA_CTRL 0x60
101 #define HINFC504_DMA_CTRL_DMA_START BIT(0)
102 #define HINFC504_DMA_CTRL_WE BIT(1)
103 #define HINFC504_DMA_CTRL_DATA_AREA_EN BIT(2)
104 #define HINFC504_DMA_CTRL_OOB_AREA_EN BIT(3)
105 #define HINFC504_DMA_CTRL_BURST4_EN BIT(4)
106 #define HINFC504_DMA_CTRL_BURST8_EN BIT(5)
107 #define HINFC504_DMA_CTRL_BURST16_EN BIT(6)
108 #define HINFC504_DMA_CTRL_ADDR_NUM_SHIFT (7)
109 #define HINFC504_DMA_CTRL_ADDR_NUM_MASK (1)
110 #define HINFC504_DMA_CTRL_CS_SHIFT (8)
111 #define HINFC504_DMA_CTRL_CS_MASK (0x03)
113 #define HINFC504_DMA_ADDR_DATA 0x64
114 #define HINFC504_DMA_ADDR_OOB 0x68
116 #define HINFC504_DMA_LEN 0x6C
117 #define HINFC504_DMA_LEN_OOB_SHIFT (16)
118 #define HINFC504_DMA_LEN_OOB_MASK (0xFFF)
120 #define HINFC504_DMA_PARA 0x70
121 #define HINFC504_DMA_PARA_DATA_RW_EN BIT(0)
122 #define HINFC504_DMA_PARA_OOB_RW_EN BIT(1)
123 #define HINFC504_DMA_PARA_DATA_EDC_EN BIT(2)
124 #define HINFC504_DMA_PARA_OOB_EDC_EN BIT(3)
125 #define HINFC504_DMA_PARA_DATA_ECC_EN BIT(4)
126 #define HINFC504_DMA_PARA_OOB_ECC_EN BIT(5)
128 #define HINFC_VERSION 0x74
129 #define HINFC504_LOG_READ_ADDR 0x7C
130 #define HINFC504_LOG_READ_LEN 0x80
132 #define HINFC504_NANDINFO_LEN 0x10
135 struct nand_chip chip
;
137 void __iomem
*iobase
;
139 struct completion cmd_complete
;
141 unsigned int command
;
143 unsigned int addr_cycle
;
145 u32 cache_addr_value
[2];
147 dma_addr_t dma_buffer
;
150 unsigned int irq_status
; /* interrupt status */
153 static inline unsigned int hinfc_read(struct hinfc_host
*host
, unsigned int reg
)
155 return readl(host
->iobase
+ reg
);
158 static inline void hinfc_write(struct hinfc_host
*host
, unsigned int value
,
161 writel(value
, host
->iobase
+ reg
);
164 static void wait_controller_finished(struct hinfc_host
*host
)
166 unsigned long timeout
= jiffies
+ HINFC504_NFC_TIMEOUT
;
169 while (time_before(jiffies
, timeout
)) {
170 val
= hinfc_read(host
, HINFC504_STATUS
);
171 if (host
->command
== NAND_CMD_ERASE2
) {
173 while (!(val
& HINFC504_READY
)) {
174 usleep_range(500, 1000);
175 val
= hinfc_read(host
, HINFC504_STATUS
);
180 if (val
& HINFC504_READY
)
184 /* wait cmd timeout */
185 dev_err(host
->dev
, "Wait NAND controller exec cmd timeout.\n");
188 static void hisi_nfc_dma_transfer(struct hinfc_host
*host
, int todev
)
190 struct nand_chip
*chip
= &host
->chip
;
191 struct mtd_info
*mtd
= nand_to_mtd(chip
);
195 hinfc_write(host
, host
->dma_buffer
, HINFC504_DMA_ADDR_DATA
);
196 hinfc_write(host
, host
->dma_oob
, HINFC504_DMA_ADDR_OOB
);
198 if (chip
->ecc
.mode
== NAND_ECC_NONE
) {
199 hinfc_write(host
, ((mtd
->oobsize
& HINFC504_DMA_LEN_OOB_MASK
)
200 << HINFC504_DMA_LEN_OOB_SHIFT
), HINFC504_DMA_LEN
);
202 hinfc_write(host
, HINFC504_DMA_PARA_DATA_RW_EN
203 | HINFC504_DMA_PARA_OOB_RW_EN
, HINFC504_DMA_PARA
);
205 if (host
->command
== NAND_CMD_READOOB
)
206 hinfc_write(host
, HINFC504_DMA_PARA_OOB_RW_EN
207 | HINFC504_DMA_PARA_OOB_EDC_EN
208 | HINFC504_DMA_PARA_OOB_ECC_EN
, HINFC504_DMA_PARA
);
210 hinfc_write(host
, HINFC504_DMA_PARA_DATA_RW_EN
211 | HINFC504_DMA_PARA_OOB_RW_EN
212 | HINFC504_DMA_PARA_DATA_EDC_EN
213 | HINFC504_DMA_PARA_OOB_EDC_EN
214 | HINFC504_DMA_PARA_DATA_ECC_EN
215 | HINFC504_DMA_PARA_OOB_ECC_EN
, HINFC504_DMA_PARA
);
219 val
= (HINFC504_DMA_CTRL_DMA_START
| HINFC504_DMA_CTRL_BURST4_EN
220 | HINFC504_DMA_CTRL_BURST8_EN
| HINFC504_DMA_CTRL_BURST16_EN
221 | HINFC504_DMA_CTRL_DATA_AREA_EN
| HINFC504_DMA_CTRL_OOB_AREA_EN
222 | ((host
->addr_cycle
== 4 ? 1 : 0)
223 << HINFC504_DMA_CTRL_ADDR_NUM_SHIFT
)
224 | ((host
->chipselect
& HINFC504_DMA_CTRL_CS_MASK
)
225 << HINFC504_DMA_CTRL_CS_SHIFT
));
228 val
|= HINFC504_DMA_CTRL_WE
;
230 init_completion(&host
->cmd_complete
);
232 hinfc_write(host
, val
, HINFC504_DMA_CTRL
);
233 ret
= wait_for_completion_timeout(&host
->cmd_complete
,
234 HINFC504_NFC_DMA_TIMEOUT
);
237 dev_err(host
->dev
, "DMA operation(irq) timeout!\n");
239 val
= hinfc_read(host
, HINFC504_DMA_CTRL
);
240 if (!(val
& HINFC504_DMA_CTRL_DMA_START
))
241 dev_err(host
->dev
, "DMA is already done but without irq ACK!\n");
243 dev_err(host
->dev
, "DMA is really timeout!\n");
247 static int hisi_nfc_send_cmd_pageprog(struct hinfc_host
*host
)
249 host
->addr_value
[0] &= 0xffff0000;
251 hinfc_write(host
, host
->addr_value
[0], HINFC504_ADDRL
);
252 hinfc_write(host
, host
->addr_value
[1], HINFC504_ADDRH
);
253 hinfc_write(host
, NAND_CMD_PAGEPROG
<< 8 | NAND_CMD_SEQIN
,
256 hisi_nfc_dma_transfer(host
, 1);
261 static int hisi_nfc_send_cmd_readstart(struct hinfc_host
*host
)
263 struct mtd_info
*mtd
= nand_to_mtd(&host
->chip
);
265 if ((host
->addr_value
[0] == host
->cache_addr_value
[0]) &&
266 (host
->addr_value
[1] == host
->cache_addr_value
[1]))
269 host
->addr_value
[0] &= 0xffff0000;
271 hinfc_write(host
, host
->addr_value
[0], HINFC504_ADDRL
);
272 hinfc_write(host
, host
->addr_value
[1], HINFC504_ADDRH
);
273 hinfc_write(host
, NAND_CMD_READSTART
<< 8 | NAND_CMD_READ0
,
276 hinfc_write(host
, 0, HINFC504_LOG_READ_ADDR
);
277 hinfc_write(host
, mtd
->writesize
+ mtd
->oobsize
,
278 HINFC504_LOG_READ_LEN
);
280 hisi_nfc_dma_transfer(host
, 0);
282 host
->cache_addr_value
[0] = host
->addr_value
[0];
283 host
->cache_addr_value
[1] = host
->addr_value
[1];
288 static int hisi_nfc_send_cmd_erase(struct hinfc_host
*host
)
290 hinfc_write(host
, host
->addr_value
[0], HINFC504_ADDRL
);
291 hinfc_write(host
, (NAND_CMD_ERASE2
<< 8) | NAND_CMD_ERASE1
,
294 hinfc_write(host
, HINFC504_OP_WAIT_READY_EN
295 | HINFC504_OP_CMD2_EN
296 | HINFC504_OP_CMD1_EN
297 | HINFC504_OP_ADDR_EN
298 | ((host
->chipselect
& HINFC504_OP_NF_CS_MASK
)
299 << HINFC504_OP_NF_CS_SHIFT
)
300 | ((host
->addr_cycle
& HINFC504_OP_ADDR_CYCLE_MASK
)
301 << HINFC504_OP_ADDR_CYCLE_SHIFT
),
304 wait_controller_finished(host
);
309 static int hisi_nfc_send_cmd_readid(struct hinfc_host
*host
)
311 hinfc_write(host
, HINFC504_NANDINFO_LEN
, HINFC504_DATA_NUM
);
312 hinfc_write(host
, NAND_CMD_READID
, HINFC504_CMD
);
313 hinfc_write(host
, 0, HINFC504_ADDRL
);
315 hinfc_write(host
, HINFC504_OP_CMD1_EN
| HINFC504_OP_ADDR_EN
316 | HINFC504_OP_READ_DATA_EN
317 | ((host
->chipselect
& HINFC504_OP_NF_CS_MASK
)
318 << HINFC504_OP_NF_CS_SHIFT
)
319 | 1 << HINFC504_OP_ADDR_CYCLE_SHIFT
, HINFC504_OP
);
321 wait_controller_finished(host
);
326 static int hisi_nfc_send_cmd_status(struct hinfc_host
*host
)
328 hinfc_write(host
, HINFC504_NANDINFO_LEN
, HINFC504_DATA_NUM
);
329 hinfc_write(host
, NAND_CMD_STATUS
, HINFC504_CMD
);
330 hinfc_write(host
, HINFC504_OP_CMD1_EN
331 | HINFC504_OP_READ_DATA_EN
332 | ((host
->chipselect
& HINFC504_OP_NF_CS_MASK
)
333 << HINFC504_OP_NF_CS_SHIFT
),
336 wait_controller_finished(host
);
341 static int hisi_nfc_send_cmd_reset(struct hinfc_host
*host
, int chipselect
)
343 hinfc_write(host
, NAND_CMD_RESET
, HINFC504_CMD
);
345 hinfc_write(host
, HINFC504_OP_CMD1_EN
346 | ((chipselect
& HINFC504_OP_NF_CS_MASK
)
347 << HINFC504_OP_NF_CS_SHIFT
)
348 | HINFC504_OP_WAIT_READY_EN
,
351 wait_controller_finished(host
);
356 static void hisi_nfc_select_chip(struct mtd_info
*mtd
, int chipselect
)
358 struct nand_chip
*chip
= mtd_to_nand(mtd
);
359 struct hinfc_host
*host
= nand_get_controller_data(chip
);
364 host
->chipselect
= chipselect
;
367 static uint8_t hisi_nfc_read_byte(struct mtd_info
*mtd
)
369 struct nand_chip
*chip
= mtd_to_nand(mtd
);
370 struct hinfc_host
*host
= nand_get_controller_data(chip
);
372 if (host
->command
== NAND_CMD_STATUS
)
373 return *(uint8_t *)(host
->mmio
);
377 if (host
->command
== NAND_CMD_READID
)
378 return *(uint8_t *)(host
->mmio
+ host
->offset
- 1);
380 return *(uint8_t *)(host
->buffer
+ host
->offset
- 1);
383 static u16
hisi_nfc_read_word(struct mtd_info
*mtd
)
385 struct nand_chip
*chip
= mtd_to_nand(mtd
);
386 struct hinfc_host
*host
= nand_get_controller_data(chip
);
389 return *(u16
*)(host
->buffer
+ host
->offset
- 2);
393 hisi_nfc_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
395 struct nand_chip
*chip
= mtd_to_nand(mtd
);
396 struct hinfc_host
*host
= nand_get_controller_data(chip
);
398 memcpy(host
->buffer
+ host
->offset
, buf
, len
);
402 static void hisi_nfc_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
404 struct nand_chip
*chip
= mtd_to_nand(mtd
);
405 struct hinfc_host
*host
= nand_get_controller_data(chip
);
407 memcpy(buf
, host
->buffer
+ host
->offset
, len
);
411 static void set_addr(struct mtd_info
*mtd
, int column
, int page_addr
)
413 struct nand_chip
*chip
= mtd_to_nand(mtd
);
414 struct hinfc_host
*host
= nand_get_controller_data(chip
);
415 unsigned int command
= host
->command
;
417 host
->addr_cycle
= 0;
418 host
->addr_value
[0] = 0;
419 host
->addr_value
[1] = 0;
421 /* Serially input address */
423 /* Adjust columns for 16 bit buswidth */
424 if (chip
->options
& NAND_BUSWIDTH_16
&&
425 !nand_opcode_8bits(command
))
428 host
->addr_value
[0] = column
& 0xffff;
429 host
->addr_cycle
= 2;
431 if (page_addr
!= -1) {
432 host
->addr_value
[0] |= (page_addr
& 0xffff)
433 << (host
->addr_cycle
* 8);
434 host
->addr_cycle
+= 2;
435 /* One more address cycle for devices > 128MiB */
436 if (chip
->chipsize
> (128 << 20)) {
437 host
->addr_cycle
+= 1;
438 if (host
->command
== NAND_CMD_ERASE1
)
439 host
->addr_value
[0] |= ((page_addr
>> 16) & 0xff) << 16;
441 host
->addr_value
[1] |= ((page_addr
>> 16) & 0xff);
446 static void hisi_nfc_cmdfunc(struct mtd_info
*mtd
, unsigned command
, int column
,
449 struct nand_chip
*chip
= mtd_to_nand(mtd
);
450 struct hinfc_host
*host
= nand_get_controller_data(chip
);
451 int is_cache_invalid
= 1;
452 unsigned int flag
= 0;
454 host
->command
= command
;
458 case NAND_CMD_READOOB
:
459 if (command
== NAND_CMD_READ0
)
460 host
->offset
= column
;
462 host
->offset
= column
+ mtd
->writesize
;
464 is_cache_invalid
= 0;
465 set_addr(mtd
, column
, page_addr
);
466 hisi_nfc_send_cmd_readstart(host
);
470 host
->offset
= column
;
471 set_addr(mtd
, column
, page_addr
);
474 case NAND_CMD_ERASE1
:
475 set_addr(mtd
, column
, page_addr
);
478 case NAND_CMD_PAGEPROG
:
479 hisi_nfc_send_cmd_pageprog(host
);
482 case NAND_CMD_ERASE2
:
483 hisi_nfc_send_cmd_erase(host
);
486 case NAND_CMD_READID
:
487 host
->offset
= column
;
488 memset(host
->mmio
, 0, 0x10);
489 hisi_nfc_send_cmd_readid(host
);
492 case NAND_CMD_STATUS
:
493 flag
= hinfc_read(host
, HINFC504_CON
);
494 if (chip
->ecc
.mode
== NAND_ECC_HW
)
496 flag
& ~(HINFC504_CON_ECCTYPE_MASK
<<
497 HINFC504_CON_ECCTYPE_SHIFT
), HINFC504_CON
);
500 memset(host
->mmio
, 0, 0x10);
501 hisi_nfc_send_cmd_status(host
);
502 hinfc_write(host
, flag
, HINFC504_CON
);
506 hisi_nfc_send_cmd_reset(host
, host
->chipselect
);
510 dev_err(host
->dev
, "Error: unsupported cmd(cmd=%x, col=%x, page=%x)\n",
511 command
, column
, page_addr
);
514 if (is_cache_invalid
) {
515 host
->cache_addr_value
[0] = ~0;
516 host
->cache_addr_value
[1] = ~0;
520 static irqreturn_t
hinfc_irq_handle(int irq
, void *devid
)
522 struct hinfc_host
*host
= devid
;
525 flag
= hinfc_read(host
, HINFC504_INTS
);
526 /* store interrupts state */
527 host
->irq_status
|= flag
;
529 if (flag
& HINFC504_INTS_DMA
) {
530 hinfc_write(host
, HINFC504_INTCLR_DMA
, HINFC504_INTCLR
);
531 complete(&host
->cmd_complete
);
532 } else if (flag
& HINFC504_INTS_CE
) {
533 hinfc_write(host
, HINFC504_INTCLR_CE
, HINFC504_INTCLR
);
534 } else if (flag
& HINFC504_INTS_UE
) {
535 hinfc_write(host
, HINFC504_INTCLR_UE
, HINFC504_INTCLR
);
541 static int hisi_nand_read_page_hwecc(struct mtd_info
*mtd
,
542 struct nand_chip
*chip
, uint8_t *buf
, int oob_required
, int page
)
544 struct hinfc_host
*host
= nand_get_controller_data(chip
);
545 int max_bitflips
= 0, stat
= 0, stat_max
= 0, status_ecc
;
548 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
549 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
551 /* errors which can not be corrected by ECC */
552 if (host
->irq_status
& HINFC504_INTS_UE
) {
553 mtd
->ecc_stats
.failed
++;
554 } else if (host
->irq_status
& HINFC504_INTS_CE
) {
555 /* TODO: need add other ECC modes! */
556 switch (chip
->ecc
.strength
) {
558 status_ecc
= hinfc_read(host
, HINFC504_ECC_STATUS
) >>
559 HINFC504_ECC_16_BIT_SHIFT
& 0x0fff;
560 stat_2
= status_ecc
& 0x3f;
561 stat_1
= status_ecc
>> 6 & 0x3f;
562 stat
= stat_1
+ stat_2
;
563 stat_max
= max_t(int, stat_1
, stat_2
);
565 mtd
->ecc_stats
.corrected
+= stat
;
566 max_bitflips
= max_t(int, max_bitflips
, stat_max
);
568 host
->irq_status
= 0;
573 static int hisi_nand_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
576 struct hinfc_host
*host
= nand_get_controller_data(chip
);
578 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
579 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
581 if (host
->irq_status
& HINFC504_INTS_UE
) {
582 host
->irq_status
= 0;
586 host
->irq_status
= 0;
590 static int hisi_nand_write_page_hwecc(struct mtd_info
*mtd
,
591 struct nand_chip
*chip
, const uint8_t *buf
, int oob_required
,
594 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
596 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
601 static void hisi_nfc_host_init(struct hinfc_host
*host
)
603 struct nand_chip
*chip
= &host
->chip
;
604 unsigned int flag
= 0;
606 host
->version
= hinfc_read(host
, HINFC_VERSION
);
607 host
->addr_cycle
= 0;
608 host
->addr_value
[0] = 0;
609 host
->addr_value
[1] = 0;
610 host
->cache_addr_value
[0] = ~0;
611 host
->cache_addr_value
[1] = ~0;
612 host
->chipselect
= 0;
614 /* default page size: 2K, ecc_none. need modify */
615 flag
= HINFC504_CON_OP_MODE_NORMAL
| HINFC504_CON_READY_BUSY_SEL
616 | ((0x001 & HINFC504_CON_PAGESIZE_MASK
)
617 << HINFC504_CON_PAGEISZE_SHIFT
)
618 | ((0x0 & HINFC504_CON_ECCTYPE_MASK
)
619 << HINFC504_CON_ECCTYPE_SHIFT
)
620 | ((chip
->options
& NAND_BUSWIDTH_16
) ?
621 HINFC504_CON_BUS_WIDTH
: 0);
622 hinfc_write(host
, flag
, HINFC504_CON
);
624 memset(host
->mmio
, 0xff, HINFC504_BUFFER_BASE_ADDRESS_LEN
);
626 hinfc_write(host
, SET_HINFC504_PWIDTH(HINFC504_W_LATCH
,
627 HINFC504_R_LATCH
, HINFC504_RW_LATCH
), HINFC504_PWIDTH
);
630 hinfc_write(host
, HINFC504_INTEN_DMA
, HINFC504_INTEN
);
633 static int hisi_ooblayout_ecc(struct mtd_info
*mtd
, int section
,
634 struct mtd_oob_region
*oobregion
)
636 /* FIXME: add ECC bytes position */
640 static int hisi_ooblayout_free(struct mtd_info
*mtd
, int section
,
641 struct mtd_oob_region
*oobregion
)
646 oobregion
->offset
= 2;
647 oobregion
->length
= 6;
652 static const struct mtd_ooblayout_ops hisi_ooblayout_ops
= {
653 .ecc
= hisi_ooblayout_ecc
,
654 .free
= hisi_ooblayout_free
,
657 static int hisi_nfc_ecc_probe(struct hinfc_host
*host
)
660 int size
, strength
, ecc_bits
;
661 struct device
*dev
= host
->dev
;
662 struct nand_chip
*chip
= &host
->chip
;
663 struct mtd_info
*mtd
= nand_to_mtd(chip
);
665 size
= chip
->ecc
.size
;
666 strength
= chip
->ecc
.strength
;
668 dev_err(dev
, "error ecc size: %d\n", size
);
672 if ((size
== 1024) && ((strength
!= 8) && (strength
!= 16) &&
673 (strength
!= 24) && (strength
!= 40))) {
674 dev_err(dev
, "ecc size and strength do not match\n");
678 chip
->ecc
.size
= size
;
679 chip
->ecc
.strength
= strength
;
681 chip
->ecc
.read_page
= hisi_nand_read_page_hwecc
;
682 chip
->ecc
.read_oob
= hisi_nand_read_oob
;
683 chip
->ecc
.write_page
= hisi_nand_write_page_hwecc
;
685 switch (chip
->ecc
.strength
) {
688 if (mtd
->writesize
== 2048)
689 mtd_set_ooblayout(mtd
, &hisi_ooblayout_ops
);
691 /* TODO: add more page size support */
694 /* TODO: add more ecc strength support */
696 dev_err(dev
, "not support strength: %d\n", chip
->ecc
.strength
);
700 flag
= hinfc_read(host
, HINFC504_CON
);
701 /* add ecc type configure */
702 flag
|= ((ecc_bits
& HINFC504_CON_ECCTYPE_MASK
)
703 << HINFC504_CON_ECCTYPE_SHIFT
);
704 hinfc_write(host
, flag
, HINFC504_CON
);
707 flag
= hinfc_read(host
, HINFC504_INTEN
) & 0xfff;
708 hinfc_write(host
, flag
| HINFC504_INTEN_UE
| HINFC504_INTEN_CE
,
714 static int hisi_nfc_probe(struct platform_device
*pdev
)
716 int ret
= 0, irq
, flag
, max_chips
= HINFC504_MAX_CHIP
;
717 struct device
*dev
= &pdev
->dev
;
718 struct hinfc_host
*host
;
719 struct nand_chip
*chip
;
720 struct mtd_info
*mtd
;
721 struct resource
*res
;
722 struct device_node
*np
= dev
->of_node
;
724 host
= devm_kzalloc(dev
, sizeof(*host
), GFP_KERNEL
);
729 platform_set_drvdata(pdev
, host
);
731 mtd
= nand_to_mtd(chip
);
733 irq
= platform_get_irq(pdev
, 0);
735 dev_err(dev
, "no IRQ resource defined\n");
740 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
741 host
->iobase
= devm_ioremap_resource(dev
, res
);
742 if (IS_ERR(host
->iobase
)) {
743 ret
= PTR_ERR(host
->iobase
);
747 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
748 host
->mmio
= devm_ioremap_resource(dev
, res
);
749 if (IS_ERR(host
->mmio
)) {
750 ret
= PTR_ERR(host
->mmio
);
751 dev_err(dev
, "devm_ioremap_resource[1] fail\n");
755 mtd
->name
= "hisi_nand";
756 mtd
->dev
.parent
= &pdev
->dev
;
758 nand_set_controller_data(chip
, host
);
759 nand_set_flash_node(chip
, np
);
760 chip
->cmdfunc
= hisi_nfc_cmdfunc
;
761 chip
->select_chip
= hisi_nfc_select_chip
;
762 chip
->read_byte
= hisi_nfc_read_byte
;
763 chip
->read_word
= hisi_nfc_read_word
;
764 chip
->write_buf
= hisi_nfc_write_buf
;
765 chip
->read_buf
= hisi_nfc_read_buf
;
766 chip
->chip_delay
= HINFC504_CHIP_DELAY
;
768 hisi_nfc_host_init(host
);
770 ret
= devm_request_irq(dev
, irq
, hinfc_irq_handle
, 0x0, "nandc", host
);
772 dev_err(dev
, "failed to request IRQ\n");
776 ret
= nand_scan_ident(mtd
, max_chips
, NULL
);
782 host
->buffer
= dmam_alloc_coherent(dev
, mtd
->writesize
+ mtd
->oobsize
,
783 &host
->dma_buffer
, GFP_KERNEL
);
789 host
->dma_oob
= host
->dma_buffer
+ mtd
->writesize
;
790 memset(host
->buffer
, 0xff, mtd
->writesize
+ mtd
->oobsize
);
792 flag
= hinfc_read(host
, HINFC504_CON
);
793 flag
&= ~(HINFC504_CON_PAGESIZE_MASK
<< HINFC504_CON_PAGEISZE_SHIFT
);
794 switch (mtd
->writesize
) {
796 flag
|= (0x001 << HINFC504_CON_PAGEISZE_SHIFT
); break;
798 * TODO: add more pagesize support,
799 * default pagesize has been set in hisi_nfc_host_init
802 dev_err(dev
, "NON-2KB page size nand flash\n");
806 hinfc_write(host
, flag
, HINFC504_CON
);
808 if (chip
->ecc
.mode
== NAND_ECC_HW
)
809 hisi_nfc_ecc_probe(host
);
811 ret
= nand_scan_tail(mtd
);
813 dev_err(dev
, "nand_scan_tail failed: %d\n", ret
);
817 ret
= mtd_device_register(mtd
, NULL
, 0);
819 dev_err(dev
, "Err MTD partition=%d\n", ret
);
831 static int hisi_nfc_remove(struct platform_device
*pdev
)
833 struct hinfc_host
*host
= platform_get_drvdata(pdev
);
834 struct mtd_info
*mtd
= nand_to_mtd(&host
->chip
);
841 #ifdef CONFIG_PM_SLEEP
842 static int hisi_nfc_suspend(struct device
*dev
)
844 struct hinfc_host
*host
= dev_get_drvdata(dev
);
845 unsigned long timeout
= jiffies
+ HINFC504_NFC_PM_TIMEOUT
;
847 while (time_before(jiffies
, timeout
)) {
848 if (((hinfc_read(host
, HINFC504_STATUS
) & 0x1) == 0x0) &&
849 (hinfc_read(host
, HINFC504_DMA_CTRL
) &
850 HINFC504_DMA_CTRL_DMA_START
)) {
856 dev_err(host
->dev
, "nand controller suspend timeout.\n");
861 static int hisi_nfc_resume(struct device
*dev
)
864 struct hinfc_host
*host
= dev_get_drvdata(dev
);
865 struct nand_chip
*chip
= &host
->chip
;
867 for (cs
= 0; cs
< chip
->numchips
; cs
++)
868 hisi_nfc_send_cmd_reset(host
, cs
);
869 hinfc_write(host
, SET_HINFC504_PWIDTH(HINFC504_W_LATCH
,
870 HINFC504_R_LATCH
, HINFC504_RW_LATCH
), HINFC504_PWIDTH
);
875 static SIMPLE_DEV_PM_OPS(hisi_nfc_pm_ops
, hisi_nfc_suspend
, hisi_nfc_resume
);
877 static const struct of_device_id nfc_id_table
[] = {
878 { .compatible
= "hisilicon,504-nfc" },
881 MODULE_DEVICE_TABLE(of
, nfc_id_table
);
883 static struct platform_driver hisi_nfc_driver
= {
886 .of_match_table
= nfc_id_table
,
887 .pm
= &hisi_nfc_pm_ops
,
889 .probe
= hisi_nfc_probe
,
890 .remove
= hisi_nfc_remove
,
893 module_platform_driver(hisi_nfc_driver
);
895 MODULE_LICENSE("GPL");
896 MODULE_AUTHOR("Zhou Wang");
897 MODULE_AUTHOR("Zhiyong Cai");
898 MODULE_DESCRIPTION("Hisilicon Nand Flash Controller Driver");