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mxc nand: modify send_page to send all pages, not only one
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36
37 #define DRIVER_NAME "mxc_nand"
38
39 /* Addresses for NFC registers */
40 #define NFC_BUF_SIZE 0xE00
41 #define NFC_BUF_ADDR 0xE04
42 #define NFC_FLASH_ADDR 0xE06
43 #define NFC_FLASH_CMD 0xE08
44 #define NFC_CONFIG 0xE0A
45 #define NFC_ECC_STATUS_RESULT 0xE0C
46 #define NFC_RSLTMAIN_AREA 0xE0E
47 #define NFC_RSLTSPARE_AREA 0xE10
48 #define NFC_WRPROT 0xE12
49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
50 #define NFC_UNLOCKEND_BLKADDR 0xE16
51 #define NFC_NF_WRPRST 0xE18
52 #define NFC_CONFIG1 0xE1A
53 #define NFC_CONFIG2 0xE1C
54
55 /* Addresses for NFC RAM BUFFER Main area 0 */
56 #define MAIN_AREA0 0x000
57 #define MAIN_AREA1 0x200
58 #define MAIN_AREA2 0x400
59 #define MAIN_AREA3 0x600
60
61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
62 #define SPARE_AREA0 0x800
63 #define SPARE_AREA1 0x810
64 #define SPARE_AREA2 0x820
65 #define SPARE_AREA3 0x830
66
67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
69 #define NFC_CMD 0x1
70
71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
73 #define NFC_ADDR 0x2
74
75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
77 #define NFC_INPUT 0x4
78
79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81 #define NFC_OUTPUT 0x8
82
83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
85 #define NFC_ID 0x10
86
87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89 #define NFC_STATUS 0x20
90
91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
92 * Status operation */
93 #define NFC_INT 0x8000
94
95 #define NFC_SP_EN (1 << 2)
96 #define NFC_ECC_EN (1 << 3)
97 #define NFC_INT_MSK (1 << 4)
98 #define NFC_BIG (1 << 5)
99 #define NFC_RST (1 << 6)
100 #define NFC_CE (1 << 7)
101 #define NFC_ONE_CYCLE (1 << 8)
102
103 struct mxc_nand_host {
104 struct mtd_info mtd;
105 struct nand_chip nand;
106 struct mtd_partition *parts;
107 struct device *dev;
108
109 void __iomem *regs;
110 int status_request;
111 int pagesize_2k;
112 struct clk *clk;
113 int clk_act;
114 int irq;
115
116 wait_queue_head_t irq_waitq;
117
118 uint8_t *data_buf;
119 unsigned int buf_start;
120 int spare_len;
121 };
122
123 /* Define delays in microsec for NAND device operations */
124 #define TROP_US_DELAY 2000
125 /* Macros to get byte and bit positions of ECC */
126 #define COLPOS(x) ((x) >> 3)
127 #define BITPOS(x) ((x) & 0xf)
128
129 /* Define single bit Error positions in Main & Spare area */
130 #define MAIN_SINGLEBIT_ERROR 0x4
131 #define SPARE_SINGLEBIT_ERROR 0x1
132
133 /* OOB placement block for use with hardware ecc generation */
134 static struct nand_ecclayout nand_hw_eccoob_smallpage = {
135 .eccbytes = 5,
136 .eccpos = {6, 7, 8, 9, 10},
137 .oobfree = {{0, 5}, {12, 4}, }
138 };
139
140 static struct nand_ecclayout nand_hw_eccoob_largepage = {
141 .eccbytes = 20,
142 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
143 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
144 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
145 };
146
147 #ifdef CONFIG_MTD_PARTITIONS
148 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
149 #endif
150
151 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
152 {
153 struct mxc_nand_host *host = dev_id;
154
155 uint16_t tmp;
156
157 tmp = readw(host->regs + NFC_CONFIG1);
158 tmp |= NFC_INT_MSK; /* Disable interrupt */
159 writew(tmp, host->regs + NFC_CONFIG1);
160
161 wake_up(&host->irq_waitq);
162
163 return IRQ_HANDLED;
164 }
165
166 /* This function polls the NANDFC to wait for the basic operation to
167 * complete by checking the INT bit of config2 register.
168 */
169 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
170 int useirq)
171 {
172 uint32_t tmp;
173
174 if (useirq) {
175 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
176
177 tmp = readw(host->regs + NFC_CONFIG1);
178 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
179 writew(tmp, host->regs + NFC_CONFIG1);
180
181 wait_event(host->irq_waitq,
182 readw(host->regs + NFC_CONFIG2) & NFC_INT);
183
184 tmp = readw(host->regs + NFC_CONFIG2);
185 tmp &= ~NFC_INT;
186 writew(tmp, host->regs + NFC_CONFIG2);
187 }
188 } else {
189 while (max_retries-- > 0) {
190 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
191 tmp = readw(host->regs + NFC_CONFIG2);
192 tmp &= ~NFC_INT;
193 writew(tmp, host->regs + NFC_CONFIG2);
194 break;
195 }
196 udelay(1);
197 }
198 if (max_retries < 0)
199 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
200 __func__);
201 }
202 }
203
204 /* This function issues the specified command to the NAND device and
205 * waits for completion. */
206 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
207 {
208 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
209
210 writew(cmd, host->regs + NFC_FLASH_CMD);
211 writew(NFC_CMD, host->regs + NFC_CONFIG2);
212
213 /* Wait for operation to complete */
214 wait_op_done(host, TROP_US_DELAY, useirq);
215 }
216
217 /* This function sends an address (or partial address) to the
218 * NAND device. The address is used to select the source/destination for
219 * a NAND command. */
220 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
221 {
222 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
223
224 writew(addr, host->regs + NFC_FLASH_ADDR);
225 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
226
227 /* Wait for operation to complete */
228 wait_op_done(host, TROP_US_DELAY, islast);
229 }
230
231 static void send_page(struct mxc_nand_host *host, unsigned int ops)
232 {
233 int bufs, i;
234
235 if (host->pagesize_2k)
236 bufs = 4;
237 else
238 bufs = 1;
239
240 for (i = 0; i < bufs; i++) {
241
242 /* NANDFC buffer 0 is used for page read/write */
243 writew(i, host->regs + NFC_BUF_ADDR);
244
245 writew(ops, host->regs + NFC_CONFIG2);
246
247 /* Wait for operation to complete */
248 wait_op_done(host, TROP_US_DELAY, true);
249 }
250 }
251
252 /* Request the NANDFC to perform a read of the NAND device ID. */
253 static void send_read_id(struct mxc_nand_host *host)
254 {
255 struct nand_chip *this = &host->nand;
256 uint16_t tmp;
257
258 /* NANDFC buffer 0 is used for device ID output */
259 writew(0x0, host->regs + NFC_BUF_ADDR);
260
261 /* Read ID into main buffer */
262 tmp = readw(host->regs + NFC_CONFIG1);
263 tmp &= ~NFC_SP_EN;
264 writew(tmp, host->regs + NFC_CONFIG1);
265
266 writew(NFC_ID, host->regs + NFC_CONFIG2);
267
268 /* Wait for operation to complete */
269 wait_op_done(host, TROP_US_DELAY, true);
270
271 if (this->options & NAND_BUSWIDTH_16) {
272 void __iomem *main_buf = host->regs + MAIN_AREA0;
273 /* compress the ID info */
274 writeb(readb(main_buf + 2), main_buf + 1);
275 writeb(readb(main_buf + 4), main_buf + 2);
276 writeb(readb(main_buf + 6), main_buf + 3);
277 writeb(readb(main_buf + 8), main_buf + 4);
278 writeb(readb(main_buf + 10), main_buf + 5);
279 }
280 memcpy(host->data_buf, host->regs + MAIN_AREA0, 16);
281 }
282
283 /* This function requests the NANDFC to perform a read of the
284 * NAND device status and returns the current status. */
285 static uint16_t get_dev_status(struct mxc_nand_host *host)
286 {
287 void __iomem *main_buf = host->regs + MAIN_AREA1;
288 uint32_t store;
289 uint16_t ret, tmp;
290 /* Issue status request to NAND device */
291
292 /* store the main area1 first word, later do recovery */
293 store = readl(main_buf);
294 /* NANDFC buffer 1 is used for device status to prevent
295 * corruption of read/write buffer on status requests. */
296 writew(1, host->regs + NFC_BUF_ADDR);
297
298 /* Read status into main buffer */
299 tmp = readw(host->regs + NFC_CONFIG1);
300 tmp &= ~NFC_SP_EN;
301 writew(tmp, host->regs + NFC_CONFIG1);
302
303 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
304
305 /* Wait for operation to complete */
306 wait_op_done(host, TROP_US_DELAY, true);
307
308 /* Status is placed in first word of main buffer */
309 /* get status, then recovery area 1 data */
310 ret = readw(main_buf);
311 writel(store, main_buf);
312
313 return ret;
314 }
315
316 /* This functions is used by upper layer to checks if device is ready */
317 static int mxc_nand_dev_ready(struct mtd_info *mtd)
318 {
319 /*
320 * NFC handles R/B internally. Therefore, this function
321 * always returns status as ready.
322 */
323 return 1;
324 }
325
326 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
327 {
328 /*
329 * If HW ECC is enabled, we turn it on during init. There is
330 * no need to enable again here.
331 */
332 }
333
334 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
335 u_char *read_ecc, u_char *calc_ecc)
336 {
337 struct nand_chip *nand_chip = mtd->priv;
338 struct mxc_nand_host *host = nand_chip->priv;
339
340 /*
341 * 1-Bit errors are automatically corrected in HW. No need for
342 * additional correction. 2-Bit errors cannot be corrected by
343 * HW ECC, so we need to return failure
344 */
345 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
346
347 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
348 DEBUG(MTD_DEBUG_LEVEL0,
349 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
350 return -1;
351 }
352
353 return 0;
354 }
355
356 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
357 u_char *ecc_code)
358 {
359 return 0;
360 }
361
362 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
363 {
364 struct nand_chip *nand_chip = mtd->priv;
365 struct mxc_nand_host *host = nand_chip->priv;
366 uint8_t ret;
367
368 /* Check for status request */
369 if (host->status_request)
370 return get_dev_status(host) & 0xFF;
371
372 ret = *(uint8_t *)(host->data_buf + host->buf_start);
373 host->buf_start++;
374
375 return ret;
376 }
377
378 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
379 {
380 struct nand_chip *nand_chip = mtd->priv;
381 struct mxc_nand_host *host = nand_chip->priv;
382 uint16_t ret;
383
384 ret = *(uint16_t *)(host->data_buf + host->buf_start);
385 host->buf_start += 2;
386
387 return ret;
388 }
389
390 /* Write data of length len to buffer buf. The data to be
391 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
392 * Operation by the NFC, the data is written to NAND Flash */
393 static void mxc_nand_write_buf(struct mtd_info *mtd,
394 const u_char *buf, int len)
395 {
396 struct nand_chip *nand_chip = mtd->priv;
397 struct mxc_nand_host *host = nand_chip->priv;
398 u16 col = host->buf_start;
399 int n = mtd->oobsize + mtd->writesize - col;
400
401 n = min(n, len);
402
403 memcpy(host->data_buf + col, buf, n);
404
405 host->buf_start += n;
406 }
407
408 /* Read the data buffer from the NAND Flash. To read the data from NAND
409 * Flash first the data output cycle is initiated by the NFC, which copies
410 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
411 */
412 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
413 {
414 struct nand_chip *nand_chip = mtd->priv;
415 struct mxc_nand_host *host = nand_chip->priv;
416 u16 col = host->buf_start;
417 int n = mtd->oobsize + mtd->writesize - col;
418
419 n = min(n, len);
420
421 memcpy(buf, host->data_buf + col, len);
422
423 host->buf_start += len;
424 }
425
426 /* Used by the upper layer to verify the data in NAND Flash
427 * with the data in the buf. */
428 static int mxc_nand_verify_buf(struct mtd_info *mtd,
429 const u_char *buf, int len)
430 {
431 return -EFAULT;
432 }
433
434 /* This function is used by upper layer for select and
435 * deselect of the NAND chip */
436 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
437 {
438 struct nand_chip *nand_chip = mtd->priv;
439 struct mxc_nand_host *host = nand_chip->priv;
440
441 switch (chip) {
442 case -1:
443 /* Disable the NFC clock */
444 if (host->clk_act) {
445 clk_disable(host->clk);
446 host->clk_act = 0;
447 }
448 break;
449 case 0:
450 /* Enable the NFC clock */
451 if (!host->clk_act) {
452 clk_enable(host->clk);
453 host->clk_act = 1;
454 }
455 break;
456
457 default:
458 break;
459 }
460 }
461
462 /*
463 * Function to transfer data to/from spare area.
464 */
465 static void copy_spare(struct mtd_info *mtd, bool bfrom)
466 {
467 struct nand_chip *this = mtd->priv;
468 struct mxc_nand_host *host = this->priv;
469 u16 i, j;
470 u16 n = mtd->writesize >> 9;
471 u8 *d = host->data_buf + mtd->writesize;
472 u8 *s = host->regs + SPARE_AREA0;
473 u16 t = host->spare_len;
474
475 j = (mtd->oobsize / n >> 1) << 1;
476
477 if (bfrom) {
478 for (i = 0; i < n - 1; i++)
479 memcpy(d + i * j, s + i * t, j);
480
481 /* the last section */
482 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
483 } else {
484 for (i = 0; i < n - 1; i++)
485 memcpy(&s[i * t], &d[i * j], j);
486
487 /* the last section */
488 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
489 }
490 }
491
492 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
493 {
494 struct nand_chip *nand_chip = mtd->priv;
495 struct mxc_nand_host *host = nand_chip->priv;
496
497 /* Write out column address, if necessary */
498 if (column != -1) {
499 /*
500 * MXC NANDFC can only perform full page+spare or
501 * spare-only read/write. When the upper layers
502 * layers perform a read/write buf operation,
503 * we will used the saved column adress to index into
504 * the full page.
505 */
506 send_addr(host, 0, page_addr == -1);
507 if (host->pagesize_2k)
508 /* another col addr cycle for 2k page */
509 send_addr(host, 0, false);
510 }
511
512 /* Write out page address, if necessary */
513 if (page_addr != -1) {
514 /* paddr_0 - p_addr_7 */
515 send_addr(host, (page_addr & 0xff), false);
516
517 if (host->pagesize_2k) {
518 if (mtd->size >= 0x10000000) {
519 /* paddr_8 - paddr_15 */
520 send_addr(host, (page_addr >> 8) & 0xff, false);
521 send_addr(host, (page_addr >> 16) & 0xff, true);
522 } else
523 /* paddr_8 - paddr_15 */
524 send_addr(host, (page_addr >> 8) & 0xff, true);
525 } else {
526 /* One more address cycle for higher density devices */
527 if (mtd->size >= 0x4000000) {
528 /* paddr_8 - paddr_15 */
529 send_addr(host, (page_addr >> 8) & 0xff, false);
530 send_addr(host, (page_addr >> 16) & 0xff, true);
531 } else
532 /* paddr_8 - paddr_15 */
533 send_addr(host, (page_addr >> 8) & 0xff, true);
534 }
535 }
536 }
537
538 /* Used by the upper layer to write command to NAND Flash for
539 * different operations to be carried out on NAND Flash */
540 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
541 int column, int page_addr)
542 {
543 struct nand_chip *nand_chip = mtd->priv;
544 struct mxc_nand_host *host = nand_chip->priv;
545
546 DEBUG(MTD_DEBUG_LEVEL3,
547 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
548 command, column, page_addr);
549
550 /* Reset command state information */
551 host->status_request = false;
552
553 /* Command pre-processing step */
554 switch (command) {
555
556 case NAND_CMD_STATUS:
557 host->buf_start = 0;
558 host->status_request = true;
559
560 send_cmd(host, command, true);
561 mxc_do_addr_cycle(mtd, column, page_addr);
562 break;
563
564 case NAND_CMD_READ0:
565 case NAND_CMD_READOOB:
566 if (command == NAND_CMD_READ0)
567 host->buf_start = column;
568 else
569 host->buf_start = column + mtd->writesize;
570
571 if (host->pagesize_2k)
572 command = NAND_CMD_READ0; /* only READ0 is valid */
573
574 send_cmd(host, command, false);
575 mxc_do_addr_cycle(mtd, column, page_addr);
576
577 if (host->pagesize_2k)
578 send_cmd(host, NAND_CMD_READSTART, true);
579
580 send_page(host, NFC_OUTPUT);
581
582 memcpy(host->data_buf, host->regs + MAIN_AREA0, mtd->writesize);
583 copy_spare(mtd, true);
584 break;
585
586 case NAND_CMD_SEQIN:
587 if (column >= mtd->writesize) {
588 /*
589 * FIXME: before send SEQIN command for write OOB,
590 * We must read one page out.
591 * For K9F1GXX has no READ1 command to set current HW
592 * pointer to spare area, we must write the whole page
593 * including OOB together.
594 */
595 if (host->pagesize_2k)
596 /* call ourself to read a page */
597 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
598 page_addr);
599
600 host->buf_start = column;
601
602 /* Set program pointer to spare region */
603 if (!host->pagesize_2k)
604 send_cmd(host, NAND_CMD_READOOB, false);
605 } else {
606 host->buf_start = column;
607
608 /* Set program pointer to page start */
609 if (!host->pagesize_2k)
610 send_cmd(host, NAND_CMD_READ0, false);
611 }
612
613 send_cmd(host, command, false);
614 mxc_do_addr_cycle(mtd, column, page_addr);
615 break;
616
617 case NAND_CMD_PAGEPROG:
618 memcpy(host->regs + MAIN_AREA0, host->data_buf, mtd->writesize);
619 copy_spare(mtd, false);
620 send_page(host, NFC_INPUT);
621 send_cmd(host, command, true);
622 mxc_do_addr_cycle(mtd, column, page_addr);
623 break;
624
625 case NAND_CMD_READID:
626 send_cmd(host, command, true);
627 mxc_do_addr_cycle(mtd, column, page_addr);
628 send_read_id(host);
629 break;
630
631 case NAND_CMD_ERASE1:
632 case NAND_CMD_ERASE2:
633 send_cmd(host, command, false);
634 mxc_do_addr_cycle(mtd, column, page_addr);
635
636 break;
637 }
638 }
639
640 static int __init mxcnd_probe(struct platform_device *pdev)
641 {
642 struct nand_chip *this;
643 struct mtd_info *mtd;
644 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
645 struct mxc_nand_host *host;
646 struct resource *res;
647 uint16_t tmp;
648 int err = 0, nr_parts = 0;
649
650 /* Allocate memory for MTD device structure and private data */
651 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
652 NAND_MAX_OOBSIZE, GFP_KERNEL);
653 if (!host)
654 return -ENOMEM;
655
656 host->data_buf = (uint8_t *)(host + 1);
657 host->spare_len = 16;
658
659 host->dev = &pdev->dev;
660 /* structures must be linked */
661 this = &host->nand;
662 mtd = &host->mtd;
663 mtd->priv = this;
664 mtd->owner = THIS_MODULE;
665 mtd->dev.parent = &pdev->dev;
666 mtd->name = "mxc_nand";
667
668 /* 50 us command delay time */
669 this->chip_delay = 5;
670
671 this->priv = host;
672 this->dev_ready = mxc_nand_dev_ready;
673 this->cmdfunc = mxc_nand_command;
674 this->select_chip = mxc_nand_select_chip;
675 this->read_byte = mxc_nand_read_byte;
676 this->read_word = mxc_nand_read_word;
677 this->write_buf = mxc_nand_write_buf;
678 this->read_buf = mxc_nand_read_buf;
679 this->verify_buf = mxc_nand_verify_buf;
680
681 host->clk = clk_get(&pdev->dev, "nfc");
682 if (IS_ERR(host->clk)) {
683 err = PTR_ERR(host->clk);
684 goto eclk;
685 }
686
687 clk_enable(host->clk);
688 host->clk_act = 1;
689
690 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
691 if (!res) {
692 err = -ENODEV;
693 goto eres;
694 }
695
696 host->regs = ioremap(res->start, resource_size(res));
697 if (!host->regs) {
698 err = -ENOMEM;
699 goto eres;
700 }
701
702 tmp = readw(host->regs + NFC_CONFIG1);
703 tmp |= NFC_INT_MSK;
704 writew(tmp, host->regs + NFC_CONFIG1);
705
706 init_waitqueue_head(&host->irq_waitq);
707
708 host->irq = platform_get_irq(pdev, 0);
709
710 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
711 if (err)
712 goto eirq;
713
714 /* Reset NAND */
715 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
716
717 /* preset operation */
718 /* Unlock the internal RAM Buffer */
719 writew(0x2, host->regs + NFC_CONFIG);
720
721 /* Blocks to be unlocked */
722 writew(0x0, host->regs + NFC_UNLOCKSTART_BLKADDR);
723 writew(0x4000, host->regs + NFC_UNLOCKEND_BLKADDR);
724
725 /* Unlock Block Command for given address range */
726 writew(0x4, host->regs + NFC_WRPROT);
727
728 this->ecc.size = 512;
729 this->ecc.bytes = 3;
730 this->ecc.layout = &nand_hw_eccoob_smallpage;
731
732 if (pdata->hw_ecc) {
733 this->ecc.calculate = mxc_nand_calculate_ecc;
734 this->ecc.hwctl = mxc_nand_enable_hwecc;
735 this->ecc.correct = mxc_nand_correct_data;
736 this->ecc.mode = NAND_ECC_HW;
737 tmp = readw(host->regs + NFC_CONFIG1);
738 tmp |= NFC_ECC_EN;
739 writew(tmp, host->regs + NFC_CONFIG1);
740 } else {
741 this->ecc.mode = NAND_ECC_SOFT;
742 tmp = readw(host->regs + NFC_CONFIG1);
743 tmp &= ~NFC_ECC_EN;
744 writew(tmp, host->regs + NFC_CONFIG1);
745 }
746
747 /* NAND bus width determines access funtions used by upper layer */
748 if (pdata->width == 2)
749 this->options |= NAND_BUSWIDTH_16;
750
751 /* first scan to find the device and get the page size */
752 if (nand_scan_ident(mtd, 1)) {
753 err = -ENXIO;
754 goto escan;
755 }
756
757 if (mtd->writesize == 2048) {
758 host->pagesize_2k = 1;
759 this->ecc.layout = &nand_hw_eccoob_largepage;
760 }
761
762 /* second phase scan */
763 if (nand_scan_tail(mtd)) {
764 err = -ENXIO;
765 goto escan;
766 }
767
768 /* Register the partitions */
769 #ifdef CONFIG_MTD_PARTITIONS
770 nr_parts =
771 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
772 if (nr_parts > 0)
773 add_mtd_partitions(mtd, host->parts, nr_parts);
774 else
775 #endif
776 {
777 pr_info("Registering %s as whole device\n", mtd->name);
778 add_mtd_device(mtd);
779 }
780
781 platform_set_drvdata(pdev, host);
782
783 return 0;
784
785 escan:
786 free_irq(host->irq, host);
787 eirq:
788 iounmap(host->regs);
789 eres:
790 clk_put(host->clk);
791 eclk:
792 kfree(host);
793
794 return err;
795 }
796
797 static int __exit mxcnd_remove(struct platform_device *pdev)
798 {
799 struct mxc_nand_host *host = platform_get_drvdata(pdev);
800
801 clk_put(host->clk);
802
803 platform_set_drvdata(pdev, NULL);
804
805 nand_release(&host->mtd);
806 free_irq(host->irq, host);
807 iounmap(host->regs);
808 kfree(host);
809
810 return 0;
811 }
812
813 #ifdef CONFIG_PM
814 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
815 {
816 struct mtd_info *mtd = platform_get_drvdata(pdev);
817 struct nand_chip *nand_chip = mtd->priv;
818 struct mxc_nand_host *host = nand_chip->priv;
819 int ret = 0;
820
821 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
822 if (mtd) {
823 ret = mtd->suspend(mtd);
824 /* Disable the NFC clock */
825 clk_disable(host->clk);
826 }
827
828 return ret;
829 }
830
831 static int mxcnd_resume(struct platform_device *pdev)
832 {
833 struct mtd_info *mtd = platform_get_drvdata(pdev);
834 struct nand_chip *nand_chip = mtd->priv;
835 struct mxc_nand_host *host = nand_chip->priv;
836 int ret = 0;
837
838 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
839
840 if (mtd) {
841 /* Enable the NFC clock */
842 clk_enable(host->clk);
843 mtd->resume(mtd);
844 }
845
846 return ret;
847 }
848
849 #else
850 # define mxcnd_suspend NULL
851 # define mxcnd_resume NULL
852 #endif /* CONFIG_PM */
853
854 static struct platform_driver mxcnd_driver = {
855 .driver = {
856 .name = DRIVER_NAME,
857 },
858 .remove = __exit_p(mxcnd_remove),
859 .suspend = mxcnd_suspend,
860 .resume = mxcnd_resume,
861 };
862
863 static int __init mxc_nd_init(void)
864 {
865 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
866 }
867
868 static void __exit mxc_nd_cleanup(void)
869 {
870 /* Unregister the device structure */
871 platform_driver_unregister(&mxcnd_driver);
872 }
873
874 module_init(mxc_nd_init);
875 module_exit(mxc_nd_cleanup);
876
877 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
878 MODULE_DESCRIPTION("MXC NAND MTD driver");
879 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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