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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
39
40 #define DRIVER_NAME "mxc_nand"
41
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() cpu_is_mx51()
45 #define nfc_is_v3() nfc_is_v3_2()
46
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR (host->regs + 0x20)
60 #define NFC_V21_UNLOCKEND_BLKADDR (host->regs + 0x22)
61 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
62 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
63 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
64
65 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
66 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
67 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
68 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
69 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
70 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
71 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
72 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
73 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
74 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
75
76 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
77
78 /*
79 * Operation modes for the NFC. Valid for v1, v2 and v3
80 * type controllers.
81 */
82 #define NFC_CMD (1 << 0)
83 #define NFC_ADDR (1 << 1)
84 #define NFC_INPUT (1 << 2)
85 #define NFC_OUTPUT (1 << 3)
86 #define NFC_ID (1 << 4)
87 #define NFC_STATUS (1 << 5)
88
89 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
90 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
91
92 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
93 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
94 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
95
96 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
97
98 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
99
100 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
101 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
102 #define NFC_V3_WRPROT_LOCK (1 << 1)
103 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
104 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
105
106 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
107
108 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
109 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
110 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
111 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
112 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
113 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
114 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
115 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
116 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
117 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
118 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
119 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
120 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
121 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
122
123 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
124 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
125 #define NFC_V3_CONFIG3_FW8 (1 << 3)
126 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
127 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
128 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
129 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
130
131 #define NFC_V3_IPC (host->regs_ip + 0x2C)
132 #define NFC_V3_IPC_CREQ (1 << 0)
133 #define NFC_V3_IPC_INT (1 << 31)
134
135 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
136
137 struct mxc_nand_host {
138 struct mtd_info mtd;
139 struct nand_chip nand;
140 struct mtd_partition *parts;
141 struct device *dev;
142
143 void *spare0;
144 void *main_area0;
145
146 void __iomem *base;
147 void __iomem *regs;
148 void __iomem *regs_axi;
149 void __iomem *regs_ip;
150 int status_request;
151 struct clk *clk;
152 int clk_act;
153 int irq;
154 int eccsize;
155
156 struct completion op_completion;
157
158 uint8_t *data_buf;
159 unsigned int buf_start;
160 int spare_len;
161
162 void (*preset)(struct mtd_info *);
163 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
164 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
165 void (*send_page)(struct mtd_info *, unsigned int);
166 void (*send_read_id)(struct mxc_nand_host *);
167 uint16_t (*get_dev_status)(struct mxc_nand_host *);
168 int (*check_int)(struct mxc_nand_host *);
169 void (*irq_control)(struct mxc_nand_host *, int);
170 };
171
172 /* OOB placement block for use with hardware ecc generation */
173 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
174 .eccbytes = 5,
175 .eccpos = {6, 7, 8, 9, 10},
176 .oobfree = {{0, 5}, {12, 4}, }
177 };
178
179 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
180 .eccbytes = 20,
181 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
182 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
183 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
184 };
185
186 /* OOB description for 512 byte pages with 16 byte OOB */
187 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
188 .eccbytes = 1 * 9,
189 .eccpos = {
190 7, 8, 9, 10, 11, 12, 13, 14, 15
191 },
192 .oobfree = {
193 {.offset = 0, .length = 5}
194 }
195 };
196
197 /* OOB description for 2048 byte pages with 64 byte OOB */
198 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
199 .eccbytes = 4 * 9,
200 .eccpos = {
201 7, 8, 9, 10, 11, 12, 13, 14, 15,
202 23, 24, 25, 26, 27, 28, 29, 30, 31,
203 39, 40, 41, 42, 43, 44, 45, 46, 47,
204 55, 56, 57, 58, 59, 60, 61, 62, 63
205 },
206 .oobfree = {
207 {.offset = 2, .length = 4},
208 {.offset = 16, .length = 7},
209 {.offset = 32, .length = 7},
210 {.offset = 48, .length = 7}
211 }
212 };
213
214 #ifdef CONFIG_MTD_PARTITIONS
215 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
216 #endif
217
218 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
219 {
220 struct mxc_nand_host *host = dev_id;
221
222 if (!host->check_int(host))
223 return IRQ_NONE;
224
225 host->irq_control(host, 0);
226
227 complete(&host->op_completion);
228
229 return IRQ_HANDLED;
230 }
231
232 static int check_int_v3(struct mxc_nand_host *host)
233 {
234 uint32_t tmp;
235
236 tmp = readl(NFC_V3_IPC);
237 if (!(tmp & NFC_V3_IPC_INT))
238 return 0;
239
240 tmp &= ~NFC_V3_IPC_INT;
241 writel(tmp, NFC_V3_IPC);
242
243 return 1;
244 }
245
246 static int check_int_v1_v2(struct mxc_nand_host *host)
247 {
248 uint32_t tmp;
249
250 tmp = readw(NFC_V1_V2_CONFIG2);
251 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
252 return 0;
253
254 if (!cpu_is_mx21())
255 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
256
257 return 1;
258 }
259
260 /*
261 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
262 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
263 * driver can enable/disable the irq line rather than simply masking the
264 * interrupts.
265 */
266 static void irq_control_mx21(struct mxc_nand_host *host, int activate)
267 {
268 if (activate)
269 enable_irq(host->irq);
270 else
271 disable_irq_nosync(host->irq);
272 }
273
274 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
275 {
276 uint16_t tmp;
277
278 tmp = readw(NFC_V1_V2_CONFIG1);
279
280 if (activate)
281 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
282 else
283 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
284
285 writew(tmp, NFC_V1_V2_CONFIG1);
286 }
287
288 static void irq_control_v3(struct mxc_nand_host *host, int activate)
289 {
290 uint32_t tmp;
291
292 tmp = readl(NFC_V3_CONFIG2);
293
294 if (activate)
295 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
296 else
297 tmp |= NFC_V3_CONFIG2_INT_MSK;
298
299 writel(tmp, NFC_V3_CONFIG2);
300 }
301
302 /* This function polls the NANDFC to wait for the basic operation to
303 * complete by checking the INT bit of config2 register.
304 */
305 static void wait_op_done(struct mxc_nand_host *host, int useirq)
306 {
307 int max_retries = 8000;
308
309 if (useirq) {
310 if (!host->check_int(host)) {
311 INIT_COMPLETION(host->op_completion);
312 host->irq_control(host, 1);
313 wait_for_completion(&host->op_completion);
314 }
315 } else {
316 while (max_retries-- > 0) {
317 if (host->check_int(host))
318 break;
319
320 udelay(1);
321 }
322 if (max_retries < 0)
323 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
324 __func__);
325 }
326 }
327
328 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
329 {
330 /* fill command */
331 writel(cmd, NFC_V3_FLASH_CMD);
332
333 /* send out command */
334 writel(NFC_CMD, NFC_V3_LAUNCH);
335
336 /* Wait for operation to complete */
337 wait_op_done(host, useirq);
338 }
339
340 /* This function issues the specified command to the NAND device and
341 * waits for completion. */
342 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
343 {
344 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
345
346 writew(cmd, NFC_V1_V2_FLASH_CMD);
347 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
348
349 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
350 int max_retries = 100;
351 /* Reset completion is indicated by NFC_CONFIG2 */
352 /* being set to 0 */
353 while (max_retries-- > 0) {
354 if (readw(NFC_V1_V2_CONFIG2) == 0) {
355 break;
356 }
357 udelay(1);
358 }
359 if (max_retries < 0)
360 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
361 __func__);
362 } else {
363 /* Wait for operation to complete */
364 wait_op_done(host, useirq);
365 }
366 }
367
368 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
369 {
370 /* fill address */
371 writel(addr, NFC_V3_FLASH_ADDR0);
372
373 /* send out address */
374 writel(NFC_ADDR, NFC_V3_LAUNCH);
375
376 wait_op_done(host, 0);
377 }
378
379 /* This function sends an address (or partial address) to the
380 * NAND device. The address is used to select the source/destination for
381 * a NAND command. */
382 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
383 {
384 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
385
386 writew(addr, NFC_V1_V2_FLASH_ADDR);
387 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
388
389 /* Wait for operation to complete */
390 wait_op_done(host, islast);
391 }
392
393 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
394 {
395 struct nand_chip *nand_chip = mtd->priv;
396 struct mxc_nand_host *host = nand_chip->priv;
397 uint32_t tmp;
398
399 tmp = readl(NFC_V3_CONFIG1);
400 tmp &= ~(7 << 4);
401 writel(tmp, NFC_V3_CONFIG1);
402
403 /* transfer data from NFC ram to nand */
404 writel(ops, NFC_V3_LAUNCH);
405
406 wait_op_done(host, false);
407 }
408
409 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
410 {
411 struct nand_chip *nand_chip = mtd->priv;
412 struct mxc_nand_host *host = nand_chip->priv;
413 int bufs, i;
414
415 if (nfc_is_v1() && mtd->writesize > 512)
416 bufs = 4;
417 else
418 bufs = 1;
419
420 for (i = 0; i < bufs; i++) {
421
422 /* NANDFC buffer 0 is used for page read/write */
423 writew(i, NFC_V1_V2_BUF_ADDR);
424
425 writew(ops, NFC_V1_V2_CONFIG2);
426
427 /* Wait for operation to complete */
428 wait_op_done(host, true);
429 }
430 }
431
432 static void send_read_id_v3(struct mxc_nand_host *host)
433 {
434 /* Read ID into main buffer */
435 writel(NFC_ID, NFC_V3_LAUNCH);
436
437 wait_op_done(host, true);
438
439 memcpy(host->data_buf, host->main_area0, 16);
440 }
441
442 /* Request the NANDFC to perform a read of the NAND device ID. */
443 static void send_read_id_v1_v2(struct mxc_nand_host *host)
444 {
445 struct nand_chip *this = &host->nand;
446
447 /* NANDFC buffer 0 is used for device ID output */
448 writew(0x0, NFC_V1_V2_BUF_ADDR);
449
450 writew(NFC_ID, NFC_V1_V2_CONFIG2);
451
452 /* Wait for operation to complete */
453 wait_op_done(host, true);
454
455 memcpy(host->data_buf, host->main_area0, 16);
456
457 if (this->options & NAND_BUSWIDTH_16) {
458 /* compress the ID info */
459 host->data_buf[1] = host->data_buf[2];
460 host->data_buf[2] = host->data_buf[4];
461 host->data_buf[3] = host->data_buf[6];
462 host->data_buf[4] = host->data_buf[8];
463 host->data_buf[5] = host->data_buf[10];
464 }
465 }
466
467 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
468 {
469 writew(NFC_STATUS, NFC_V3_LAUNCH);
470 wait_op_done(host, true);
471
472 return readl(NFC_V3_CONFIG1) >> 16;
473 }
474
475 /* This function requests the NANDFC to perform a read of the
476 * NAND device status and returns the current status. */
477 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
478 {
479 void __iomem *main_buf = host->main_area0;
480 uint32_t store;
481 uint16_t ret;
482
483 writew(0x0, NFC_V1_V2_BUF_ADDR);
484
485 /*
486 * The device status is stored in main_area0. To
487 * prevent corruption of the buffer save the value
488 * and restore it afterwards.
489 */
490 store = readl(main_buf);
491
492 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
493 wait_op_done(host, true);
494
495 ret = readw(main_buf);
496
497 writel(store, main_buf);
498
499 return ret;
500 }
501
502 /* This functions is used by upper layer to checks if device is ready */
503 static int mxc_nand_dev_ready(struct mtd_info *mtd)
504 {
505 /*
506 * NFC handles R/B internally. Therefore, this function
507 * always returns status as ready.
508 */
509 return 1;
510 }
511
512 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
513 {
514 /*
515 * If HW ECC is enabled, we turn it on during init. There is
516 * no need to enable again here.
517 */
518 }
519
520 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
521 u_char *read_ecc, u_char *calc_ecc)
522 {
523 struct nand_chip *nand_chip = mtd->priv;
524 struct mxc_nand_host *host = nand_chip->priv;
525
526 /*
527 * 1-Bit errors are automatically corrected in HW. No need for
528 * additional correction. 2-Bit errors cannot be corrected by
529 * HW ECC, so we need to return failure
530 */
531 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
532
533 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
534 DEBUG(MTD_DEBUG_LEVEL0,
535 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
536 return -1;
537 }
538
539 return 0;
540 }
541
542 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
543 u_char *read_ecc, u_char *calc_ecc)
544 {
545 struct nand_chip *nand_chip = mtd->priv;
546 struct mxc_nand_host *host = nand_chip->priv;
547 u32 ecc_stat, err;
548 int no_subpages = 1;
549 int ret = 0;
550 u8 ecc_bit_mask, err_limit;
551
552 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
553 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
554
555 no_subpages = mtd->writesize >> 9;
556
557 if (nfc_is_v21())
558 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
559 else
560 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
561
562 do {
563 err = ecc_stat & ecc_bit_mask;
564 if (err > err_limit) {
565 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
566 return -1;
567 } else {
568 ret += err;
569 }
570 ecc_stat >>= 4;
571 } while (--no_subpages);
572
573 mtd->ecc_stats.corrected += ret;
574 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
575
576 return ret;
577 }
578
579 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
580 u_char *ecc_code)
581 {
582 return 0;
583 }
584
585 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
586 {
587 struct nand_chip *nand_chip = mtd->priv;
588 struct mxc_nand_host *host = nand_chip->priv;
589 uint8_t ret;
590
591 /* Check for status request */
592 if (host->status_request)
593 return host->get_dev_status(host) & 0xFF;
594
595 ret = *(uint8_t *)(host->data_buf + host->buf_start);
596 host->buf_start++;
597
598 return ret;
599 }
600
601 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
602 {
603 struct nand_chip *nand_chip = mtd->priv;
604 struct mxc_nand_host *host = nand_chip->priv;
605 uint16_t ret;
606
607 ret = *(uint16_t *)(host->data_buf + host->buf_start);
608 host->buf_start += 2;
609
610 return ret;
611 }
612
613 /* Write data of length len to buffer buf. The data to be
614 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
615 * Operation by the NFC, the data is written to NAND Flash */
616 static void mxc_nand_write_buf(struct mtd_info *mtd,
617 const u_char *buf, int len)
618 {
619 struct nand_chip *nand_chip = mtd->priv;
620 struct mxc_nand_host *host = nand_chip->priv;
621 u16 col = host->buf_start;
622 int n = mtd->oobsize + mtd->writesize - col;
623
624 n = min(n, len);
625
626 memcpy(host->data_buf + col, buf, n);
627
628 host->buf_start += n;
629 }
630
631 /* Read the data buffer from the NAND Flash. To read the data from NAND
632 * Flash first the data output cycle is initiated by the NFC, which copies
633 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
634 */
635 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
636 {
637 struct nand_chip *nand_chip = mtd->priv;
638 struct mxc_nand_host *host = nand_chip->priv;
639 u16 col = host->buf_start;
640 int n = mtd->oobsize + mtd->writesize - col;
641
642 n = min(n, len);
643
644 memcpy(buf, host->data_buf + col, len);
645
646 host->buf_start += len;
647 }
648
649 /* Used by the upper layer to verify the data in NAND Flash
650 * with the data in the buf. */
651 static int mxc_nand_verify_buf(struct mtd_info *mtd,
652 const u_char *buf, int len)
653 {
654 return -EFAULT;
655 }
656
657 /* This function is used by upper layer for select and
658 * deselect of the NAND chip */
659 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
660 {
661 struct nand_chip *nand_chip = mtd->priv;
662 struct mxc_nand_host *host = nand_chip->priv;
663
664 switch (chip) {
665 case -1:
666 /* Disable the NFC clock */
667 if (host->clk_act) {
668 clk_disable(host->clk);
669 host->clk_act = 0;
670 }
671 break;
672 case 0:
673 /* Enable the NFC clock */
674 if (!host->clk_act) {
675 clk_enable(host->clk);
676 host->clk_act = 1;
677 }
678 break;
679
680 default:
681 break;
682 }
683 }
684
685 /*
686 * Function to transfer data to/from spare area.
687 */
688 static void copy_spare(struct mtd_info *mtd, bool bfrom)
689 {
690 struct nand_chip *this = mtd->priv;
691 struct mxc_nand_host *host = this->priv;
692 u16 i, j;
693 u16 n = mtd->writesize >> 9;
694 u8 *d = host->data_buf + mtd->writesize;
695 u8 *s = host->spare0;
696 u16 t = host->spare_len;
697
698 j = (mtd->oobsize / n >> 1) << 1;
699
700 if (bfrom) {
701 for (i = 0; i < n - 1; i++)
702 memcpy(d + i * j, s + i * t, j);
703
704 /* the last section */
705 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
706 } else {
707 for (i = 0; i < n - 1; i++)
708 memcpy(&s[i * t], &d[i * j], j);
709
710 /* the last section */
711 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
712 }
713 }
714
715 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
716 {
717 struct nand_chip *nand_chip = mtd->priv;
718 struct mxc_nand_host *host = nand_chip->priv;
719
720 /* Write out column address, if necessary */
721 if (column != -1) {
722 /*
723 * MXC NANDFC can only perform full page+spare or
724 * spare-only read/write. When the upper layers
725 * layers perform a read/write buf operation,
726 * we will used the saved column address to index into
727 * the full page.
728 */
729 host->send_addr(host, 0, page_addr == -1);
730 if (mtd->writesize > 512)
731 /* another col addr cycle for 2k page */
732 host->send_addr(host, 0, false);
733 }
734
735 /* Write out page address, if necessary */
736 if (page_addr != -1) {
737 /* paddr_0 - p_addr_7 */
738 host->send_addr(host, (page_addr & 0xff), false);
739
740 if (mtd->writesize > 512) {
741 if (mtd->size >= 0x10000000) {
742 /* paddr_8 - paddr_15 */
743 host->send_addr(host, (page_addr >> 8) & 0xff, false);
744 host->send_addr(host, (page_addr >> 16) & 0xff, true);
745 } else
746 /* paddr_8 - paddr_15 */
747 host->send_addr(host, (page_addr >> 8) & 0xff, true);
748 } else {
749 /* One more address cycle for higher density devices */
750 if (mtd->size >= 0x4000000) {
751 /* paddr_8 - paddr_15 */
752 host->send_addr(host, (page_addr >> 8) & 0xff, false);
753 host->send_addr(host, (page_addr >> 16) & 0xff, true);
754 } else
755 /* paddr_8 - paddr_15 */
756 host->send_addr(host, (page_addr >> 8) & 0xff, true);
757 }
758 }
759 }
760
761 /*
762 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
763 * on how much oob the nand chip has. For 8bit ecc we need at least
764 * 26 bytes of oob data per 512 byte block.
765 */
766 static int get_eccsize(struct mtd_info *mtd)
767 {
768 int oobbytes_per_512 = 0;
769
770 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
771
772 if (oobbytes_per_512 < 26)
773 return 4;
774 else
775 return 8;
776 }
777
778 static void preset_v1_v2(struct mtd_info *mtd)
779 {
780 struct nand_chip *nand_chip = mtd->priv;
781 struct mxc_nand_host *host = nand_chip->priv;
782 uint16_t config1 = 0;
783
784 if (nand_chip->ecc.mode == NAND_ECC_HW)
785 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
786
787 if (nfc_is_v21())
788 config1 |= NFC_V2_CONFIG1_FP_INT;
789
790 if (!cpu_is_mx21())
791 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
792
793 if (nfc_is_v21() && mtd->writesize) {
794 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
795
796 host->eccsize = get_eccsize(mtd);
797 if (host->eccsize == 4)
798 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
799
800 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
801 } else {
802 host->eccsize = 1;
803 }
804
805 writew(config1, NFC_V1_V2_CONFIG1);
806 /* preset operation */
807
808 /* Unlock the internal RAM Buffer */
809 writew(0x2, NFC_V1_V2_CONFIG);
810
811 /* Blocks to be unlocked */
812 if (nfc_is_v21()) {
813 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR);
814 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR);
815 } else if (nfc_is_v1()) {
816 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
817 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
818 } else
819 BUG();
820
821 /* Unlock Block Command for given address range */
822 writew(0x4, NFC_V1_V2_WRPROT);
823 }
824
825 static void preset_v3(struct mtd_info *mtd)
826 {
827 struct nand_chip *chip = mtd->priv;
828 struct mxc_nand_host *host = chip->priv;
829 uint32_t config2, config3;
830 int i, addr_phases;
831
832 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
833 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
834
835 /* Unlock the internal RAM Buffer */
836 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
837 NFC_V3_WRPROT);
838
839 /* Blocks to be unlocked */
840 for (i = 0; i < NAND_MAX_CHIPS; i++)
841 writel(0x0 | (0xffff << 16),
842 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
843
844 writel(0, NFC_V3_IPC);
845
846 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
847 NFC_V3_CONFIG2_2CMD_PHASES |
848 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
849 NFC_V3_CONFIG2_ST_CMD(0x70) |
850 NFC_V3_CONFIG2_INT_MSK |
851 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
852
853 if (chip->ecc.mode == NAND_ECC_HW)
854 config2 |= NFC_V3_CONFIG2_ECC_EN;
855
856 addr_phases = fls(chip->pagemask) >> 3;
857
858 if (mtd->writesize == 2048) {
859 config2 |= NFC_V3_CONFIG2_PS_2048;
860 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
861 } else if (mtd->writesize == 4096) {
862 config2 |= NFC_V3_CONFIG2_PS_4096;
863 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
864 } else {
865 config2 |= NFC_V3_CONFIG2_PS_512;
866 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
867 }
868
869 if (mtd->writesize) {
870 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
871 host->eccsize = get_eccsize(mtd);
872 if (host->eccsize == 8)
873 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
874 }
875
876 writel(config2, NFC_V3_CONFIG2);
877
878 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
879 NFC_V3_CONFIG3_NO_SDMA |
880 NFC_V3_CONFIG3_RBB_MODE |
881 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
882 NFC_V3_CONFIG3_ADD_OP(0);
883
884 if (!(chip->options & NAND_BUSWIDTH_16))
885 config3 |= NFC_V3_CONFIG3_FW8;
886
887 writel(config3, NFC_V3_CONFIG3);
888
889 writel(0, NFC_V3_DELAY_LINE);
890 }
891
892 /* Used by the upper layer to write command to NAND Flash for
893 * different operations to be carried out on NAND Flash */
894 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
895 int column, int page_addr)
896 {
897 struct nand_chip *nand_chip = mtd->priv;
898 struct mxc_nand_host *host = nand_chip->priv;
899
900 DEBUG(MTD_DEBUG_LEVEL3,
901 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
902 command, column, page_addr);
903
904 /* Reset command state information */
905 host->status_request = false;
906
907 /* Command pre-processing step */
908 switch (command) {
909 case NAND_CMD_RESET:
910 host->preset(mtd);
911 host->send_cmd(host, command, false);
912 break;
913
914 case NAND_CMD_STATUS:
915 host->buf_start = 0;
916 host->status_request = true;
917
918 host->send_cmd(host, command, true);
919 mxc_do_addr_cycle(mtd, column, page_addr);
920 break;
921
922 case NAND_CMD_READ0:
923 case NAND_CMD_READOOB:
924 if (command == NAND_CMD_READ0)
925 host->buf_start = column;
926 else
927 host->buf_start = column + mtd->writesize;
928
929 command = NAND_CMD_READ0; /* only READ0 is valid */
930
931 host->send_cmd(host, command, false);
932 mxc_do_addr_cycle(mtd, column, page_addr);
933
934 if (mtd->writesize > 512)
935 host->send_cmd(host, NAND_CMD_READSTART, true);
936
937 host->send_page(mtd, NFC_OUTPUT);
938
939 memcpy(host->data_buf, host->main_area0, mtd->writesize);
940 copy_spare(mtd, true);
941 break;
942
943 case NAND_CMD_SEQIN:
944 if (column >= mtd->writesize)
945 /* call ourself to read a page */
946 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
947
948 host->buf_start = column;
949
950 host->send_cmd(host, command, false);
951 mxc_do_addr_cycle(mtd, column, page_addr);
952 break;
953
954 case NAND_CMD_PAGEPROG:
955 memcpy(host->main_area0, host->data_buf, mtd->writesize);
956 copy_spare(mtd, false);
957 host->send_page(mtd, NFC_INPUT);
958 host->send_cmd(host, command, true);
959 mxc_do_addr_cycle(mtd, column, page_addr);
960 break;
961
962 case NAND_CMD_READID:
963 host->send_cmd(host, command, true);
964 mxc_do_addr_cycle(mtd, column, page_addr);
965 host->send_read_id(host);
966 host->buf_start = column;
967 break;
968
969 case NAND_CMD_ERASE1:
970 case NAND_CMD_ERASE2:
971 host->send_cmd(host, command, false);
972 mxc_do_addr_cycle(mtd, column, page_addr);
973
974 break;
975 }
976 }
977
978 /*
979 * The generic flash bbt decriptors overlap with our ecc
980 * hardware, so define some i.MX specific ones.
981 */
982 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
983 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
984
985 static struct nand_bbt_descr bbt_main_descr = {
986 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
987 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
988 .offs = 0,
989 .len = 4,
990 .veroffs = 4,
991 .maxblocks = 4,
992 .pattern = bbt_pattern,
993 };
994
995 static struct nand_bbt_descr bbt_mirror_descr = {
996 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
997 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
998 .offs = 0,
999 .len = 4,
1000 .veroffs = 4,
1001 .maxblocks = 4,
1002 .pattern = mirror_pattern,
1003 };
1004
1005 static int __init mxcnd_probe(struct platform_device *pdev)
1006 {
1007 struct nand_chip *this;
1008 struct mtd_info *mtd;
1009 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1010 struct mxc_nand_host *host;
1011 struct resource *res;
1012 int err = 0, nr_parts = 0;
1013 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1014
1015 /* Allocate memory for MTD device structure and private data */
1016 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1017 NAND_MAX_OOBSIZE, GFP_KERNEL);
1018 if (!host)
1019 return -ENOMEM;
1020
1021 host->data_buf = (uint8_t *)(host + 1);
1022
1023 host->dev = &pdev->dev;
1024 /* structures must be linked */
1025 this = &host->nand;
1026 mtd = &host->mtd;
1027 mtd->priv = this;
1028 mtd->owner = THIS_MODULE;
1029 mtd->dev.parent = &pdev->dev;
1030 mtd->name = DRIVER_NAME;
1031
1032 /* 50 us command delay time */
1033 this->chip_delay = 5;
1034
1035 this->priv = host;
1036 this->dev_ready = mxc_nand_dev_ready;
1037 this->cmdfunc = mxc_nand_command;
1038 this->select_chip = mxc_nand_select_chip;
1039 this->read_byte = mxc_nand_read_byte;
1040 this->read_word = mxc_nand_read_word;
1041 this->write_buf = mxc_nand_write_buf;
1042 this->read_buf = mxc_nand_read_buf;
1043 this->verify_buf = mxc_nand_verify_buf;
1044
1045 host->clk = clk_get(&pdev->dev, "nfc");
1046 if (IS_ERR(host->clk)) {
1047 err = PTR_ERR(host->clk);
1048 goto eclk;
1049 }
1050
1051 clk_enable(host->clk);
1052 host->clk_act = 1;
1053
1054 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1055 if (!res) {
1056 err = -ENODEV;
1057 goto eres;
1058 }
1059
1060 host->base = ioremap(res->start, resource_size(res));
1061 if (!host->base) {
1062 err = -ENOMEM;
1063 goto eres;
1064 }
1065
1066 host->main_area0 = host->base;
1067
1068 if (nfc_is_v1() || nfc_is_v21()) {
1069 host->preset = preset_v1_v2;
1070 host->send_cmd = send_cmd_v1_v2;
1071 host->send_addr = send_addr_v1_v2;
1072 host->send_page = send_page_v1_v2;
1073 host->send_read_id = send_read_id_v1_v2;
1074 host->get_dev_status = get_dev_status_v1_v2;
1075 host->check_int = check_int_v1_v2;
1076 if (cpu_is_mx21())
1077 host->irq_control = irq_control_mx21;
1078 else
1079 host->irq_control = irq_control_v1_v2;
1080 }
1081
1082 if (nfc_is_v21()) {
1083 host->regs = host->base + 0x1e00;
1084 host->spare0 = host->base + 0x1000;
1085 host->spare_len = 64;
1086 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1087 oob_largepage = &nandv2_hw_eccoob_largepage;
1088 this->ecc.bytes = 9;
1089 } else if (nfc_is_v1()) {
1090 host->regs = host->base + 0xe00;
1091 host->spare0 = host->base + 0x800;
1092 host->spare_len = 16;
1093 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1094 oob_largepage = &nandv1_hw_eccoob_largepage;
1095 this->ecc.bytes = 3;
1096 host->eccsize = 1;
1097 } else if (nfc_is_v3_2()) {
1098 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1099 if (!res) {
1100 err = -ENODEV;
1101 goto eirq;
1102 }
1103 host->regs_ip = ioremap(res->start, resource_size(res));
1104 if (!host->regs_ip) {
1105 err = -ENOMEM;
1106 goto eirq;
1107 }
1108 host->regs_axi = host->base + 0x1e00;
1109 host->spare0 = host->base + 0x1000;
1110 host->spare_len = 64;
1111 host->preset = preset_v3;
1112 host->send_cmd = send_cmd_v3;
1113 host->send_addr = send_addr_v3;
1114 host->send_page = send_page_v3;
1115 host->send_read_id = send_read_id_v3;
1116 host->check_int = check_int_v3;
1117 host->get_dev_status = get_dev_status_v3;
1118 host->irq_control = irq_control_v3;
1119 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1120 oob_largepage = &nandv2_hw_eccoob_largepage;
1121 } else
1122 BUG();
1123
1124 this->ecc.size = 512;
1125 this->ecc.layout = oob_smallpage;
1126
1127 if (pdata->hw_ecc) {
1128 this->ecc.calculate = mxc_nand_calculate_ecc;
1129 this->ecc.hwctl = mxc_nand_enable_hwecc;
1130 if (nfc_is_v1())
1131 this->ecc.correct = mxc_nand_correct_data_v1;
1132 else
1133 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1134 this->ecc.mode = NAND_ECC_HW;
1135 } else {
1136 this->ecc.mode = NAND_ECC_SOFT;
1137 }
1138
1139 /* NAND bus width determines access funtions used by upper layer */
1140 if (pdata->width == 2)
1141 this->options |= NAND_BUSWIDTH_16;
1142
1143 if (pdata->flash_bbt) {
1144 this->bbt_td = &bbt_main_descr;
1145 this->bbt_md = &bbt_mirror_descr;
1146 /* update flash based bbt */
1147 this->options |= NAND_USE_FLASH_BBT;
1148 }
1149
1150 init_completion(&host->op_completion);
1151
1152 host->irq = platform_get_irq(pdev, 0);
1153
1154 /*
1155 * mask the interrupt. For i.MX21 explicitely call
1156 * irq_control_v1_v2 to use the mask bit. We can't call
1157 * disable_irq_nosync() for an interrupt we do not own yet.
1158 */
1159 if (cpu_is_mx21())
1160 irq_control_v1_v2(host, 0);
1161 else
1162 host->irq_control(host, 0);
1163
1164 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1165 if (err)
1166 goto eirq;
1167
1168 host->irq_control(host, 0);
1169
1170 /*
1171 * Now that the interrupt is disabled make sure the interrupt
1172 * mask bit is cleared on i.MX21. Otherwise we can't read
1173 * the interrupt status bit on this machine.
1174 */
1175 if (cpu_is_mx21())
1176 irq_control_v1_v2(host, 1);
1177
1178 /* first scan to find the device and get the page size */
1179 if (nand_scan_ident(mtd, 1, NULL)) {
1180 err = -ENXIO;
1181 goto escan;
1182 }
1183
1184 /* Call preset again, with correct writesize this time */
1185 host->preset(mtd);
1186
1187 if (mtd->writesize == 2048)
1188 this->ecc.layout = oob_largepage;
1189
1190 /* second phase scan */
1191 if (nand_scan_tail(mtd)) {
1192 err = -ENXIO;
1193 goto escan;
1194 }
1195
1196 /* Register the partitions */
1197 #ifdef CONFIG_MTD_PARTITIONS
1198 nr_parts =
1199 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1200 if (nr_parts > 0)
1201 add_mtd_partitions(mtd, host->parts, nr_parts);
1202 else if (pdata->parts)
1203 add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
1204 else
1205 #endif
1206 {
1207 pr_info("Registering %s as whole device\n", mtd->name);
1208 add_mtd_device(mtd);
1209 }
1210
1211 platform_set_drvdata(pdev, host);
1212
1213 return 0;
1214
1215 escan:
1216 free_irq(host->irq, host);
1217 eirq:
1218 if (host->regs_ip)
1219 iounmap(host->regs_ip);
1220 iounmap(host->base);
1221 eres:
1222 clk_put(host->clk);
1223 eclk:
1224 kfree(host);
1225
1226 return err;
1227 }
1228
1229 static int __devexit mxcnd_remove(struct platform_device *pdev)
1230 {
1231 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1232
1233 clk_put(host->clk);
1234
1235 platform_set_drvdata(pdev, NULL);
1236
1237 nand_release(&host->mtd);
1238 free_irq(host->irq, host);
1239 if (host->regs_ip)
1240 iounmap(host->regs_ip);
1241 iounmap(host->base);
1242 kfree(host);
1243
1244 return 0;
1245 }
1246
1247 static struct platform_driver mxcnd_driver = {
1248 .driver = {
1249 .name = DRIVER_NAME,
1250 },
1251 .remove = __devexit_p(mxcnd_remove),
1252 };
1253
1254 static int __init mxc_nd_init(void)
1255 {
1256 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1257 }
1258
1259 static void __exit mxc_nd_cleanup(void)
1260 {
1261 /* Unregister the device structure */
1262 platform_driver_unregister(&mxcnd_driver);
1263 }
1264
1265 module_init(mxc_nd_init);
1266 module_exit(mxc_nd_cleanup);
1267
1268 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1269 MODULE_DESCRIPTION("MXC NAND MTD driver");
1270 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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