2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
37 #define DRIVER_NAME "mxc_nand"
39 /* Addresses for NFC registers */
40 #define NFC_BUF_SIZE 0xE00
41 #define NFC_BUF_ADDR 0xE04
42 #define NFC_FLASH_ADDR 0xE06
43 #define NFC_FLASH_CMD 0xE08
44 #define NFC_CONFIG 0xE0A
45 #define NFC_ECC_STATUS_RESULT 0xE0C
46 #define NFC_RSLTMAIN_AREA 0xE0E
47 #define NFC_RSLTSPARE_AREA 0xE10
48 #define NFC_WRPROT 0xE12
49 #define NFC_UNLOCKSTART_BLKADDR 0xE14
50 #define NFC_UNLOCKEND_BLKADDR 0xE16
51 #define NFC_NF_WRPRST 0xE18
52 #define NFC_CONFIG1 0xE1A
53 #define NFC_CONFIG2 0xE1C
55 /* Addresses for NFC RAM BUFFER Main area 0 */
56 #define MAIN_AREA0 0x000
57 #define MAIN_AREA1 0x200
58 #define MAIN_AREA2 0x400
59 #define MAIN_AREA3 0x600
61 /* Addresses for NFC SPARE BUFFER Spare area 0 */
62 #define SPARE_AREA0 0x800
63 #define SPARE_AREA1 0x810
64 #define SPARE_AREA2 0x820
65 #define SPARE_AREA3 0x830
67 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
68 * for Command operation */
71 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
72 * for Address operation */
75 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
76 * for Input operation */
79 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
80 * for Data Output operation */
81 #define NFC_OUTPUT 0x8
83 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
84 * for Read ID operation */
87 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
88 * for Read Status operation */
89 #define NFC_STATUS 0x20
91 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
93 #define NFC_INT 0x8000
95 #define NFC_SP_EN (1 << 2)
96 #define NFC_ECC_EN (1 << 3)
97 #define NFC_INT_MSK (1 << 4)
98 #define NFC_BIG (1 << 5)
99 #define NFC_RST (1 << 6)
100 #define NFC_CE (1 << 7)
101 #define NFC_ONE_CYCLE (1 << 8)
103 struct mxc_nand_host
{
105 struct nand_chip nand
;
106 struct mtd_partition
*parts
;
118 wait_queue_head_t irq_waitq
;
121 /* Define delays in microsec for NAND device operations */
122 #define TROP_US_DELAY 2000
123 /* Macros to get byte and bit positions of ECC */
124 #define COLPOS(x) ((x) >> 3)
125 #define BITPOS(x) ((x) & 0xf)
127 /* Define single bit Error positions in Main & Spare area */
128 #define MAIN_SINGLEBIT_ERROR 0x4
129 #define SPARE_SINGLEBIT_ERROR 0x1
131 /* OOB placement block for use with hardware ecc generation */
132 static struct nand_ecclayout nand_hw_eccoob_smallpage
= {
134 .eccpos
= {6, 7, 8, 9, 10},
135 .oobfree
= {{0, 5}, {12, 4}, }
138 static struct nand_ecclayout nand_hw_eccoob_largepage
= {
140 .eccpos
= {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
141 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
142 .oobfree
= {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
145 #ifdef CONFIG_MTD_PARTITIONS
146 static const char *part_probes
[] = { "RedBoot", "cmdlinepart", NULL
};
149 static irqreturn_t
mxc_nfc_irq(int irq
, void *dev_id
)
151 struct mxc_nand_host
*host
= dev_id
;
155 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
156 tmp
|= NFC_INT_MSK
; /* Disable interrupt */
157 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
159 wake_up(&host
->irq_waitq
);
164 /* This function polls the NANDFC to wait for the basic operation to
165 * complete by checking the INT bit of config2 register.
167 static void wait_op_done(struct mxc_nand_host
*host
, int max_retries
,
168 uint16_t param
, int useirq
)
173 if ((readw(host
->regs
+ NFC_CONFIG2
) & NFC_INT
) == 0) {
175 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
176 tmp
&= ~NFC_INT_MSK
; /* Enable interrupt */
177 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
179 wait_event(host
->irq_waitq
,
180 readw(host
->regs
+ NFC_CONFIG2
) & NFC_INT
);
182 tmp
= readw(host
->regs
+ NFC_CONFIG2
);
184 writew(tmp
, host
->regs
+ NFC_CONFIG2
);
187 while (max_retries
-- > 0) {
188 if (readw(host
->regs
+ NFC_CONFIG2
) & NFC_INT
) {
189 tmp
= readw(host
->regs
+ NFC_CONFIG2
);
191 writew(tmp
, host
->regs
+ NFC_CONFIG2
);
197 DEBUG(MTD_DEBUG_LEVEL0
, "%s(%d): INT not set\n",
202 /* This function issues the specified command to the NAND device and
203 * waits for completion. */
204 static void send_cmd(struct mxc_nand_host
*host
, uint16_t cmd
, int useirq
)
206 DEBUG(MTD_DEBUG_LEVEL3
, "send_cmd(host, 0x%x, %d)\n", cmd
, useirq
);
208 writew(cmd
, host
->regs
+ NFC_FLASH_CMD
);
209 writew(NFC_CMD
, host
->regs
+ NFC_CONFIG2
);
211 /* Wait for operation to complete */
212 wait_op_done(host
, TROP_US_DELAY
, cmd
, useirq
);
215 /* This function sends an address (or partial address) to the
216 * NAND device. The address is used to select the source/destination for
218 static void send_addr(struct mxc_nand_host
*host
, uint16_t addr
, int islast
)
220 DEBUG(MTD_DEBUG_LEVEL3
, "send_addr(host, 0x%x %d)\n", addr
, islast
);
222 writew(addr
, host
->regs
+ NFC_FLASH_ADDR
);
223 writew(NFC_ADDR
, host
->regs
+ NFC_CONFIG2
);
225 /* Wait for operation to complete */
226 wait_op_done(host
, TROP_US_DELAY
, addr
, islast
);
229 /* This function requests the NANDFC to initate the transfer
230 * of data currently in the NANDFC RAM buffer to the NAND device. */
231 static void send_prog_page(struct mxc_nand_host
*host
, uint8_t buf_id
,
234 DEBUG(MTD_DEBUG_LEVEL3
, "send_prog_page (%d)\n", spare_only
);
236 /* NANDFC buffer 0 is used for page read/write */
237 writew(buf_id
, host
->regs
+ NFC_BUF_ADDR
);
239 /* Configure spare or page+spare access */
240 if (!host
->pagesize_2k
) {
241 uint16_t config1
= readw(host
->regs
+ NFC_CONFIG1
);
243 config1
|= NFC_SP_EN
;
245 config1
&= ~(NFC_SP_EN
);
246 writew(config1
, host
->regs
+ NFC_CONFIG1
);
249 writew(NFC_INPUT
, host
->regs
+ NFC_CONFIG2
);
251 /* Wait for operation to complete */
252 wait_op_done(host
, TROP_US_DELAY
, spare_only
, true);
255 /* Requests NANDFC to initated the transfer of data from the
256 * NAND device into in the NANDFC ram buffer. */
257 static void send_read_page(struct mxc_nand_host
*host
, uint8_t buf_id
,
260 DEBUG(MTD_DEBUG_LEVEL3
, "send_read_page (%d)\n", spare_only
);
262 /* NANDFC buffer 0 is used for page read/write */
263 writew(buf_id
, host
->regs
+ NFC_BUF_ADDR
);
265 /* Configure spare or page+spare access */
266 if (!host
->pagesize_2k
) {
267 uint32_t config1
= readw(host
->regs
+ NFC_CONFIG1
);
269 config1
|= NFC_SP_EN
;
271 config1
&= ~NFC_SP_EN
;
272 writew(config1
, host
->regs
+ NFC_CONFIG1
);
275 writew(NFC_OUTPUT
, host
->regs
+ NFC_CONFIG2
);
277 /* Wait for operation to complete */
278 wait_op_done(host
, TROP_US_DELAY
, spare_only
, true);
281 /* Request the NANDFC to perform a read of the NAND device ID. */
282 static void send_read_id(struct mxc_nand_host
*host
)
284 struct nand_chip
*this = &host
->nand
;
287 /* NANDFC buffer 0 is used for device ID output */
288 writew(0x0, host
->regs
+ NFC_BUF_ADDR
);
290 /* Read ID into main buffer */
291 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
293 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
295 writew(NFC_ID
, host
->regs
+ NFC_CONFIG2
);
297 /* Wait for operation to complete */
298 wait_op_done(host
, TROP_US_DELAY
, 0, true);
300 if (this->options
& NAND_BUSWIDTH_16
) {
301 void __iomem
*main_buf
= host
->regs
+ MAIN_AREA0
;
302 /* compress the ID info */
303 writeb(readb(main_buf
+ 2), main_buf
+ 1);
304 writeb(readb(main_buf
+ 4), main_buf
+ 2);
305 writeb(readb(main_buf
+ 6), main_buf
+ 3);
306 writeb(readb(main_buf
+ 8), main_buf
+ 4);
307 writeb(readb(main_buf
+ 10), main_buf
+ 5);
311 /* This function requests the NANDFC to perform a read of the
312 * NAND device status and returns the current status. */
313 static uint16_t get_dev_status(struct mxc_nand_host
*host
)
315 void __iomem
*main_buf
= host
->regs
+ MAIN_AREA1
;
318 /* Issue status request to NAND device */
320 /* store the main area1 first word, later do recovery */
321 store
= readl(main_buf
);
322 /* NANDFC buffer 1 is used for device status to prevent
323 * corruption of read/write buffer on status requests. */
324 writew(1, host
->regs
+ NFC_BUF_ADDR
);
326 /* Read status into main buffer */
327 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
329 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
331 writew(NFC_STATUS
, host
->regs
+ NFC_CONFIG2
);
333 /* Wait for operation to complete */
334 wait_op_done(host
, TROP_US_DELAY
, 0, true);
336 /* Status is placed in first word of main buffer */
337 /* get status, then recovery area 1 data */
338 ret
= readw(main_buf
);
339 writel(store
, main_buf
);
344 /* This functions is used by upper layer to checks if device is ready */
345 static int mxc_nand_dev_ready(struct mtd_info
*mtd
)
348 * NFC handles R/B internally. Therefore, this function
349 * always returns status as ready.
354 static void mxc_nand_enable_hwecc(struct mtd_info
*mtd
, int mode
)
357 * If HW ECC is enabled, we turn it on during init. There is
358 * no need to enable again here.
362 static int mxc_nand_correct_data(struct mtd_info
*mtd
, u_char
*dat
,
363 u_char
*read_ecc
, u_char
*calc_ecc
)
365 struct nand_chip
*nand_chip
= mtd
->priv
;
366 struct mxc_nand_host
*host
= nand_chip
->priv
;
369 * 1-Bit errors are automatically corrected in HW. No need for
370 * additional correction. 2-Bit errors cannot be corrected by
371 * HW ECC, so we need to return failure
373 uint16_t ecc_status
= readw(host
->regs
+ NFC_ECC_STATUS_RESULT
);
375 if (((ecc_status
& 0x3) == 2) || ((ecc_status
>> 2) == 2)) {
376 DEBUG(MTD_DEBUG_LEVEL0
,
377 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
384 static int mxc_nand_calculate_ecc(struct mtd_info
*mtd
, const u_char
*dat
,
390 static u_char
mxc_nand_read_byte(struct mtd_info
*mtd
)
392 struct nand_chip
*nand_chip
= mtd
->priv
;
393 struct mxc_nand_host
*host
= nand_chip
->priv
;
395 uint16_t col
, rd_word
;
396 uint16_t __iomem
*main_buf
= host
->regs
+ MAIN_AREA0
;
397 uint16_t __iomem
*spare_buf
= host
->regs
+ SPARE_AREA0
;
399 /* Check for status request */
400 if (host
->status_request
)
401 return get_dev_status(host
) & 0xFF;
403 /* Get column for 16-bit access */
404 col
= host
->col_addr
>> 1;
406 /* If we are accessing the spare region */
407 if (host
->spare_only
)
408 rd_word
= readw(&spare_buf
[col
]);
410 rd_word
= readw(&main_buf
[col
]);
412 /* Pick upper/lower byte of word from RAM buffer */
413 if (host
->col_addr
& 0x1)
414 ret
= (rd_word
>> 8) & 0xFF;
416 ret
= rd_word
& 0xFF;
418 /* Update saved column address */
424 static uint16_t mxc_nand_read_word(struct mtd_info
*mtd
)
426 struct nand_chip
*nand_chip
= mtd
->priv
;
427 struct mxc_nand_host
*host
= nand_chip
->priv
;
428 uint16_t col
, rd_word
, ret
;
431 DEBUG(MTD_DEBUG_LEVEL3
,
432 "mxc_nand_read_word(col = %d)\n", host
->col_addr
);
434 col
= host
->col_addr
;
435 /* Adjust saved column address */
436 if (col
< mtd
->writesize
&& host
->spare_only
)
437 col
+= mtd
->writesize
;
439 if (col
< mtd
->writesize
)
440 p
= (host
->regs
+ MAIN_AREA0
) + (col
>> 1);
442 p
= (host
->regs
+ SPARE_AREA0
) + ((col
- mtd
->writesize
) >> 1);
446 ret
= (rd_word
>> 8) & 0xff;
447 rd_word
= readw(&p
[1]);
448 ret
|= (rd_word
<< 8) & 0xff00;
453 /* Update saved column address */
454 host
->col_addr
= col
+ 2;
459 /* Write data of length len to buffer buf. The data to be
460 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
461 * Operation by the NFC, the data is written to NAND Flash */
462 static void mxc_nand_write_buf(struct mtd_info
*mtd
,
463 const u_char
*buf
, int len
)
465 struct nand_chip
*nand_chip
= mtd
->priv
;
466 struct mxc_nand_host
*host
= nand_chip
->priv
;
469 DEBUG(MTD_DEBUG_LEVEL3
,
470 "mxc_nand_write_buf(col = %d, len = %d)\n", host
->col_addr
,
473 col
= host
->col_addr
;
475 /* Adjust saved column address */
476 if (col
< mtd
->writesize
&& host
->spare_only
)
477 col
+= mtd
->writesize
;
479 n
= mtd
->writesize
+ mtd
->oobsize
- col
;
482 DEBUG(MTD_DEBUG_LEVEL3
,
483 "%s:%d: col = %d, n = %d\n", __func__
, __LINE__
, col
, n
);
488 if (col
< mtd
->writesize
)
489 p
= host
->regs
+ MAIN_AREA0
+ (col
& ~3);
491 p
= host
->regs
+ SPARE_AREA0
-
492 mtd
->writesize
+ (col
& ~3);
494 DEBUG(MTD_DEBUG_LEVEL3
, "%s:%d: p = %p\n", __func__
,
497 if (((col
| (int)&buf
[i
]) & 3) || n
< 16) {
500 if (col
& 3 || n
< 4)
506 data
= (data
& 0xffffff00) |
513 data
= (data
& 0xffff00ff) |
520 data
= (data
& 0xff00ffff) |
527 data
= (data
& 0x00ffffff) |
536 int m
= mtd
->writesize
- col
;
538 if (col
>= mtd
->writesize
)
543 DEBUG(MTD_DEBUG_LEVEL3
,
544 "%s:%d: n = %d, m = %d, i = %d, col = %d\n",
545 __func__
, __LINE__
, n
, m
, i
, col
);
547 memcpy(p
, &buf
[i
], m
);
553 /* Update saved column address */
554 host
->col_addr
= col
;
557 /* Read the data buffer from the NAND Flash. To read the data from NAND
558 * Flash first the data output cycle is initiated by the NFC, which copies
559 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
561 static void mxc_nand_read_buf(struct mtd_info
*mtd
, u_char
*buf
, int len
)
563 struct nand_chip
*nand_chip
= mtd
->priv
;
564 struct mxc_nand_host
*host
= nand_chip
->priv
;
567 DEBUG(MTD_DEBUG_LEVEL3
,
568 "mxc_nand_read_buf(col = %d, len = %d)\n", host
->col_addr
, len
);
570 col
= host
->col_addr
;
572 /* Adjust saved column address */
573 if (col
< mtd
->writesize
&& host
->spare_only
)
574 col
+= mtd
->writesize
;
576 n
= mtd
->writesize
+ mtd
->oobsize
- col
;
582 if (col
< mtd
->writesize
)
583 p
= host
->regs
+ MAIN_AREA0
+ (col
& ~3);
585 p
= host
->regs
+ SPARE_AREA0
-
586 mtd
->writesize
+ (col
& ~3);
588 if (((col
| (int)&buf
[i
]) & 3) || n
< 16) {
595 buf
[i
++] = (uint8_t) (data
);
601 buf
[i
++] = (uint8_t) (data
>> 8);
607 buf
[i
++] = (uint8_t) (data
>> 16);
613 buf
[i
++] = (uint8_t) (data
>> 24);
619 int m
= mtd
->writesize
- col
;
621 if (col
>= mtd
->writesize
)
625 memcpy(&buf
[i
], p
, m
);
631 /* Update saved column address */
632 host
->col_addr
= col
;
636 /* Used by the upper layer to verify the data in NAND Flash
637 * with the data in the buf. */
638 static int mxc_nand_verify_buf(struct mtd_info
*mtd
,
639 const u_char
*buf
, int len
)
644 /* This function is used by upper layer for select and
645 * deselect of the NAND chip */
646 static void mxc_nand_select_chip(struct mtd_info
*mtd
, int chip
)
648 struct nand_chip
*nand_chip
= mtd
->priv
;
649 struct mxc_nand_host
*host
= nand_chip
->priv
;
651 #ifdef CONFIG_MTD_NAND_MXC_FORCE_CE
653 DEBUG(MTD_DEBUG_LEVEL0
,
654 "ERROR: Illegal chip select (chip = %d)\n", chip
);
659 writew(readw(host
->regs
+ NFC_CONFIG1
) & ~NFC_CE
,
660 host
->regs
+ NFC_CONFIG1
);
664 writew(readw(host
->regs
+ NFC_CONFIG1
) | NFC_CE
,
665 host
->regs
+ NFC_CONFIG1
);
670 /* Disable the NFC clock */
672 clk_disable(host
->clk
);
677 /* Enable the NFC clock */
678 if (!host
->clk_act
) {
679 clk_enable(host
->clk
);
689 /* Used by the upper layer to write command to NAND Flash for
690 * different operations to be carried out on NAND Flash */
691 static void mxc_nand_command(struct mtd_info
*mtd
, unsigned command
,
692 int column
, int page_addr
)
694 struct nand_chip
*nand_chip
= mtd
->priv
;
695 struct mxc_nand_host
*host
= nand_chip
->priv
;
698 DEBUG(MTD_DEBUG_LEVEL3
,
699 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
700 command
, column
, page_addr
);
702 /* Reset command state information */
703 host
->status_request
= false;
705 /* Command pre-processing step */
708 case NAND_CMD_STATUS
:
710 host
->status_request
= true;
714 host
->col_addr
= column
;
715 host
->spare_only
= false;
719 case NAND_CMD_READOOB
:
720 host
->col_addr
= column
;
721 host
->spare_only
= true;
723 if (host
->pagesize_2k
)
724 command
= NAND_CMD_READ0
; /* only READ0 is valid */
728 if (column
>= mtd
->writesize
) {
730 * FIXME: before send SEQIN command for write OOB,
731 * We must read one page out.
732 * For K9F1GXX has no READ1 command to set current HW
733 * pointer to spare area, we must write the whole page
734 * including OOB together.
736 if (host
->pagesize_2k
)
737 /* call ourself to read a page */
738 mxc_nand_command(mtd
, NAND_CMD_READ0
, 0,
741 host
->col_addr
= column
- mtd
->writesize
;
742 host
->spare_only
= true;
744 /* Set program pointer to spare region */
745 if (!host
->pagesize_2k
)
746 send_cmd(host
, NAND_CMD_READOOB
, false);
748 host
->spare_only
= false;
749 host
->col_addr
= column
;
751 /* Set program pointer to page start */
752 if (!host
->pagesize_2k
)
753 send_cmd(host
, NAND_CMD_READ0
, false);
758 case NAND_CMD_PAGEPROG
:
759 send_prog_page(host
, 0, host
->spare_only
);
761 if (host
->pagesize_2k
) {
762 /* data in 4 areas datas */
763 send_prog_page(host
, 1, host
->spare_only
);
764 send_prog_page(host
, 2, host
->spare_only
);
765 send_prog_page(host
, 3, host
->spare_only
);
770 case NAND_CMD_ERASE1
:
775 /* Write out the command to the device. */
776 send_cmd(host
, command
, useirq
);
778 /* Write out column address, if necessary */
781 * MXC NANDFC can only perform full page+spare or
782 * spare-only read/write. When the upper layers
783 * layers perform a read/write buf operation,
784 * we will used the saved column adress to index into
787 send_addr(host
, 0, page_addr
== -1);
788 if (host
->pagesize_2k
)
789 /* another col addr cycle for 2k page */
790 send_addr(host
, 0, false);
793 /* Write out page address, if necessary */
794 if (page_addr
!= -1) {
795 /* paddr_0 - p_addr_7 */
796 send_addr(host
, (page_addr
& 0xff), false);
798 if (host
->pagesize_2k
) {
799 if (mtd
->size
>= 0x10000000) {
800 /* paddr_8 - paddr_15 */
801 send_addr(host
, (page_addr
>> 8) & 0xff, false);
802 send_addr(host
, (page_addr
>> 16) & 0xff, true);
804 /* paddr_8 - paddr_15 */
805 send_addr(host
, (page_addr
>> 8) & 0xff, true);
807 /* One more address cycle for higher density devices */
808 if (mtd
->size
>= 0x4000000) {
809 /* paddr_8 - paddr_15 */
810 send_addr(host
, (page_addr
>> 8) & 0xff, false);
811 send_addr(host
, (page_addr
>> 16) & 0xff, true);
813 /* paddr_8 - paddr_15 */
814 send_addr(host
, (page_addr
>> 8) & 0xff, true);
818 /* Command post-processing step */
824 case NAND_CMD_READOOB
:
826 if (host
->pagesize_2k
) {
827 /* send read confirm command */
828 send_cmd(host
, NAND_CMD_READSTART
, true);
829 /* read for each AREA */
830 send_read_page(host
, 0, host
->spare_only
);
831 send_read_page(host
, 1, host
->spare_only
);
832 send_read_page(host
, 2, host
->spare_only
);
833 send_read_page(host
, 3, host
->spare_only
);
835 send_read_page(host
, 0, host
->spare_only
);
838 case NAND_CMD_READID
:
843 case NAND_CMD_PAGEPROG
:
846 case NAND_CMD_STATUS
:
849 case NAND_CMD_ERASE2
:
854 static int __init
mxcnd_probe(struct platform_device
*pdev
)
856 struct nand_chip
*this;
857 struct mtd_info
*mtd
;
858 struct mxc_nand_platform_data
*pdata
= pdev
->dev
.platform_data
;
859 struct mxc_nand_host
*host
;
860 struct resource
*res
;
862 int err
= 0, nr_parts
= 0;
864 /* Allocate memory for MTD device structure and private data */
865 host
= kzalloc(sizeof(struct mxc_nand_host
), GFP_KERNEL
);
869 host
->dev
= &pdev
->dev
;
870 /* structures must be linked */
874 mtd
->owner
= THIS_MODULE
;
875 mtd
->dev
.parent
= &pdev
->dev
;
876 mtd
->name
= "mxc_nand";
878 /* 50 us command delay time */
879 this->chip_delay
= 5;
882 this->dev_ready
= mxc_nand_dev_ready
;
883 this->cmdfunc
= mxc_nand_command
;
884 this->select_chip
= mxc_nand_select_chip
;
885 this->read_byte
= mxc_nand_read_byte
;
886 this->read_word
= mxc_nand_read_word
;
887 this->write_buf
= mxc_nand_write_buf
;
888 this->read_buf
= mxc_nand_read_buf
;
889 this->verify_buf
= mxc_nand_verify_buf
;
891 host
->clk
= clk_get(&pdev
->dev
, "nfc");
892 if (IS_ERR(host
->clk
)) {
893 err
= PTR_ERR(host
->clk
);
897 clk_enable(host
->clk
);
900 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
906 host
->regs
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
912 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
914 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
916 init_waitqueue_head(&host
->irq_waitq
);
918 host
->irq
= platform_get_irq(pdev
, 0);
920 err
= request_irq(host
->irq
, mxc_nfc_irq
, 0, "mxc_nd", host
);
925 this->ecc
.calculate
= mxc_nand_calculate_ecc
;
926 this->ecc
.hwctl
= mxc_nand_enable_hwecc
;
927 this->ecc
.correct
= mxc_nand_correct_data
;
928 this->ecc
.mode
= NAND_ECC_HW
;
929 this->ecc
.size
= 512;
931 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
933 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
935 this->ecc
.size
= 512;
937 this->ecc
.layout
= &nand_hw_eccoob_smallpage
;
938 this->ecc
.mode
= NAND_ECC_SOFT
;
939 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
941 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
945 this->cmdfunc(mtd
, NAND_CMD_RESET
, -1, -1);
947 /* preset operation */
948 /* Unlock the internal RAM Buffer */
949 writew(0x2, host
->regs
+ NFC_CONFIG
);
951 /* Blocks to be unlocked */
952 writew(0x0, host
->regs
+ NFC_UNLOCKSTART_BLKADDR
);
953 writew(0x4000, host
->regs
+ NFC_UNLOCKEND_BLKADDR
);
955 /* Unlock Block Command for given address range */
956 writew(0x4, host
->regs
+ NFC_WRPROT
);
958 /* NAND bus width determines access funtions used by upper layer */
959 if (pdata
->width
== 2) {
960 this->options
|= NAND_BUSWIDTH_16
;
961 this->ecc
.layout
= &nand_hw_eccoob_smallpage
;
964 /* first scan to find the device and get the page size */
965 if (nand_scan_ident(mtd
, 1)) {
970 host
->pagesize_2k
= (mtd
->writesize
== 2048) ? 1 : 0;
972 if (this->ecc
.mode
== NAND_ECC_HW
) {
973 switch (mtd
->oobsize
) {
975 this->ecc
.layout
= &nand_hw_eccoob_smallpage
;
978 this->ecc
.layout
= &nand_hw_eccoob_smallpage
;
981 this->ecc
.layout
= &nand_hw_eccoob_largepage
;
984 /* page size not handled by HW ECC */
985 /* switching back to soft ECC */
986 this->ecc
.size
= 512;
988 this->ecc
.layout
= &nand_hw_eccoob_smallpage
;
989 this->ecc
.mode
= NAND_ECC_SOFT
;
990 this->ecc
.calculate
= NULL
;
991 this->ecc
.correct
= NULL
;
992 this->ecc
.hwctl
= NULL
;
993 tmp
= readw(host
->regs
+ NFC_CONFIG1
);
995 writew(tmp
, host
->regs
+ NFC_CONFIG1
);
1000 /* second phase scan */
1001 if (nand_scan_tail(mtd
)) {
1006 /* Register the partitions */
1007 #ifdef CONFIG_MTD_PARTITIONS
1009 parse_mtd_partitions(mtd
, part_probes
, &host
->parts
, 0);
1011 add_mtd_partitions(mtd
, host
->parts
, nr_parts
);
1015 pr_info("Registering %s as whole device\n", mtd
->name
);
1016 add_mtd_device(mtd
);
1019 platform_set_drvdata(pdev
, host
);
1024 free_irq(host
->irq
, host
);
1026 iounmap(host
->regs
);
1035 static int __exit
mxcnd_remove(struct platform_device
*pdev
)
1037 struct mxc_nand_host
*host
= platform_get_drvdata(pdev
);
1041 platform_set_drvdata(pdev
, NULL
);
1043 nand_release(&host
->mtd
);
1044 free_irq(host
->irq
, host
);
1045 iounmap(host
->regs
);
1052 static int mxcnd_suspend(struct platform_device
*pdev
, pm_message_t state
)
1054 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1055 struct nand_chip
*nand_chip
= mtd
->priv
;
1056 struct mxc_nand_host
*host
= nand_chip
->priv
;
1059 DEBUG(MTD_DEBUG_LEVEL0
, "MXC_ND : NAND suspend\n");
1061 ret
= mtd
->suspend(mtd
);
1062 /* Disable the NFC clock */
1063 clk_disable(host
->clk
);
1069 static int mxcnd_resume(struct platform_device
*pdev
)
1071 struct mtd_info
*mtd
= platform_get_drvdata(pdev
);
1072 struct nand_chip
*nand_chip
= mtd
->priv
;
1073 struct mxc_nand_host
*host
= nand_chip
->priv
;
1076 DEBUG(MTD_DEBUG_LEVEL0
, "MXC_ND : NAND resume\n");
1079 /* Enable the NFC clock */
1080 clk_enable(host
->clk
);
1088 # define mxcnd_suspend NULL
1089 # define mxcnd_resume NULL
1090 #endif /* CONFIG_PM */
1092 static struct platform_driver mxcnd_driver
= {
1094 .name
= DRIVER_NAME
,
1096 .remove
= __exit_p(mxcnd_remove
),
1097 .suspend
= mxcnd_suspend
,
1098 .resume
= mxcnd_resume
,
1101 static int __init
mxc_nd_init(void)
1103 return platform_driver_probe(&mxcnd_driver
, mxcnd_probe
);
1106 static void __exit
mxc_nd_cleanup(void)
1108 /* Unregister the device structure */
1109 platform_driver_unregister(&mxcnd_driver
);
1112 module_init(mxc_nd_init
);
1113 module_exit(mxc_nd_cleanup
);
1115 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1116 MODULE_DESCRIPTION("MXC NAND MTD driver");
1117 MODULE_LICENSE("GPL");