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[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
37
38 #define DRIVER_NAME "mxc_nand"
39
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
42
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0xE00
45 #define NFC_BUF_ADDR 0xE04
46 #define NFC_FLASH_ADDR 0xE06
47 #define NFC_FLASH_CMD 0xE08
48 #define NFC_CONFIG 0xE0A
49 #define NFC_ECC_STATUS_RESULT 0xE0C
50 #define NFC_RSLTMAIN_AREA 0xE0E
51 #define NFC_RSLTSPARE_AREA 0xE10
52 #define NFC_WRPROT 0xE12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0xe16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0xe22
57 #define NFC_NF_WRPRST 0xE18
58 #define NFC_CONFIG1 0xE1A
59 #define NFC_CONFIG2 0xE1C
60
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
63 #define NFC_CMD 0x1
64
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
67 #define NFC_ADDR 0x2
68
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
71 #define NFC_INPUT 0x4
72
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
76
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
79 #define NFC_ID 0x10
80
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
84
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
86 * Status operation */
87 #define NFC_INT 0x8000
88
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
96
97 struct mxc_nand_host {
98 struct mtd_info mtd;
99 struct nand_chip nand;
100 struct mtd_partition *parts;
101 struct device *dev;
102
103 void *spare0;
104 void *main_area0;
105 void *main_area1;
106
107 void __iomem *base;
108 void __iomem *regs;
109 int status_request;
110 struct clk *clk;
111 int clk_act;
112 int irq;
113
114 wait_queue_head_t irq_waitq;
115
116 uint8_t *data_buf;
117 unsigned int buf_start;
118 int spare_len;
119 };
120
121 /* OOB placement block for use with hardware ecc generation */
122 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
123 .eccbytes = 5,
124 .eccpos = {6, 7, 8, 9, 10},
125 .oobfree = {{0, 5}, {12, 4}, }
126 };
127
128 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
129 .eccbytes = 20,
130 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
131 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
132 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
133 };
134
135 /* OOB description for 512 byte pages with 16 byte OOB */
136 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
137 .eccbytes = 1 * 9,
138 .eccpos = {
139 7, 8, 9, 10, 11, 12, 13, 14, 15
140 },
141 .oobfree = {
142 {.offset = 0, .length = 5}
143 }
144 };
145
146 /* OOB description for 2048 byte pages with 64 byte OOB */
147 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
148 .eccbytes = 4 * 9,
149 .eccpos = {
150 7, 8, 9, 10, 11, 12, 13, 14, 15,
151 23, 24, 25, 26, 27, 28, 29, 30, 31,
152 39, 40, 41, 42, 43, 44, 45, 46, 47,
153 55, 56, 57, 58, 59, 60, 61, 62, 63
154 },
155 .oobfree = {
156 {.offset = 2, .length = 4},
157 {.offset = 16, .length = 7},
158 {.offset = 32, .length = 7},
159 {.offset = 48, .length = 7}
160 }
161 };
162
163 #ifdef CONFIG_MTD_PARTITIONS
164 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
165 #endif
166
167 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
168 {
169 struct mxc_nand_host *host = dev_id;
170
171 uint16_t tmp;
172
173 tmp = readw(host->regs + NFC_CONFIG1);
174 tmp |= NFC_INT_MSK; /* Disable interrupt */
175 writew(tmp, host->regs + NFC_CONFIG1);
176
177 wake_up(&host->irq_waitq);
178
179 return IRQ_HANDLED;
180 }
181
182 /* This function polls the NANDFC to wait for the basic operation to
183 * complete by checking the INT bit of config2 register.
184 */
185 static void wait_op_done(struct mxc_nand_host *host, int useirq)
186 {
187 uint32_t tmp;
188 int max_retries = 2000;
189
190 if (useirq) {
191 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
192
193 tmp = readw(host->regs + NFC_CONFIG1);
194 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
195 writew(tmp, host->regs + NFC_CONFIG1);
196
197 wait_event(host->irq_waitq,
198 readw(host->regs + NFC_CONFIG2) & NFC_INT);
199
200 tmp = readw(host->regs + NFC_CONFIG2);
201 tmp &= ~NFC_INT;
202 writew(tmp, host->regs + NFC_CONFIG2);
203 }
204 } else {
205 while (max_retries-- > 0) {
206 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
207 tmp = readw(host->regs + NFC_CONFIG2);
208 tmp &= ~NFC_INT;
209 writew(tmp, host->regs + NFC_CONFIG2);
210 break;
211 }
212 udelay(1);
213 }
214 if (max_retries < 0)
215 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
216 __func__);
217 }
218 }
219
220 /* This function issues the specified command to the NAND device and
221 * waits for completion. */
222 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
223 {
224 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
225
226 writew(cmd, host->regs + NFC_FLASH_CMD);
227 writew(NFC_CMD, host->regs + NFC_CONFIG2);
228
229 /* Wait for operation to complete */
230 wait_op_done(host, useirq);
231 }
232
233 /* This function sends an address (or partial address) to the
234 * NAND device. The address is used to select the source/destination for
235 * a NAND command. */
236 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
237 {
238 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
239
240 writew(addr, host->regs + NFC_FLASH_ADDR);
241 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
242
243 /* Wait for operation to complete */
244 wait_op_done(host, islast);
245 }
246
247 static void send_page(struct mtd_info *mtd, unsigned int ops)
248 {
249 struct nand_chip *nand_chip = mtd->priv;
250 struct mxc_nand_host *host = nand_chip->priv;
251 int bufs, i;
252
253 if (nfc_is_v1() && mtd->writesize > 512)
254 bufs = 4;
255 else
256 bufs = 1;
257
258 for (i = 0; i < bufs; i++) {
259
260 /* NANDFC buffer 0 is used for page read/write */
261 writew(i, host->regs + NFC_BUF_ADDR);
262
263 writew(ops, host->regs + NFC_CONFIG2);
264
265 /* Wait for operation to complete */
266 wait_op_done(host, true);
267 }
268 }
269
270 /* Request the NANDFC to perform a read of the NAND device ID. */
271 static void send_read_id(struct mxc_nand_host *host)
272 {
273 struct nand_chip *this = &host->nand;
274
275 /* NANDFC buffer 0 is used for device ID output */
276 writew(0x0, host->regs + NFC_BUF_ADDR);
277
278 writew(NFC_ID, host->regs + NFC_CONFIG2);
279
280 /* Wait for operation to complete */
281 wait_op_done(host, true);
282
283 if (this->options & NAND_BUSWIDTH_16) {
284 void __iomem *main_buf = host->main_area0;
285 /* compress the ID info */
286 writeb(readb(main_buf + 2), main_buf + 1);
287 writeb(readb(main_buf + 4), main_buf + 2);
288 writeb(readb(main_buf + 6), main_buf + 3);
289 writeb(readb(main_buf + 8), main_buf + 4);
290 writeb(readb(main_buf + 10), main_buf + 5);
291 }
292 memcpy(host->data_buf, host->main_area0, 16);
293 }
294
295 /* This function requests the NANDFC to perform a read of the
296 * NAND device status and returns the current status. */
297 static uint16_t get_dev_status(struct mxc_nand_host *host)
298 {
299 void __iomem *main_buf = host->main_area1;
300 uint32_t store;
301 uint16_t ret;
302 /* Issue status request to NAND device */
303
304 /* store the main area1 first word, later do recovery */
305 store = readl(main_buf);
306 /* NANDFC buffer 1 is used for device status to prevent
307 * corruption of read/write buffer on status requests. */
308 writew(1, host->regs + NFC_BUF_ADDR);
309
310 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
311
312 /* Wait for operation to complete */
313 wait_op_done(host, true);
314
315 /* Status is placed in first word of main buffer */
316 /* get status, then recovery area 1 data */
317 ret = readw(main_buf);
318 writel(store, main_buf);
319
320 return ret;
321 }
322
323 /* This functions is used by upper layer to checks if device is ready */
324 static int mxc_nand_dev_ready(struct mtd_info *mtd)
325 {
326 /*
327 * NFC handles R/B internally. Therefore, this function
328 * always returns status as ready.
329 */
330 return 1;
331 }
332
333 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
334 {
335 /*
336 * If HW ECC is enabled, we turn it on during init. There is
337 * no need to enable again here.
338 */
339 }
340
341 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
342 u_char *read_ecc, u_char *calc_ecc)
343 {
344 struct nand_chip *nand_chip = mtd->priv;
345 struct mxc_nand_host *host = nand_chip->priv;
346
347 /*
348 * 1-Bit errors are automatically corrected in HW. No need for
349 * additional correction. 2-Bit errors cannot be corrected by
350 * HW ECC, so we need to return failure
351 */
352 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
353
354 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
355 DEBUG(MTD_DEBUG_LEVEL0,
356 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
357 return -1;
358 }
359
360 return 0;
361 }
362
363 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
364 u_char *ecc_code)
365 {
366 return 0;
367 }
368
369 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
370 {
371 struct nand_chip *nand_chip = mtd->priv;
372 struct mxc_nand_host *host = nand_chip->priv;
373 uint8_t ret;
374
375 /* Check for status request */
376 if (host->status_request)
377 return get_dev_status(host) & 0xFF;
378
379 ret = *(uint8_t *)(host->data_buf + host->buf_start);
380 host->buf_start++;
381
382 return ret;
383 }
384
385 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
386 {
387 struct nand_chip *nand_chip = mtd->priv;
388 struct mxc_nand_host *host = nand_chip->priv;
389 uint16_t ret;
390
391 ret = *(uint16_t *)(host->data_buf + host->buf_start);
392 host->buf_start += 2;
393
394 return ret;
395 }
396
397 /* Write data of length len to buffer buf. The data to be
398 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
399 * Operation by the NFC, the data is written to NAND Flash */
400 static void mxc_nand_write_buf(struct mtd_info *mtd,
401 const u_char *buf, int len)
402 {
403 struct nand_chip *nand_chip = mtd->priv;
404 struct mxc_nand_host *host = nand_chip->priv;
405 u16 col = host->buf_start;
406 int n = mtd->oobsize + mtd->writesize - col;
407
408 n = min(n, len);
409
410 memcpy(host->data_buf + col, buf, n);
411
412 host->buf_start += n;
413 }
414
415 /* Read the data buffer from the NAND Flash. To read the data from NAND
416 * Flash first the data output cycle is initiated by the NFC, which copies
417 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
418 */
419 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
420 {
421 struct nand_chip *nand_chip = mtd->priv;
422 struct mxc_nand_host *host = nand_chip->priv;
423 u16 col = host->buf_start;
424 int n = mtd->oobsize + mtd->writesize - col;
425
426 n = min(n, len);
427
428 memcpy(buf, host->data_buf + col, len);
429
430 host->buf_start += len;
431 }
432
433 /* Used by the upper layer to verify the data in NAND Flash
434 * with the data in the buf. */
435 static int mxc_nand_verify_buf(struct mtd_info *mtd,
436 const u_char *buf, int len)
437 {
438 return -EFAULT;
439 }
440
441 /* This function is used by upper layer for select and
442 * deselect of the NAND chip */
443 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
444 {
445 struct nand_chip *nand_chip = mtd->priv;
446 struct mxc_nand_host *host = nand_chip->priv;
447
448 switch (chip) {
449 case -1:
450 /* Disable the NFC clock */
451 if (host->clk_act) {
452 clk_disable(host->clk);
453 host->clk_act = 0;
454 }
455 break;
456 case 0:
457 /* Enable the NFC clock */
458 if (!host->clk_act) {
459 clk_enable(host->clk);
460 host->clk_act = 1;
461 }
462 break;
463
464 default:
465 break;
466 }
467 }
468
469 /*
470 * Function to transfer data to/from spare area.
471 */
472 static void copy_spare(struct mtd_info *mtd, bool bfrom)
473 {
474 struct nand_chip *this = mtd->priv;
475 struct mxc_nand_host *host = this->priv;
476 u16 i, j;
477 u16 n = mtd->writesize >> 9;
478 u8 *d = host->data_buf + mtd->writesize;
479 u8 *s = host->spare0;
480 u16 t = host->spare_len;
481
482 j = (mtd->oobsize / n >> 1) << 1;
483
484 if (bfrom) {
485 for (i = 0; i < n - 1; i++)
486 memcpy(d + i * j, s + i * t, j);
487
488 /* the last section */
489 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
490 } else {
491 for (i = 0; i < n - 1; i++)
492 memcpy(&s[i * t], &d[i * j], j);
493
494 /* the last section */
495 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
496 }
497 }
498
499 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
500 {
501 struct nand_chip *nand_chip = mtd->priv;
502 struct mxc_nand_host *host = nand_chip->priv;
503
504 /* Write out column address, if necessary */
505 if (column != -1) {
506 /*
507 * MXC NANDFC can only perform full page+spare or
508 * spare-only read/write. When the upper layers
509 * layers perform a read/write buf operation,
510 * we will used the saved column adress to index into
511 * the full page.
512 */
513 send_addr(host, 0, page_addr == -1);
514 if (mtd->writesize > 512)
515 /* another col addr cycle for 2k page */
516 send_addr(host, 0, false);
517 }
518
519 /* Write out page address, if necessary */
520 if (page_addr != -1) {
521 /* paddr_0 - p_addr_7 */
522 send_addr(host, (page_addr & 0xff), false);
523
524 if (mtd->writesize > 512) {
525 if (mtd->size >= 0x10000000) {
526 /* paddr_8 - paddr_15 */
527 send_addr(host, (page_addr >> 8) & 0xff, false);
528 send_addr(host, (page_addr >> 16) & 0xff, true);
529 } else
530 /* paddr_8 - paddr_15 */
531 send_addr(host, (page_addr >> 8) & 0xff, true);
532 } else {
533 /* One more address cycle for higher density devices */
534 if (mtd->size >= 0x4000000) {
535 /* paddr_8 - paddr_15 */
536 send_addr(host, (page_addr >> 8) & 0xff, false);
537 send_addr(host, (page_addr >> 16) & 0xff, true);
538 } else
539 /* paddr_8 - paddr_15 */
540 send_addr(host, (page_addr >> 8) & 0xff, true);
541 }
542 }
543 }
544
545 /* Used by the upper layer to write command to NAND Flash for
546 * different operations to be carried out on NAND Flash */
547 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
548 int column, int page_addr)
549 {
550 struct nand_chip *nand_chip = mtd->priv;
551 struct mxc_nand_host *host = nand_chip->priv;
552
553 DEBUG(MTD_DEBUG_LEVEL3,
554 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
555 command, column, page_addr);
556
557 /* Reset command state information */
558 host->status_request = false;
559
560 /* Command pre-processing step */
561 switch (command) {
562
563 case NAND_CMD_STATUS:
564 host->buf_start = 0;
565 host->status_request = true;
566
567 send_cmd(host, command, true);
568 mxc_do_addr_cycle(mtd, column, page_addr);
569 break;
570
571 case NAND_CMD_READ0:
572 case NAND_CMD_READOOB:
573 if (command == NAND_CMD_READ0)
574 host->buf_start = column;
575 else
576 host->buf_start = column + mtd->writesize;
577
578 if (mtd->writesize > 512)
579 command = NAND_CMD_READ0; /* only READ0 is valid */
580
581 send_cmd(host, command, false);
582 mxc_do_addr_cycle(mtd, column, page_addr);
583
584 if (mtd->writesize > 512)
585 send_cmd(host, NAND_CMD_READSTART, true);
586
587 send_page(mtd, NFC_OUTPUT);
588
589 memcpy(host->data_buf, host->main_area0, mtd->writesize);
590 copy_spare(mtd, true);
591 break;
592
593 case NAND_CMD_SEQIN:
594 if (column >= mtd->writesize) {
595 /*
596 * FIXME: before send SEQIN command for write OOB,
597 * We must read one page out.
598 * For K9F1GXX has no READ1 command to set current HW
599 * pointer to spare area, we must write the whole page
600 * including OOB together.
601 */
602 if (mtd->writesize > 512)
603 /* call ourself to read a page */
604 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
605 page_addr);
606
607 host->buf_start = column;
608
609 /* Set program pointer to spare region */
610 if (mtd->writesize == 512)
611 send_cmd(host, NAND_CMD_READOOB, false);
612 } else {
613 host->buf_start = column;
614
615 /* Set program pointer to page start */
616 if (mtd->writesize == 512)
617 send_cmd(host, NAND_CMD_READ0, false);
618 }
619
620 send_cmd(host, command, false);
621 mxc_do_addr_cycle(mtd, column, page_addr);
622 break;
623
624 case NAND_CMD_PAGEPROG:
625 memcpy(host->main_area0, host->data_buf, mtd->writesize);
626 copy_spare(mtd, false);
627 send_page(mtd, NFC_INPUT);
628 send_cmd(host, command, true);
629 mxc_do_addr_cycle(mtd, column, page_addr);
630 break;
631
632 case NAND_CMD_READID:
633 send_cmd(host, command, true);
634 mxc_do_addr_cycle(mtd, column, page_addr);
635 send_read_id(host);
636 host->buf_start = column;
637 break;
638
639 case NAND_CMD_ERASE1:
640 case NAND_CMD_ERASE2:
641 send_cmd(host, command, false);
642 mxc_do_addr_cycle(mtd, column, page_addr);
643
644 break;
645 }
646 }
647
648 /*
649 * The generic flash bbt decriptors overlap with our ecc
650 * hardware, so define some i.MX specific ones.
651 */
652 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
653 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
654
655 static struct nand_bbt_descr bbt_main_descr = {
656 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
657 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
658 .offs = 0,
659 .len = 4,
660 .veroffs = 4,
661 .maxblocks = 4,
662 .pattern = bbt_pattern,
663 };
664
665 static struct nand_bbt_descr bbt_mirror_descr = {
666 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
667 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
668 .offs = 0,
669 .len = 4,
670 .veroffs = 4,
671 .maxblocks = 4,
672 .pattern = mirror_pattern,
673 };
674
675 static int __init mxcnd_probe(struct platform_device *pdev)
676 {
677 struct nand_chip *this;
678 struct mtd_info *mtd;
679 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
680 struct mxc_nand_host *host;
681 struct resource *res;
682 uint16_t tmp;
683 int err = 0, nr_parts = 0;
684 struct nand_ecclayout *oob_smallpage, *oob_largepage;
685
686 /* Allocate memory for MTD device structure and private data */
687 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
688 NAND_MAX_OOBSIZE, GFP_KERNEL);
689 if (!host)
690 return -ENOMEM;
691
692 host->data_buf = (uint8_t *)(host + 1);
693
694 host->dev = &pdev->dev;
695 /* structures must be linked */
696 this = &host->nand;
697 mtd = &host->mtd;
698 mtd->priv = this;
699 mtd->owner = THIS_MODULE;
700 mtd->dev.parent = &pdev->dev;
701 mtd->name = "mxc_nand";
702
703 /* 50 us command delay time */
704 this->chip_delay = 5;
705
706 this->priv = host;
707 this->dev_ready = mxc_nand_dev_ready;
708 this->cmdfunc = mxc_nand_command;
709 this->select_chip = mxc_nand_select_chip;
710 this->read_byte = mxc_nand_read_byte;
711 this->read_word = mxc_nand_read_word;
712 this->write_buf = mxc_nand_write_buf;
713 this->read_buf = mxc_nand_read_buf;
714 this->verify_buf = mxc_nand_verify_buf;
715
716 host->clk = clk_get(&pdev->dev, "nfc");
717 if (IS_ERR(host->clk)) {
718 err = PTR_ERR(host->clk);
719 goto eclk;
720 }
721
722 clk_enable(host->clk);
723 host->clk_act = 1;
724
725 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
726 if (!res) {
727 err = -ENODEV;
728 goto eres;
729 }
730
731 host->base = ioremap(res->start, resource_size(res));
732 if (!host->base) {
733 err = -ENOMEM;
734 goto eres;
735 }
736
737 host->main_area0 = host->base;
738 host->main_area1 = host->base + 0x200;
739
740 if (nfc_is_v21()) {
741 host->regs = host->base + 0x1000;
742 host->spare0 = host->base + 0x1000;
743 host->spare_len = 64;
744 oob_smallpage = &nandv2_hw_eccoob_smallpage;
745 oob_largepage = &nandv2_hw_eccoob_largepage;
746 } else if (nfc_is_v1()) {
747 host->regs = host->base;
748 host->spare0 = host->base + 0x800;
749 host->spare_len = 16;
750 oob_smallpage = &nandv1_hw_eccoob_smallpage;
751 oob_largepage = &nandv1_hw_eccoob_largepage;
752 } else
753 BUG();
754
755 /* disable interrupt and spare enable */
756 tmp = readw(host->regs + NFC_CONFIG1);
757 tmp |= NFC_INT_MSK;
758 tmp &= ~NFC_SP_EN;
759 writew(tmp, host->regs + NFC_CONFIG1);
760
761 init_waitqueue_head(&host->irq_waitq);
762
763 host->irq = platform_get_irq(pdev, 0);
764
765 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
766 if (err)
767 goto eirq;
768
769 /* Reset NAND */
770 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
771
772 /* preset operation */
773 /* Unlock the internal RAM Buffer */
774 writew(0x2, host->regs + NFC_CONFIG);
775
776 /* Blocks to be unlocked */
777 if (nfc_is_v21()) {
778 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
779 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
780 this->ecc.bytes = 9;
781 } else if (nfc_is_v1()) {
782 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
783 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
784 this->ecc.bytes = 3;
785 } else
786 BUG();
787
788 /* Unlock Block Command for given address range */
789 writew(0x4, host->regs + NFC_WRPROT);
790
791 this->ecc.size = 512;
792 this->ecc.layout = oob_smallpage;
793
794 if (pdata->hw_ecc) {
795 this->ecc.calculate = mxc_nand_calculate_ecc;
796 this->ecc.hwctl = mxc_nand_enable_hwecc;
797 this->ecc.correct = mxc_nand_correct_data;
798 this->ecc.mode = NAND_ECC_HW;
799 tmp = readw(host->regs + NFC_CONFIG1);
800 tmp |= NFC_ECC_EN;
801 writew(tmp, host->regs + NFC_CONFIG1);
802 } else {
803 this->ecc.mode = NAND_ECC_SOFT;
804 tmp = readw(host->regs + NFC_CONFIG1);
805 tmp &= ~NFC_ECC_EN;
806 writew(tmp, host->regs + NFC_CONFIG1);
807 }
808
809 /* NAND bus width determines access funtions used by upper layer */
810 if (pdata->width == 2)
811 this->options |= NAND_BUSWIDTH_16;
812
813 if (pdata->flash_bbt) {
814 this->bbt_td = &bbt_main_descr;
815 this->bbt_md = &bbt_mirror_descr;
816 /* update flash based bbt */
817 this->options |= NAND_USE_FLASH_BBT;
818 }
819
820 /* first scan to find the device and get the page size */
821 if (nand_scan_ident(mtd, 1)) {
822 err = -ENXIO;
823 goto escan;
824 }
825
826 if (mtd->writesize == 2048)
827 this->ecc.layout = oob_largepage;
828
829 /* second phase scan */
830 if (nand_scan_tail(mtd)) {
831 err = -ENXIO;
832 goto escan;
833 }
834
835 /* Register the partitions */
836 #ifdef CONFIG_MTD_PARTITIONS
837 nr_parts =
838 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
839 if (nr_parts > 0)
840 add_mtd_partitions(mtd, host->parts, nr_parts);
841 else
842 #endif
843 {
844 pr_info("Registering %s as whole device\n", mtd->name);
845 add_mtd_device(mtd);
846 }
847
848 platform_set_drvdata(pdev, host);
849
850 return 0;
851
852 escan:
853 free_irq(host->irq, host);
854 eirq:
855 iounmap(host->base);
856 eres:
857 clk_put(host->clk);
858 eclk:
859 kfree(host);
860
861 return err;
862 }
863
864 static int __exit mxcnd_remove(struct platform_device *pdev)
865 {
866 struct mxc_nand_host *host = platform_get_drvdata(pdev);
867
868 clk_put(host->clk);
869
870 platform_set_drvdata(pdev, NULL);
871
872 nand_release(&host->mtd);
873 free_irq(host->irq, host);
874 iounmap(host->base);
875 kfree(host);
876
877 return 0;
878 }
879
880 #ifdef CONFIG_PM
881 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
882 {
883 struct mtd_info *mtd = platform_get_drvdata(pdev);
884 struct nand_chip *nand_chip = mtd->priv;
885 struct mxc_nand_host *host = nand_chip->priv;
886 int ret = 0;
887
888 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
889 if (mtd) {
890 ret = mtd->suspend(mtd);
891 /* Disable the NFC clock */
892 clk_disable(host->clk);
893 }
894
895 return ret;
896 }
897
898 static int mxcnd_resume(struct platform_device *pdev)
899 {
900 struct mtd_info *mtd = platform_get_drvdata(pdev);
901 struct nand_chip *nand_chip = mtd->priv;
902 struct mxc_nand_host *host = nand_chip->priv;
903 int ret = 0;
904
905 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
906
907 if (mtd) {
908 /* Enable the NFC clock */
909 clk_enable(host->clk);
910 mtd->resume(mtd);
911 }
912
913 return ret;
914 }
915
916 #else
917 # define mxcnd_suspend NULL
918 # define mxcnd_resume NULL
919 #endif /* CONFIG_PM */
920
921 static struct platform_driver mxcnd_driver = {
922 .driver = {
923 .name = DRIVER_NAME,
924 },
925 .remove = __exit_p(mxcnd_remove),
926 .suspend = mxcnd_suspend,
927 .resume = mxcnd_resume,
928 };
929
930 static int __init mxc_nd_init(void)
931 {
932 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
933 }
934
935 static void __exit mxc_nd_cleanup(void)
936 {
937 /* Unregister the device structure */
938 platform_driver_unregister(&mxcnd_driver);
939 }
940
941 module_init(mxc_nd_init);
942 module_exit(mxc_nd_cleanup);
943
944 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
945 MODULE_DESCRIPTION("MXC NAND MTD driver");
946 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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