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mxc_nand: Add NFC V2 support
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33
34 #include <asm/mach/flash.h>
35 #include <mach/mxc_nand.h>
36 #include <mach/hardware.h>
37
38 #define DRIVER_NAME "mxc_nand"
39
40 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
41 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27())
42
43 /* Addresses for NFC registers */
44 #define NFC_BUF_SIZE 0xE00
45 #define NFC_BUF_ADDR 0xE04
46 #define NFC_FLASH_ADDR 0xE06
47 #define NFC_FLASH_CMD 0xE08
48 #define NFC_CONFIG 0xE0A
49 #define NFC_ECC_STATUS_RESULT 0xE0C
50 #define NFC_RSLTMAIN_AREA 0xE0E
51 #define NFC_RSLTSPARE_AREA 0xE10
52 #define NFC_WRPROT 0xE12
53 #define NFC_V1_UNLOCKSTART_BLKADDR 0xe14
54 #define NFC_V1_UNLOCKEND_BLKADDR 0xe16
55 #define NFC_V21_UNLOCKSTART_BLKADDR 0xe20
56 #define NFC_V21_UNLOCKEND_BLKADDR 0xe22
57 #define NFC_NF_WRPRST 0xE18
58 #define NFC_CONFIG1 0xE1A
59 #define NFC_CONFIG2 0xE1C
60
61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
62 * for Command operation */
63 #define NFC_CMD 0x1
64
65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
66 * for Address operation */
67 #define NFC_ADDR 0x2
68
69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
70 * for Input operation */
71 #define NFC_INPUT 0x4
72
73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
74 * for Data Output operation */
75 #define NFC_OUTPUT 0x8
76
77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
78 * for Read ID operation */
79 #define NFC_ID 0x10
80
81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
82 * for Read Status operation */
83 #define NFC_STATUS 0x20
84
85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
86 * Status operation */
87 #define NFC_INT 0x8000
88
89 #define NFC_SP_EN (1 << 2)
90 #define NFC_ECC_EN (1 << 3)
91 #define NFC_INT_MSK (1 << 4)
92 #define NFC_BIG (1 << 5)
93 #define NFC_RST (1 << 6)
94 #define NFC_CE (1 << 7)
95 #define NFC_ONE_CYCLE (1 << 8)
96
97 struct mxc_nand_host {
98 struct mtd_info mtd;
99 struct nand_chip nand;
100 struct mtd_partition *parts;
101 struct device *dev;
102
103 void *spare0;
104 void *main_area0;
105 void *main_area1;
106
107 void __iomem *base;
108 void __iomem *regs;
109 int status_request;
110 struct clk *clk;
111 int clk_act;
112 int irq;
113
114 wait_queue_head_t irq_waitq;
115
116 uint8_t *data_buf;
117 unsigned int buf_start;
118 int spare_len;
119 };
120
121 /* Define delays in microsec for NAND device operations */
122 #define TROP_US_DELAY 2000
123
124 /* OOB placement block for use with hardware ecc generation */
125 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
126 .eccbytes = 5,
127 .eccpos = {6, 7, 8, 9, 10},
128 .oobfree = {{0, 5}, {12, 4}, }
129 };
130
131 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
132 .eccbytes = 20,
133 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
134 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
135 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
136 };
137
138 /* OOB description for 512 byte pages with 16 byte OOB */
139 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
140 .eccbytes = 1 * 9,
141 .eccpos = {
142 7, 8, 9, 10, 11, 12, 13, 14, 15
143 },
144 .oobfree = {
145 {.offset = 0, .length = 5}
146 }
147 };
148
149 /* OOB description for 2048 byte pages with 64 byte OOB */
150 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
151 .eccbytes = 4 * 9,
152 .eccpos = {
153 7, 8, 9, 10, 11, 12, 13, 14, 15,
154 23, 24, 25, 26, 27, 28, 29, 30, 31,
155 39, 40, 41, 42, 43, 44, 45, 46, 47,
156 55, 56, 57, 58, 59, 60, 61, 62, 63
157 },
158 .oobfree = {
159 {.offset = 2, .length = 4},
160 {.offset = 16, .length = 7},
161 {.offset = 32, .length = 7},
162 {.offset = 48, .length = 7}
163 }
164 };
165
166 #ifdef CONFIG_MTD_PARTITIONS
167 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
168 #endif
169
170 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
171 {
172 struct mxc_nand_host *host = dev_id;
173
174 uint16_t tmp;
175
176 tmp = readw(host->regs + NFC_CONFIG1);
177 tmp |= NFC_INT_MSK; /* Disable interrupt */
178 writew(tmp, host->regs + NFC_CONFIG1);
179
180 wake_up(&host->irq_waitq);
181
182 return IRQ_HANDLED;
183 }
184
185 /* This function polls the NANDFC to wait for the basic operation to
186 * complete by checking the INT bit of config2 register.
187 */
188 static void wait_op_done(struct mxc_nand_host *host, int max_retries,
189 int useirq)
190 {
191 uint32_t tmp;
192
193 if (useirq) {
194 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
195
196 tmp = readw(host->regs + NFC_CONFIG1);
197 tmp &= ~NFC_INT_MSK; /* Enable interrupt */
198 writew(tmp, host->regs + NFC_CONFIG1);
199
200 wait_event(host->irq_waitq,
201 readw(host->regs + NFC_CONFIG2) & NFC_INT);
202
203 tmp = readw(host->regs + NFC_CONFIG2);
204 tmp &= ~NFC_INT;
205 writew(tmp, host->regs + NFC_CONFIG2);
206 }
207 } else {
208 while (max_retries-- > 0) {
209 if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
210 tmp = readw(host->regs + NFC_CONFIG2);
211 tmp &= ~NFC_INT;
212 writew(tmp, host->regs + NFC_CONFIG2);
213 break;
214 }
215 udelay(1);
216 }
217 if (max_retries < 0)
218 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
219 __func__);
220 }
221 }
222
223 /* This function issues the specified command to the NAND device and
224 * waits for completion. */
225 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
226 {
227 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
228
229 writew(cmd, host->regs + NFC_FLASH_CMD);
230 writew(NFC_CMD, host->regs + NFC_CONFIG2);
231
232 /* Wait for operation to complete */
233 wait_op_done(host, TROP_US_DELAY, useirq);
234 }
235
236 /* This function sends an address (or partial address) to the
237 * NAND device. The address is used to select the source/destination for
238 * a NAND command. */
239 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
240 {
241 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
242
243 writew(addr, host->regs + NFC_FLASH_ADDR);
244 writew(NFC_ADDR, host->regs + NFC_CONFIG2);
245
246 /* Wait for operation to complete */
247 wait_op_done(host, TROP_US_DELAY, islast);
248 }
249
250 static void send_page(struct mtd_info *mtd, unsigned int ops)
251 {
252 struct nand_chip *nand_chip = mtd->priv;
253 struct mxc_nand_host *host = nand_chip->priv;
254 int bufs, i;
255
256 if (nfc_is_v1() && mtd->writesize > 512)
257 bufs = 4;
258 else
259 bufs = 1;
260
261 for (i = 0; i < bufs; i++) {
262
263 /* NANDFC buffer 0 is used for page read/write */
264 writew(i, host->regs + NFC_BUF_ADDR);
265
266 writew(ops, host->regs + NFC_CONFIG2);
267
268 /* Wait for operation to complete */
269 wait_op_done(host, TROP_US_DELAY, true);
270 }
271 }
272
273 /* Request the NANDFC to perform a read of the NAND device ID. */
274 static void send_read_id(struct mxc_nand_host *host)
275 {
276 struct nand_chip *this = &host->nand;
277 uint16_t tmp;
278
279 /* NANDFC buffer 0 is used for device ID output */
280 writew(0x0, host->regs + NFC_BUF_ADDR);
281
282 /* Read ID into main buffer */
283 tmp = readw(host->regs + NFC_CONFIG1);
284 tmp &= ~NFC_SP_EN;
285 writew(tmp, host->regs + NFC_CONFIG1);
286
287 writew(NFC_ID, host->regs + NFC_CONFIG2);
288
289 /* Wait for operation to complete */
290 wait_op_done(host, TROP_US_DELAY, true);
291
292 if (this->options & NAND_BUSWIDTH_16) {
293 void __iomem *main_buf = host->main_area0;
294 /* compress the ID info */
295 writeb(readb(main_buf + 2), main_buf + 1);
296 writeb(readb(main_buf + 4), main_buf + 2);
297 writeb(readb(main_buf + 6), main_buf + 3);
298 writeb(readb(main_buf + 8), main_buf + 4);
299 writeb(readb(main_buf + 10), main_buf + 5);
300 }
301 memcpy(host->data_buf, host->main_area0, 16);
302 }
303
304 /* This function requests the NANDFC to perform a read of the
305 * NAND device status and returns the current status. */
306 static uint16_t get_dev_status(struct mxc_nand_host *host)
307 {
308 void __iomem *main_buf = host->main_area1;
309 uint32_t store;
310 uint16_t ret, tmp;
311 /* Issue status request to NAND device */
312
313 /* store the main area1 first word, later do recovery */
314 store = readl(main_buf);
315 /* NANDFC buffer 1 is used for device status to prevent
316 * corruption of read/write buffer on status requests. */
317 writew(1, host->regs + NFC_BUF_ADDR);
318
319 /* Read status into main buffer */
320 tmp = readw(host->regs + NFC_CONFIG1);
321 tmp &= ~NFC_SP_EN;
322 writew(tmp, host->regs + NFC_CONFIG1);
323
324 writew(NFC_STATUS, host->regs + NFC_CONFIG2);
325
326 /* Wait for operation to complete */
327 wait_op_done(host, TROP_US_DELAY, true);
328
329 /* Status is placed in first word of main buffer */
330 /* get status, then recovery area 1 data */
331 ret = readw(main_buf);
332 writel(store, main_buf);
333
334 return ret;
335 }
336
337 /* This functions is used by upper layer to checks if device is ready */
338 static int mxc_nand_dev_ready(struct mtd_info *mtd)
339 {
340 /*
341 * NFC handles R/B internally. Therefore, this function
342 * always returns status as ready.
343 */
344 return 1;
345 }
346
347 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
348 {
349 /*
350 * If HW ECC is enabled, we turn it on during init. There is
351 * no need to enable again here.
352 */
353 }
354
355 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
356 u_char *read_ecc, u_char *calc_ecc)
357 {
358 struct nand_chip *nand_chip = mtd->priv;
359 struct mxc_nand_host *host = nand_chip->priv;
360
361 /*
362 * 1-Bit errors are automatically corrected in HW. No need for
363 * additional correction. 2-Bit errors cannot be corrected by
364 * HW ECC, so we need to return failure
365 */
366 uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
367
368 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
369 DEBUG(MTD_DEBUG_LEVEL0,
370 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
371 return -1;
372 }
373
374 return 0;
375 }
376
377 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
378 u_char *ecc_code)
379 {
380 return 0;
381 }
382
383 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
384 {
385 struct nand_chip *nand_chip = mtd->priv;
386 struct mxc_nand_host *host = nand_chip->priv;
387 uint8_t ret;
388
389 /* Check for status request */
390 if (host->status_request)
391 return get_dev_status(host) & 0xFF;
392
393 ret = *(uint8_t *)(host->data_buf + host->buf_start);
394 host->buf_start++;
395
396 return ret;
397 }
398
399 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
400 {
401 struct nand_chip *nand_chip = mtd->priv;
402 struct mxc_nand_host *host = nand_chip->priv;
403 uint16_t ret;
404
405 ret = *(uint16_t *)(host->data_buf + host->buf_start);
406 host->buf_start += 2;
407
408 return ret;
409 }
410
411 /* Write data of length len to buffer buf. The data to be
412 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
413 * Operation by the NFC, the data is written to NAND Flash */
414 static void mxc_nand_write_buf(struct mtd_info *mtd,
415 const u_char *buf, int len)
416 {
417 struct nand_chip *nand_chip = mtd->priv;
418 struct mxc_nand_host *host = nand_chip->priv;
419 u16 col = host->buf_start;
420 int n = mtd->oobsize + mtd->writesize - col;
421
422 n = min(n, len);
423
424 memcpy(host->data_buf + col, buf, n);
425
426 host->buf_start += n;
427 }
428
429 /* Read the data buffer from the NAND Flash. To read the data from NAND
430 * Flash first the data output cycle is initiated by the NFC, which copies
431 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
432 */
433 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
434 {
435 struct nand_chip *nand_chip = mtd->priv;
436 struct mxc_nand_host *host = nand_chip->priv;
437 u16 col = host->buf_start;
438 int n = mtd->oobsize + mtd->writesize - col;
439
440 n = min(n, len);
441
442 memcpy(buf, host->data_buf + col, len);
443
444 host->buf_start += len;
445 }
446
447 /* Used by the upper layer to verify the data in NAND Flash
448 * with the data in the buf. */
449 static int mxc_nand_verify_buf(struct mtd_info *mtd,
450 const u_char *buf, int len)
451 {
452 return -EFAULT;
453 }
454
455 /* This function is used by upper layer for select and
456 * deselect of the NAND chip */
457 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
458 {
459 struct nand_chip *nand_chip = mtd->priv;
460 struct mxc_nand_host *host = nand_chip->priv;
461
462 switch (chip) {
463 case -1:
464 /* Disable the NFC clock */
465 if (host->clk_act) {
466 clk_disable(host->clk);
467 host->clk_act = 0;
468 }
469 break;
470 case 0:
471 /* Enable the NFC clock */
472 if (!host->clk_act) {
473 clk_enable(host->clk);
474 host->clk_act = 1;
475 }
476 break;
477
478 default:
479 break;
480 }
481 }
482
483 /*
484 * Function to transfer data to/from spare area.
485 */
486 static void copy_spare(struct mtd_info *mtd, bool bfrom)
487 {
488 struct nand_chip *this = mtd->priv;
489 struct mxc_nand_host *host = this->priv;
490 u16 i, j;
491 u16 n = mtd->writesize >> 9;
492 u8 *d = host->data_buf + mtd->writesize;
493 u8 *s = host->spare0;
494 u16 t = host->spare_len;
495
496 j = (mtd->oobsize / n >> 1) << 1;
497
498 if (bfrom) {
499 for (i = 0; i < n - 1; i++)
500 memcpy(d + i * j, s + i * t, j);
501
502 /* the last section */
503 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
504 } else {
505 for (i = 0; i < n - 1; i++)
506 memcpy(&s[i * t], &d[i * j], j);
507
508 /* the last section */
509 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
510 }
511 }
512
513 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
514 {
515 struct nand_chip *nand_chip = mtd->priv;
516 struct mxc_nand_host *host = nand_chip->priv;
517
518 /* Write out column address, if necessary */
519 if (column != -1) {
520 /*
521 * MXC NANDFC can only perform full page+spare or
522 * spare-only read/write. When the upper layers
523 * layers perform a read/write buf operation,
524 * we will used the saved column adress to index into
525 * the full page.
526 */
527 send_addr(host, 0, page_addr == -1);
528 if (mtd->writesize > 512)
529 /* another col addr cycle for 2k page */
530 send_addr(host, 0, false);
531 }
532
533 /* Write out page address, if necessary */
534 if (page_addr != -1) {
535 /* paddr_0 - p_addr_7 */
536 send_addr(host, (page_addr & 0xff), false);
537
538 if (mtd->writesize > 512) {
539 if (mtd->size >= 0x10000000) {
540 /* paddr_8 - paddr_15 */
541 send_addr(host, (page_addr >> 8) & 0xff, false);
542 send_addr(host, (page_addr >> 16) & 0xff, true);
543 } else
544 /* paddr_8 - paddr_15 */
545 send_addr(host, (page_addr >> 8) & 0xff, true);
546 } else {
547 /* One more address cycle for higher density devices */
548 if (mtd->size >= 0x4000000) {
549 /* paddr_8 - paddr_15 */
550 send_addr(host, (page_addr >> 8) & 0xff, false);
551 send_addr(host, (page_addr >> 16) & 0xff, true);
552 } else
553 /* paddr_8 - paddr_15 */
554 send_addr(host, (page_addr >> 8) & 0xff, true);
555 }
556 }
557 }
558
559 /* Used by the upper layer to write command to NAND Flash for
560 * different operations to be carried out on NAND Flash */
561 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
562 int column, int page_addr)
563 {
564 struct nand_chip *nand_chip = mtd->priv;
565 struct mxc_nand_host *host = nand_chip->priv;
566
567 DEBUG(MTD_DEBUG_LEVEL3,
568 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
569 command, column, page_addr);
570
571 /* Reset command state information */
572 host->status_request = false;
573
574 /* Command pre-processing step */
575 switch (command) {
576
577 case NAND_CMD_STATUS:
578 host->buf_start = 0;
579 host->status_request = true;
580
581 send_cmd(host, command, true);
582 mxc_do_addr_cycle(mtd, column, page_addr);
583 break;
584
585 case NAND_CMD_READ0:
586 case NAND_CMD_READOOB:
587 if (command == NAND_CMD_READ0)
588 host->buf_start = column;
589 else
590 host->buf_start = column + mtd->writesize;
591
592 if (mtd->writesize > 512)
593 command = NAND_CMD_READ0; /* only READ0 is valid */
594
595 send_cmd(host, command, false);
596 mxc_do_addr_cycle(mtd, column, page_addr);
597
598 if (mtd->writesize > 512)
599 send_cmd(host, NAND_CMD_READSTART, true);
600
601 send_page(mtd, NFC_OUTPUT);
602
603 memcpy(host->data_buf, host->main_area0, mtd->writesize);
604 copy_spare(mtd, true);
605 break;
606
607 case NAND_CMD_SEQIN:
608 if (column >= mtd->writesize) {
609 /*
610 * FIXME: before send SEQIN command for write OOB,
611 * We must read one page out.
612 * For K9F1GXX has no READ1 command to set current HW
613 * pointer to spare area, we must write the whole page
614 * including OOB together.
615 */
616 if (mtd->writesize > 512)
617 /* call ourself to read a page */
618 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
619 page_addr);
620
621 host->buf_start = column;
622
623 /* Set program pointer to spare region */
624 if (mtd->writesize == 512)
625 send_cmd(host, NAND_CMD_READOOB, false);
626 } else {
627 host->buf_start = column;
628
629 /* Set program pointer to page start */
630 if (mtd->writesize == 512)
631 send_cmd(host, NAND_CMD_READ0, false);
632 }
633
634 send_cmd(host, command, false);
635 mxc_do_addr_cycle(mtd, column, page_addr);
636 break;
637
638 case NAND_CMD_PAGEPROG:
639 memcpy(host->main_area0, host->data_buf, mtd->writesize);
640 copy_spare(mtd, false);
641 send_page(mtd, NFC_INPUT);
642 send_cmd(host, command, true);
643 mxc_do_addr_cycle(mtd, column, page_addr);
644 break;
645
646 case NAND_CMD_READID:
647 send_cmd(host, command, true);
648 mxc_do_addr_cycle(mtd, column, page_addr);
649 send_read_id(host);
650 host->buf_start = column;
651 break;
652
653 case NAND_CMD_ERASE1:
654 case NAND_CMD_ERASE2:
655 send_cmd(host, command, false);
656 mxc_do_addr_cycle(mtd, column, page_addr);
657
658 break;
659 }
660 }
661
662 static int __init mxcnd_probe(struct platform_device *pdev)
663 {
664 struct nand_chip *this;
665 struct mtd_info *mtd;
666 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
667 struct mxc_nand_host *host;
668 struct resource *res;
669 uint16_t tmp;
670 int err = 0, nr_parts = 0;
671 struct nand_ecclayout *oob_smallpage, *oob_largepage;
672
673 /* Allocate memory for MTD device structure and private data */
674 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
675 NAND_MAX_OOBSIZE, GFP_KERNEL);
676 if (!host)
677 return -ENOMEM;
678
679 host->data_buf = (uint8_t *)(host + 1);
680
681 host->dev = &pdev->dev;
682 /* structures must be linked */
683 this = &host->nand;
684 mtd = &host->mtd;
685 mtd->priv = this;
686 mtd->owner = THIS_MODULE;
687 mtd->dev.parent = &pdev->dev;
688 mtd->name = "mxc_nand";
689
690 /* 50 us command delay time */
691 this->chip_delay = 5;
692
693 this->priv = host;
694 this->dev_ready = mxc_nand_dev_ready;
695 this->cmdfunc = mxc_nand_command;
696 this->select_chip = mxc_nand_select_chip;
697 this->read_byte = mxc_nand_read_byte;
698 this->read_word = mxc_nand_read_word;
699 this->write_buf = mxc_nand_write_buf;
700 this->read_buf = mxc_nand_read_buf;
701 this->verify_buf = mxc_nand_verify_buf;
702
703 host->clk = clk_get(&pdev->dev, "nfc");
704 if (IS_ERR(host->clk)) {
705 err = PTR_ERR(host->clk);
706 goto eclk;
707 }
708
709 clk_enable(host->clk);
710 host->clk_act = 1;
711
712 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
713 if (!res) {
714 err = -ENODEV;
715 goto eres;
716 }
717
718 host->base = ioremap(res->start, resource_size(res));
719 if (!host->base) {
720 err = -ENOMEM;
721 goto eres;
722 }
723
724 host->main_area0 = host->base;
725 host->main_area1 = host->base + 0x200;
726
727 if (nfc_is_v21()) {
728 host->regs = host->base + 0x1000;
729 host->spare0 = host->base + 0x1000;
730 host->spare_len = 64;
731 oob_smallpage = &nandv2_hw_eccoob_smallpage;
732 oob_largepage = &nandv2_hw_eccoob_largepage;
733 } else if (nfc_is_v1()) {
734 host->regs = host->base;
735 host->spare0 = host->base + 0x800;
736 host->spare_len = 16;
737 oob_smallpage = &nandv1_hw_eccoob_smallpage;
738 oob_largepage = &nandv1_hw_eccoob_largepage;
739 } else
740 BUG();
741
742 tmp = readw(host->regs + NFC_CONFIG1);
743 tmp |= NFC_INT_MSK;
744 writew(tmp, host->regs + NFC_CONFIG1);
745
746 init_waitqueue_head(&host->irq_waitq);
747
748 host->irq = platform_get_irq(pdev, 0);
749
750 err = request_irq(host->irq, mxc_nfc_irq, 0, "mxc_nd", host);
751 if (err)
752 goto eirq;
753
754 /* Reset NAND */
755 this->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
756
757 /* preset operation */
758 /* Unlock the internal RAM Buffer */
759 writew(0x2, host->regs + NFC_CONFIG);
760
761 /* Blocks to be unlocked */
762 if (nfc_is_v21()) {
763 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
764 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
765 this->ecc.bytes = 9;
766 } else if (nfc_is_v1()) {
767 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
768 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
769 this->ecc.bytes = 3;
770 } else
771 BUG();
772
773 /* Unlock Block Command for given address range */
774 writew(0x4, host->regs + NFC_WRPROT);
775
776 this->ecc.size = 512;
777 this->ecc.layout = oob_smallpage;
778
779 if (pdata->hw_ecc) {
780 this->ecc.calculate = mxc_nand_calculate_ecc;
781 this->ecc.hwctl = mxc_nand_enable_hwecc;
782 this->ecc.correct = mxc_nand_correct_data;
783 this->ecc.mode = NAND_ECC_HW;
784 tmp = readw(host->regs + NFC_CONFIG1);
785 tmp |= NFC_ECC_EN;
786 writew(tmp, host->regs + NFC_CONFIG1);
787 } else {
788 this->ecc.mode = NAND_ECC_SOFT;
789 tmp = readw(host->regs + NFC_CONFIG1);
790 tmp &= ~NFC_ECC_EN;
791 writew(tmp, host->regs + NFC_CONFIG1);
792 }
793
794 /* NAND bus width determines access funtions used by upper layer */
795 if (pdata->width == 2)
796 this->options |= NAND_BUSWIDTH_16;
797
798 /* first scan to find the device and get the page size */
799 if (nand_scan_ident(mtd, 1)) {
800 err = -ENXIO;
801 goto escan;
802 }
803
804 if (mtd->writesize == 2048)
805 this->ecc.layout = oob_largepage;
806
807 /* second phase scan */
808 if (nand_scan_tail(mtd)) {
809 err = -ENXIO;
810 goto escan;
811 }
812
813 /* Register the partitions */
814 #ifdef CONFIG_MTD_PARTITIONS
815 nr_parts =
816 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
817 if (nr_parts > 0)
818 add_mtd_partitions(mtd, host->parts, nr_parts);
819 else
820 #endif
821 {
822 pr_info("Registering %s as whole device\n", mtd->name);
823 add_mtd_device(mtd);
824 }
825
826 platform_set_drvdata(pdev, host);
827
828 return 0;
829
830 escan:
831 free_irq(host->irq, host);
832 eirq:
833 iounmap(host->base);
834 eres:
835 clk_put(host->clk);
836 eclk:
837 kfree(host);
838
839 return err;
840 }
841
842 static int __exit mxcnd_remove(struct platform_device *pdev)
843 {
844 struct mxc_nand_host *host = platform_get_drvdata(pdev);
845
846 clk_put(host->clk);
847
848 platform_set_drvdata(pdev, NULL);
849
850 nand_release(&host->mtd);
851 free_irq(host->irq, host);
852 iounmap(host->base);
853 kfree(host);
854
855 return 0;
856 }
857
858 #ifdef CONFIG_PM
859 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
860 {
861 struct mtd_info *mtd = platform_get_drvdata(pdev);
862 struct nand_chip *nand_chip = mtd->priv;
863 struct mxc_nand_host *host = nand_chip->priv;
864 int ret = 0;
865
866 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
867 if (mtd) {
868 ret = mtd->suspend(mtd);
869 /* Disable the NFC clock */
870 clk_disable(host->clk);
871 }
872
873 return ret;
874 }
875
876 static int mxcnd_resume(struct platform_device *pdev)
877 {
878 struct mtd_info *mtd = platform_get_drvdata(pdev);
879 struct nand_chip *nand_chip = mtd->priv;
880 struct mxc_nand_host *host = nand_chip->priv;
881 int ret = 0;
882
883 DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
884
885 if (mtd) {
886 /* Enable the NFC clock */
887 clk_enable(host->clk);
888 mtd->resume(mtd);
889 }
890
891 return ret;
892 }
893
894 #else
895 # define mxcnd_suspend NULL
896 # define mxcnd_resume NULL
897 #endif /* CONFIG_PM */
898
899 static struct platform_driver mxcnd_driver = {
900 .driver = {
901 .name = DRIVER_NAME,
902 },
903 .remove = __exit_p(mxcnd_remove),
904 .suspend = mxcnd_suspend,
905 .resume = mxcnd_resume,
906 };
907
908 static int __init mxc_nd_init(void)
909 {
910 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
911 }
912
913 static void __exit mxc_nd_cleanup(void)
914 {
915 /* Unregister the device structure */
916 platform_driver_unregister(&mxcnd_driver);
917 }
918
919 module_init(mxc_nd_init);
920 module_exit(mxc_nd_cleanup);
921
922 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
923 MODULE_DESCRIPTION("MXC NAND MTD driver");
924 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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