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Merge branch 'fixefi' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6
[deliverable/linux.git] / drivers / mtd / nand / mxc_nand.c
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/init.h>
23 #include <linux/module.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/completion.h>
35
36 #include <asm/mach/flash.h>
37 #include <mach/mxc_nand.h>
38 #include <mach/hardware.h>
39
40 #define DRIVER_NAME "mxc_nand"
41
42 #define nfc_is_v21() (cpu_is_mx25() || cpu_is_mx35())
43 #define nfc_is_v1() (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
44 #define nfc_is_v3_2() cpu_is_mx51()
45 #define nfc_is_v3() nfc_is_v3_2()
46
47 /* Addresses for NFC registers */
48 #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
49 #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
50 #define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
51 #define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
52 #define NFC_V1_V2_CONFIG (host->regs + 0x0a)
53 #define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
54 #define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
55 #define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
56 #define NFC_V1_V2_WRPROT (host->regs + 0x12)
57 #define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
58 #define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
59 #define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
60 #define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
61 #define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
62 #define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
63 #define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
64 #define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
65 #define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
66 #define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
67 #define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
68 #define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
69 #define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
70
71 #define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
72 #define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
73 #define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
74 #define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
75 #define NFC_V1_V2_CONFIG1_BIG (1 << 5)
76 #define NFC_V1_V2_CONFIG1_RST (1 << 6)
77 #define NFC_V1_V2_CONFIG1_CE (1 << 7)
78 #define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
79 #define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
80 #define NFC_V2_CONFIG1_FP_INT (1 << 11)
81
82 #define NFC_V1_V2_CONFIG2_INT (1 << 15)
83
84 /*
85 * Operation modes for the NFC. Valid for v1, v2 and v3
86 * type controllers.
87 */
88 #define NFC_CMD (1 << 0)
89 #define NFC_ADDR (1 << 1)
90 #define NFC_INPUT (1 << 2)
91 #define NFC_OUTPUT (1 << 3)
92 #define NFC_ID (1 << 4)
93 #define NFC_STATUS (1 << 5)
94
95 #define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
96 #define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
97
98 #define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
99 #define NFC_V3_CONFIG1_SP_EN (1 << 0)
100 #define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
101
102 #define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
103
104 #define NFC_V3_LAUNCH (host->regs_axi + 0x40)
105
106 #define NFC_V3_WRPROT (host->regs_ip + 0x0)
107 #define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
108 #define NFC_V3_WRPROT_LOCK (1 << 1)
109 #define NFC_V3_WRPROT_UNLOCK (1 << 2)
110 #define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
111
112 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
113
114 #define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
115 #define NFC_V3_CONFIG2_PS_512 (0 << 0)
116 #define NFC_V3_CONFIG2_PS_2048 (1 << 0)
117 #define NFC_V3_CONFIG2_PS_4096 (2 << 0)
118 #define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
119 #define NFC_V3_CONFIG2_ECC_EN (1 << 3)
120 #define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
121 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
122 #define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
123 #define NFC_V3_CONFIG2_PPB(x) (((x) & 0x3) << 7)
124 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
125 #define NFC_V3_CONFIG2_INT_MSK (1 << 15)
126 #define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
127 #define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
128
129 #define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
130 #define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
131 #define NFC_V3_CONFIG3_FW8 (1 << 3)
132 #define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
133 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
134 #define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
135 #define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
136
137 #define NFC_V3_IPC (host->regs_ip + 0x2C)
138 #define NFC_V3_IPC_CREQ (1 << 0)
139 #define NFC_V3_IPC_INT (1 << 31)
140
141 #define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
142
143 struct mxc_nand_host {
144 struct mtd_info mtd;
145 struct nand_chip nand;
146 struct mtd_partition *parts;
147 struct device *dev;
148
149 void *spare0;
150 void *main_area0;
151
152 void __iomem *base;
153 void __iomem *regs;
154 void __iomem *regs_axi;
155 void __iomem *regs_ip;
156 int status_request;
157 struct clk *clk;
158 int clk_act;
159 int irq;
160 int eccsize;
161 int active_cs;
162
163 struct completion op_completion;
164
165 uint8_t *data_buf;
166 unsigned int buf_start;
167 int spare_len;
168
169 void (*preset)(struct mtd_info *);
170 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
171 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
172 void (*send_page)(struct mtd_info *, unsigned int);
173 void (*send_read_id)(struct mxc_nand_host *);
174 uint16_t (*get_dev_status)(struct mxc_nand_host *);
175 int (*check_int)(struct mxc_nand_host *);
176 void (*irq_control)(struct mxc_nand_host *, int);
177 };
178
179 /* OOB placement block for use with hardware ecc generation */
180 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
181 .eccbytes = 5,
182 .eccpos = {6, 7, 8, 9, 10},
183 .oobfree = {{0, 5}, {12, 4}, }
184 };
185
186 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
187 .eccbytes = 20,
188 .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
189 38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
190 .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
191 };
192
193 /* OOB description for 512 byte pages with 16 byte OOB */
194 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
195 .eccbytes = 1 * 9,
196 .eccpos = {
197 7, 8, 9, 10, 11, 12, 13, 14, 15
198 },
199 .oobfree = {
200 {.offset = 0, .length = 5}
201 }
202 };
203
204 /* OOB description for 2048 byte pages with 64 byte OOB */
205 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
206 .eccbytes = 4 * 9,
207 .eccpos = {
208 7, 8, 9, 10, 11, 12, 13, 14, 15,
209 23, 24, 25, 26, 27, 28, 29, 30, 31,
210 39, 40, 41, 42, 43, 44, 45, 46, 47,
211 55, 56, 57, 58, 59, 60, 61, 62, 63
212 },
213 .oobfree = {
214 {.offset = 2, .length = 4},
215 {.offset = 16, .length = 7},
216 {.offset = 32, .length = 7},
217 {.offset = 48, .length = 7}
218 }
219 };
220
221 /* OOB description for 4096 byte pages with 128 byte OOB */
222 static struct nand_ecclayout nandv2_hw_eccoob_4k = {
223 .eccbytes = 8 * 9,
224 .eccpos = {
225 7, 8, 9, 10, 11, 12, 13, 14, 15,
226 23, 24, 25, 26, 27, 28, 29, 30, 31,
227 39, 40, 41, 42, 43, 44, 45, 46, 47,
228 55, 56, 57, 58, 59, 60, 61, 62, 63,
229 71, 72, 73, 74, 75, 76, 77, 78, 79,
230 87, 88, 89, 90, 91, 92, 93, 94, 95,
231 103, 104, 105, 106, 107, 108, 109, 110, 111,
232 119, 120, 121, 122, 123, 124, 125, 126, 127,
233 },
234 .oobfree = {
235 {.offset = 2, .length = 4},
236 {.offset = 16, .length = 7},
237 {.offset = 32, .length = 7},
238 {.offset = 48, .length = 7},
239 {.offset = 64, .length = 7},
240 {.offset = 80, .length = 7},
241 {.offset = 96, .length = 7},
242 {.offset = 112, .length = 7},
243 }
244 };
245
246 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
247
248 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
249 {
250 struct mxc_nand_host *host = dev_id;
251
252 if (!host->check_int(host))
253 return IRQ_NONE;
254
255 host->irq_control(host, 0);
256
257 complete(&host->op_completion);
258
259 return IRQ_HANDLED;
260 }
261
262 static int check_int_v3(struct mxc_nand_host *host)
263 {
264 uint32_t tmp;
265
266 tmp = readl(NFC_V3_IPC);
267 if (!(tmp & NFC_V3_IPC_INT))
268 return 0;
269
270 tmp &= ~NFC_V3_IPC_INT;
271 writel(tmp, NFC_V3_IPC);
272
273 return 1;
274 }
275
276 static int check_int_v1_v2(struct mxc_nand_host *host)
277 {
278 uint32_t tmp;
279
280 tmp = readw(NFC_V1_V2_CONFIG2);
281 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
282 return 0;
283
284 if (!cpu_is_mx21())
285 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
286
287 return 1;
288 }
289
290 /*
291 * It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
292 * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
293 * driver can enable/disable the irq line rather than simply masking the
294 * interrupts.
295 */
296 static void irq_control_mx21(struct mxc_nand_host *host, int activate)
297 {
298 if (activate)
299 enable_irq(host->irq);
300 else
301 disable_irq_nosync(host->irq);
302 }
303
304 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
305 {
306 uint16_t tmp;
307
308 tmp = readw(NFC_V1_V2_CONFIG1);
309
310 if (activate)
311 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
312 else
313 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
314
315 writew(tmp, NFC_V1_V2_CONFIG1);
316 }
317
318 static void irq_control_v3(struct mxc_nand_host *host, int activate)
319 {
320 uint32_t tmp;
321
322 tmp = readl(NFC_V3_CONFIG2);
323
324 if (activate)
325 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
326 else
327 tmp |= NFC_V3_CONFIG2_INT_MSK;
328
329 writel(tmp, NFC_V3_CONFIG2);
330 }
331
332 /* This function polls the NANDFC to wait for the basic operation to
333 * complete by checking the INT bit of config2 register.
334 */
335 static void wait_op_done(struct mxc_nand_host *host, int useirq)
336 {
337 int max_retries = 8000;
338
339 if (useirq) {
340 if (!host->check_int(host)) {
341 INIT_COMPLETION(host->op_completion);
342 host->irq_control(host, 1);
343 wait_for_completion(&host->op_completion);
344 }
345 } else {
346 while (max_retries-- > 0) {
347 if (host->check_int(host))
348 break;
349
350 udelay(1);
351 }
352 if (max_retries < 0)
353 DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
354 __func__);
355 }
356 }
357
358 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
359 {
360 /* fill command */
361 writel(cmd, NFC_V3_FLASH_CMD);
362
363 /* send out command */
364 writel(NFC_CMD, NFC_V3_LAUNCH);
365
366 /* Wait for operation to complete */
367 wait_op_done(host, useirq);
368 }
369
370 /* This function issues the specified command to the NAND device and
371 * waits for completion. */
372 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
373 {
374 DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
375
376 writew(cmd, NFC_V1_V2_FLASH_CMD);
377 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
378
379 if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
380 int max_retries = 100;
381 /* Reset completion is indicated by NFC_CONFIG2 */
382 /* being set to 0 */
383 while (max_retries-- > 0) {
384 if (readw(NFC_V1_V2_CONFIG2) == 0) {
385 break;
386 }
387 udelay(1);
388 }
389 if (max_retries < 0)
390 DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
391 __func__);
392 } else {
393 /* Wait for operation to complete */
394 wait_op_done(host, useirq);
395 }
396 }
397
398 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
399 {
400 /* fill address */
401 writel(addr, NFC_V3_FLASH_ADDR0);
402
403 /* send out address */
404 writel(NFC_ADDR, NFC_V3_LAUNCH);
405
406 wait_op_done(host, 0);
407 }
408
409 /* This function sends an address (or partial address) to the
410 * NAND device. The address is used to select the source/destination for
411 * a NAND command. */
412 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
413 {
414 DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
415
416 writew(addr, NFC_V1_V2_FLASH_ADDR);
417 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
418
419 /* Wait for operation to complete */
420 wait_op_done(host, islast);
421 }
422
423 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
424 {
425 struct nand_chip *nand_chip = mtd->priv;
426 struct mxc_nand_host *host = nand_chip->priv;
427 uint32_t tmp;
428
429 tmp = readl(NFC_V3_CONFIG1);
430 tmp &= ~(7 << 4);
431 writel(tmp, NFC_V3_CONFIG1);
432
433 /* transfer data from NFC ram to nand */
434 writel(ops, NFC_V3_LAUNCH);
435
436 wait_op_done(host, false);
437 }
438
439 static void send_page_v1_v2(struct mtd_info *mtd, unsigned int ops)
440 {
441 struct nand_chip *nand_chip = mtd->priv;
442 struct mxc_nand_host *host = nand_chip->priv;
443 int bufs, i;
444
445 if (nfc_is_v1() && mtd->writesize > 512)
446 bufs = 4;
447 else
448 bufs = 1;
449
450 for (i = 0; i < bufs; i++) {
451
452 /* NANDFC buffer 0 is used for page read/write */
453 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
454
455 writew(ops, NFC_V1_V2_CONFIG2);
456
457 /* Wait for operation to complete */
458 wait_op_done(host, true);
459 }
460 }
461
462 static void send_read_id_v3(struct mxc_nand_host *host)
463 {
464 /* Read ID into main buffer */
465 writel(NFC_ID, NFC_V3_LAUNCH);
466
467 wait_op_done(host, true);
468
469 memcpy(host->data_buf, host->main_area0, 16);
470 }
471
472 /* Request the NANDFC to perform a read of the NAND device ID. */
473 static void send_read_id_v1_v2(struct mxc_nand_host *host)
474 {
475 struct nand_chip *this = &host->nand;
476
477 /* NANDFC buffer 0 is used for device ID output */
478 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
479
480 writew(NFC_ID, NFC_V1_V2_CONFIG2);
481
482 /* Wait for operation to complete */
483 wait_op_done(host, true);
484
485 memcpy(host->data_buf, host->main_area0, 16);
486
487 if (this->options & NAND_BUSWIDTH_16) {
488 /* compress the ID info */
489 host->data_buf[1] = host->data_buf[2];
490 host->data_buf[2] = host->data_buf[4];
491 host->data_buf[3] = host->data_buf[6];
492 host->data_buf[4] = host->data_buf[8];
493 host->data_buf[5] = host->data_buf[10];
494 }
495 }
496
497 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
498 {
499 writew(NFC_STATUS, NFC_V3_LAUNCH);
500 wait_op_done(host, true);
501
502 return readl(NFC_V3_CONFIG1) >> 16;
503 }
504
505 /* This function requests the NANDFC to perform a read of the
506 * NAND device status and returns the current status. */
507 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
508 {
509 void __iomem *main_buf = host->main_area0;
510 uint32_t store;
511 uint16_t ret;
512
513 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
514
515 /*
516 * The device status is stored in main_area0. To
517 * prevent corruption of the buffer save the value
518 * and restore it afterwards.
519 */
520 store = readl(main_buf);
521
522 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
523 wait_op_done(host, true);
524
525 ret = readw(main_buf);
526
527 writel(store, main_buf);
528
529 return ret;
530 }
531
532 /* This functions is used by upper layer to checks if device is ready */
533 static int mxc_nand_dev_ready(struct mtd_info *mtd)
534 {
535 /*
536 * NFC handles R/B internally. Therefore, this function
537 * always returns status as ready.
538 */
539 return 1;
540 }
541
542 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
543 {
544 /*
545 * If HW ECC is enabled, we turn it on during init. There is
546 * no need to enable again here.
547 */
548 }
549
550 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
551 u_char *read_ecc, u_char *calc_ecc)
552 {
553 struct nand_chip *nand_chip = mtd->priv;
554 struct mxc_nand_host *host = nand_chip->priv;
555
556 /*
557 * 1-Bit errors are automatically corrected in HW. No need for
558 * additional correction. 2-Bit errors cannot be corrected by
559 * HW ECC, so we need to return failure
560 */
561 uint16_t ecc_status = readw(NFC_V1_V2_ECC_STATUS_RESULT);
562
563 if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
564 DEBUG(MTD_DEBUG_LEVEL0,
565 "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
566 return -1;
567 }
568
569 return 0;
570 }
571
572 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
573 u_char *read_ecc, u_char *calc_ecc)
574 {
575 struct nand_chip *nand_chip = mtd->priv;
576 struct mxc_nand_host *host = nand_chip->priv;
577 u32 ecc_stat, err;
578 int no_subpages = 1;
579 int ret = 0;
580 u8 ecc_bit_mask, err_limit;
581
582 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
583 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
584
585 no_subpages = mtd->writesize >> 9;
586
587 if (nfc_is_v21())
588 ecc_stat = readl(NFC_V1_V2_ECC_STATUS_RESULT);
589 else
590 ecc_stat = readl(NFC_V3_ECC_STATUS_RESULT);
591
592 do {
593 err = ecc_stat & ecc_bit_mask;
594 if (err > err_limit) {
595 printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
596 return -1;
597 } else {
598 ret += err;
599 }
600 ecc_stat >>= 4;
601 } while (--no_subpages);
602
603 mtd->ecc_stats.corrected += ret;
604 pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
605
606 return ret;
607 }
608
609 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
610 u_char *ecc_code)
611 {
612 return 0;
613 }
614
615 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
616 {
617 struct nand_chip *nand_chip = mtd->priv;
618 struct mxc_nand_host *host = nand_chip->priv;
619 uint8_t ret;
620
621 /* Check for status request */
622 if (host->status_request)
623 return host->get_dev_status(host) & 0xFF;
624
625 ret = *(uint8_t *)(host->data_buf + host->buf_start);
626 host->buf_start++;
627
628 return ret;
629 }
630
631 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
632 {
633 struct nand_chip *nand_chip = mtd->priv;
634 struct mxc_nand_host *host = nand_chip->priv;
635 uint16_t ret;
636
637 ret = *(uint16_t *)(host->data_buf + host->buf_start);
638 host->buf_start += 2;
639
640 return ret;
641 }
642
643 /* Write data of length len to buffer buf. The data to be
644 * written on NAND Flash is first copied to RAMbuffer. After the Data Input
645 * Operation by the NFC, the data is written to NAND Flash */
646 static void mxc_nand_write_buf(struct mtd_info *mtd,
647 const u_char *buf, int len)
648 {
649 struct nand_chip *nand_chip = mtd->priv;
650 struct mxc_nand_host *host = nand_chip->priv;
651 u16 col = host->buf_start;
652 int n = mtd->oobsize + mtd->writesize - col;
653
654 n = min(n, len);
655
656 memcpy(host->data_buf + col, buf, n);
657
658 host->buf_start += n;
659 }
660
661 /* Read the data buffer from the NAND Flash. To read the data from NAND
662 * Flash first the data output cycle is initiated by the NFC, which copies
663 * the data to RAMbuffer. This data of length len is then copied to buffer buf.
664 */
665 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
666 {
667 struct nand_chip *nand_chip = mtd->priv;
668 struct mxc_nand_host *host = nand_chip->priv;
669 u16 col = host->buf_start;
670 int n = mtd->oobsize + mtd->writesize - col;
671
672 n = min(n, len);
673
674 memcpy(buf, host->data_buf + col, n);
675
676 host->buf_start += n;
677 }
678
679 /* Used by the upper layer to verify the data in NAND Flash
680 * with the data in the buf. */
681 static int mxc_nand_verify_buf(struct mtd_info *mtd,
682 const u_char *buf, int len)
683 {
684 return -EFAULT;
685 }
686
687 /* This function is used by upper layer for select and
688 * deselect of the NAND chip */
689 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
690 {
691 struct nand_chip *nand_chip = mtd->priv;
692 struct mxc_nand_host *host = nand_chip->priv;
693
694 if (chip == -1) {
695 /* Disable the NFC clock */
696 if (host->clk_act) {
697 clk_disable(host->clk);
698 host->clk_act = 0;
699 }
700 return;
701 }
702
703 if (!host->clk_act) {
704 /* Enable the NFC clock */
705 clk_enable(host->clk);
706 host->clk_act = 1;
707 }
708
709 if (nfc_is_v21()) {
710 host->active_cs = chip;
711 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
712 }
713 }
714
715 /*
716 * Function to transfer data to/from spare area.
717 */
718 static void copy_spare(struct mtd_info *mtd, bool bfrom)
719 {
720 struct nand_chip *this = mtd->priv;
721 struct mxc_nand_host *host = this->priv;
722 u16 i, j;
723 u16 n = mtd->writesize >> 9;
724 u8 *d = host->data_buf + mtd->writesize;
725 u8 *s = host->spare0;
726 u16 t = host->spare_len;
727
728 j = (mtd->oobsize / n >> 1) << 1;
729
730 if (bfrom) {
731 for (i = 0; i < n - 1; i++)
732 memcpy(d + i * j, s + i * t, j);
733
734 /* the last section */
735 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
736 } else {
737 for (i = 0; i < n - 1; i++)
738 memcpy(&s[i * t], &d[i * j], j);
739
740 /* the last section */
741 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
742 }
743 }
744
745 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
746 {
747 struct nand_chip *nand_chip = mtd->priv;
748 struct mxc_nand_host *host = nand_chip->priv;
749
750 /* Write out column address, if necessary */
751 if (column != -1) {
752 /*
753 * MXC NANDFC can only perform full page+spare or
754 * spare-only read/write. When the upper layers
755 * perform a read/write buf operation, the saved column
756 * address is used to index into the full page.
757 */
758 host->send_addr(host, 0, page_addr == -1);
759 if (mtd->writesize > 512)
760 /* another col addr cycle for 2k page */
761 host->send_addr(host, 0, false);
762 }
763
764 /* Write out page address, if necessary */
765 if (page_addr != -1) {
766 /* paddr_0 - p_addr_7 */
767 host->send_addr(host, (page_addr & 0xff), false);
768
769 if (mtd->writesize > 512) {
770 if (mtd->size >= 0x10000000) {
771 /* paddr_8 - paddr_15 */
772 host->send_addr(host, (page_addr >> 8) & 0xff, false);
773 host->send_addr(host, (page_addr >> 16) & 0xff, true);
774 } else
775 /* paddr_8 - paddr_15 */
776 host->send_addr(host, (page_addr >> 8) & 0xff, true);
777 } else {
778 /* One more address cycle for higher density devices */
779 if (mtd->size >= 0x4000000) {
780 /* paddr_8 - paddr_15 */
781 host->send_addr(host, (page_addr >> 8) & 0xff, false);
782 host->send_addr(host, (page_addr >> 16) & 0xff, true);
783 } else
784 /* paddr_8 - paddr_15 */
785 host->send_addr(host, (page_addr >> 8) & 0xff, true);
786 }
787 }
788 }
789
790 /*
791 * v2 and v3 type controllers can do 4bit or 8bit ecc depending
792 * on how much oob the nand chip has. For 8bit ecc we need at least
793 * 26 bytes of oob data per 512 byte block.
794 */
795 static int get_eccsize(struct mtd_info *mtd)
796 {
797 int oobbytes_per_512 = 0;
798
799 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
800
801 if (oobbytes_per_512 < 26)
802 return 4;
803 else
804 return 8;
805 }
806
807 static void preset_v1_v2(struct mtd_info *mtd)
808 {
809 struct nand_chip *nand_chip = mtd->priv;
810 struct mxc_nand_host *host = nand_chip->priv;
811 uint16_t config1 = 0;
812
813 if (nand_chip->ecc.mode == NAND_ECC_HW)
814 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
815
816 if (nfc_is_v21())
817 config1 |= NFC_V2_CONFIG1_FP_INT;
818
819 if (!cpu_is_mx21())
820 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
821
822 if (nfc_is_v21() && mtd->writesize) {
823 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
824
825 host->eccsize = get_eccsize(mtd);
826 if (host->eccsize == 4)
827 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
828
829 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
830 } else {
831 host->eccsize = 1;
832 }
833
834 writew(config1, NFC_V1_V2_CONFIG1);
835 /* preset operation */
836
837 /* Unlock the internal RAM Buffer */
838 writew(0x2, NFC_V1_V2_CONFIG);
839
840 /* Blocks to be unlocked */
841 if (nfc_is_v21()) {
842 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
843 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
844 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
845 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
846 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
847 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
848 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
849 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
850 } else if (nfc_is_v1()) {
851 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
852 writew(0x4000, NFC_V1_UNLOCKEND_BLKADDR);
853 } else
854 BUG();
855
856 /* Unlock Block Command for given address range */
857 writew(0x4, NFC_V1_V2_WRPROT);
858 }
859
860 static void preset_v3(struct mtd_info *mtd)
861 {
862 struct nand_chip *chip = mtd->priv;
863 struct mxc_nand_host *host = chip->priv;
864 uint32_t config2, config3;
865 int i, addr_phases;
866
867 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
868 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
869
870 /* Unlock the internal RAM Buffer */
871 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
872 NFC_V3_WRPROT);
873
874 /* Blocks to be unlocked */
875 for (i = 0; i < NAND_MAX_CHIPS; i++)
876 writel(0x0 | (0xffff << 16),
877 NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
878
879 writel(0, NFC_V3_IPC);
880
881 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
882 NFC_V3_CONFIG2_2CMD_PHASES |
883 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
884 NFC_V3_CONFIG2_ST_CMD(0x70) |
885 NFC_V3_CONFIG2_INT_MSK |
886 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
887
888 if (chip->ecc.mode == NAND_ECC_HW)
889 config2 |= NFC_V3_CONFIG2_ECC_EN;
890
891 addr_phases = fls(chip->pagemask) >> 3;
892
893 if (mtd->writesize == 2048) {
894 config2 |= NFC_V3_CONFIG2_PS_2048;
895 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
896 } else if (mtd->writesize == 4096) {
897 config2 |= NFC_V3_CONFIG2_PS_4096;
898 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
899 } else {
900 config2 |= NFC_V3_CONFIG2_PS_512;
901 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
902 }
903
904 if (mtd->writesize) {
905 config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
906 host->eccsize = get_eccsize(mtd);
907 if (host->eccsize == 8)
908 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
909 }
910
911 writel(config2, NFC_V3_CONFIG2);
912
913 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
914 NFC_V3_CONFIG3_NO_SDMA |
915 NFC_V3_CONFIG3_RBB_MODE |
916 NFC_V3_CONFIG3_SBB(6) | /* Reset default */
917 NFC_V3_CONFIG3_ADD_OP(0);
918
919 if (!(chip->options & NAND_BUSWIDTH_16))
920 config3 |= NFC_V3_CONFIG3_FW8;
921
922 writel(config3, NFC_V3_CONFIG3);
923
924 writel(0, NFC_V3_DELAY_LINE);
925 }
926
927 /* Used by the upper layer to write command to NAND Flash for
928 * different operations to be carried out on NAND Flash */
929 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
930 int column, int page_addr)
931 {
932 struct nand_chip *nand_chip = mtd->priv;
933 struct mxc_nand_host *host = nand_chip->priv;
934
935 DEBUG(MTD_DEBUG_LEVEL3,
936 "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
937 command, column, page_addr);
938
939 /* Reset command state information */
940 host->status_request = false;
941
942 /* Command pre-processing step */
943 switch (command) {
944 case NAND_CMD_RESET:
945 host->preset(mtd);
946 host->send_cmd(host, command, false);
947 break;
948
949 case NAND_CMD_STATUS:
950 host->buf_start = 0;
951 host->status_request = true;
952
953 host->send_cmd(host, command, true);
954 mxc_do_addr_cycle(mtd, column, page_addr);
955 break;
956
957 case NAND_CMD_READ0:
958 case NAND_CMD_READOOB:
959 if (command == NAND_CMD_READ0)
960 host->buf_start = column;
961 else
962 host->buf_start = column + mtd->writesize;
963
964 command = NAND_CMD_READ0; /* only READ0 is valid */
965
966 host->send_cmd(host, command, false);
967 mxc_do_addr_cycle(mtd, column, page_addr);
968
969 if (mtd->writesize > 512)
970 host->send_cmd(host, NAND_CMD_READSTART, true);
971
972 host->send_page(mtd, NFC_OUTPUT);
973
974 memcpy(host->data_buf, host->main_area0, mtd->writesize);
975 copy_spare(mtd, true);
976 break;
977
978 case NAND_CMD_SEQIN:
979 if (column >= mtd->writesize)
980 /* call ourself to read a page */
981 mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
982
983 host->buf_start = column;
984
985 host->send_cmd(host, command, false);
986 mxc_do_addr_cycle(mtd, column, page_addr);
987 break;
988
989 case NAND_CMD_PAGEPROG:
990 memcpy(host->main_area0, host->data_buf, mtd->writesize);
991 copy_spare(mtd, false);
992 host->send_page(mtd, NFC_INPUT);
993 host->send_cmd(host, command, true);
994 mxc_do_addr_cycle(mtd, column, page_addr);
995 break;
996
997 case NAND_CMD_READID:
998 host->send_cmd(host, command, true);
999 mxc_do_addr_cycle(mtd, column, page_addr);
1000 host->send_read_id(host);
1001 host->buf_start = column;
1002 break;
1003
1004 case NAND_CMD_ERASE1:
1005 case NAND_CMD_ERASE2:
1006 host->send_cmd(host, command, false);
1007 mxc_do_addr_cycle(mtd, column, page_addr);
1008
1009 break;
1010 }
1011 }
1012
1013 /*
1014 * The generic flash bbt decriptors overlap with our ecc
1015 * hardware, so define some i.MX specific ones.
1016 */
1017 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1018 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1019
1020 static struct nand_bbt_descr bbt_main_descr = {
1021 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1022 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1023 .offs = 0,
1024 .len = 4,
1025 .veroffs = 4,
1026 .maxblocks = 4,
1027 .pattern = bbt_pattern,
1028 };
1029
1030 static struct nand_bbt_descr bbt_mirror_descr = {
1031 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1032 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1033 .offs = 0,
1034 .len = 4,
1035 .veroffs = 4,
1036 .maxblocks = 4,
1037 .pattern = mirror_pattern,
1038 };
1039
1040 static int __init mxcnd_probe(struct platform_device *pdev)
1041 {
1042 struct nand_chip *this;
1043 struct mtd_info *mtd;
1044 struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
1045 struct mxc_nand_host *host;
1046 struct resource *res;
1047 int err = 0, __maybe_unused nr_parts = 0;
1048 struct nand_ecclayout *oob_smallpage, *oob_largepage;
1049
1050 /* Allocate memory for MTD device structure and private data */
1051 host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
1052 NAND_MAX_OOBSIZE, GFP_KERNEL);
1053 if (!host)
1054 return -ENOMEM;
1055
1056 host->data_buf = (uint8_t *)(host + 1);
1057
1058 host->dev = &pdev->dev;
1059 /* structures must be linked */
1060 this = &host->nand;
1061 mtd = &host->mtd;
1062 mtd->priv = this;
1063 mtd->owner = THIS_MODULE;
1064 mtd->dev.parent = &pdev->dev;
1065 mtd->name = DRIVER_NAME;
1066
1067 /* 50 us command delay time */
1068 this->chip_delay = 5;
1069
1070 this->priv = host;
1071 this->dev_ready = mxc_nand_dev_ready;
1072 this->cmdfunc = mxc_nand_command;
1073 this->select_chip = mxc_nand_select_chip;
1074 this->read_byte = mxc_nand_read_byte;
1075 this->read_word = mxc_nand_read_word;
1076 this->write_buf = mxc_nand_write_buf;
1077 this->read_buf = mxc_nand_read_buf;
1078 this->verify_buf = mxc_nand_verify_buf;
1079
1080 host->clk = clk_get(&pdev->dev, "nfc");
1081 if (IS_ERR(host->clk)) {
1082 err = PTR_ERR(host->clk);
1083 goto eclk;
1084 }
1085
1086 clk_enable(host->clk);
1087 host->clk_act = 1;
1088
1089 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1090 if (!res) {
1091 err = -ENODEV;
1092 goto eres;
1093 }
1094
1095 host->base = ioremap(res->start, resource_size(res));
1096 if (!host->base) {
1097 err = -ENOMEM;
1098 goto eres;
1099 }
1100
1101 host->main_area0 = host->base;
1102
1103 if (nfc_is_v1() || nfc_is_v21()) {
1104 host->preset = preset_v1_v2;
1105 host->send_cmd = send_cmd_v1_v2;
1106 host->send_addr = send_addr_v1_v2;
1107 host->send_page = send_page_v1_v2;
1108 host->send_read_id = send_read_id_v1_v2;
1109 host->get_dev_status = get_dev_status_v1_v2;
1110 host->check_int = check_int_v1_v2;
1111 if (cpu_is_mx21())
1112 host->irq_control = irq_control_mx21;
1113 else
1114 host->irq_control = irq_control_v1_v2;
1115 }
1116
1117 if (nfc_is_v21()) {
1118 host->regs = host->base + 0x1e00;
1119 host->spare0 = host->base + 0x1000;
1120 host->spare_len = 64;
1121 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1122 oob_largepage = &nandv2_hw_eccoob_largepage;
1123 this->ecc.bytes = 9;
1124 } else if (nfc_is_v1()) {
1125 host->regs = host->base + 0xe00;
1126 host->spare0 = host->base + 0x800;
1127 host->spare_len = 16;
1128 oob_smallpage = &nandv1_hw_eccoob_smallpage;
1129 oob_largepage = &nandv1_hw_eccoob_largepage;
1130 this->ecc.bytes = 3;
1131 host->eccsize = 1;
1132 } else if (nfc_is_v3_2()) {
1133 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1134 if (!res) {
1135 err = -ENODEV;
1136 goto eirq;
1137 }
1138 host->regs_ip = ioremap(res->start, resource_size(res));
1139 if (!host->regs_ip) {
1140 err = -ENOMEM;
1141 goto eirq;
1142 }
1143 host->regs_axi = host->base + 0x1e00;
1144 host->spare0 = host->base + 0x1000;
1145 host->spare_len = 64;
1146 host->preset = preset_v3;
1147 host->send_cmd = send_cmd_v3;
1148 host->send_addr = send_addr_v3;
1149 host->send_page = send_page_v3;
1150 host->send_read_id = send_read_id_v3;
1151 host->check_int = check_int_v3;
1152 host->get_dev_status = get_dev_status_v3;
1153 host->irq_control = irq_control_v3;
1154 oob_smallpage = &nandv2_hw_eccoob_smallpage;
1155 oob_largepage = &nandv2_hw_eccoob_largepage;
1156 } else
1157 BUG();
1158
1159 this->ecc.size = 512;
1160 this->ecc.layout = oob_smallpage;
1161
1162 if (pdata->hw_ecc) {
1163 this->ecc.calculate = mxc_nand_calculate_ecc;
1164 this->ecc.hwctl = mxc_nand_enable_hwecc;
1165 if (nfc_is_v1())
1166 this->ecc.correct = mxc_nand_correct_data_v1;
1167 else
1168 this->ecc.correct = mxc_nand_correct_data_v2_v3;
1169 this->ecc.mode = NAND_ECC_HW;
1170 } else {
1171 this->ecc.mode = NAND_ECC_SOFT;
1172 }
1173
1174 /* NAND bus width determines access funtions used by upper layer */
1175 if (pdata->width == 2)
1176 this->options |= NAND_BUSWIDTH_16;
1177
1178 if (pdata->flash_bbt) {
1179 this->bbt_td = &bbt_main_descr;
1180 this->bbt_md = &bbt_mirror_descr;
1181 /* update flash based bbt */
1182 this->options |= NAND_USE_FLASH_BBT;
1183 }
1184
1185 init_completion(&host->op_completion);
1186
1187 host->irq = platform_get_irq(pdev, 0);
1188
1189 /*
1190 * mask the interrupt. For i.MX21 explicitely call
1191 * irq_control_v1_v2 to use the mask bit. We can't call
1192 * disable_irq_nosync() for an interrupt we do not own yet.
1193 */
1194 if (cpu_is_mx21())
1195 irq_control_v1_v2(host, 0);
1196 else
1197 host->irq_control(host, 0);
1198
1199 err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
1200 if (err)
1201 goto eirq;
1202
1203 host->irq_control(host, 0);
1204
1205 /*
1206 * Now that the interrupt is disabled make sure the interrupt
1207 * mask bit is cleared on i.MX21. Otherwise we can't read
1208 * the interrupt status bit on this machine.
1209 */
1210 if (cpu_is_mx21())
1211 irq_control_v1_v2(host, 1);
1212
1213 /* first scan to find the device and get the page size */
1214 if (nand_scan_ident(mtd, nfc_is_v21() ? 4 : 1, NULL)) {
1215 err = -ENXIO;
1216 goto escan;
1217 }
1218
1219 /* Call preset again, with correct writesize this time */
1220 host->preset(mtd);
1221
1222 if (mtd->writesize == 2048)
1223 this->ecc.layout = oob_largepage;
1224 if (nfc_is_v21() && mtd->writesize == 4096)
1225 this->ecc.layout = &nandv2_hw_eccoob_4k;
1226
1227 /* second phase scan */
1228 if (nand_scan_tail(mtd)) {
1229 err = -ENXIO;
1230 goto escan;
1231 }
1232
1233 /* Register the partitions */
1234 nr_parts =
1235 parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
1236 if (nr_parts > 0)
1237 mtd_device_register(mtd, host->parts, nr_parts);
1238 else if (pdata->parts)
1239 mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
1240 else {
1241 pr_info("Registering %s as whole device\n", mtd->name);
1242 mtd_device_register(mtd, NULL, 0);
1243 }
1244
1245 platform_set_drvdata(pdev, host);
1246
1247 return 0;
1248
1249 escan:
1250 free_irq(host->irq, host);
1251 eirq:
1252 if (host->regs_ip)
1253 iounmap(host->regs_ip);
1254 iounmap(host->base);
1255 eres:
1256 clk_put(host->clk);
1257 eclk:
1258 kfree(host);
1259
1260 return err;
1261 }
1262
1263 static int __devexit mxcnd_remove(struct platform_device *pdev)
1264 {
1265 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1266
1267 clk_put(host->clk);
1268
1269 platform_set_drvdata(pdev, NULL);
1270
1271 nand_release(&host->mtd);
1272 free_irq(host->irq, host);
1273 if (host->regs_ip)
1274 iounmap(host->regs_ip);
1275 iounmap(host->base);
1276 kfree(host);
1277
1278 return 0;
1279 }
1280
1281 static struct platform_driver mxcnd_driver = {
1282 .driver = {
1283 .name = DRIVER_NAME,
1284 },
1285 .remove = __devexit_p(mxcnd_remove),
1286 };
1287
1288 static int __init mxc_nd_init(void)
1289 {
1290 return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
1291 }
1292
1293 static void __exit mxc_nd_cleanup(void)
1294 {
1295 /* Unregister the device structure */
1296 platform_driver_unregister(&mxcnd_driver);
1297 }
1298
1299 module_init(mxc_nd_init);
1300 module_exit(mxc_nd_cleanup);
1301
1302 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1303 MODULE_DESCRIPTION("MXC NAND MTD driver");
1304 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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